WO2020111521A1 - Dram 1t basée sur un thyristor de type vertical à deux bornes - Google Patents

Dram 1t basée sur un thyristor de type vertical à deux bornes Download PDF

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WO2020111521A1
WO2020111521A1 PCT/KR2019/014087 KR2019014087W WO2020111521A1 WO 2020111521 A1 WO2020111521 A1 WO 2020111521A1 KR 2019014087 W KR2019014087 W KR 2019014087W WO 2020111521 A1 WO2020111521 A1 WO 2020111521A1
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dram
base layer
emitter layer
layer
type material
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Korean (ko)
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박재근
유상동
심태헌
김민원
이병석
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한양대학교 산학협력단
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1027—Thyristors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1012—Base regions of thyristors
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present invention relates to a technical idea for forming a 2-terminal vertical thyristor-based 1T DRAM, by forming a 2-terminal vertical thyristor-based 1T DRAM using a Schottky contact between the base and the emitter, the operation It is about a 2-terminal vertical thyristor-based 1T DRAM that solves the temperature dependency problem and secures a memory margin.
  • DRAM dynamic random access memory
  • MTJ magnetic tunnel junction
  • MTJ magnetic tunnel junction
  • p-STT-MRAM perpendicular spin-torque-transfer magnetic random access memory
  • the thyristor-based 1T-DRAM uses 3 terminals (anode, cathode, gate), and in 2018, Hanyang University applied Applied to the research on the 2-terminal thyristor-based cross-point memory that can operate without a selector element.
  • Hanyang University applied Applied to the research on the 2-terminal thyristor-based cross-point memory that can operate without a selector element.
  • the thyristor-based 1T-DRAM has a total of three terminals, one at the anode and the other at the ends of the pnpn structure, and one gate at one of the center base regions. Based on the horizontal structure, there is a limit to scaling down.
  • the 2-terminal vertical thyristor-based 1T DRAM of p-n-p-n or n-p-n-p structure has an advantage in scaling down compared to the 3-terminal, but has a problem in that the memory margin decreases as the operating temperature increases.
  • FIG. 1 is a view for explaining a two-terminal vertical thyristor-based 1T DRAM according to the prior art.
  • a two-terminal vertical thyristor-based 1T DRAM 100 includes a first emitter layer 110, a first base layer 120, a second base layer 130, and a second emitter layer 140. It can be formed to include.
  • the first emitter layer 110 may be connected to the cathode 150 or may serve as the cathode 150, and may be formed using a first conductivity type or a second conductivity type material.
  • the first base layer 120 and the second base layer 130 are formed using different conductive type materials, and may be operated as a base region.
  • the second emitter layer 140 may be connected to the anode 160 or may serve as the anode 160, and may be formed using a first conductivity type or a second conductivity type material.
  • the second emitter layer 140 may be formed using a second conductivity type material.
  • the first conductivity-type material may include n-type impurities
  • the second conductivity-type material may include p-type impurities
  • the 2-terminal thyristor-based 1T DRAM 100 may exhibit a p-n-p-n or n-p-n-p structure.
  • FIG. 2A illustrates an energy-band-diagram of a conventional two-terminal vertical thyristor-based 1T DRAM.
  • Figure 2b illustrates the electrical characteristics of the conventional 2-terminal vertical thyristor-based 1T DRAM by temperature.
  • FIG. 2C is a diagram illustrating a memory margin of a conventional 2-terminal vertical thyristor-based 1T DRAM according to temperature change.
  • the conventional two-terminal vertical thyristor-based 1T DRAM has a pnpn structure
  • the latch-up voltage (V LU ) is 2.78V as the operating temperature increases to 300K, 320K, 340K, 360K, 380K, 400K , 2.39V, 1.90V, 1.37V, 0.88V, 0.50V
  • the latch-down voltage (V LD ) is reduced to 0.54V, 0.50V, 0.44V, 0.42V, 0.34V, 0.32V.
  • the memory margin may represent a difference between the latch up voltage (V LU ) and the latch down voltage (V LD ).
  • the conventional two-terminal vertical thyristor-based 1T DRAM has an advantage in scaling down, but there is a disadvantage that the memory margin decreases as the operating temperature increases.
  • the present invention may be intended to secure the operational stability of the memory even at high temperatures by replacing the emitter layer connected to at least one of the positive electrode or the negative electrode with a metal material using a Schottky contact.
  • the present invention may be intended to reduce the aspect ratio of the memory cell by reducing the thickness of the emitter layer by replacing the emitter layer with a metal material using a Schottky contact.
  • the present invention can be aimed at reducing the operating temperature dependence of the memory by replacing the emitter layer with a metal material using a Schottky contact.
  • the present invention may be intended to overcome the physical limitations on the memory cell structure by replacing the emitter layer with a metal material using a Schottky contact.
  • a 2-terminal vertical thyristor-based 1T DRAM is a first emitter layer formed of a first conductivity type material, and a second conductivity type material on the first emitter layer.
  • a second base layer vertically formed of the first conductive material on the first base layer, and on the second base layer
  • the second base layer may include a second emitter layer vertically formed of a metal material that forms a Schottky contact.
  • the metal material includes at least one of gold (Au), cobalt (Co), copper (Cu), iron (Fe), nickel (Ni), palladium (Pd), platinum (Pt), and ruthenium (Ru) can do.
  • the first emitter layer may be formed of a metal material that forms a Schottky contact with the first base layer by replacing the first conductive type material.
  • the second emitter layer may output a latch up voltage of 1.58V to 2.83V in a temperature range of 300K to 400K.
  • the second emitter layer may output a latch down voltage of 0.8V to 0.89V in a temperature range of 300K to 400K.
  • the first conductivity type material may include n-type impurities, and the second conductivity type material may include p-type impurities.
  • a 2-terminal vertical thyristor-based 1T DRAM is a first emitter layer formed of a metal material, and the first emitter on the first emitter layer.
  • a first base layer vertically formed of a second conductive type material forming a Schottky contact with a layer, and a second vertically formed of the first conductive type material on the first base layer It may include a base layer and a second emitter layer vertically formed of a second conductive type material on the second base layer.
  • the second emitter layer may be formed of a metal material that forms a Schottky contact with the second base layer by replacing the second conductive type material.
  • a 2-terminal vertical thyristor-based 1T DRAM is a first emitter layer formed of a first conductivity type material, and a second conductivity type material on the first emitter layer.
  • a first base layer vertically formed, a second base layer vertically formed of the first conductive material on the first base layer, and on the second base layer
  • a second emitter layer vertically formed of a metal material forming a Schottky contact with the second base layer, and the first conductive type material on the second emitter layer
  • the present invention can secure the operational stability of the memory even at high temperatures by replacing the emitter layer connected to at least one of the positive electrode or the negative electrode with a metal material using a Schottky contact.
  • the present invention can reduce the aspect ratio of the memory cell by reducing the thickness of the emitter layer by replacing the emitter layer with a metal material using a Schottky contact.
  • the present invention can reduce the dependence of the operating temperature of the memory by replacing the emitter layer with a metal material using a Schottky contact.
  • 1 to 2c are views illustrating a conventional two-terminal vertical thyristor-based 1T DRAM.
  • FIG 3 is a view for explaining the structure of a two-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • 4A is a diagram illustrating an energy band diagram of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • 4B is a diagram illustrating electrical characteristics of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • 4C is a diagram illustrating the operating temperature dependence of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 5 is a view for explaining a flowchart related to a method of manufacturing a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • 6A and 6B are diagrams illustrating a double-layer structure of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 7A is a diagram illustrating an energy band diagram of a 2 terminal vertical thyristor based 1T DRAM having a conventional double stacked structure.
  • FIG. 7B is a diagram illustrating an energy band diagram of a two-terminal vertical thyristor-based 1T DRAM having a double stacked structure according to an embodiment of the present invention.
  • 8A is a diagram for explaining electrical characteristics of a two-terminal vertical thyristor-based 1T DRAM having a conventional double stacked structure.
  • 8B is a diagram for explaining electrical characteristics of a 2-terminal vertical thyristor-based 1T DRAM having a double-layered structure according to an embodiment of the present invention.
  • first or second may be used to describe various components, but the components should not be limited by the terms. The above terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of rights according to the concept of the present invention, the first component may be referred to as the second component, Similarly, the second component may also be referred to as the first component.
  • FIG 3 is a view for explaining the structure of a two-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 3 illustrates the structure of a two-terminal vertical thyristor-based 1T DRAM formed by replacing an emitter layer with metal using a Schottky contact.
  • a 2-terminal vertical thyristor-based 1T DRAM 300 includes a first emitter layer 310, a first base layer 320, a second base layer 330, and And a second emitter layer 340.
  • the first emitter layer 310 may be formed of a first conductivity type material.
  • the first emitter layer 310 may be formed by adding a first conductivity type impurity at a high concentration.
  • the first emitter layer 310 may be formed to have a region thickness of about 100 nm.
  • the first emitter layer 310 may be formed of a metal material that forms a Schottky contact with the first base layer by replacing the first conductive type material.
  • the first base layer 320 may be vertically formed of a second conductive type material on the first emitter layer 310.
  • the first base layer 320 may be formed using a second conductive material having a low concentration compared to the first emitter layer 310.
  • the second base layer 330 may be vertically formed of a first conductive type material on the first base layer 320.
  • the second base layer 320 may be formed using a first conductivity type material having the same concentration as the first base layer 320.
  • the first base layer 320 and the second base layer 330 may be operated as a base region.
  • each region of the first base layer 320 and the second base layer 330 may be about 100 nm.
  • the second emitter layer 340 may be vertically formed on the second base layer 330 using a metal material that forms a Schottky contact with the second base layer.
  • the second emitter layer 340 may output a latch up voltage of 1.58V to 2.83V in a temperature range of 300K to 400K.
  • the latch-up voltage decreases to 2.83V, 2.64V, 2.40V, 2.13V, 1.85V, 1.58V Can be output.
  • the latch-up voltage can be reduced to 0.89V, 0.86V, 0.83V, 0.82V, 0.80V, 0.80 and output. .
  • the present invention can reduce the aspect ratio of the memory cell by reducing the thickness of the emitter layer by replacing the emitter layer with a metal material using a Schottky contact.
  • the cathode 350 may be connected to the first emitter layer 310 or the first emitter layer 310 may be operated as the cathode 350.
  • the anode 360 may be connected to the second emitter layer 340 or the second emitter layer 340 may be operated as the anode 360.
  • the cathode 350 and the anode 360 have a thickness of about 20 nm, and a doping concentration may be 1 x 10 18 cm -3 .
  • the metal material is at least one of gold (Au), cobalt (Co), copper (Cu), iron (Fe), nickel (Ni), palladium (Pd), platinum (Pt), and ruthenium (Ru). It may include.
  • the first conductivity-type material may include n-type impurities
  • the second conductivity-type material may include p-type impurities
  • the two-terminal vertical thyristor-based 1T DRAM 300 converts the state of the memory to "1" or "0" based on changes in the potential of the first base layer 320 and the second base layer 330. And can operate as a memory.
  • the 2-terminal thyristor-based 1T DRAM 300 induces a latch-up when the state of the first base layer 320 is high in the read state, thereby causing the memory state to be " 1", when the state of the first base layer 320 is low, causing blocking, resulting in a memory state of "0", a low off current of pA level and about 10 ⁇ A current It may have a high read current.
  • 4A is a diagram illustrating an energy band diagram of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • the first base layer and the second base layer of the two-terminal vertical thyristor-based 1T DRAM may be located between 0.2 mm and 0.3 mm on the horizontal axis of the graph.
  • 4B is a diagram illustrating electrical characteristics of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 4B illustrates electrical characteristics corresponding to a change in the anode voltage according to the anode current based on a temperature range change of 300K to 400K in a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • the reduction of the anode voltage is relatively small in the high temperature range of the 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • the 2-terminal vertical thyristor-based 1T DRAM can secure a relatively high memory margin compared to the conventional 2-terminal vertical thyristor-based 1T DRAM.
  • the present invention can secure the operational stability of the memory even at high temperatures by replacing the emitter layer connected to at least one of the anode or the cathode with a metal material using a Schottky contact.
  • 4C is a diagram illustrating the operating temperature dependence of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 4C shows the change of the latch-up voltage (V LU ) and the latch-down voltage (V LD ) based on a temperature range change of 300K to 400K in a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • the reduction of the latch-up voltage (V LU ) and the latch-down voltage (V LD ) is relatively high in the high temperature range of the 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention. small.
  • the 2-terminal vertical thyristor-based 1T DRAM can secure a relatively high memory margin compared to the conventional 2-terminal vertical thyristor-based 1T DRAM.
  • the present invention can reduce the dependence of the operating temperature of the memory by replacing the emitter layer with a metal material using a Schottky contact.
  • FIG. 5 is a view for explaining a flowchart related to a method of manufacturing a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • a method of manufacturing a 2-terminal vertical thyristor-based 1T DRAM forms a first emitter layer using a first conductivity type material.
  • a first emitter layer may be formed by doping impurities of a first conductivity type on a substrate.
  • the first emitter layer can be operated as a cathode or connected to the cathode.
  • a method of manufacturing a two-terminal vertical thyristor-based 1T DRAM may form a first base layer using a second conductive material.
  • a first base layer may be vertically formed by doping a second conductive type impurity on the first emitter layer.
  • a method of manufacturing a two-terminal vertical thyristor-based 1T DRAM forms a second base layer using a first conductivity type material.
  • a second base layer may be vertically formed by doping a first conductive type impurity on the first base layer.
  • a method of manufacturing a two-terminal vertical thyristor-based 1T DRAM may use a metal material to form a second emitter layer.
  • the method of manufacturing a two-terminal vertical thyristor-based 1T DRAM uses a metal material that forms a second base (Schottky Contact with the second base layer on the layer) and vertically emits the second emitter layer. Can form.
  • the second emitter layer can be operated as an anode or connected to the anode.
  • 6A is a diagram illustrating a double-layer structure of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 6A illustrates a double stacked structure in a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • a two-terminal vertical thyristor-based 1T DRAM 600 may be formed on a substrate 610, and includes a first emitter layer 620, a first base layer 630, and a second base layer ( 640), a second emitter layer 650, a third base layer 641, a fourth base layer 631 and a third emitter layer 621 may be formed.
  • the first emitter layer 620 may be formed of a first conductive type material, and a high concentration of first impurities may be doped.
  • the first base layer 630 may be vertically formed of a second conductive type material on the first emitter layer 620, and is relatively relatively doped than the doping concentration of the first emitter layer 620.
  • the second impurity at a low concentration may be formed by doping.
  • the second base layer 640 may be vertically formed of a first conductive type material on the first base layer 630, and the first impurity having the same concentration as the doping concentration of the first base layer 630 may be It can be formed by doping.
  • the second emitter layer 650 may be vertically formed of a metal material that forms a Schottky contact with the second base layer 640 on the second base layer 640.
  • the second emitter layer 650 may also be referred to as a metal layer.
  • the third base layer 641 may be vertically formed of the first conductive type material on the second emitter layer 650.
  • the fourth base layer 631 may be vertically formed of a second conductive type material on the third base layer 641.
  • the third emitter layer 621 may be vertically formed of a first conductive type material on the fourth base layer 631.
  • the second emitter layer 650 may function as an anode, and the first emitter layer 620 and the third emitter layer 621 may act as a cathode.
  • 6B is a diagram illustrating a double-layer structure of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 6B illustrates a three-dimensional stereogram of the two-terminal vertical thyristor-based 1T DRAM described in FIG. 6A.
  • a two-terminal vertical thyristor-based 1T DRAM 600 may be formed on a substrate 610, and includes a first emitter layer 620, a first base layer 630, and a second base layer ( 640), including a second emitter layer 650, a third base layer is vertically formed using the same material as the second base layer 640 on the second emitter layer 650, and on the third base layer
  • a fourth base layer is vertically formed using the same material as the first base layer 630, and a third emitter layer is vertically formed using the same material as the first emitter layer 620 on the fourth base layer.
  • the first emitter layer 620 and the third emitter layer may be connected to a bit line, and the second emitter layer 650 may be connected to a word line.
  • the two-terminal vertical thyristor-based 1T DRAM 600 may be operated as a cross-point memory device based on a double-stacked structure.
  • the 2-terminal vertical thyristor-based 1T DRAM 600 may also be referred to as a 3D cross-point memory device.
  • FIG. 7A is a diagram illustrating an energy band diagram of a conventional 2T vertical thyristor-based 1T DRAM having a dual-stack structure
  • FIG. 7B is a 2-terminal vertical thyristor-based double-stack structure according to an embodiment of the present invention. It is a diagram to explain the energy band diagram of 1T DRAM.
  • FIG. 7A a change in the anode voltage 700 and the cathode voltage 701 in each layer of a conventional two-terminal vertical thyristor-based 1T DRAM is illustrated.
  • an anode of a metal layer forming a Schottky contact with a base layer may be positioned at a junction of 0.3 to 0.4.
  • the two-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention has a relatively small drop in the latch-down voltage, so a higher memory margin can be secured.
  • FIG. 8A is a diagram for explaining electrical characteristics of a conventional 2-terminal vertical thyristor-based 1T DRAM having a dual-stacked structure
  • FIG. 8B is a 2-terminal vertical thyristor-based 1T having a dual-stacked structure according to an embodiment of the present invention. This diagram explains the electrical characteristics of DRAM.
  • a two-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention has a relatively small decrease in anode voltage in a high temperature range.
  • the 2-terminal vertical thyristor-based 1T DRAM can secure a relatively high memory margin compared to the conventional 2-terminal vertical thyristor-based 1T DRAM.
  • the device described above may be implemented with hardware components, software components, and/or combinations of hardware components and software components.
  • the devices and components described in the embodiments include, for example, processors, controllers, arithmetic logic units (ALUs), digital signal processors (micro signal processors), microcomputers, field programmable arrays (FPAs), It may be implemented using one or more general purpose computers or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions.
  • the processing device may run an operating system (OS) and one or more software applications running on the operating system.
  • the processing device may access, store, manipulate, process, and generate data in response to the execution of the software.
  • OS operating system
  • the processing device may access, store, manipulate, process, and generate data in response to the execution of the software.
  • a processing device may be described as one being used, but a person having ordinary skill in the art, the processing device may include a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that may include.
  • the processing device may include a plurality of processors or a processor and a controller.
  • other processing configurations such as parallel processors, are possible.
  • the method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium.
  • the computer-readable medium may include program instructions, data files, data structures, or the like alone or in combination.
  • the program instructions recorded in the medium may be specially designed and configured for the embodiments or may be known and usable by those skilled in computer software.
  • Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs, DVDs, and magnetic media such as floptical disks.
  • -Hardware devices specifically configured to store and execute program instructions such as magneto-optical media, and ROM, RAM, flash memory, and the like.
  • program instructions include high-level language code that can be executed by a computer using an interpreter, etc., as well as machine language codes produced by a compiler.
  • the hardware device described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente invention concerne une DRAM 1T basée sur un thyristor de type vertical à deux bornes. Selon un mode de réalisation de la présente invention, la DRAM 1T basée sur un thyristor de type vertical à deux bornes peut comprendre : une première couche d'émetteur formée d'un premier matériau conducteur ; une première couche de base formée verticalement d'un second matériau conducteur sur la première couche d'émetteur ; une seconde couche de base formée verticalement du premier matériau conducteur sur la première couche de base ; et une seconde couche d'émetteur formée verticalement d'un matériau métallique sur la seconde couche de base, le matériau métallique étant en contact Schottky avec la seconde couche de base.
PCT/KR2019/014087 2018-11-27 2019-10-24 Dram 1t basée sur un thyristor de type vertical à deux bornes WO2020111521A1 (fr)

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KR1020180148145A KR102156685B1 (ko) 2018-11-27 2018-11-27 2단자 수직형 사이리스터 기반 1t 디램

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KR102579907B1 (ko) 2021-07-12 2023-09-18 한양대학교 산학협력단 전하 플라즈마에 기초하는 사이리스터 및 이를 포함하는 크로스-포인트 메모리 어레이

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JP2003224259A (ja) * 2002-01-29 2003-08-08 Shindengen Electric Mfg Co Ltd 二端子サイリスタ
KR20100130419A (ko) * 2009-06-03 2010-12-13 삼성전자주식회사 이종접합 다이오드와 그 제조방법 및 이종접합 다이오드를 포함하는 전자소자
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