WO2018174377A1 - Procédé de fabrication d'un transistor à effet de champ à effet tunnel et procédé d'amélioration du courant d'attaque d'un transistor à effet de champ à effet tunnel par traitement de pré-chauffage à ultra-faible puissance - Google Patents

Procédé de fabrication d'un transistor à effet de champ à effet tunnel et procédé d'amélioration du courant d'attaque d'un transistor à effet de champ à effet tunnel par traitement de pré-chauffage à ultra-faible puissance Download PDF

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WO2018174377A1
WO2018174377A1 PCT/KR2017/014455 KR2017014455W WO2018174377A1 WO 2018174377 A1 WO2018174377 A1 WO 2018174377A1 KR 2017014455 W KR2017014455 W KR 2017014455W WO 2018174377 A1 WO2018174377 A1 WO 2018174377A1
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Prior art keywords
effect transistor
tunneling field
field effect
substrate
current
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PCT/KR2017/014455
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English (en)
Korean (ko)
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최양규
박준영
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한국과학기술원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes

Definitions

  • the present invention relates to a method for manufacturing a tunneling field effect transistor and a method for improving a driving current of a tunneling field effect transistor through ultra low power electrothermal treatment. More particularly, the present invention relates to a method of improving driving current of a tunneling field effect transistor by using joule heat generated through currents applied to the source electrode and the drain electrode.
  • the tunneling field effect transistor is characterized in that its mechanism is different when compared with a conventional field effect transistor (MOSFET). While the driving principle of a conventional MOSFET transistor is a drift of a carrier by a channel and a drain voltage formed by a gate voltage, a tunneling field effect transistor is a tunneling phenomenon of a carrier based on an energy band characteristic by a gate voltage and a drain voltage. It works.
  • MOSFET field effect transistor
  • the conventional MOSFET transistor includes a pn junction having an npn type or a pnp type structure, whereas the tunneling field effect transistor includes a pin junction (p type / intrinsic / n type) structure. This is a major difference in terms of performance.
  • the tunneling field effect transistor has a characteristic of excellent sub-threshold slope (SS) characteristics when compared with a conventional MOSFET transistor.
  • the SS characteristic is one of the key indicators of the transistor's performance, indicating how good the transistor is as a switch. The lower the SS characteristic, the lower the standby power consumption.
  • Conventional MOSFET transistors have a physical limit of SS characteristics of 60 mV / dec.
  • Tunneling field-effect transistors may have SS characteristics lower than 60 mV / dec, which have been overcome by existing limitations.
  • a tunneling field effect transistor using a tunneling mechanism has a disadvantage of having a low driving current due to an operating mechanism based on a tunneling probability of a carrier.
  • the driving current is related to the operating speed of the transistor, and the higher the driving current, the faster the switching function. Therefore, the method of improving the drive current of a tunneling field effect transistor becomes a problem.
  • the present invention is directed to a method for improving the performance of a tunneling field effect transistor, and to provide a method of increasing the driving current of a tunneling field effect transistor through ultra low power electrothermal treatment.
  • a method of manufacturing a tunneling field effect transistor which includes: (a) patterning the substrate and performing an etching process Forming a channel, (b) forming an insulating film on the substrate on which the channel is formed and below the channel, (c) forming a gate insulating film on the surface of the channel (d) forming a gate electrode on the gate insulating film, and (e) forming a photoresist pattern on the substrate on which the gate electrode is formed, and performing an ion implantation process to form a source electrode or a drain electrode. It includes.
  • the substrate may include a substrate including a III-V material, a silicon germanium substrate including germanium and silicon, a germanium substrate, a substrate including an organic material, an insulating layer buried silicon substrate, an insulating layer buried strained silicon substrate, and an insulating layer buried And at least one of a germanium substrate, an insulating layer buried strained germanium substrate, an insulating layer buried silicon germanium substrate, and a heavily doped junctionless substrate.
  • the channel formed in step (a) may be a nano-wire channel or a nano-sheet channel.
  • the channel may include graphene, carbon nanotubes, or molybdenum sulfur dioxide (MoS 2).
  • the gate insulating film formed in step (c) may be a silicon oxide film or a high-k film.
  • the gate insulating film may be formed of silicon oxide, nitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zinc oxide, lanthanum oxide, and It may include at least one of hafnium silicon oxide.
  • the gate electrode formed in step (d) may include metal or polysilicon.
  • the gate electrode may include aluminum (Al), molybdenum (Mo), magnesium (Mg), chromium (Cr), palladium (Pd), gold (Au), platinum (Pt), titanium (Ti), and titanium nitride (TiN). ), And tantalum nitride (TaN).
  • a gate material may be deposited on the gate insulating layer, and the gate material may be patterned to form the gate electrode.
  • a first photoresist layer pattern is formed on the substrate, p + type impurity ions are implanted to form the source electrode, the first photoresist layer pattern is removed, and a second photoresist layer pattern is formed on the substrate.
  • the drain electrode may be formed by implanting n + type impurity ions.
  • a method of improving the driving current of a tunneling field effect transistor is a method of improving the driving current of a tunneling field effect transistor, which includes (a) turning off the gate electrode ( turn off), (b) applying a current between the source electrode and the drain electrode to perform an electrothermal treatment on the tunneling field effect transistor, and (c) ions implanted into the source electrode and the drain electrode Activating the same.
  • applying a current between the source electrode and the drain electrode may apply a pin diode reverse current between the source electrode and the drain electrode.
  • applying a current between the source electrode and the drain electrode may apply a pin diode forward current between the source electrode and the drain electrode.
  • the method may further include a simulation step of optimizing the amount of current required for the electrothermal treatment and the time for performing the electrothermal treatment in the step (b).
  • a method of improving a driving current of a tunneling field effect transistor includes: (a) turning off a gate electrode of the tunneling field effect transistor, (b) Performing an electrothermal treatment on the tunneling field effect transistor by applying a current between the source electrode and the drain electrode of the tunneling field effect transistor, and (c) activating ions implanted into the source electrode and the drain electrode.
  • the effect of improving the driving current is increased compared to forming the substrate of the tunneling field effect transistor by using a silicon germanium substrate or the like, and the cost of manufacturing the tunneling field effect transistor can be reduced.
  • the ultra-low power electrothermal treatment according to the present invention can efficiently achieve driving current characteristics without degrading the reliability of the tunneling field effect transistor.
  • FIG. 1A to 1D illustrate a manufacturing process of a tunneling field effect transistor based on nanowires and a structure of a transistor according to an embodiment of the present invention.
  • FIGS. 2A and 2B illustrate a method of increasing the driving current of a tunneling field effect transistor through ultra low power electrothermal treatment according to the present invention.
  • Figure 2c is an energy band diagram showing that the tunneling barrier of the pin diode is shortened after the ultra low power electrothermal treatment according to the present invention.
  • FIG. 2D is electrical measurement data confirming that the reverse current of the pin diode is improved due to the shortened tunneling barrier.
  • 3A is electrical measurement data verifying that driving current characteristics of a tunneling field effect transistor are improved through ultra low power electrothermal treatment according to the present invention.
  • 3B is electrical measurement data showing a drive current characteristic of a transistor according to a voltage applied for ultra low power electrothermal treatment according to the present invention.
  • the driving current characteristics may be improved through (1) a process during transistor manufacture or (2) a process after transistor manufacture.
  • the method of increasing the width of the channel is the simplest. However, as the area of the channel increases, the technique increases in contrast to the current trend of increasing not only the sub-threshold slope (SS) but also the degree of integration of semiconductor chips.
  • SS sub-threshold slope
  • tunneling field effect transistors having a plurality of vertically stacked channels have been studied. This is to keep the area of the channel as conventional, but to manufacture a plurality of channels are stacked in a direction perpendicular to the substrate, to have a more improved drive current characteristics in the same area.
  • this method is difficult to source-drain ion-implantation due to the distant separation between multiple channels, and the depth of focus of subsequent lithography processes due to the high gate height. There is a difficulty in the manufacturing process due to the reduction or the difficulty of the etching (etch) process.
  • electro-thermal treatment helps to improve the performance of the transistor.
  • the electrothermal treatment is effective for the recovery of the sub-threshold slope (SS), the driving current, and the gate insulating film, but the amount of power consumed to perform the electrothermal treatment is mW, which is practically difficult to apply to the tunneling field effect transistor. This exists. This is because the tunneling field effect transistor itself is a transistor manufactured and designed for low power consumption.
  • the present invention proposes a method capable of improving driving current characteristics of a tunneling field effect transistor through ultra low power electrothermal treatment.
  • FIG. 1A to 1D illustrate a manufacturing process of a tunneling field effect transistor based on nanowires and a structure of a transistor according to an embodiment of the present invention.
  • the substrate 100 may be an intrinsic substrate made of single crystal silicon.
  • a nanowire 300 that can be used as a channel 900 of a tunneling field effect transistor is manufactured through a patterning process and an etching process.
  • the etching process may be used a variety of methods such as dry etching, wet etching, plasma etching, it is possible to control the size of the cross-section of the nanowire 300 through the sacrificial oxidation (sacrificaial oxidation). Further, in the present invention, a process of curing the damage generated in the etching process may be further performed.
  • an insulating film 200 for shallow trenched isolation (STI) is deposited to prevent leakage current of the tunneling field effect transistor.
  • the gate insulating layer 800 is formed on the nanowire 300 exposed to the outside.
  • the gate insulating film 800 may be a silicon oxide film or a high-k film.
  • the gate electrode 600 is deposited on the gate insulating film 800 and a patterning process is performed.
  • a chemical mechanical planarization (CMP) process may be performed, and the gate electrode 600 may be formed of metal or polysilicon.
  • a photoresist layer 500 is patterned and formed on the front side of the substrate 100. This is for forming the source electrode 400.
  • the source electrode 400 is formed by implanting high concentration p + type impurity ions (Group III element).
  • the photoresist film 500 for forming the source electrode 400 is removed, and the photoresist film 500 is patterned again on the front side of the substrate 100 as shown in FIG. 1C. This is for forming the drain electrode 700. Then, a high concentration n + type impurity ion (group 5 element) is implanted to form a drain electrode 700.
  • the tunneling field effect transistor thus manufactured includes a pin diode in which the source electrode 400, the channel 900, and the drain electrode 700 have p-type, intrinsic, and n-type polarities, respectively.
  • the surface roughness of the nanowire shape is relieved through a hydrogen annealing process, whereby a tunneling field effect transistor shown in FIG. 1D is manufactured.
  • the hydrogen annealing process may optionally be applied according to the preceding process or preparation method.
  • FIG. 2A and 2B illustrate a method of increasing the driving current of a tunneling field effect transistor through ultra low power electrothermal treatment according to the present invention.
  • Figure 2c is an energy band diagram showing that the tunneling barrier of the pin diode is shortened after the ultra low power electrothermal treatment according to the present invention.
  • FIG. 2D is electrical measurement data confirming that the reverse current of the pin diode is improved due to the shortened tunneling barrier.
  • the method of increasing the driving current of the tunneling field effect transistor through the ultra low power electrothermal treatment by applying a reverse voltage to the pin diode existing between the source electrode 400 and the drain electrode 700, Generate a current.
  • the gate electrode 600 proceeds in an off state (OFF state).
  • the slope of the energy band diagram is more steeply formed as shown in FIG. 2C, so that the tunneling barrier is shortened. Due to this, more electrons can have the effect of tunneling.
  • the reverse current of the pin diode included in the tunneling field effect transistor further increases as shown in FIG. 2D.
  • 3A is electrical measurement data verifying that driving current characteristics of a tunneling field effect transistor are improved through ultra low power electrothermal treatment according to the present invention.
  • 3B is electrical measurement data showing a drive current characteristic of a transistor according to a voltage applied for ultra low power electrothermal treatment according to the present invention.
  • 4 is electrical measurement data demonstrating that the characteristics of the gate insulating film leakage current do not change significantly before and after the ultra low power electrothermal treatment according to the present invention.
  • FIG. 3A After the ultra low power electrothermal treatment described above, the electrical characteristics of the actually measured tunneling field effect transistor are shown in FIG. 3A. Through this, it was experimentally verified that the driving current of the tunneling field effect transistor can be improved up to 10 times after the ultra low power electrothermal treatment, and the reverse voltage of the pin diode applied to the ultra low power electrothermal treatment is shown in FIG. As it increases, it can be seen that the characteristics of the driving current of the transistor improve.
  • FIG. 4 is data obtained by measuring to confirm that the damage of the gate insulating film 800 and the reliability deterioration of the transistor do not occur due to the ultra low power electrothermal treatment according to the present invention.
  • the leakage current of the gate insulating film 800 is not significantly changed before and after the ultra low power electrothermal treatment according to the present invention. Through this, it can be verified that the ultra low power electrothermal treatment according to the present invention does not cause a problem in the performance degradation of the transistor.
  • the ultra-low power electrothermal treatment according to the present invention By using the ultra-low power electrothermal treatment according to the present invention, the effect of improving the driving current is increased compared to forming the substrate of the tunneling field effect transistor using a silicon germanium substrate or the like, and the cost of manufacturing the tunneling field effect transistor can be reduced. .
  • the ultra low power electrothermal treatment according to the present invention can efficiently achieve driving current characteristics without deteriorating the reliability of the tunneling field effect transistor.
  • the disadvantage of the low driving current caused by the driving principle of the conventional tunneling field effect transistor is improved by artificial heat treatment occurring between the source electrode and the drain electrode.
  • a pin diode reverse current is applied between the source electrode and the drain electrode, thereby generating high temperature heat locally at the source electrode and the drain electrode.
  • the power consumed for the electrothermal treatment is in microwatts ( ⁇ W) rather than nanowatts (nW).
  • the effect of improving the driving current is increased compared to forming the substrate of the tunneling field effect transistor by using a silicon germanium substrate or the like, and the cost of manufacturing the tunneling field effect transistor can be reduced.
  • the ultra-low power electrothermal treatment according to the present invention can efficiently achieve driving current characteristics without degrading the reliability of the tunneling field effect transistor.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un transistor à effet de champ à effet tunnel et un procédé pour améliorer un courant d'attaque du transistor à effet de champ à effet tunnel par un traitement de pré-chauffage à ultra-faible puissance. Le procédé d'amélioration d'un courant d'attaque d'un transistor à effet de champ à effet tunnel comprend les étapes consistant : (a) à éteindre une électrode de grille ; (b) à appliquer un courant entre une électrode de source et une électrode de drain de manière à effectuer un traitement de pré-chauffage sur le transistor à effet de champ à effet tunnel ; et (c) à activer des ions implantés dans l'électrode de source et l'électrode de drain.
PCT/KR2017/014455 2017-03-22 2017-12-11 Procédé de fabrication d'un transistor à effet de champ à effet tunnel et procédé d'amélioration du courant d'attaque d'un transistor à effet de champ à effet tunnel par traitement de pré-chauffage à ultra-faible puissance WO2018174377A1 (fr)

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KR10-2017-0035884 2017-03-22
KR1020170035884A KR101838910B1 (ko) 2017-03-22 2017-03-22 터널링 전계효과 트랜지스터의 제조 방법 및 초 저전력 전열처리를 통한 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법

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KR102095641B1 (ko) * 2018-07-18 2020-03-31 한국과학기술원 국부적 발열 현상을 이용하여 트랜지스터의 출력전류를 증가시키는 어닐링 방법
US11791342B2 (en) 2021-11-17 2023-10-17 International Business Machines Corporation Varactor integrated with complementary metal-oxide semiconductor devices
KR102527196B1 (ko) * 2021-11-29 2023-04-27 한양대학교 산학협력단 매몰 드레인 구조를 갖는 터널링 전계 효과 트랜지스터

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KR100668355B1 (ko) * 2006-02-16 2007-01-12 삼성전자주식회사 캐리어 트래핑 물질을 구비한 유니폴라 탄소나노튜브 및유니폴라 전계효과 트랜지스터
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KR20160064079A (ko) * 2013-10-03 2016-06-07 인텔 코포레이션 나노와이어 트랜지스터들을 위한 내부 스페이서들 및 그 제조 방법
KR20160131677A (ko) * 2015-05-08 2016-11-16 한국과학기술원 수직 적층형 나노와이어 형성 방법 및 수직 적층형 나노와이어를 포함하는 트랜지스터 제조 방법

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KR100668355B1 (ko) * 2006-02-16 2007-01-12 삼성전자주식회사 캐리어 트래핑 물질을 구비한 유니폴라 탄소나노튜브 및유니폴라 전계효과 트랜지스터
KR20090006511A (ko) * 2007-07-12 2009-01-15 엘지전자 주식회사 동력 전달 장치 및 냉장고용 제빙 어셈블리
KR20150054012A (ko) * 2012-12-21 2015-05-19 인텔 코포레이션 축소된 스케일의 공진 터널링 전계 효과 트랜지스터
KR20160064079A (ko) * 2013-10-03 2016-06-07 인텔 코포레이션 나노와이어 트랜지스터들을 위한 내부 스페이서들 및 그 제조 방법
KR20160131677A (ko) * 2015-05-08 2016-11-16 한국과학기술원 수직 적층형 나노와이어 형성 방법 및 수직 적층형 나노와이어를 포함하는 트랜지스터 제조 방법

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