WO2018174377A1 - Method for manufacturing tunneling field-effect transistor and method for enhancing driving current of tunneling field-effect transistor through ultra-low power pre-heat treatment - Google Patents

Method for manufacturing tunneling field-effect transistor and method for enhancing driving current of tunneling field-effect transistor through ultra-low power pre-heat treatment Download PDF

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WO2018174377A1
WO2018174377A1 PCT/KR2017/014455 KR2017014455W WO2018174377A1 WO 2018174377 A1 WO2018174377 A1 WO 2018174377A1 KR 2017014455 W KR2017014455 W KR 2017014455W WO 2018174377 A1 WO2018174377 A1 WO 2018174377A1
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effect transistor
tunneling field
field effect
substrate
current
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Korean (ko)
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최양규
박준영
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한국과학기술원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1606—Graphene
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes

Definitions

  • the present invention relates to a method for manufacturing a tunneling field effect transistor and a method for improving a driving current of a tunneling field effect transistor through ultra low power electrothermal treatment. More particularly, the present invention relates to a method of improving driving current of a tunneling field effect transistor by using joule heat generated through currents applied to the source electrode and the drain electrode.
  • the tunneling field effect transistor is characterized in that its mechanism is different when compared with a conventional field effect transistor (MOSFET). While the driving principle of a conventional MOSFET transistor is a drift of a carrier by a channel and a drain voltage formed by a gate voltage, a tunneling field effect transistor is a tunneling phenomenon of a carrier based on an energy band characteristic by a gate voltage and a drain voltage. It works.
  • MOSFET field effect transistor
  • the conventional MOSFET transistor includes a pn junction having an npn type or a pnp type structure, whereas the tunneling field effect transistor includes a pin junction (p type / intrinsic / n type) structure. This is a major difference in terms of performance.
  • the tunneling field effect transistor has a characteristic of excellent sub-threshold slope (SS) characteristics when compared with a conventional MOSFET transistor.
  • the SS characteristic is one of the key indicators of the transistor's performance, indicating how good the transistor is as a switch. The lower the SS characteristic, the lower the standby power consumption.
  • Conventional MOSFET transistors have a physical limit of SS characteristics of 60 mV / dec.
  • Tunneling field-effect transistors may have SS characteristics lower than 60 mV / dec, which have been overcome by existing limitations.
  • a tunneling field effect transistor using a tunneling mechanism has a disadvantage of having a low driving current due to an operating mechanism based on a tunneling probability of a carrier.
  • the driving current is related to the operating speed of the transistor, and the higher the driving current, the faster the switching function. Therefore, the method of improving the drive current of a tunneling field effect transistor becomes a problem.
  • the present invention is directed to a method for improving the performance of a tunneling field effect transistor, and to provide a method of increasing the driving current of a tunneling field effect transistor through ultra low power electrothermal treatment.
  • a method of manufacturing a tunneling field effect transistor which includes: (a) patterning the substrate and performing an etching process Forming a channel, (b) forming an insulating film on the substrate on which the channel is formed and below the channel, (c) forming a gate insulating film on the surface of the channel (d) forming a gate electrode on the gate insulating film, and (e) forming a photoresist pattern on the substrate on which the gate electrode is formed, and performing an ion implantation process to form a source electrode or a drain electrode. It includes.
  • the substrate may include a substrate including a III-V material, a silicon germanium substrate including germanium and silicon, a germanium substrate, a substrate including an organic material, an insulating layer buried silicon substrate, an insulating layer buried strained silicon substrate, and an insulating layer buried And at least one of a germanium substrate, an insulating layer buried strained germanium substrate, an insulating layer buried silicon germanium substrate, and a heavily doped junctionless substrate.
  • the channel formed in step (a) may be a nano-wire channel or a nano-sheet channel.
  • the channel may include graphene, carbon nanotubes, or molybdenum sulfur dioxide (MoS 2).
  • the gate insulating film formed in step (c) may be a silicon oxide film or a high-k film.
  • the gate insulating film may be formed of silicon oxide, nitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zinc oxide, lanthanum oxide, and It may include at least one of hafnium silicon oxide.
  • the gate electrode formed in step (d) may include metal or polysilicon.
  • the gate electrode may include aluminum (Al), molybdenum (Mo), magnesium (Mg), chromium (Cr), palladium (Pd), gold (Au), platinum (Pt), titanium (Ti), and titanium nitride (TiN). ), And tantalum nitride (TaN).
  • a gate material may be deposited on the gate insulating layer, and the gate material may be patterned to form the gate electrode.
  • a first photoresist layer pattern is formed on the substrate, p + type impurity ions are implanted to form the source electrode, the first photoresist layer pattern is removed, and a second photoresist layer pattern is formed on the substrate.
  • the drain electrode may be formed by implanting n + type impurity ions.
  • a method of improving the driving current of a tunneling field effect transistor is a method of improving the driving current of a tunneling field effect transistor, which includes (a) turning off the gate electrode ( turn off), (b) applying a current between the source electrode and the drain electrode to perform an electrothermal treatment on the tunneling field effect transistor, and (c) ions implanted into the source electrode and the drain electrode Activating the same.
  • applying a current between the source electrode and the drain electrode may apply a pin diode reverse current between the source electrode and the drain electrode.
  • applying a current between the source electrode and the drain electrode may apply a pin diode forward current between the source electrode and the drain electrode.
  • the method may further include a simulation step of optimizing the amount of current required for the electrothermal treatment and the time for performing the electrothermal treatment in the step (b).
  • a method of improving a driving current of a tunneling field effect transistor includes: (a) turning off a gate electrode of the tunneling field effect transistor, (b) Performing an electrothermal treatment on the tunneling field effect transistor by applying a current between the source electrode and the drain electrode of the tunneling field effect transistor, and (c) activating ions implanted into the source electrode and the drain electrode.
  • the effect of improving the driving current is increased compared to forming the substrate of the tunneling field effect transistor by using a silicon germanium substrate or the like, and the cost of manufacturing the tunneling field effect transistor can be reduced.
  • the ultra-low power electrothermal treatment according to the present invention can efficiently achieve driving current characteristics without degrading the reliability of the tunneling field effect transistor.
  • FIG. 1A to 1D illustrate a manufacturing process of a tunneling field effect transistor based on nanowires and a structure of a transistor according to an embodiment of the present invention.
  • FIGS. 2A and 2B illustrate a method of increasing the driving current of a tunneling field effect transistor through ultra low power electrothermal treatment according to the present invention.
  • Figure 2c is an energy band diagram showing that the tunneling barrier of the pin diode is shortened after the ultra low power electrothermal treatment according to the present invention.
  • FIG. 2D is electrical measurement data confirming that the reverse current of the pin diode is improved due to the shortened tunneling barrier.
  • 3A is electrical measurement data verifying that driving current characteristics of a tunneling field effect transistor are improved through ultra low power electrothermal treatment according to the present invention.
  • 3B is electrical measurement data showing a drive current characteristic of a transistor according to a voltage applied for ultra low power electrothermal treatment according to the present invention.
  • the driving current characteristics may be improved through (1) a process during transistor manufacture or (2) a process after transistor manufacture.
  • the method of increasing the width of the channel is the simplest. However, as the area of the channel increases, the technique increases in contrast to the current trend of increasing not only the sub-threshold slope (SS) but also the degree of integration of semiconductor chips.
  • SS sub-threshold slope
  • tunneling field effect transistors having a plurality of vertically stacked channels have been studied. This is to keep the area of the channel as conventional, but to manufacture a plurality of channels are stacked in a direction perpendicular to the substrate, to have a more improved drive current characteristics in the same area.
  • this method is difficult to source-drain ion-implantation due to the distant separation between multiple channels, and the depth of focus of subsequent lithography processes due to the high gate height. There is a difficulty in the manufacturing process due to the reduction or the difficulty of the etching (etch) process.
  • electro-thermal treatment helps to improve the performance of the transistor.
  • the electrothermal treatment is effective for the recovery of the sub-threshold slope (SS), the driving current, and the gate insulating film, but the amount of power consumed to perform the electrothermal treatment is mW, which is practically difficult to apply to the tunneling field effect transistor. This exists. This is because the tunneling field effect transistor itself is a transistor manufactured and designed for low power consumption.
  • the present invention proposes a method capable of improving driving current characteristics of a tunneling field effect transistor through ultra low power electrothermal treatment.
  • FIG. 1A to 1D illustrate a manufacturing process of a tunneling field effect transistor based on nanowires and a structure of a transistor according to an embodiment of the present invention.
  • the substrate 100 may be an intrinsic substrate made of single crystal silicon.
  • a nanowire 300 that can be used as a channel 900 of a tunneling field effect transistor is manufactured through a patterning process and an etching process.
  • the etching process may be used a variety of methods such as dry etching, wet etching, plasma etching, it is possible to control the size of the cross-section of the nanowire 300 through the sacrificial oxidation (sacrificaial oxidation). Further, in the present invention, a process of curing the damage generated in the etching process may be further performed.
  • an insulating film 200 for shallow trenched isolation (STI) is deposited to prevent leakage current of the tunneling field effect transistor.
  • the gate insulating layer 800 is formed on the nanowire 300 exposed to the outside.
  • the gate insulating film 800 may be a silicon oxide film or a high-k film.
  • the gate electrode 600 is deposited on the gate insulating film 800 and a patterning process is performed.
  • a chemical mechanical planarization (CMP) process may be performed, and the gate electrode 600 may be formed of metal or polysilicon.
  • a photoresist layer 500 is patterned and formed on the front side of the substrate 100. This is for forming the source electrode 400.
  • the source electrode 400 is formed by implanting high concentration p + type impurity ions (Group III element).
  • the photoresist film 500 for forming the source electrode 400 is removed, and the photoresist film 500 is patterned again on the front side of the substrate 100 as shown in FIG. 1C. This is for forming the drain electrode 700. Then, a high concentration n + type impurity ion (group 5 element) is implanted to form a drain electrode 700.
  • the tunneling field effect transistor thus manufactured includes a pin diode in which the source electrode 400, the channel 900, and the drain electrode 700 have p-type, intrinsic, and n-type polarities, respectively.
  • the surface roughness of the nanowire shape is relieved through a hydrogen annealing process, whereby a tunneling field effect transistor shown in FIG. 1D is manufactured.
  • the hydrogen annealing process may optionally be applied according to the preceding process or preparation method.
  • FIG. 2A and 2B illustrate a method of increasing the driving current of a tunneling field effect transistor through ultra low power electrothermal treatment according to the present invention.
  • Figure 2c is an energy band diagram showing that the tunneling barrier of the pin diode is shortened after the ultra low power electrothermal treatment according to the present invention.
  • FIG. 2D is electrical measurement data confirming that the reverse current of the pin diode is improved due to the shortened tunneling barrier.
  • the method of increasing the driving current of the tunneling field effect transistor through the ultra low power electrothermal treatment by applying a reverse voltage to the pin diode existing between the source electrode 400 and the drain electrode 700, Generate a current.
  • the gate electrode 600 proceeds in an off state (OFF state).
  • the slope of the energy band diagram is more steeply formed as shown in FIG. 2C, so that the tunneling barrier is shortened. Due to this, more electrons can have the effect of tunneling.
  • the reverse current of the pin diode included in the tunneling field effect transistor further increases as shown in FIG. 2D.
  • 3A is electrical measurement data verifying that driving current characteristics of a tunneling field effect transistor are improved through ultra low power electrothermal treatment according to the present invention.
  • 3B is electrical measurement data showing a drive current characteristic of a transistor according to a voltage applied for ultra low power electrothermal treatment according to the present invention.
  • 4 is electrical measurement data demonstrating that the characteristics of the gate insulating film leakage current do not change significantly before and after the ultra low power electrothermal treatment according to the present invention.
  • FIG. 3A After the ultra low power electrothermal treatment described above, the electrical characteristics of the actually measured tunneling field effect transistor are shown in FIG. 3A. Through this, it was experimentally verified that the driving current of the tunneling field effect transistor can be improved up to 10 times after the ultra low power electrothermal treatment, and the reverse voltage of the pin diode applied to the ultra low power electrothermal treatment is shown in FIG. As it increases, it can be seen that the characteristics of the driving current of the transistor improve.
  • FIG. 4 is data obtained by measuring to confirm that the damage of the gate insulating film 800 and the reliability deterioration of the transistor do not occur due to the ultra low power electrothermal treatment according to the present invention.
  • the leakage current of the gate insulating film 800 is not significantly changed before and after the ultra low power electrothermal treatment according to the present invention. Through this, it can be verified that the ultra low power electrothermal treatment according to the present invention does not cause a problem in the performance degradation of the transistor.
  • the ultra-low power electrothermal treatment according to the present invention By using the ultra-low power electrothermal treatment according to the present invention, the effect of improving the driving current is increased compared to forming the substrate of the tunneling field effect transistor using a silicon germanium substrate or the like, and the cost of manufacturing the tunneling field effect transistor can be reduced. .
  • the ultra low power electrothermal treatment according to the present invention can efficiently achieve driving current characteristics without deteriorating the reliability of the tunneling field effect transistor.
  • the disadvantage of the low driving current caused by the driving principle of the conventional tunneling field effect transistor is improved by artificial heat treatment occurring between the source electrode and the drain electrode.
  • a pin diode reverse current is applied between the source electrode and the drain electrode, thereby generating high temperature heat locally at the source electrode and the drain electrode.
  • the power consumed for the electrothermal treatment is in microwatts ( ⁇ W) rather than nanowatts (nW).
  • the effect of improving the driving current is increased compared to forming the substrate of the tunneling field effect transistor by using a silicon germanium substrate or the like, and the cost of manufacturing the tunneling field effect transistor can be reduced.
  • the ultra-low power electrothermal treatment according to the present invention can efficiently achieve driving current characteristics without degrading the reliability of the tunneling field effect transistor.

Abstract

Provided are a method for manufacturing a tunneling field-effect transistor and a method for improving a driving current of the tunneling field-effect transistor through an ultra-low power pre-heat treatment. The method for enhancing a driving current of a tunneling field-effect transistor comprises the steps of: (a) turning off a gate electrode; (b) applying a current between a source electrode and a drain electrode so as to perform a pre-heat treatment on the tunneling field-effect transistor; and (c) activating ions implanted in the source electrode and the drain electrode.

Description

터널링 전계효과 트랜지스터의 제조 방법 및 초 저전력 전열처리를 통한 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법Method for manufacturing tunneling field effect transistor and improving driving current of tunneling field effect transistor through ultra low power electrothermal treatment
본 발명은 터널링 전계효과 트랜지스터의 제조 방법 및 초 저전력 전열처리를 통한 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법에 관한 것이다. 보다 상세하게는 소스 전극과 드레인 전극에 인가된 전류를 통해 발생하는 줄열(joule heat)을 이용하여, 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법에 관한 것이다.The present invention relates to a method for manufacturing a tunneling field effect transistor and a method for improving a driving current of a tunneling field effect transistor through ultra low power electrothermal treatment. More particularly, the present invention relates to a method of improving driving current of a tunneling field effect transistor by using joule heat generated through currents applied to the source electrode and the drain electrode.
터널링 전계효과 트랜지스터는 기존의 전계효과 트랜지스터(MOSFET) 와 비교했을 때, 그 메커니즘이 상이한 것을 특징으로 한다. 기존의 MOSFET 트랜지스터의 구동원리가 게이트 전압에 의해 형성된 채널과 드레인 전압에 의한 캐리어의 드리프트 형식으로 이루어지는 반면, 터널링 전계효과 트랜지스터는 게이트 전압과 드레인 전압에 의한 에너지 밴드 특성을 기반으로 한 캐리어의 터널링 현상으로 동작한다. The tunneling field effect transistor is characterized in that its mechanism is different when compared with a conventional field effect transistor (MOSFET). While the driving principle of a conventional MOSFET transistor is a drift of a carrier by a channel and a drain voltage formed by a gate voltage, a tunneling field effect transistor is a tunneling phenomenon of a carrier based on an energy band characteristic by a gate voltage and a drain voltage. It works.
이러한 구동원리의 차이로 인하여, 기존의 MOSFET 트랜지스터가 npn 타입 또는 pnp 타입 구조를 갖는 pn 접합을 포함하는데 반해, 터널링 전계효과 트랜지스터는 pin 접합(p타입/intrinsic/n타입) 형태를 포함하는 것이 구조적인 측면에서의 주요한 차이이다.Due to the difference in driving principle, the conventional MOSFET transistor includes a pn junction having an npn type or a pnp type structure, whereas the tunneling field effect transistor includes a pin junction (p type / intrinsic / n type) structure. This is a major difference in terms of performance.
이와 같은 구조 및 구동원리의 차이로 인하여, 터널링 전계효과 트랜지스터는 기존의 MOSFET 트랜지스터와 비교해 볼 때, sub-threshold slope(SS) 특성이 매우 뛰어나다는 특성을 갖는다. SS 특성은 트랜지스터의 성능을 평가하는 주요 지표 중 하나로써 트랜지스터가 얼마나 스위치로써의 역할이 우수한지를 알려주며, SS 특성 값이 낮을 수록 더 낮은 대기전력을 소모한다. 기존의 MOSFET 트랜지스터는 60 mV/dec 라는 SS 특성에 있어서의 물리적 한계가 있다. 하지만 터널링 전계효과 트랜지스터는 기존의 한계를 벗어나 60 mV/dec 보다 더 낮은 SS 특성 값을 가질 수 있으며, 관련 내용은 이미 여러 연구를 통해 검증되었다. Due to such a difference in structure and driving principle, the tunneling field effect transistor has a characteristic of excellent sub-threshold slope (SS) characteristics when compared with a conventional MOSFET transistor. The SS characteristic is one of the key indicators of the transistor's performance, indicating how good the transistor is as a switch. The lower the SS characteristic, the lower the standby power consumption. Conventional MOSFET transistors have a physical limit of SS characteristics of 60 mV / dec. Tunneling field-effect transistors, however, may have SS characteristics lower than 60 mV / dec, which have been overcome by existing limitations.
하지만, 드리프트 메커니즘을 사용하는 MOSFET과 달리, 터널링 메커니즘을 사용하는 터널링 전계효과 트랜지스터는 캐리어의 터널링 확률에 근거한 동작 메커니즘으로 인하여 낮은 구동전류를 가진다는 단점을 갖고 있다. 구동전류는 트랜지스터의 동작 속도와 연관이 있으며, 높은 구동전류를 가질수록 빠른 스위치 기능을 수행할 수 있다. 따라서, 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법이 문제가 된다. However, unlike a MOSFET using a drift mechanism, a tunneling field effect transistor using a tunneling mechanism has a disadvantage of having a low driving current due to an operating mechanism based on a tunneling probability of a carrier. The driving current is related to the operating speed of the transistor, and the higher the driving current, the faster the switching function. Therefore, the method of improving the drive current of a tunneling field effect transistor becomes a problem.
본 발명이 해결하고자 하는 기술적 과제는, 터널링 전계효과 트랜지스터의 성능을 향상시킬 수 있는 방법에 관한 것으로, 초 저전력 전열처리를 통해 터널링 전계효과 트랜지스터의 구동전류를 증가시키는 방법을 제공하는 것이다. The present invention is directed to a method for improving the performance of a tunneling field effect transistor, and to provide a method of increasing the driving current of a tunneling field effect transistor through ultra low power electrothermal treatment.
다만, 본 발명이 해결하고자 하는 기술적 과제는 상기 과제로 한정되는 것이 아니며, 본 발명의 기술적 사상 및 영역으로부터 벗어나지 않는 범위에서 다양하게 확장될 수 있다. However, the technical problem to be solved by the present invention is not limited to the above problem, and can be variously expanded in a range not departing from the technical spirit and scope of the present invention.
상기 과제를 해결하기 위한 본 발명의 일 실시예에 따른 터널링 전계효과 트랜지스터의 제조 방법은, 기판 상에 형성된 터널링 전계효과 트랜지스터의 제조 방법으로서, (a) 상기 기판을 패터닝하고, 식각 공정을 수행하여 채널을 형성하는 단계, (b) 상기 채널이 형성된 상기 기판 상(on) 및 상기 채널의 하부(below)에, 절연막을 형성하는 단계, (c) 상기 채널의 표면 상에 게이트 절연막을 형성하는 단계, (d) 상기 게이트 절연막 상에 게이트 전극을 형성하는 단계, 및 (e) 상기 게이트 전극이 형성된 상기 기판 상에 감광막 패턴을 형성하고, 이온주입 공정을 수행하여 소스 전극 또는 드레인 전극을 형성하는 단계를 포함한다. According to an aspect of the present invention, there is provided a method of manufacturing a tunneling field effect transistor, which includes: (a) patterning the substrate and performing an etching process Forming a channel, (b) forming an insulating film on the substrate on which the channel is formed and below the channel, (c) forming a gate insulating film on the surface of the channel (d) forming a gate electrode on the gate insulating film, and (e) forming a photoresist pattern on the substrate on which the gate electrode is formed, and performing an ion implantation process to form a source electrode or a drain electrode. It includes.
상기 기판은, Ⅲ-V족 물질을 포함하는 기판, 게르마늄과 실리콘을 포함하는 실리콘 게르마늄 기판, 게르마늄 기판, 유기물을 포함하는 기판, 절연층 매몰 실리콘 기판, 절연층 매몰 스트레인드 실리콘 기판, 절연층 매몰 게르마늄 기판, 절연층 매몰 스트레인드 게르마늄 기판, 절연층 매몰 실리콘 게르마늄 기판, 및 고농도로 도핑된 무접합(junctionless) 기판 중 적어도 하나를 포함할 수 있다. The substrate may include a substrate including a III-V material, a silicon germanium substrate including germanium and silicon, a germanium substrate, a substrate including an organic material, an insulating layer buried silicon substrate, an insulating layer buried strained silicon substrate, and an insulating layer buried And at least one of a germanium substrate, an insulating layer buried strained germanium substrate, an insulating layer buried silicon germanium substrate, and a heavily doped junctionless substrate.
상기 (a) 단계에서 형성되는 상기 채널은 나노와이어(nano-wire) 채널 또는 나노면(nano-sheet) 채널일 수 있다. The channel formed in step (a) may be a nano-wire channel or a nano-sheet channel.
상기 채널은 그래핀, 탄소나노튜브, 또는 이산화황몰리브덴(MoS2)을 포함할 수 있다. The channel may include graphene, carbon nanotubes, or molybdenum sulfur dioxide (MoS 2).
상기 (c) 단계에서 형성되는 상기 게이트 절연막은, 실리콘 산화막 또는 고유전막(High-k)일 수 있다. The gate insulating film formed in step (c) may be a silicon oxide film or a high-k film.
상기 게이트 절연막은 산화 실리콘(silicon oxide), 질화막, 산화 알루미늄(aluminum oxide), 산화 하프늄(hafnium oxide), 산화질화 하프늄(hafnium oxynitride), 산화 아연(zinc oxide), 란타늄 옥사이드(lanthanum oxide), 및 하프늄 실리콘 옥사이드(hafnium silicon oxide) 중 적어도 하나를 포함할 수 있다. The gate insulating film may be formed of silicon oxide, nitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zinc oxide, lanthanum oxide, and It may include at least one of hafnium silicon oxide.
상기 (d) 단계에서 형성되는 상기 게이트 전극은, 금속 또는 폴리 실리콘을 포함할 수 있다. The gate electrode formed in step (d) may include metal or polysilicon.
상기 게이트 전극은, 알루미늄(Al), 몰리브덴(Mo), 마그네슘(Mg), 크롬(Cr), 팔라듐(Pd), 금(Au), 백금(Pt), 타이타늄(Ti), 타이타늄나이트라이드(TiN), 및 탄탈럼나이트라이드(TaN) 중 적어도 하나를 포함할 수 있다. The gate electrode may include aluminum (Al), molybdenum (Mo), magnesium (Mg), chromium (Cr), palladium (Pd), gold (Au), platinum (Pt), titanium (Ti), and titanium nitride (TiN). ), And tantalum nitride (TaN).
상기 (d) 단계는, 상기 게이트 절연막 상에 게이트 물질을 증착하고, 상기 게이트 물질을 패터닝하여 상기 게이트 전극을 형성할 수 있다. In the step (d), a gate material may be deposited on the gate insulating layer, and the gate material may be patterned to form the gate electrode.
상기 (e) 단계는, 상기 기판 상에 제1 감광막 패턴을 형성하고, p+형 불순물 이온을 주입하여 상기 소스 전극을 형성하고, 상기 제1 감광막 패턴을 제거한 후 상기 기판 상에 제2 감광막 패턴을 형성하고, n+형 불순물 이온을 주입하여 상기 드레인 전극을 형성할 수 있다. In the step (e), a first photoresist layer pattern is formed on the substrate, p + type impurity ions are implanted to form the source electrode, the first photoresist layer pattern is removed, and a second photoresist layer pattern is formed on the substrate. The drain electrode may be formed by implanting n + type impurity ions.
상기 과제를 해결하기 위한 본 발명의 일 실시예에 따른 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법은, 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법으로서, (a) 상기 게이트 전극을 턴오프(turn off) 시키는 단계, (b) 상기 소스 전극과 상기 드레인 전극 사이에 전류를 인가하여 상기 터널링 전계효과 트랜지스터에 전열처리를 수행하는 단계, 및 (c) 상기 소스 전극과 상기 드레인 전극에 주입된 이온을 활성화 시키는 단계를 포함한다. In order to solve the above problems, a method of improving the driving current of a tunneling field effect transistor according to an embodiment of the present invention is a method of improving the driving current of a tunneling field effect transistor, which includes (a) turning off the gate electrode ( turn off), (b) applying a current between the source electrode and the drain electrode to perform an electrothermal treatment on the tunneling field effect transistor, and (c) ions implanted into the source electrode and the drain electrode Activating the same.
상기 (b) 단계에서 상기 소스 전극과 상기 드레인 전극 사이에 전류를 인가하는 것은, 상기 소스 전극과 상기 드레인 전극 사이에 pin 다이오드 역방향 전류를 인가할 수 있다. In the step (b), applying a current between the source electrode and the drain electrode may apply a pin diode reverse current between the source electrode and the drain electrode.
상기 (b) 단계에서 상기 소스 전극과 상기 드레인 전극 사이에 전류를 인가하는 것은, 상기 소스 전극과 상기 드레인 전극 사이에 pin 다이오드 정방향 전류를 인가할 수 있다. In the step (b), applying a current between the source electrode and the drain electrode may apply a pin diode forward current between the source electrode and the drain electrode.
상기 (b) 단계에서의 상기 전열처리를 위해 필요한 상기 전류의 양 및 전열처리를 수행하는 시간을 최적화하는 시뮬레이션 단계를 더 포함할 수 있다. The method may further include a simulation step of optimizing the amount of current required for the electrothermal treatment and the time for performing the electrothermal treatment in the step (b).
상기 과제를 해결하기 위한 본 발명의 일 실시예에 따른 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법은, (a) 터널링 전계효과 트랜지스터의 게이트 전극을 턴오프(turn off) 시키는 단계, (b) 상기 터널링 전계효과 트랜지스터의 소스 전극 및 드레인 전극 사이에 전류를 인가하여 상기 터널링 전계효과 트랜지스터에 전열처리를 수행하는 단계, 및 (c) 상기 소스 전극과 상기 드레인 전극에 주입된 이온을 활성화 시키는 단계를 포함한다. In order to solve the above problems, a method of improving a driving current of a tunneling field effect transistor according to an embodiment of the present invention includes: (a) turning off a gate electrode of the tunneling field effect transistor, (b) Performing an electrothermal treatment on the tunneling field effect transistor by applying a current between the source electrode and the drain electrode of the tunneling field effect transistor, and (c) activating ions implanted into the source electrode and the drain electrode. Include.
본 발명의 기타 구체적인 사항들은 상세한 설명 및 도면들에 포함되어 있다.Other specific details of the invention are included in the detailed description and drawings.
본 발명에 따르면, 구동전류가 향상된 터널링 전계효과 트랜지스터를 구현 및 제조할 수 있다.According to the present invention, it is possible to implement and manufacture a tunneling field effect transistor with improved driving current.
또한, 본 발명에 따르면, 터널링 전계효과 트랜지스터의 기판을 실리콘 게르마늄 기판 등으로 형성하는 것보다 구동전류 향상의 효과가 증대되며, 터널링 전계효과 트랜지스터를 제조하는 비용을 감소시킬 수 있다. In addition, according to the present invention, the effect of improving the driving current is increased compared to forming the substrate of the tunneling field effect transistor by using a silicon germanium substrate or the like, and the cost of manufacturing the tunneling field effect transistor can be reduced.
특히, 본 발명에 따른 초 저전력 전열처리는 터널링 전계효과 트랜지스터의 신뢰성을 열화시키지 않고, 효율적으로 구동전류 특성 개선을 달성할 수 있다.In particular, the ultra-low power electrothermal treatment according to the present invention can efficiently achieve driving current characteristics without degrading the reliability of the tunneling field effect transistor.
다만, 본 발명의 효과는 상기 효과들로 한정되는 것이 아니며, 본 발명의 기술적 사상 및 영역으로부터 벗어나지 않는 범위에서 다양하게 확장될 수 있다. However, the effects of the present invention are not limited to the above effects, and may be variously expanded within the scope without departing from the spirit and scope of the present invention.
도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 나노와이어를 기반으로 한 터널링 전계효과 트랜지스터의 제조 과정 및 트랜지스터의 구조를 도시한다.1A to 1D illustrate a manufacturing process of a tunneling field effect transistor based on nanowires and a structure of a transistor according to an embodiment of the present invention.
도 2a 및 도 2b는 본 발명에 따른 초 저전력 전열처리를 통한 터널링 전계효과 트랜지스터의 구동전류를 증가시키는 방법을 나타내는 도면이다. 2A and 2B illustrate a method of increasing the driving current of a tunneling field effect transistor through ultra low power electrothermal treatment according to the present invention.
도 2c는 본 발명에 따른 초 저전력 전열처리 후 pin 다이오드의 터널링 배리어가 짧아진 것을 보여주는 에너지 밴드 다이어그램이다. Figure 2c is an energy band diagram showing that the tunneling barrier of the pin diode is shortened after the ultra low power electrothermal treatment according to the present invention.
도 2d는 짧아진 터널링 배리어로 인하여 pin 다이오드의 역방향 전류가 향상된 것을 확인할 수 있는 전기적 측정 데이터이다.FIG. 2D is electrical measurement data confirming that the reverse current of the pin diode is improved due to the shortened tunneling barrier.
도 3a는 본 발명에 따른 초 저전력 전열처리를 통해 터널링 전계효과 트랜지스터의 구동전류 특성이 향상되는 것을 검증한 전기적 측정 데이터이다. 3A is electrical measurement data verifying that driving current characteristics of a tunneling field effect transistor are improved through ultra low power electrothermal treatment according to the present invention.
도 3b는 본 발명에 따른 초 저전력 전열처리를 위해 인가되는 전압에 따라 트랜지스터의 구동전류 특성을 나타내는 전기적 측정 데이터이다. 3B is electrical measurement data showing a drive current characteristic of a transistor according to a voltage applied for ultra low power electrothermal treatment according to the present invention.
도 4는 본 발명에 따른 초 저전력 전열처리 전후에 게이트 절연막 누설전류가 특성이 크게 변하지 않음을 증명하는 전기적 측정 데이터이다.4 is electrical measurement data demonstrating that the characteristics of the gate insulating film leakage current do not change significantly before and after the ultra low power electrothermal treatment according to the present invention.
본 발명의 이점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해질 것이다. 그러나, 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명은 청구항의 범주에 의해 정의될 뿐이다. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, only the present embodiments to make the disclosure of the present invention complete, and common knowledge in the art to which the present invention pertains. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims.
후술하는 본 발명에 대한 상세한 설명은, 본 발명이 실시될 수 있는 특정 실시예를 예시로서 도시하는 첨부 도면을 참조한다. 이들 실시예는 당업자가 본 발명을 실시할 수 있기에 충분하도록 상세히 설명된다. 본 발명의 다양한 실시예는 서로 다르지만 상호 배타적일 필요는 없음이 이해되어야 한다. 예를 들어, 여기에 기재되어 있는 특정 형상, 구조 및 특성은 일 실시예에 관련하여 본 발명의 기술적 사상 및 범위를 벗어나지 않으면서 다른 실시예로 구현될 수 있다. 또한, 각각의 개시된 실시예 내의 개별 구성요소의 위치 또는 배치는 본 발명의 기술적 사상 및 범위를 벗어나지 않으면서 변경될 수 있음이 이해되어야 한다. 따라서, 후술하는 상세한 설명은 한정적인 의미로서 취하려는 것이 아니며, 본 발명의 범위는, 적절하게 설명된다면, 그 청구항들이 주장하는 것과 균등한 모든 범위와 더불어 첨부된 청구항에 의해서만 한정된다. DETAILED DESCRIPTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention with respect to one embodiment. In addition, it is to be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
본 명세서에서 사용된 용어는 실시예들을 설명하기 위한 것이며, 본 발명을 제한하고자 하는 것은 아니다. 본 명세서에서, 단수형은 문구에서 특별히 언급하지 않는 한 복수형도 포함한다. 명세서에서 사용되는 "포함한다(comprises)" 및/또는 "포함하는(comprising)"은 언급된 구성요소, 단계, 동작 및/또는 소자는 하나 이상의 다른 구성요소, 단계, 동작 및/또는 소자의 존재 또는 추가를 배제하지 않는다.The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.
다른 정의가 없다면, 본 명세서에서 사용되는 모든 용어(기술 및 과학적 용어를 포함)는 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 공통적으로 이해될 수 있는 의미로 사용될 수 있을 것이다. 또한, 일반적으로 사용되는 사전에 정의되어 있는 용어들은 명백하게 특별히 정의되어 있지 않는 한 이상적으로 또는 과도하게 해석되지 않는다.Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, terms that are defined in a commonly used dictionary are not ideally or excessively interpreted unless they are specifically defined clearly.
이하, 첨부한 도면들을 참조하여, 본 발명의 바람직한 실시예들을 보다 상세하게 설명하고자 한다. 도면 상의 동일한 구성요소에 대해서는 동일한 참조 부호를 사용하고 동일한 구성요소에 대해서 중복된 설명은 생략한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.
터널링 전계효과 트랜지스터의 낮은 구동전류 특성을 개선하기 위해서는, (1) 트랜지스터 제조 중 공정 또는 (2) 트랜지스터 제조 후 공정을 통해 구동전류 특성을 개선할 수 있다.In order to improve the low driving current characteristics of the tunneling field effect transistor, the driving current characteristics may be improved through (1) a process during transistor manufacture or (2) a process after transistor manufacture.
먼저, (1) 제조 중 공정의 관점에서는, 채널의 면적(width)을 증가시키는 방법이 가장 간단하다. 하지만, 채널의 면적이 커지면 SS(sub-threshold slope)가 증가할 뿐만 아니라, 반도체 칩의 집적도가 증가하는 현재의 추세와 비교해 보았을 때, 이 기술은 그에 역행하는 방법이 된다. First, (1) From the viewpoint of the manufacturing process, the method of increasing the width of the channel is the simplest. However, as the area of the channel increases, the technique increases in contrast to the current trend of increasing not only the sub-threshold slope (SS) but also the degree of integration of semiconductor chips.
이 점을 개선하고자, 다수의 수직 적층형 채널을 가지는 터널링 전계효과 트랜지스터가 연구되고 있다. 이는 채널의 면적은 기존과 같이 작게 유지시키되, 다수의 채널을 기판에 수직인 방향으로 적층되도록 제조하여, 동일 면적에서 더 향상된 구동전류 특성을 갖도록 한 것이다. 하지만, 이 방법은 다수의 채널간의 먼 이격으로 인해 소스와 드레인의 이온 주입공정(ion-implantation)의 어려움, 높은 게이트 높이(height)로 인해 후속의 리소그래피(lithography) 공정의 DOF(depth of focus)의 감소 또는 식각(etch) 공정의 어려움 등이 존재하여 제조 공정상의 어려움이 있다. To improve this point, tunneling field effect transistors having a plurality of vertically stacked channels have been studied. This is to keep the area of the channel as conventional, but to manufacture a plurality of channels are stacked in a direction perpendicular to the substrate, to have a more improved drive current characteristics in the same area. However, this method is difficult to source-drain ion-implantation due to the distant separation between multiple channels, and the depth of focus of subsequent lithography processes due to the high gate height. There is a difficulty in the manufacturing process due to the reduction or the difficulty of the etching (etch) process.
그리고, (2) 제조 후 공정의 관점에서는, 전열처리(electro-thermal treatment)가 트랜지스터의 성능 개선에 도움이 된다. 구체적으로 SS(sub-threshold slope), 구동전류, 게이트 절연막의 복구에 전열처리가 효과적이지만, 전열처리를 수행하기 위해 소모되는 전력의 크기가 mW 단위로서, 터널링 전계효과 트랜지스터에 적용하기에 현실적으로 어려움이 존재한다. 왜냐하면, 터널링 전계효과 트랜지스터 자체가 저전력 소모를 위해 제조 및 고안된 트랜지스터이기 때문이다.(2) In view of the post-manufacturing process, electro-thermal treatment helps to improve the performance of the transistor. In particular, the electrothermal treatment is effective for the recovery of the sub-threshold slope (SS), the driving current, and the gate insulating film, but the amount of power consumed to perform the electrothermal treatment is mW, which is practically difficult to apply to the tunneling field effect transistor. This exists. This is because the tunneling field effect transistor itself is a transistor manufactured and designed for low power consumption.
본 발명에서는, 전열처리 공정에서의 상기의 단점을 해결하기 위해, 초 저전력 전열처리를 통해 터널링 전계효과 트랜지스터의 구동전류 특성을 향상시킬 수 있는 방법을 제안한다.In order to solve the above disadvantages in the electrothermal treatment process, the present invention proposes a method capable of improving driving current characteristics of a tunneling field effect transistor through ultra low power electrothermal treatment.
도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 나노와이어를 기반으로 한 터널링 전계효과 트랜지스터의 제조 과정 및 트랜지스터의 구조를 도시한다. 1A to 1D illustrate a manufacturing process of a tunneling field effect transistor based on nanowires and a structure of a transistor according to an embodiment of the present invention.
도 1a 내지 도 1d를 참조하면, 기판(substrate)(100)이 제공된다. 기판(100)은 단결정 실리콘으로 제조된 고유의(intrinsic) 기판이 사용될 수 있다. 1A-1D, a substrate 100 is provided. The substrate 100 may be an intrinsic substrate made of single crystal silicon.
제공된 기판(100)에 대해, 패터닝 공정과 식각 공정을 통해 터널링 전계효과 트랜지스터의 채널(900)로 이용될 수 있는 나노와이어(300)를 제조한다. 이 때, 식각 공정은 건식 식각, 습식 식각, 플라즈마 식각 등 다양한 방법이 사용될 수 있으며, 희생 산화(sacrificaial oxidation)를 통해 나노와이어(300)의 단면의 크기를 제어할 수 있다. 그리고, 본 발명에서는 식각 공정에서 발생한 손상(damage)을 치료(curing)하는 공정이 더 수행될 수 있다. For the provided substrate 100, a nanowire 300 that can be used as a channel 900 of a tunneling field effect transistor is manufactured through a patterning process and an etching process. At this time, the etching process may be used a variety of methods such as dry etching, wet etching, plasma etching, it is possible to control the size of the cross-section of the nanowire 300 through the sacrificial oxidation (sacrificaial oxidation). Further, in the present invention, a process of curing the damage generated in the etching process may be further performed.
나노와이어(300)가 제조된 후, 터널링 전계효과 트랜지스터의 누설전류를 방지하기 위한 STI(Shallow Trenched Isolation)용 절연막(200)을 증착한다. After the nanowire 300 is manufactured, an insulating film 200 for shallow trenched isolation (STI) is deposited to prevent leakage current of the tunneling field effect transistor.
이어서, 외부로 노출된 나노와이어(300) 상에 게이트 절연막(800)을 형성한다. 여기서, 게이트 절연막(800)은 실리콘 산화막 또는 고유전막(High-k)일 수 있다. Subsequently, the gate insulating layer 800 is formed on the nanowire 300 exposed to the outside. The gate insulating film 800 may be a silicon oxide film or a high-k film.
이어서, 게이트 절연막(800) 상에 게이트 전극(600)을 증착하고 패터닝 공정을 수행한다. 이 때, 화학적-기계적 연마(Chemical Mechanical Planarization; CMP) 공정이 수행될 수 있으며, 게이트 전극(600)은 금속 또는 폴리 실리콘으로 형성될 수 있다. Subsequently, the gate electrode 600 is deposited on the gate insulating film 800 and a patterning process is performed. In this case, a chemical mechanical planarization (CMP) process may be performed, and the gate electrode 600 may be formed of metal or polysilicon.
이 후, 도 1b와 같이, 기판(100)의 전면(front side)에 감광막(photoresist layer)(500)을 패터닝하여 형성한다. 이는 소스 전극(400)을 형성하기 위한 것이다. 그리고, 고농도 p+형 불순물 이온(3족 원소)을 주입하여 소스 전극(400)을 형성한다.Thereafter, as shown in FIG. 1B, a photoresist layer 500 is patterned and formed on the front side of the substrate 100. This is for forming the source electrode 400. The source electrode 400 is formed by implanting high concentration p + type impurity ions (Group III element).
이 후, 소스 전극(400) 형성을 위한 감광막(500)을 제거하고 도 1c와 같이, 기판(100)의 전면(front side)에 다시 감광막(500)을 패터닝하여 형성한다. 이는 드레인 전극(700)을 형성하기 위한 것이다. 그리고, 고농도 n+형 불순물 이온(5족 원소)을 주입하여 드레인 전극(700)을 형성한다.Thereafter, the photoresist film 500 for forming the source electrode 400 is removed, and the photoresist film 500 is patterned again on the front side of the substrate 100 as shown in FIG. 1C. This is for forming the drain electrode 700. Then, a high concentration n + type impurity ion (group 5 element) is implanted to form a drain electrode 700.
이에 따라 제조된 터널링 전계효과 트랜지스터는 소스 전극(400), 채널(900), 드레인 전극(700)이 각각 p형, intrinsic형, n형의 극성을 갖는 pin 다이오드를 포함하게 된다.The tunneling field effect transistor thus manufactured includes a pin diode in which the source electrode 400, the channel 900, and the drain electrode 700 have p-type, intrinsic, and n-type polarities, respectively.
마지막으로, 수소 어닐링(hydrogen annealing) 공정을 거쳐 나노와이어 형상의 표면 거칠기를 완화시켜, 도 1d에 도시되어 있는 터널링 전계효과 트랜지스터가 제조된다. 수소 어닐링 공정은 선행 공정 또는 제조 방법에 따라 선택적으로 적용될 수 있다.Finally, the surface roughness of the nanowire shape is relieved through a hydrogen annealing process, whereby a tunneling field effect transistor shown in FIG. 1D is manufactured. The hydrogen annealing process may optionally be applied according to the preceding process or preparation method.
본 발명에 따른 트랜지스터 제조 방법과 관련한 상기 설명에 있어서, 본 발명의 본질을 흐리지 않고자, 종래 트랜지스터 제조 방법에서 일반적으로 이루어지는 공정에 대해서는 상세한 설명을 생략하였다. 하지만, 구체적으로 설명되지 않은 공정의 경우에도, 당업자라면 본 발명을 이해하는데 어려움이 없을 것이다.In the above description of the transistor manufacturing method according to the present invention, in order not to obscure the essence of the present invention, a detailed description of the steps generally performed in the conventional transistor manufacturing method is omitted. However, even in the case of processes not specifically described, those skilled in the art will have no difficulty understanding the present invention.
이하에서는 상기의 과정에 따라 제조된 터널링 전계효과 트랜지스터에 대해 구동전류 특성을 향상시키는 방법에 대하여 설명한다. Hereinafter, a method of improving driving current characteristics of a tunneling field effect transistor manufactured according to the above process will be described.
도 2a 및 도 2b는 본 발명에 따른 초 저전력 전열처리를 통한 터널링 전계효과 트랜지스터의 구동전류를 증가시키는 방법을 나타내는 도면이다. 도 2c는 본 발명에 따른 초 저전력 전열처리 후 pin 다이오드의 터널링 배리어가 짧아진 것을 보여주는 에너지 밴드 다이어그램이다. 도 2d는 짧아진 터널링 배리어로 인하여 pin 다이오드의 역방향 전류가 향상된 것을 확인할 수 있는 전기적 측정 데이터이다.2A and 2B illustrate a method of increasing the driving current of a tunneling field effect transistor through ultra low power electrothermal treatment according to the present invention. Figure 2c is an energy band diagram showing that the tunneling barrier of the pin diode is shortened after the ultra low power electrothermal treatment according to the present invention. FIG. 2D is electrical measurement data confirming that the reverse current of the pin diode is improved due to the shortened tunneling barrier.
우선, 본 발명에 따른 초 저전력 전열처리를 통한 터널링 전계효과 트랜지스터의 구동전류를 증가시키는 방법은, 소스 전극(400)과 드레인 전극(700) 사이에 존재하는 pin 다이오드에 역방향 전압을 인가하여, 역방향 전류를 발생시킨다. 이 때, 소모되는 전력을 최소화하기 위하여, 게이트 전극(600)은 꺼져있는 상태(OFF 상태)에서 진행한다.First, the method of increasing the driving current of the tunneling field effect transistor through the ultra low power electrothermal treatment according to the present invention, by applying a reverse voltage to the pin diode existing between the source electrode 400 and the drain electrode 700, Generate a current. At this time, in order to minimize the power consumed, the gate electrode 600 proceeds in an off state (OFF state).
이 때, 소스 전극(400)과 드레인 전극(700)사이에 6V 내지 8V의 역방향 전류를 흘려주게 되면, 줄 열(Joule heat)이 발생하게 되는데, 이 열은 높은 열 전도도를 지닌 게이트 전극(600)으로는 방출이 원활한 반면, 게이트 전극으로 둘러쌓여 있지 않은 부분에서는 열 방출이 원활하지 못해, 도 2a 및 2b와 같이 높은 열을 발생시키게 된다. 이 때, 역방향 전류의 지속시간은 100 마이크로초 이하이며, 소모되는 전류는 수백 nW 정도이다. 역방향 전류를 인가하여 발생한 열은, 소스 전극(400)과 드레인 전극(700)에 주입된 이온을 활성화(activation) 및 재배치시키기 위한 목적으로 이용되며, 이는 본 발명에서의 초 저전력 전열처리에 해당한다. At this time, if a reverse current of 6V to 8V is flowed between the source electrode 400 and the drain electrode 700, Joule heat is generated, which is a gate electrode 600 having a high thermal conductivity. ), While the emission is smooth, heat dissipation is not smooth in the portion not surrounded by the gate electrode, thereby generating high heat as shown in FIGS. 2A and 2B. At this time, the duration of the reverse current is 100 microseconds or less, and the current consumed is about several hundred nW. The heat generated by applying the reverse current is used for the purpose of activating and rearranging the ions implanted into the source electrode 400 and the drain electrode 700, which corresponds to the ultra low power electrothermal treatment in the present invention. .
소스 전극(400) 및 드레인 전극(700)에 주입된 이온이 활성화 되면, 도 2c와 같이 에너지 밴드 다이어그램의 기울기가 더욱 가파르게 형성되어 터널링 배리어(tunneling barrier)가 짧아지게 되는데, 짧아진 터널링 배리어의 길이로 인해, 더 많은 전자들이 터널링하는 효과를 가질 수 있다. When the ions implanted into the source electrode 400 and the drain electrode 700 are activated, the slope of the energy band diagram is more steeply formed as shown in FIG. 2C, so that the tunneling barrier is shortened. Due to this, more electrons can have the effect of tunneling.
이 때, 터널링되는 전자 개수의 증가로 인해 도 2d와 같이 터널링 전계효과 트랜지스터가 포함하고 있는 pin 다이오드의 역방향 전류가 더욱 증가하게 된다.At this time, due to an increase in the number of tunneled electrons, the reverse current of the pin diode included in the tunneling field effect transistor further increases as shown in FIG. 2D.
도 3a는 본 발명에 따른 초 저전력 전열처리를 통해 터널링 전계효과 트랜지스터의 구동전류 특성이 향상되는 것을 검증한 전기적 측정 데이터이다. 도 3b는 본 발명에 따른 초 저전력 전열처리를 위해 인가되는 전압에 따라 트랜지스터의 구동전류 특성을 나타내는 전기적 측정 데이터이다. 도 4는 본 발명에 따른 초 저전력 전열처리 전후에 게이트 절연막 누설전류가 특성이 크게 변하지 않음을 증명하는 전기적 측정 데이터이다.3A is electrical measurement data verifying that driving current characteristics of a tunneling field effect transistor are improved through ultra low power electrothermal treatment according to the present invention. 3B is electrical measurement data showing a drive current characteristic of a transistor according to a voltage applied for ultra low power electrothermal treatment according to the present invention. 4 is electrical measurement data demonstrating that the characteristics of the gate insulating film leakage current do not change significantly before and after the ultra low power electrothermal treatment according to the present invention.
상기에서 설명한 초 저전력 전열처리 이후, 실제 측정된 터널링 전계효과 트랜지스터의 전기적 특성은 도 3a에 도시되어 있다. 이를 통해, 초 저전력 전열처리 이후 터널링 전계효과 트랜지스터의 구동전류의 크기가 최대 10배 정도까지 향상될 수 있음을 실험적으로 검증하였으며, 도 3b를 통해 초 저전력 전열처리에 인가되는 pin 다이오드의 역방향 전압이 커짐에 따라, 트랜지스터의 구동전류의 특성이 향상됨을 확인할 수 있다.After the ultra low power electrothermal treatment described above, the electrical characteristics of the actually measured tunneling field effect transistor are shown in FIG. 3A. Through this, it was experimentally verified that the driving current of the tunneling field effect transistor can be improved up to 10 times after the ultra low power electrothermal treatment, and the reverse voltage of the pin diode applied to the ultra low power electrothermal treatment is shown in FIG. As it increases, it can be seen that the characteristics of the driving current of the transistor improve.
도 4는 본 발명에 따른 초 저전력 전열처리로 인해 게이트 절연막(800)의 손상 및 트랜지스터의 신뢰성 저하가 발생하지 않는지 확인하기 위해 측정하여 얻은 데이터이다. 도 4를 참조하면, 본 발명에 따른 초 저전력 전열처리 전후에 게이트 절연막(800)의 누설전류가 크게 변동이 없음을 알 수 있다. 이를 통해, 본 발명에 따른 초 저전력 전열처리가 트랜지스터의 성능저하에 문제를 일으키지 않음을 검증할 수 있다. 4 is data obtained by measuring to confirm that the damage of the gate insulating film 800 and the reliability deterioration of the transistor do not occur due to the ultra low power electrothermal treatment according to the present invention. Referring to FIG. 4, it can be seen that the leakage current of the gate insulating film 800 is not significantly changed before and after the ultra low power electrothermal treatment according to the present invention. Through this, it can be verified that the ultra low power electrothermal treatment according to the present invention does not cause a problem in the performance degradation of the transistor.
본 발명에 따른 초 저전력 전열처리를 이용하면, 터널링 전계효과 트랜지스터의 기판을 실리콘 게르마늄 기판 등으로 형성하는 것보다 구동전류 향상의 효과가 증대되며, 터널링 전계효과 트랜지스터를 제조하는 비용을 감소시킬 수 있다. 본 발명에 따른 초 저전력 전열처리는 터널링 전계효과 트랜지스터의 신뢰성을 열화시키지 않고, 효율적으로 구동전류 특성 개선을 달성할 수 있다.By using the ultra-low power electrothermal treatment according to the present invention, the effect of improving the driving current is increased compared to forming the substrate of the tunneling field effect transistor using a silicon germanium substrate or the like, and the cost of manufacturing the tunneling field effect transistor can be reduced. . The ultra low power electrothermal treatment according to the present invention can efficiently achieve driving current characteristics without deteriorating the reliability of the tunneling field effect transistor.
본 발명에서는, 기존의 터널링 전계효과 트랜지스터의 구동 원리에서 기인한 낮은 구동전류의 단점을 소스 전극과 드레인 전극사이에서 발생하는 인위적인 전열처리를 통해 개선한다. 전열처리에 대한 구체적인 방법으로는 pin 다이오드 역방향 전류를 소스 전극과 드레인 전극 사이에 인가함으로서, 소스 전극과 드레인 전극에 국부적으로 고온의 열을 발생시킨다. In the present invention, the disadvantage of the low driving current caused by the driving principle of the conventional tunneling field effect transistor is improved by artificial heat treatment occurring between the source electrode and the drain electrode. As a specific method for the electrothermal treatment, a pin diode reverse current is applied between the source electrode and the drain electrode, thereby generating high temperature heat locally at the source electrode and the drain electrode.
이 때, 발생된 열을 통해 소스 전극과 드레인 전극에 주입된 이온에서 활성화가 발생하고, 이를 통해 터널링 전계효과 트랜지스터의 구동 전류가 개선될 수 있다. 또한, 전열처리를 위해 소모되는 전력이 나노와트(nW) 단위가 아니라, 마이크로와트(μW) 단위인 것은 또한 주목할 만한 요소이다. At this time, activation occurs in the ions implanted into the source electrode and the drain electrode through the generated heat, thereby driving current of the tunneling field effect transistor can be improved. It is also noteworthy that the power consumed for the electrothermal treatment is in microwatts (μW) rather than nanowatts (nW).
이상에서 실시예들에 설명된 특징, 구조, 효과 등은 본 발명의 하나의 실시예에 포함되며, 반드시 하나의 실시예에만 한정되는 것은 아니다. 나아가, 각 실시예에서 예시된 특징, 구조, 효과 등은 실시예들이 속하는 분야의 통상의 지식을 가지는 자에 의해 다른 실시예들에 대해서도 조합 또는 변형되어 실시 가능하다. 따라서 이러한 조합과 변형에 관계된 내용들은 본 발명의 범위에 포함되는 것으로 해석되어야 할 것이다.Features, structures, effects, etc. described in the above embodiments are included in one embodiment of the present invention, and are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, contents related to such combinations and modifications should be construed as being included in the scope of the present invention.
또한, 이상에서 실시예를 중심으로 설명하였으나 이는 단지 예시일 뿐 본 발명을 한정하는 것이 아니며, 본 발명이 속하는 분야의 통상의 지식을 가진 자라면 본 실시예의 본질적인 특성을 벗어나지 않는 범위에서 이상에 예시되지 않은 여러 가지의 변형과 응용이 가능함을 알 수 있을 것이다. 예를 들어, 실시예에 구체적으로 나타난 각 구성 요소는 변형하여 실시할 수 있는 것이다. 그리고 이러한 변형과 응용에 관계된 차이점들은 첨부된 청구범위에서 규정하는 본 발명의 범위에 포함되는 것으로 해석되어야 할 것이다.In addition, the above description has been made with reference to the embodiment, which is merely an example, and is not intended to limit the present invention. Those skilled in the art to which the present invention pertains will be illustrated as above without departing from the essential characteristics of the present embodiment. It will be appreciated that various modifications and applications are possible. For example, each component specifically shown in the embodiment can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.
본 발명에 따르면, 구동전류가 향상된 터널링 전계효과 트랜지스터를 구현 및 제조할 수 있다.According to the present invention, it is possible to implement and manufacture a tunneling field effect transistor with improved driving current.
또한, 본 발명에 따르면, 터널링 전계효과 트랜지스터의 기판을 실리콘 게르마늄 기판 등으로 형성하는 것보다 구동전류 향상의 효과가 증대되며, 터널링 전계효과 트랜지스터를 제조하는 비용을 감소시킬 수 있다. In addition, according to the present invention, the effect of improving the driving current is increased compared to forming the substrate of the tunneling field effect transistor by using a silicon germanium substrate or the like, and the cost of manufacturing the tunneling field effect transistor can be reduced.
특히, 본 발명에 따른 초 저전력 전열처리는 터널링 전계효과 트랜지스터의 신뢰성을 열화시키지 않고, 효율적으로 구동전류 특성 개선을 달성할 수 있다.In particular, the ultra-low power electrothermal treatment according to the present invention can efficiently achieve driving current characteristics without degrading the reliability of the tunneling field effect transistor.
다만, 본 발명의 효과는 상기 효과들로 한정되는 것이 아니며, 본 발명의 기술적 사상 및 영역으로부터 벗어나지 않는 범위에서 다양하게 확장될 수 있다. However, the effects of the present invention are not limited to the above effects, and may be variously expanded within the scope without departing from the spirit and scope of the present invention.

Claims (15)

  1. 기판 상에 형성된 터널링 전계효과 트랜지스터의 제조 방법으로서,A method of manufacturing a tunneling field effect transistor formed on a substrate,
    (a) 상기 기판을 패터닝하고, 식각 공정을 수행하여 채널을 형성하는 단계;(a) patterning the substrate and performing an etching process to form a channel;
    (b) 상기 채널이 형성된 상기 기판 상(on) 및 상기 채널의 하부(below)에, 절연막을 형성하는 단계;(b) forming an insulating film on the substrate on which the channel is formed and below the channel;
    (c) 상기 채널의 표면 상에 게이트 절연막을 형성하는 단계;(c) forming a gate insulating film on the surface of the channel;
    (d) 상기 게이트 절연막 상에 게이트 전극을 형성하는 단계; 및(d) forming a gate electrode on the gate insulating film; And
    (e) 상기 게이트 전극이 형성된 상기 기판 상에 감광막 패턴을 형성하고, 이온주입 공정을 수행하여 소스 전극 또는 드레인 전극을 형성하는 단계를 포함하는, 터널링 전계효과 트랜지스터의 제조 방법. (e) forming a photoresist pattern on the substrate on which the gate electrode is formed, and performing a ion implantation process to form a source electrode or a drain electrode.
  2. 제1항에 있어서,The method of claim 1,
    상기 기판은, Ⅲ-V족 물질을 포함하는 기판, 게르마늄과 실리콘을 포함하는 실리콘 게르마늄 기판, 게르마늄 기판, 유기물을 포함하는 기판, 절연층 매몰 실리콘 기판, 절연층 매몰 스트레인드 실리콘 기판, 절연층 매몰 게르마늄 기판, 절연층 매몰 스트레인드 게르마늄 기판, 절연층 매몰 실리콘 게르마늄 기판, 및 고농도로 도핑된 무접합(junctionless) 기판 중 적어도 하나를 포함하는, 터널링 전계효과 트랜지스터의 제조 방법. The substrate may include a substrate including a III-V material, a silicon germanium substrate including germanium and silicon, a germanium substrate, a substrate including an organic material, an insulating layer buried silicon substrate, an insulating layer buried strained silicon substrate, and an insulating layer buried A method of manufacturing a tunneling field effect transistor, comprising at least one of a germanium substrate, an insulating layer buried strained germanium substrate, an insulating layer buried silicon germanium substrate, and a heavily doped junctionless substrate.
  3. 제1항에 있어서,The method of claim 1,
    상기 (a) 단계에서 형성되는 상기 채널은 나노와이어(nano-wire) 채널 또는 나노면(nano-sheet) 채널인, 터널링 전계효과 트랜지스터의 제조 방법.The channel formed in the step (a) is a nano-wire (nano-wire) channel or nano-sheet (nano-sheet) channel, manufacturing method of a tunneling field effect transistor.
  4. 제3항에 있어서,The method of claim 3,
    상기 채널은 그래핀, 탄소나노튜브, 또는 이산화황몰리브덴(MoS2)을 포함하는, 터널링 전계효과 트랜지스터의 제조 방법.The channel includes graphene, carbon nanotubes, or molybdenum sulfur dioxide (MoS2), a method of manufacturing a tunneling field effect transistor.
  5. 제1항에 있어서,The method of claim 1,
    상기 (c) 단계에서 형성되는 상기 게이트 절연막은, 실리콘 산화막 또는 고유전막(High-k)인, 터널링 전계효과 트랜지스터의 제조 방법.The gate insulating film formed in step (c) is a silicon oxide film or a high-k film (High-k) manufacturing method of the tunneling field effect transistor.
  6. 제5항에 있어서,The method of claim 5,
    상기 게이트 절연막은 산화 실리콘(silicon oxide), 질화막, 산화 알루미늄(aluminum oxide), 산화 하프늄(hafnium oxide), 산화질화 하프늄(hafnium oxynitride), 산화 아연(zinc oxide), 란타늄 옥사이드(lanthanum oxide), 및 하프늄 실리콘 옥사이드(hafnium silicon oxide) 중 적어도 하나를 포함하는, 터널링 전계효과 트랜지스터의 제조 방법.The gate insulating film may be formed of silicon oxide, nitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zinc oxide, lanthanum oxide, and A method of manufacturing a tunneling field effect transistor, comprising at least one of hafnium silicon oxide.
  7. 제1항에 있어서,The method of claim 1,
    상기 (d) 단계에서 형성되는 상기 게이트 전극은, 금속 또는 폴리 실리콘을 포함하는, 터널링 전계효과 트랜지스터의 제조 방법.The gate electrode formed in the step (d) comprises a metal or polysilicon, manufacturing method of a tunneling field effect transistor.
  8. 제7항에 있어서,The method of claim 7, wherein
    상기 게이트 전극은, 알루미늄(Al), 몰리브덴(Mo), 마그네슘(Mg), 크롬(Cr), 팔라듐(Pd), 금(Au), 백금(Pt), 타이타늄(Ti), 타이타늄나이트라이드(TiN), 및 탄탈럼나이트라이드(TaN) 중 적어도 하나를 포함하는, 터널링 전계효과 트랜지스터의 제조 방법.The gate electrode may include aluminum (Al), molybdenum (Mo), magnesium (Mg), chromium (Cr), palladium (Pd), gold (Au), platinum (Pt), titanium (Ti), and titanium nitride (TiN). And tantalum nitride (TaN).
  9. 제1항에 있어서,The method of claim 1,
    상기 (d) 단계는, 상기 게이트 절연막 상에 게이트 물질을 증착하고, 상기 게이트 물질을 패터닝하여 상기 게이트 전극을 형성하는, 터널링 전계효과 트랜지스터의 제조 방법.In the step (d), a gate material is deposited on the gate insulating film, and the gate material is patterned to form the gate electrode.
  10. 제1항에 있어서,The method of claim 1,
    상기 (e) 단계는, 상기 기판 상에 제1 감광막 패턴을 형성하고, p+형 불순물 이온을 주입하여 상기 소스 전극을 형성하고, 상기 제1 감광막 패턴을 제거한 후 상기 기판 상에 제2 감광막 패턴을 형성하고, n+형 불순물 이온을 주입하여 상기 드레인 전극을 형성하는, 터널링 전계효과 트랜지스터의 제조 방법.In the step (e), a first photoresist layer pattern is formed on the substrate, p + type impurity ions are implanted to form the source electrode, the first photoresist layer pattern is removed, and a second photoresist layer pattern is formed on the substrate. And implanting n + -type impurity ions to form the drain electrode.
  11. 상기 제1항 내지 제10항 중 어느 한 항에 따라 제조된 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법으로서,A method of improving the driving current of a tunneling field effect transistor manufactured according to any one of claims 1 to 10,
    (a) 상기 게이트 전극을 턴오프(turn off) 시키는 단계;(a) turning off the gate electrode;
    (b) 상기 소스 전극과 상기 드레인 전극 사이에 전류를 인가하여 상기 터널링 전계효과 트랜지스터에 전열처리를 수행하는 단계; 및(b) performing an electrothermal treatment on the tunneling field effect transistor by applying a current between the source electrode and the drain electrode; And
    (c) 상기 소스 전극과 상기 드레인 전극에 주입된 이온을 활성화 시키는 단계를 포함하는, 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법.(c) activating ions implanted in the source electrode and the drain electrode, wherein the driving current of the tunneling field effect transistor is enhanced.
  12. 제11항에 있어서,The method of claim 11,
    상기 (b) 단계에서 상기 소스 전극과 상기 드레인 전극 사이에 전류를 인가하는 것은, 상기 소스 전극과 상기 드레인 전극 사이에 pin 다이오드 역방향 전류를 인가하는, 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법.Applying a current between the source electrode and the drain electrode in the step (b), applying a pin diode reverse current between the source electrode and the drain electrode, the driving current of the tunneling field effect transistor.
  13. 제11항에 있어서,The method of claim 11,
    상기 (b) 단계에서 상기 소스 전극과 상기 드레인 전극 사이에 전류를 인가하는 것은, 상기 소스 전극과 상기 드레인 전극 사이에 pin 다이오드 정방향 전류를 인가하는, 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법.Applying a current between the source electrode and the drain electrode in the step (b), applying a pin diode forward current between the source electrode and the drain electrode, improving the drive current of the tunneling field effect transistor.
  14. 제11항에 있어서,The method of claim 11,
    상기 (b) 단계에서의 상기 전열처리를 위해 필요한 상기 전류의 양 및 전열처리를 수행하는 시간을 최적화하는 시뮬레이션 단계를 더 포함하는, 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법.And (b) a simulation step of optimizing the amount of current required for the electrothermal treatment in step (b) and the time for performing the electrothermal treatment.
  15. (a) 터널링 전계효과 트랜지스터의 게이트 전극을 턴오프(turn off) 시키는 단계;(a) turning off the gate electrode of the tunneling field effect transistor;
    (b) 상기 터널링 전계효과 트랜지스터의 소스 전극 및 드레인 전극 사이에 전류를 인가하여 상기 터널링 전계효과 트랜지스터에 전열처리를 수행하는 단계; 및(b) performing an electrothermal treatment on the tunneling field effect transistor by applying a current between the source electrode and the drain electrode of the tunneling field effect transistor; And
    (c) 상기 소스 전극과 상기 드레인 전극에 주입된 이온을 활성화 시키는 단계를 포함하는, 터널링 전계효과 트랜지스터의 구동전류를 향상시키는 방법.(c) activating ions implanted in the source electrode and the drain electrode, wherein the driving current of the tunneling field effect transistor is enhanced.
PCT/KR2017/014455 2017-03-22 2017-12-11 Method for manufacturing tunneling field-effect transistor and method for enhancing driving current of tunneling field-effect transistor through ultra-low power pre-heat treatment WO2018174377A1 (en)

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