WO2020111521A1 - Two-terminal vertical type thyristor-based 1t dram - Google Patents

Two-terminal vertical type thyristor-based 1t dram Download PDF

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WO2020111521A1
WO2020111521A1 PCT/KR2019/014087 KR2019014087W WO2020111521A1 WO 2020111521 A1 WO2020111521 A1 WO 2020111521A1 KR 2019014087 W KR2019014087 W KR 2019014087W WO 2020111521 A1 WO2020111521 A1 WO 2020111521A1
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dram
base layer
emitter layer
layer
type material
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French (fr)
Korean (ko)
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박재근
유상동
심태헌
김민원
이병석
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한양대학교 산학협력단
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1027—Thyristors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1012—Base regions of thyristors
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present invention relates to a technical idea for forming a 2-terminal vertical thyristor-based 1T DRAM, by forming a 2-terminal vertical thyristor-based 1T DRAM using a Schottky contact between the base and the emitter, the operation It is about a 2-terminal vertical thyristor-based 1T DRAM that solves the temperature dependency problem and secures a memory margin.
  • DRAM dynamic random access memory
  • MTJ magnetic tunnel junction
  • MTJ magnetic tunnel junction
  • p-STT-MRAM perpendicular spin-torque-transfer magnetic random access memory
  • the thyristor-based 1T-DRAM uses 3 terminals (anode, cathode, gate), and in 2018, Hanyang University applied Applied to the research on the 2-terminal thyristor-based cross-point memory that can operate without a selector element.
  • Hanyang University applied Applied to the research on the 2-terminal thyristor-based cross-point memory that can operate without a selector element.
  • the thyristor-based 1T-DRAM has a total of three terminals, one at the anode and the other at the ends of the pnpn structure, and one gate at one of the center base regions. Based on the horizontal structure, there is a limit to scaling down.
  • the 2-terminal vertical thyristor-based 1T DRAM of p-n-p-n or n-p-n-p structure has an advantage in scaling down compared to the 3-terminal, but has a problem in that the memory margin decreases as the operating temperature increases.
  • FIG. 1 is a view for explaining a two-terminal vertical thyristor-based 1T DRAM according to the prior art.
  • a two-terminal vertical thyristor-based 1T DRAM 100 includes a first emitter layer 110, a first base layer 120, a second base layer 130, and a second emitter layer 140. It can be formed to include.
  • the first emitter layer 110 may be connected to the cathode 150 or may serve as the cathode 150, and may be formed using a first conductivity type or a second conductivity type material.
  • the first base layer 120 and the second base layer 130 are formed using different conductive type materials, and may be operated as a base region.
  • the second emitter layer 140 may be connected to the anode 160 or may serve as the anode 160, and may be formed using a first conductivity type or a second conductivity type material.
  • the second emitter layer 140 may be formed using a second conductivity type material.
  • the first conductivity-type material may include n-type impurities
  • the second conductivity-type material may include p-type impurities
  • the 2-terminal thyristor-based 1T DRAM 100 may exhibit a p-n-p-n or n-p-n-p structure.
  • FIG. 2A illustrates an energy-band-diagram of a conventional two-terminal vertical thyristor-based 1T DRAM.
  • Figure 2b illustrates the electrical characteristics of the conventional 2-terminal vertical thyristor-based 1T DRAM by temperature.
  • FIG. 2C is a diagram illustrating a memory margin of a conventional 2-terminal vertical thyristor-based 1T DRAM according to temperature change.
  • the conventional two-terminal vertical thyristor-based 1T DRAM has a pnpn structure
  • the latch-up voltage (V LU ) is 2.78V as the operating temperature increases to 300K, 320K, 340K, 360K, 380K, 400K , 2.39V, 1.90V, 1.37V, 0.88V, 0.50V
  • the latch-down voltage (V LD ) is reduced to 0.54V, 0.50V, 0.44V, 0.42V, 0.34V, 0.32V.
  • the memory margin may represent a difference between the latch up voltage (V LU ) and the latch down voltage (V LD ).
  • the conventional two-terminal vertical thyristor-based 1T DRAM has an advantage in scaling down, but there is a disadvantage that the memory margin decreases as the operating temperature increases.
  • the present invention may be intended to secure the operational stability of the memory even at high temperatures by replacing the emitter layer connected to at least one of the positive electrode or the negative electrode with a metal material using a Schottky contact.
  • the present invention may be intended to reduce the aspect ratio of the memory cell by reducing the thickness of the emitter layer by replacing the emitter layer with a metal material using a Schottky contact.
  • the present invention can be aimed at reducing the operating temperature dependence of the memory by replacing the emitter layer with a metal material using a Schottky contact.
  • the present invention may be intended to overcome the physical limitations on the memory cell structure by replacing the emitter layer with a metal material using a Schottky contact.
  • a 2-terminal vertical thyristor-based 1T DRAM is a first emitter layer formed of a first conductivity type material, and a second conductivity type material on the first emitter layer.
  • a second base layer vertically formed of the first conductive material on the first base layer, and on the second base layer
  • the second base layer may include a second emitter layer vertically formed of a metal material that forms a Schottky contact.
  • the metal material includes at least one of gold (Au), cobalt (Co), copper (Cu), iron (Fe), nickel (Ni), palladium (Pd), platinum (Pt), and ruthenium (Ru) can do.
  • the first emitter layer may be formed of a metal material that forms a Schottky contact with the first base layer by replacing the first conductive type material.
  • the second emitter layer may output a latch up voltage of 1.58V to 2.83V in a temperature range of 300K to 400K.
  • the second emitter layer may output a latch down voltage of 0.8V to 0.89V in a temperature range of 300K to 400K.
  • the first conductivity type material may include n-type impurities, and the second conductivity type material may include p-type impurities.
  • a 2-terminal vertical thyristor-based 1T DRAM is a first emitter layer formed of a metal material, and the first emitter on the first emitter layer.
  • a first base layer vertically formed of a second conductive type material forming a Schottky contact with a layer, and a second vertically formed of the first conductive type material on the first base layer It may include a base layer and a second emitter layer vertically formed of a second conductive type material on the second base layer.
  • the second emitter layer may be formed of a metal material that forms a Schottky contact with the second base layer by replacing the second conductive type material.
  • a 2-terminal vertical thyristor-based 1T DRAM is a first emitter layer formed of a first conductivity type material, and a second conductivity type material on the first emitter layer.
  • a first base layer vertically formed, a second base layer vertically formed of the first conductive material on the first base layer, and on the second base layer
  • a second emitter layer vertically formed of a metal material forming a Schottky contact with the second base layer, and the first conductive type material on the second emitter layer
  • the present invention can secure the operational stability of the memory even at high temperatures by replacing the emitter layer connected to at least one of the positive electrode or the negative electrode with a metal material using a Schottky contact.
  • the present invention can reduce the aspect ratio of the memory cell by reducing the thickness of the emitter layer by replacing the emitter layer with a metal material using a Schottky contact.
  • the present invention can reduce the dependence of the operating temperature of the memory by replacing the emitter layer with a metal material using a Schottky contact.
  • 1 to 2c are views illustrating a conventional two-terminal vertical thyristor-based 1T DRAM.
  • FIG 3 is a view for explaining the structure of a two-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • 4A is a diagram illustrating an energy band diagram of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • 4B is a diagram illustrating electrical characteristics of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • 4C is a diagram illustrating the operating temperature dependence of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 5 is a view for explaining a flowchart related to a method of manufacturing a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • 6A and 6B are diagrams illustrating a double-layer structure of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 7A is a diagram illustrating an energy band diagram of a 2 terminal vertical thyristor based 1T DRAM having a conventional double stacked structure.
  • FIG. 7B is a diagram illustrating an energy band diagram of a two-terminal vertical thyristor-based 1T DRAM having a double stacked structure according to an embodiment of the present invention.
  • 8A is a diagram for explaining electrical characteristics of a two-terminal vertical thyristor-based 1T DRAM having a conventional double stacked structure.
  • 8B is a diagram for explaining electrical characteristics of a 2-terminal vertical thyristor-based 1T DRAM having a double-layered structure according to an embodiment of the present invention.
  • first or second may be used to describe various components, but the components should not be limited by the terms. The above terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of rights according to the concept of the present invention, the first component may be referred to as the second component, Similarly, the second component may also be referred to as the first component.
  • FIG 3 is a view for explaining the structure of a two-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 3 illustrates the structure of a two-terminal vertical thyristor-based 1T DRAM formed by replacing an emitter layer with metal using a Schottky contact.
  • a 2-terminal vertical thyristor-based 1T DRAM 300 includes a first emitter layer 310, a first base layer 320, a second base layer 330, and And a second emitter layer 340.
  • the first emitter layer 310 may be formed of a first conductivity type material.
  • the first emitter layer 310 may be formed by adding a first conductivity type impurity at a high concentration.
  • the first emitter layer 310 may be formed to have a region thickness of about 100 nm.
  • the first emitter layer 310 may be formed of a metal material that forms a Schottky contact with the first base layer by replacing the first conductive type material.
  • the first base layer 320 may be vertically formed of a second conductive type material on the first emitter layer 310.
  • the first base layer 320 may be formed using a second conductive material having a low concentration compared to the first emitter layer 310.
  • the second base layer 330 may be vertically formed of a first conductive type material on the first base layer 320.
  • the second base layer 320 may be formed using a first conductivity type material having the same concentration as the first base layer 320.
  • the first base layer 320 and the second base layer 330 may be operated as a base region.
  • each region of the first base layer 320 and the second base layer 330 may be about 100 nm.
  • the second emitter layer 340 may be vertically formed on the second base layer 330 using a metal material that forms a Schottky contact with the second base layer.
  • the second emitter layer 340 may output a latch up voltage of 1.58V to 2.83V in a temperature range of 300K to 400K.
  • the latch-up voltage decreases to 2.83V, 2.64V, 2.40V, 2.13V, 1.85V, 1.58V Can be output.
  • the latch-up voltage can be reduced to 0.89V, 0.86V, 0.83V, 0.82V, 0.80V, 0.80 and output. .
  • the present invention can reduce the aspect ratio of the memory cell by reducing the thickness of the emitter layer by replacing the emitter layer with a metal material using a Schottky contact.
  • the cathode 350 may be connected to the first emitter layer 310 or the first emitter layer 310 may be operated as the cathode 350.
  • the anode 360 may be connected to the second emitter layer 340 or the second emitter layer 340 may be operated as the anode 360.
  • the cathode 350 and the anode 360 have a thickness of about 20 nm, and a doping concentration may be 1 x 10 18 cm -3 .
  • the metal material is at least one of gold (Au), cobalt (Co), copper (Cu), iron (Fe), nickel (Ni), palladium (Pd), platinum (Pt), and ruthenium (Ru). It may include.
  • the first conductivity-type material may include n-type impurities
  • the second conductivity-type material may include p-type impurities
  • the two-terminal vertical thyristor-based 1T DRAM 300 converts the state of the memory to "1" or "0" based on changes in the potential of the first base layer 320 and the second base layer 330. And can operate as a memory.
  • the 2-terminal thyristor-based 1T DRAM 300 induces a latch-up when the state of the first base layer 320 is high in the read state, thereby causing the memory state to be " 1", when the state of the first base layer 320 is low, causing blocking, resulting in a memory state of "0", a low off current of pA level and about 10 ⁇ A current It may have a high read current.
  • 4A is a diagram illustrating an energy band diagram of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • the first base layer and the second base layer of the two-terminal vertical thyristor-based 1T DRAM may be located between 0.2 mm and 0.3 mm on the horizontal axis of the graph.
  • 4B is a diagram illustrating electrical characteristics of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 4B illustrates electrical characteristics corresponding to a change in the anode voltage according to the anode current based on a temperature range change of 300K to 400K in a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • the reduction of the anode voltage is relatively small in the high temperature range of the 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • the 2-terminal vertical thyristor-based 1T DRAM can secure a relatively high memory margin compared to the conventional 2-terminal vertical thyristor-based 1T DRAM.
  • the present invention can secure the operational stability of the memory even at high temperatures by replacing the emitter layer connected to at least one of the anode or the cathode with a metal material using a Schottky contact.
  • 4C is a diagram illustrating the operating temperature dependence of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 4C shows the change of the latch-up voltage (V LU ) and the latch-down voltage (V LD ) based on a temperature range change of 300K to 400K in a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • the reduction of the latch-up voltage (V LU ) and the latch-down voltage (V LD ) is relatively high in the high temperature range of the 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention. small.
  • the 2-terminal vertical thyristor-based 1T DRAM can secure a relatively high memory margin compared to the conventional 2-terminal vertical thyristor-based 1T DRAM.
  • the present invention can reduce the dependence of the operating temperature of the memory by replacing the emitter layer with a metal material using a Schottky contact.
  • FIG. 5 is a view for explaining a flowchart related to a method of manufacturing a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • a method of manufacturing a 2-terminal vertical thyristor-based 1T DRAM forms a first emitter layer using a first conductivity type material.
  • a first emitter layer may be formed by doping impurities of a first conductivity type on a substrate.
  • the first emitter layer can be operated as a cathode or connected to the cathode.
  • a method of manufacturing a two-terminal vertical thyristor-based 1T DRAM may form a first base layer using a second conductive material.
  • a first base layer may be vertically formed by doping a second conductive type impurity on the first emitter layer.
  • a method of manufacturing a two-terminal vertical thyristor-based 1T DRAM forms a second base layer using a first conductivity type material.
  • a second base layer may be vertically formed by doping a first conductive type impurity on the first base layer.
  • a method of manufacturing a two-terminal vertical thyristor-based 1T DRAM may use a metal material to form a second emitter layer.
  • the method of manufacturing a two-terminal vertical thyristor-based 1T DRAM uses a metal material that forms a second base (Schottky Contact with the second base layer on the layer) and vertically emits the second emitter layer. Can form.
  • the second emitter layer can be operated as an anode or connected to the anode.
  • 6A is a diagram illustrating a double-layer structure of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 6A illustrates a double stacked structure in a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • a two-terminal vertical thyristor-based 1T DRAM 600 may be formed on a substrate 610, and includes a first emitter layer 620, a first base layer 630, and a second base layer ( 640), a second emitter layer 650, a third base layer 641, a fourth base layer 631 and a third emitter layer 621 may be formed.
  • the first emitter layer 620 may be formed of a first conductive type material, and a high concentration of first impurities may be doped.
  • the first base layer 630 may be vertically formed of a second conductive type material on the first emitter layer 620, and is relatively relatively doped than the doping concentration of the first emitter layer 620.
  • the second impurity at a low concentration may be formed by doping.
  • the second base layer 640 may be vertically formed of a first conductive type material on the first base layer 630, and the first impurity having the same concentration as the doping concentration of the first base layer 630 may be It can be formed by doping.
  • the second emitter layer 650 may be vertically formed of a metal material that forms a Schottky contact with the second base layer 640 on the second base layer 640.
  • the second emitter layer 650 may also be referred to as a metal layer.
  • the third base layer 641 may be vertically formed of the first conductive type material on the second emitter layer 650.
  • the fourth base layer 631 may be vertically formed of a second conductive type material on the third base layer 641.
  • the third emitter layer 621 may be vertically formed of a first conductive type material on the fourth base layer 631.
  • the second emitter layer 650 may function as an anode, and the first emitter layer 620 and the third emitter layer 621 may act as a cathode.
  • 6B is a diagram illustrating a double-layer structure of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
  • FIG. 6B illustrates a three-dimensional stereogram of the two-terminal vertical thyristor-based 1T DRAM described in FIG. 6A.
  • a two-terminal vertical thyristor-based 1T DRAM 600 may be formed on a substrate 610, and includes a first emitter layer 620, a first base layer 630, and a second base layer ( 640), including a second emitter layer 650, a third base layer is vertically formed using the same material as the second base layer 640 on the second emitter layer 650, and on the third base layer
  • a fourth base layer is vertically formed using the same material as the first base layer 630, and a third emitter layer is vertically formed using the same material as the first emitter layer 620 on the fourth base layer.
  • the first emitter layer 620 and the third emitter layer may be connected to a bit line, and the second emitter layer 650 may be connected to a word line.
  • the two-terminal vertical thyristor-based 1T DRAM 600 may be operated as a cross-point memory device based on a double-stacked structure.
  • the 2-terminal vertical thyristor-based 1T DRAM 600 may also be referred to as a 3D cross-point memory device.
  • FIG. 7A is a diagram illustrating an energy band diagram of a conventional 2T vertical thyristor-based 1T DRAM having a dual-stack structure
  • FIG. 7B is a 2-terminal vertical thyristor-based double-stack structure according to an embodiment of the present invention. It is a diagram to explain the energy band diagram of 1T DRAM.
  • FIG. 7A a change in the anode voltage 700 and the cathode voltage 701 in each layer of a conventional two-terminal vertical thyristor-based 1T DRAM is illustrated.
  • an anode of a metal layer forming a Schottky contact with a base layer may be positioned at a junction of 0.3 to 0.4.
  • the two-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention has a relatively small drop in the latch-down voltage, so a higher memory margin can be secured.
  • FIG. 8A is a diagram for explaining electrical characteristics of a conventional 2-terminal vertical thyristor-based 1T DRAM having a dual-stacked structure
  • FIG. 8B is a 2-terminal vertical thyristor-based 1T having a dual-stacked structure according to an embodiment of the present invention. This diagram explains the electrical characteristics of DRAM.
  • a two-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention has a relatively small decrease in anode voltage in a high temperature range.
  • the 2-terminal vertical thyristor-based 1T DRAM can secure a relatively high memory margin compared to the conventional 2-terminal vertical thyristor-based 1T DRAM.
  • the device described above may be implemented with hardware components, software components, and/or combinations of hardware components and software components.
  • the devices and components described in the embodiments include, for example, processors, controllers, arithmetic logic units (ALUs), digital signal processors (micro signal processors), microcomputers, field programmable arrays (FPAs), It may be implemented using one or more general purpose computers or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions.
  • the processing device may run an operating system (OS) and one or more software applications running on the operating system.
  • the processing device may access, store, manipulate, process, and generate data in response to the execution of the software.
  • OS operating system
  • the processing device may access, store, manipulate, process, and generate data in response to the execution of the software.
  • a processing device may be described as one being used, but a person having ordinary skill in the art, the processing device may include a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that may include.
  • the processing device may include a plurality of processors or a processor and a controller.
  • other processing configurations such as parallel processors, are possible.
  • the method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium.
  • the computer-readable medium may include program instructions, data files, data structures, or the like alone or in combination.
  • the program instructions recorded in the medium may be specially designed and configured for the embodiments or may be known and usable by those skilled in computer software.
  • Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs, DVDs, and magnetic media such as floptical disks.
  • -Hardware devices specifically configured to store and execute program instructions such as magneto-optical media, and ROM, RAM, flash memory, and the like.
  • program instructions include high-level language code that can be executed by a computer using an interpreter, etc., as well as machine language codes produced by a compiler.
  • the hardware device described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

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Abstract

The present invention relates to a two-terminal vertical type thyristor-based 1T DRAM. According to an embodiment of the present invention, the two-terminal vertical type thyristor-based 1T DRAM may comprise: a first emitter layer formed of a first conductive material; a first base layer vertically formed of a second conductive material on the first emitter layer; a second base layer vertically formed of the first conductive material on the first base layer; and a second emitter layer vertically formed of a metal material on the second base layer, the metal material being in Schottky contact with the second base layer.

Description

2단자 수직형 사이리스터 기반 1T 디램2-terminal thyristor-based 1T DRAM
본 발명은 2단자 수직형 사이리스터 기반 1T 디램을 형성하기 위한 기술적 사상에 관한 것으로서, 베이스와 에미터 사이에서 쇼트키 컨택(Schottky Contact)을 이용하여 2단자 수직형 사이리스터 기반 1T 디램을 형성함으로써, 동작 온도 의존성 문제를 해결하고, 메모리 마진을 확보하는 2단자 수직형 사이리스터 기반 1T 디램에 관한 것 이다.The present invention relates to a technical idea for forming a 2-terminal vertical thyristor-based 1T DRAM, by forming a 2-terminal vertical thyristor-based 1T DRAM using a Schottky contact between the base and the emitter, the operation It is about a 2-terminal vertical thyristor-based 1T DRAM that solves the temperature dependency problem and secures a memory margin.
현재 1개의 선택 트랜지스터(1T)와 1개의 커패시터(1C)의 메모리 셀 구조(1T+1C)를 가지는 디램(Dynamic Random Access Memory, DRAM)의 물리적 한계(디자인 룰 10 nm이하)를 극복하기 위해 커패시터를 자기터널접합 (MTJ: magnetic tunnel junction)으로 대체한 1T+1R 구조의 p-STT-MRAM (perpendicular spin-torque-transfer magnetic random access memory), 커패시터 대신 SOI (silicon on insulator) 기판의 바디(body)에 전하를 저장하는 1T 구조의 SOI 기반 1T-DRAM, 사이리스터 기반의 1T-DRAM이 솔루션(solution)으로 연구되고 있다.A capacitor to overcome the physical limitations (design rule 10 nm or less) of a dynamic random access memory (DRAM) having a memory cell structure (1T+1C) of one selection transistor 1T and one capacitor 1C. Is a magnetic tunnel junction (MTJ) replaced by a magnetic tunnel junction (MTJ) p-STT-MRAM (perpendicular spin-torque-transfer magnetic random access memory), instead of a capacitor, the body of a silicon on insulator (SOI) substrate SOI-based 1T-DRAM of 1T structure storing charge in ), and 1T-DRAM of thyristor are being studied as solutions.
현재까지 사이리스터 기반의 1T-DRAM은 3단자(anode, cathode, gate)를 사용하고 있으며, 2018년 한양대학교에서 selector 소자 없이 동작 가능한 2단자 수직형 사이리스터 기반의 cross-point 메모리에 대한 연구 내용을 Applied Physics Letters에 발표하였다.To date, the thyristor-based 1T-DRAM uses 3 terminals (anode, cathode, gate), and in 2018, Hanyang University applied Applied to the research on the 2-terminal thyristor-based cross-point memory that can operate without a selector element. Physics Letters.
메모리 반도체의 성능가속화 요구는 지금까지 주 메모리 반도체인 디램에 있어 매년 평균 2nm의 스케일링 다운(scaling down)을 추진해오고 있었으나, 이러한 경향을 따르면 2020 년도에는 10nm 급 대역으로 스케일링 다운되어 물리적 한계에 도달할 것으로 예상된다.The demand to accelerate the performance of memory semiconductors has been pushing an average of 2nm of scaling down every year for DRAM, the main memory semiconductor, but according to this trend, it will be scaled down to a 10nm band in 2020 to reach the physical limit. Is expected.
사이리스터 기반 1T-DRAM의 경우 p-n-p-n 구조에서 양 끝에 양극(anode)와 음극(cathode) 2단자, 그리고 가운데 베이스(base) 영역 중 한 곳에 게이트(gate) 1단자로 총 3단자를 갖고 있으며, SOI 기판을 기반으로 하여 수평구조로 이루어져서 스케일링 다운에 한계를 가지고 있다.The thyristor-based 1T-DRAM has a total of three terminals, one at the anode and the other at the ends of the pnpn structure, and one gate at one of the center base regions. Based on the horizontal structure, there is a limit to scaling down.
p-n-p-n 또는 n-p-n-p 구조의 2단자 수직형 사이리스터 기반 1T 디램은 3단자에 비하여 스케일링 다운에서의 이점이 있지만, 동작 온도가 올라감에 따라 메모리 마진(memory margin)이 감소한다는 문제점이 있다.The 2-terminal vertical thyristor-based 1T DRAM of p-n-p-n or n-p-n-p structure has an advantage in scaling down compared to the 3-terminal, but has a problem in that the memory margin decreases as the operating temperature increases.
도 1은 종래 기술에 따른 2단자 수직형 사이리스터 기반 1T 디램을 설명하는 도면이다.1 is a view for explaining a two-terminal vertical thyristor-based 1T DRAM according to the prior art.
도 1을 참고하면, 2단자 수직형 사이리스터 기반 1T 디램(100)은 제1 에미터층(110), 제1 베이스층(120), 제2 베이스층(130) 및 제2 에미터층(140)을 포함하도록 형성될 수 있다.Referring to FIG. 1, a two-terminal vertical thyristor-based 1T DRAM 100 includes a first emitter layer 110, a first base layer 120, a second base layer 130, and a second emitter layer 140. It can be formed to include.
제1 에미터층(110)은 음극(150)에 연결되거나 음극(150)의 역할을 수행할 수 있으며, 제1 도전형 또는 제2 도전형 물질을 이용하여 형성될 수 있다.The first emitter layer 110 may be connected to the cathode 150 or may serve as the cathode 150, and may be formed using a first conductivity type or a second conductivity type material.
제1 베이스층(120)과 제2 베이스층(130)은 서로 다른 도전형 물질을 이용하여 형성되며, 베이스 영역으로서 동작될 수 있다.The first base layer 120 and the second base layer 130 are formed using different conductive type materials, and may be operated as a base region.
제2 에미터층(140)은 양극(160)에 연결되거나 양극(160)의 역할을 수행할 수 있고, 제1 도전형 또는 제2 도전형 물질을 이용하여 형성될 수 있다.The second emitter layer 140 may be connected to the anode 160 or may serve as the anode 160, and may be formed using a first conductivity type or a second conductivity type material.
예를 들어, 제1 에미터층(110)이 제1 도전형 물질을 이용하여 형성될 경우, 제2 에미터층(140)은 제2 도전형 물질을 이용하여 형성될 수 있다.For example, when the first emitter layer 110 is formed using a first conductivity type material, the second emitter layer 140 may be formed using a second conductivity type material.
예를 들어, 제1 도전형 물질은 n형 불순물을 포함하고, 제2 도전형 물질은 p형 불순물을 포함할 수 있다.For example, the first conductivity-type material may include n-type impurities, and the second conductivity-type material may include p-type impurities.
예를 들어, 2단자 수직형 사이리스터 기반 1T 디램(100)은 p-n-p-n 또는 n-p-n-p 구조를 나타낼 수 있다.For example, the 2-terminal thyristor-based 1T DRAM 100 may exhibit a p-n-p-n or n-p-n-p structure.
도 2a는 종래의 2단자 수직형 사이리스터 기반 1T 디램의 에너지 밴드 다이어그램(energy-band-diagram)을 설명한다.2A illustrates an energy-band-diagram of a conventional two-terminal vertical thyristor-based 1T DRAM.
도 2a를 참고하면, 종래의 2단자 수직형 사이리스터 기반 1T 디램을 구성하는 각 층에서 양극 전압(200)과 음극 전압(201)의 변화를 확인할 수 있다.Referring to Figure 2a, it can be seen the change in the anode voltage 200 and the cathode voltage 201 in each layer constituting the conventional two-terminal vertical thyristor-based 1T DRAM.
도 2b는 종래의 2단자 수직형 사이리스터 기반 1T 디램의 온도별 전기적 특성을 설명한다.Figure 2b illustrates the electrical characteristics of the conventional 2-terminal vertical thyristor-based 1T DRAM by temperature.
도 2b를 참고하면, 종래의 2단자 수직형 사이리스터 기반 1T 디램의 300K, 320K, 340K, 360K, 380K, 400K의 온도에서 동작시킴에 따른 전기적 특성 변화를 확인할 수 있다.Referring to Figure 2b, it can be seen that the change in electrical characteristics according to the operation at a temperature of 300K, 320K, 340K, 360K, 380K, 400K of a conventional two-terminal vertical thyristor-based 1T DRAM.
도 2c는 온도 변화에 따른 종래의 2단자 수직형 사이리스터 기반 1T 디램의 메모리 마진을 설명하는 도면이다.FIG. 2C is a diagram illustrating a memory margin of a conventional 2-terminal vertical thyristor-based 1T DRAM according to temperature change.
도 2c를 참고하면, 종래의 2단자 수직형 사이리스터 기반 1T 디램은 p-n-p-n구조를 갖고, 동작 온도가 300K, 320K, 340K, 360K, 380K, 400K으로 증가함에 따라 래치 업 전압(VLU)는 2.78V, 2.39V, 1.90V, 1.37V, 0.88V, 0.50V로 감소하며, 래치 다운 전압(VLD)은 0.54V, 0.50V, 0.44V, 0.42V, 0.34V, 0.32V로 감소한다.Referring to Figure 2c, the conventional two-terminal vertical thyristor-based 1T DRAM has a pnpn structure, the latch-up voltage (V LU ) is 2.78V as the operating temperature increases to 300K, 320K, 340K, 360K, 380K, 400K , 2.39V, 1.90V, 1.37V, 0.88V, 0.50V, and the latch-down voltage (V LD ) is reduced to 0.54V, 0.50V, 0.44V, 0.42V, 0.34V, 0.32V.
즉, 종래의 2단자 수직형 사이리스터 기반 1T 디램은 동작 온도가 올라감에 따라 래치 업 전압(VLU)이 크게 감소하고, 래치 다운 전압(VLD)가 상대적으로 조금 감소하여 결과적으로 메모리 마진(memory margin)이 감소될 수 있다. 여기서, 메모리 마진은 래치 업 전압(VLU)과 래치 다운 전압(VLD)의 차이를 나타낼 수 있다.That is, in the conventional 2-terminal vertical thyristor-based 1T DRAM, as the operating temperature increases, the latch-up voltage (V LU ) greatly decreases, and the latch-down voltage (V LD ) decreases relatively, resulting in a memory margin. margin) can be reduced. Here, the memory margin may represent a difference between the latch up voltage (V LU ) and the latch down voltage (V LD ).
도 2a 내지 도 2c에 따르면, 종래의 2단자 수직형 사이리스터 기반 1T 디램은 스케일링 다운에서의 이점은 있지만, 동작 온도가 올라감에 따라 메모리 마진이 감소한다는 단점이 존재한다.According to Figures 2a to 2c, the conventional two-terminal vertical thyristor-based 1T DRAM has an advantage in scaling down, but there is a disadvantage that the memory margin decreases as the operating temperature increases.
따라서, 디램의 스케일링 다운을 처리함과 동시에 메모리 마진을 확보하는 2단자 수직형 사이리스터 기반 1T 디램이 제안될 필요성이 존재한다.Accordingly, there is a need to propose a 2-terminal vertical thyristor-based 1T DRAM that secures a memory margin while processing scaling down of the DRAM.
본 발명은 양극 또는 음극 중 적어도 하나와 연결되는 에미터층을 쇼트키 컨택(schottky contact)을 이용하여 메탈 물질로 대체함으로써 고온에서도 메모리의 동작 안정성을 확보하는 것을 목적으로 할 수 있다.The present invention may be intended to secure the operational stability of the memory even at high temperatures by replacing the emitter layer connected to at least one of the positive electrode or the negative electrode with a metal material using a Schottky contact.
본 발명은 에미터층을 쇼트키 컨택(schottky contact)을 이용하여 메탈 물질로 대체함으로써 에미터층의 두께를 감소시켜 메모리셀의 종횡비(aspect ratio)를 낮추는 것을 목적으로 할 수 있다.The present invention may be intended to reduce the aspect ratio of the memory cell by reducing the thickness of the emitter layer by replacing the emitter layer with a metal material using a Schottky contact.
본 발명은 에미터층을 쇼트키 컨택(schottky contact)을 이용하여 메탈 물질로 대체함으로써 메모리의 동작 온도 의존성을 감소시키는 것을 목적으로 할 수 있다.The present invention can be aimed at reducing the operating temperature dependence of the memory by replacing the emitter layer with a metal material using a Schottky contact.
본 발명은 에미터층을 쇼트키 컨택(schottky contact)을 이용하여 메탈 물질로 대체함으로써 메모리셀 구조 상의 물리적 한계를 극복하는 것을 목적으로 할 수 있다.The present invention may be intended to overcome the physical limitations on the memory cell structure by replacing the emitter layer with a metal material using a Schottky contact.
본 발명의 일실시예에 따르면 2단자 수직형 사이리스터 기반 1T 디램은 제1 도전형 물질로 형성되는 제1 에미터(emitter)층, 상기 제1 에미터(emitter)층 상에 제2 도전형 물질로 수직 형성되는 제1 베이스(base)층, 상기 제1 베이스(base)층 상에 상기 제1 도전형 물질로 수직 형성되는 제2 베이스(base)층 및 상기 제2 베이스(base)층 상에 상기 제2 베이스(base)층과 쇼트키 컨택(Schottky Contact)을 이루는 메탈 물질로 수직 형성되는 제2 에미터(emitter)층을 포함할 수 있다.According to an embodiment of the present invention, a 2-terminal vertical thyristor-based 1T DRAM is a first emitter layer formed of a first conductivity type material, and a second conductivity type material on the first emitter layer. On a first base layer vertically formed, a second base layer vertically formed of the first conductive material on the first base layer, and on the second base layer The second base layer may include a second emitter layer vertically formed of a metal material that forms a Schottky contact.
상기 메탈 물질은 금(Au), 코발트(Co), 구리(Cu), 철(Fe), 니켈(Ni), 팔라듐(Pd), 백금(Pt), 류테늄(Ru) 중 적어도 하나 이상을 포함할 수 있다.The metal material includes at least one of gold (Au), cobalt (Co), copper (Cu), iron (Fe), nickel (Ni), palladium (Pd), platinum (Pt), and ruthenium (Ru) can do.
상기 제1 에미터(emitter)층은 상기 제1 도전형 물질을 대체하여 상기 제1 베이스층과 쇼트키 컨택(Schottky Contact)을 이루는 메탈 물질로 형성될 수 있다.The first emitter layer may be formed of a metal material that forms a Schottky contact with the first base layer by replacing the first conductive type material.
상기 제2 에미터(emitter)층은 300K 내지 400K의 온도 범위에서 1.58V 내지 2.83V의 래치 업 전압(latch up voltage)을 출력할 수 있다.The second emitter layer may output a latch up voltage of 1.58V to 2.83V in a temperature range of 300K to 400K.
상기 제2 에미터(emitter)층은 300K 내지 400K의 온도 범위에서 0.8V 내지 0.89V의 래치 다운 전압(latch down voltage)을 출력할 수 있다.The second emitter layer may output a latch down voltage of 0.8V to 0.89V in a temperature range of 300K to 400K.
상기 제1 도전형 물질은 n형 불순물을 포함하고, 상기 제2 도전형 물질은 p형 불순물을 포함할 수 있다.The first conductivity type material may include n-type impurities, and the second conductivity type material may include p-type impurities.
본 발명의 일실시예에 따르면 2단자 수직형 사이리스터 기반 1T 디램은 메탈 물질로 형성되는 제1 에미터(emitter)층, 상기 제1 에미터(emitter)층 상에 상기 제1 에미터(emitter)층과 쇼트키 컨택(Schottky Contact)을 이루는 제2 도전형 물질로 수직 형성되는 제1 베이스(base)층, 상기 제1 베이스(base)층 상에 상기 제1 도전형 물질로 수직 형성되는 제2 베이스(base)층 및 상기 제2 베이스(base)층 상에 제2 도전형 물질로 수직 형성되는 제2 에미터(emitter)층을 포함할 수 있다.According to an embodiment of the present invention, a 2-terminal vertical thyristor-based 1T DRAM is a first emitter layer formed of a metal material, and the first emitter on the first emitter layer. A first base layer vertically formed of a second conductive type material forming a Schottky contact with a layer, and a second vertically formed of the first conductive type material on the first base layer It may include a base layer and a second emitter layer vertically formed of a second conductive type material on the second base layer.
상기 제2 에미터(emitter)층은 상기 제2 도전형 물질을 대체하여 상기 제2 베이스층과 쇼트키 컨택(Schottky Contact)을 이루는 메탈 물질로 형성될 수 있다.The second emitter layer may be formed of a metal material that forms a Schottky contact with the second base layer by replacing the second conductive type material.
본 발명의 일실시예에 따르면 2단자 수직형 사이리스터 기반 1T 디램은 제1 도전형 물질로 형성되는 제1 에미터(emitter)층, 상기 제1 에미터(emitter)층 상에 제2 도전형 물질로 수직 형성되는 제1 베이스(base)층, 상기 제1 베이스(base)층 상에 상기 제1 도전형 물질로 수직 형성되는 제2 베이스(base)층 및 상기 제2 베이스(base)층 상에 상기 제2 베이스(base)층과 쇼트키 컨택(Schottky Contact)을 이루는 메탈 물질로 수직 형성되는 제2 에미터(emitter)층, 상기 제2 에미터(emitter)층 상에 상기 제1 도전형 물질로 수직 형성되는 제3 베이스(base)층, 상기 제3 베이스(base)층 상에 상기 제2 도전형 물질로 수직 형성되는 제4 베이스(base)층 및 상기 제4 베이스(base)층 상에 상기 제1 도전형 물질로 형성되는 제3 에미터(emitter)층을 포함할 수 있다.According to an embodiment of the present invention, a 2-terminal vertical thyristor-based 1T DRAM is a first emitter layer formed of a first conductivity type material, and a second conductivity type material on the first emitter layer. On a first base layer vertically formed, a second base layer vertically formed of the first conductive material on the first base layer, and on the second base layer A second emitter layer vertically formed of a metal material forming a Schottky contact with the second base layer, and the first conductive type material on the second emitter layer On a third base layer vertically formed, on a fourth base layer vertically formed of the second conductive material on the third base layer and on the fourth base layer And a third emitter layer formed of the first conductive type material.
본 발명은 양극 또는 음극 중 적어도 하나와 연결되는 에미터층을 쇼트키 컨택(schottky contact)을 이용하여 메탈 물질로 대체함으로써 고온에서도 메모리의 동작 안정성을 확보할 수 있다.The present invention can secure the operational stability of the memory even at high temperatures by replacing the emitter layer connected to at least one of the positive electrode or the negative electrode with a metal material using a Schottky contact.
본 발명은 에미터층을 쇼트키 컨택(schottky contact)을 이용하여 메탈 물질로 대체함으로써 에미터층의 두께를 감소시켜 메모리셀의 종횡비(aspect ratio)를 낮출 수 있다.The present invention can reduce the aspect ratio of the memory cell by reducing the thickness of the emitter layer by replacing the emitter layer with a metal material using a Schottky contact.
본 발명은 에미터층을 쇼트키 컨택(schottky contact)을 이용하여 메탈 물질로 대체함으로써 메모리의 동작 온도 의존성을 감소시킬 수 있다.The present invention can reduce the dependence of the operating temperature of the memory by replacing the emitter layer with a metal material using a Schottky contact.
도 1 내지 도 2c는 종래의 2단자 수직형 사이리스터 기반 1T 디램을 설명하는 도면이다.1 to 2c are views illustrating a conventional two-terminal vertical thyristor-based 1T DRAM.
도 3은 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램의 구조를 설명하는 도면이다.3 is a view for explaining the structure of a two-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
도 4a는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램의 에너지 밴드 다이어그램을 설명하는 도면이다.4A is a diagram illustrating an energy band diagram of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
도 4b는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램의 전기적 특성을 설명하는 도면이다.4B is a diagram illustrating electrical characteristics of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
도 4c는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램의 동작 온도 의존성을 설명하는 도면이다.4C is a diagram illustrating the operating temperature dependence of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
도 5는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램의 제조 방법과 관련된 흐름도를 설명하는 도면이다.5 is a view for explaining a flowchart related to a method of manufacturing a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
도 6a 및 도 6b는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램의 이중 적층 구조를 설명하는 도면이다.6A and 6B are diagrams illustrating a double-layer structure of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
도 7a는 종래의 이중 적층 구조를 갖는 2단자 수직형 사이리스터 기반 1T 디램의 에너지 밴드 다이어그램을 설명하는 도면이다.7A is a diagram illustrating an energy band diagram of a 2 terminal vertical thyristor based 1T DRAM having a conventional double stacked structure.
도 7b는 본 발명의 일실시예에 따른 이중 적층 구조를 갖는 2단자 수직형 사이리스터 기반 1T 디램의 에너지 밴드 다이어그램을 설명하는 도면이다.7B is a diagram illustrating an energy band diagram of a two-terminal vertical thyristor-based 1T DRAM having a double stacked structure according to an embodiment of the present invention.
도 8a는 종래의 이중 적층 구조를 갖는 2단자 수직형 사이리스터 기반 1T 디램의 전기적 특성을 설명하는 도면이다.8A is a diagram for explaining electrical characteristics of a two-terminal vertical thyristor-based 1T DRAM having a conventional double stacked structure.
도 8b는 본 발명의 일실시예에 따른 이중 적층 구조를 갖는 2단자 수직형 사이리스터 기반 1T 디램의 전기적 특성을 설명하는 도면이다.8B is a diagram for explaining electrical characteristics of a 2-terminal vertical thyristor-based 1T DRAM having a double-layered structure according to an embodiment of the present invention.
본 명세서에 개시되어 있는 본 발명의 개념에 따른 실시예들에 대해서 특정한 구조적 또는 기능적 설명들은 단지 본 발명의 개념에 따른 실시예들을 설명하기 위한 목적으로 예시된 것으로서, 본 발명의 개념에 따른 실시예들은 다양한 형태로 실시될 수 있으며 본 명세서에 설명된 실시예들에 한정되지 않는다.Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in this specification are exemplified only for the purpose of illustrating the embodiments according to the concept of the present invention, and the embodiments according to the concept of the present invention These can be implemented in various forms and are not limited to the embodiments described herein.
본 발명의 개념에 따른 실시예들은 다양한 변경들을 가할 수 있고 여러 가지 형태들을 가질 수 있으므로 실시예들을 도면에 예시하고 본 명세서에 상세하게 설명하고자 한다. 그러나, 이는 본 발명의 개념에 따른 실시예들을 특정한 개시형태들에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 변경, 균등물, 또는 대체물을 포함한다.Embodiments according to the concept of the present invention can be applied to various changes and have various forms, so the embodiments will be illustrated in the drawings and described in detail herein. However, this is not intended to limit the embodiments according to the concept of the present invention to specific disclosure forms, and includes modifications, equivalents, or substitutes included in the spirit and scope of the present invention.
제1 또는 제2 등의 용어를 다양한 구성요소들을 설명하는데 사용될 수 있지만, 상기 구성요소들은 상기 용어들에 의해 한정되어서는 안 된다. 상기 용어들은 하나의 구성요소를 다른 구성요소로부터 구별하는 목적으로만, 예를 들어 본 발명의 개념에 따른 권리 범위로부터 이탈되지 않은 채, 제1 구성요소는 제2 구성요소로 명명될 수 있고, 유사하게 제2 구성요소는 제1 구성요소로도 명명될 수 있다.Terms such as first or second may be used to describe various components, but the components should not be limited by the terms. The above terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of rights according to the concept of the present invention, the first component may be referred to as the second component, Similarly, the second component may also be referred to as the first component.
어떤 구성요소가 다른 구성요소에 "연결되어" 있다거나 "접속되어" 있다고 언급된 때에는, 그 다른 구성요소에 직접적으로 연결되어 있거나 또는 접속되어 있을 수도 있지만, 중간에 다른 구성요소가 존재할 수도 있다고 이해되어야 할 것이다. 반면에, 어떤 구성요소가 다른 구성요소에 "직접 연결되어" 있다거나 "직접 접속되어" 있다고 언급된 때에는, 중간에 다른 구성요소가 존재하지 않는 것으로 이해되어야 할 것이다. 구성요소들 간의 관계를 설명하는 표현들, 예를 들어 "~사이에"와 "바로~사이에" 또는 "~에 직접 이웃하는" 등도 마찬가지로 해석되어야 한다.When an element is said to be "connected" or "connected" to another component, it is understood that other components may be directly connected to or connected to the other component, but there may be other components in between. It should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that no other component exists in the middle. Expressions describing the relationship between the components, for example, "between" and "immediately between" or "directly adjacent to" should be interpreted similarly.
본 명세서에서 사용한 용어는 단지 특정한 실시예들을 설명하기 위해 사용된 것으로, 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함한다. 본 명세서에서, "포함하다" 또는 "가지다" 등의 용어는 설시된 특징, 숫자, 단계, 동작, 구성요소, 부분품 또는 이들을 조합한 것이 존재함으로 지정하려는 것이지, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성요소, 부분품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해되어야 한다.The terminology used herein is only used to describe specific embodiments and is not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the terms "include" or "have" are intended to designate the presence of a feature, number, step, action, component, part, or combination thereof as described, one or more other features or numbers, It should be understood that the presence or addition possibilities of steps, actions, components, parts or combinations thereof are not excluded in advance.
다르게 정의되지 않는 한, 기술적이거나 과학적인 용어를 포함해서 여기서 사용되는 모든 용어들은 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에 의해 일반적으로 이해되는 것과 동일한 의미를 가진다. 일반적으로 사용되는 사전에 정의되어 있는 것과 같은 용어들은 관련 기술의 문맥상 가지는 의미와 일치하는 의미를 갖는 것으로 해석되어야 하며, 본 명세서에서 명백하게 정의하지 않는 한, 이상적이거나 과도하게 형식적인 의미로 해석되지 않는다.Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person skilled in the art to which the present invention pertains. Terms, such as those defined in a commonly used dictionary, should be interpreted as having meanings consistent with meanings in the context of related technologies, and should not be interpreted as ideal or excessively formal meanings unless explicitly defined herein. Does not.
이하, 실시예들을 첨부된 도면을 참조하여 상세하게 설명한다. 그러나, 특허출원의 범위가 이러한 실시예들에 의해 제한되거나 한정되는 것은 아니다. 각 도면에 제시된 동일한 참조 부호는 동일한 부재를 나타낸다.Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the scope of the patent application is not limited or limited by these embodiments. The same reference numerals in each drawing denote the same members.
도 3은 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램의 구조를 설명하는 도면이다.3 is a view for explaining the structure of a two-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
보다 구체적으로, 도 3은 쇼트키 컨택(Schottky Contact)을 이용하여 에미터(emitter)층을 메탈로 대체하여 형성된 2단자 수직형 사이리스터 기반 1T 디램의 구조를 예시한다.More specifically, FIG. 3 illustrates the structure of a two-terminal vertical thyristor-based 1T DRAM formed by replacing an emitter layer with metal using a Schottky contact.
도 3을 참고하면, 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램(300)은 제1 에미터층(310), 제1 베이스층(320), 제2 베이스층(330) 및 제2 에미터층(340)을 포함한다.Referring to FIG. 3, a 2-terminal vertical thyristor-based 1T DRAM 300 according to an embodiment of the present invention includes a first emitter layer 310, a first base layer 320, a second base layer 330, and And a second emitter layer 340.
일례로, 제1 에미터층(310)은 제1 도전형 물질로 형성될 수 있다. 여기서, 제1 에미터층(310)은 제1 도전형 불순물이 고농도로 첨가되어 형성될 수 있다.In one example, the first emitter layer 310 may be formed of a first conductivity type material. Here, the first emitter layer 310 may be formed by adding a first conductivity type impurity at a high concentration.
예를 들어, 제1 에미터층(310)은 영역(region)의 두께가 약 100nm로 형성될 수 있다.For example, the first emitter layer 310 may be formed to have a region thickness of about 100 nm.
본 발명의 일실시예에 따르면 제1 에미터층(310)은 제1 도전형 물질을 대체하여 제1 베이스층과 쇼트키 컨택(Schottky Contact)을 이루는 메탈 물질로 형성될 수 도 있다.According to an embodiment of the present invention, the first emitter layer 310 may be formed of a metal material that forms a Schottky contact with the first base layer by replacing the first conductive type material.
본 발명의 일실시예에 따르면 제1 베이스층(320)은 제1 에미터층(310) 상에 제2 도전형 물질로 수직 형성될 수 있다.According to an embodiment of the present invention, the first base layer 320 may be vertically formed of a second conductive type material on the first emitter layer 310.
예를 들어, 제1 베이스층(320)은 제1 에미터층(310)에 대비하여 저 농도의 제2 도전형 물질을 이용하여 형성될 수 있다.For example, the first base layer 320 may be formed using a second conductive material having a low concentration compared to the first emitter layer 310.
일례로, 제2 베이스층(330)은 제1 베이스층(320) 상에 제1 도전형 물질로 수직 형성될 수 있다.For example, the second base layer 330 may be vertically formed of a first conductive type material on the first base layer 320.
예를 들어, 제2 베이스층(320)은 제1 베이스층(320)과 동일한 농도의 제1 도전형 물질을 이용하여 형성될 수 있다.For example, the second base layer 320 may be formed using a first conductivity type material having the same concentration as the first base layer 320.
일례로, 제1 베이스층(320)과 제2 베이스층(330)은 베이스 영역으로서 동작될 수 있다.In one example, the first base layer 320 and the second base layer 330 may be operated as a base region.
예를 들어, 제1 베이스층(320)과 제2 베이스층(330) 각각 영역의 두께는 약 100nm일 수 있다.For example, the thickness of each region of the first base layer 320 and the second base layer 330 may be about 100 nm.
본 발명의 일실시예에 따르면 제2 에미터층(340)은 제2 베이스층(330) 상에 제2 베이스층과 쇼트키 컨택을 이루는 메탈 물질로 수직 형성될 수 있다.According to an embodiment of the present invention, the second emitter layer 340 may be vertically formed on the second base layer 330 using a metal material that forms a Schottky contact with the second base layer.
일례로, 제2 에미터층(340)은 300K 내지 400K의 온도 범위에서 1.58V 내지 2.83V의 래치 업 전압(latch up voltage)을 출력할 수 있다.For example, the second emitter layer 340 may output a latch up voltage of 1.58V to 2.83V in a temperature range of 300K to 400K.
보다 구체적으로, 제2 에미터층(340)은 300K, 320K, 340K, 360K, 380K, 400K으로 증가함에 따라 래치 업 전압이 2.83V, 2.64V, 2.40V, 2.13V, 1.85V, 1.58V로 감소되어 출력할 수 있다.More specifically, as the second emitter layer 340 increases to 300K, 320K, 340K, 360K, 380K, 400K, the latch-up voltage decreases to 2.83V, 2.64V, 2.40V, 2.13V, 1.85V, 1.58V Can be output.
제2 에미터층(340)은 300K, 320K, 340K, 360K, 380K, 400K으로 증가함에 따라 래치 업 전압이 0.89V, 0.86V, 0.83V, 0.82V, 0.80V, 0.80로 감소되어 출력할 수 있다.As the second emitter layer 340 increases to 300K, 320K, 340K, 360K, 380K, and 400K, the latch-up voltage can be reduced to 0.89V, 0.86V, 0.83V, 0.82V, 0.80V, 0.80 and output. .
따라서, 본 발명은 에미터층을 쇼트키 컨택(schottky contact)을 이용하여 메탈 물질로 대체함으로써 에미터층의 두께를 감소시켜 메모리셀의 종횡비(aspect ratio)를 낮출 수 있다.Therefore, the present invention can reduce the aspect ratio of the memory cell by reducing the thickness of the emitter layer by replacing the emitter layer with a metal material using a Schottky contact.
본 발명의 일실시예에 따르면 음극(350)은 제1 에미터층(310)과 연결되거나, 제1 에미터층(310)이 음극(350)으로 동작될 수 있다.According to an embodiment of the present invention, the cathode 350 may be connected to the first emitter layer 310 or the first emitter layer 310 may be operated as the cathode 350.
일례로 양극(360)은 제2 에미터층(340)과 연결되거나, 제2 에미터층(340)이 양극(360)으로 동작될 수 있다.For example, the anode 360 may be connected to the second emitter layer 340 or the second emitter layer 340 may be operated as the anode 360.
음극(350) 및 양극(360)은 영역의 두께가 약 20nm이고, 도핑 농도는 1 x 1018 cm-3로 형성될 수 있다.The cathode 350 and the anode 360 have a thickness of about 20 nm, and a doping concentration may be 1 x 10 18 cm -3 .
일례로, 메탈 물질은 금(Au), 코발트(Co), 구리(Cu), 철(Fe), 니켈(Ni), 팔라듐(Pd), 백금(Pt), 류테늄(Ru) 중 적어도 하나 이상을 포함할 수 있다.In one example, the metal material is at least one of gold (Au), cobalt (Co), copper (Cu), iron (Fe), nickel (Ni), palladium (Pd), platinum (Pt), and ruthenium (Ru). It may include.
본 발명의 일실시예에 따르면 제1 도전형 물질은 n형 불순물을 포함하고, 제2 도전형 물질은 p형 불순물을 포함할 수 있다.According to an embodiment of the present invention, the first conductivity-type material may include n-type impurities, and the second conductivity-type material may include p-type impurities.
2단자 수직형 사이리스터 기반 1T 디램(300)은 제1 베이스층(320)과 제2 베이스층(330)의 포텐셜(potentional)의 변화에 기반하여 메모리의 상태가 "1" 또는 "0"으로 변환되어 메모리로서 동작할 수 있다.The two-terminal vertical thyristor-based 1T DRAM 300 converts the state of the memory to "1" or "0" based on changes in the potential of the first base layer 320 and the second base layer 330. And can operate as a memory.
제1 베이스층(320)과 제2 베이스층(330)의 포텐셜(potentional)이 상승하면 메모리의 상태가 "1"이 되고, 포텐셜(potentional)이 하강하면 메모리의 상태가 "0"이 될 수 있다.When the potential of the first base layer 320 and the second base layer 330 rises, the memory state becomes "1", and when the potential decreases, the memory state becomes "0". have.
또한, 2단자 수직형 사이리스터 기반 1T 디램(300)은 리드(read) 상태에서는 제1 베이스층(320)의 상태가 하이(high)인 경우 래치 업(latch-up)을 유발하여 메모리 상태가 "1"이 되고, 제1 베이스층(320)의 상태가 로우(low)인 경우 블록(blocking)을 유발하여 메모리 상태가 "0"이 되며 pA 레벨의 낮은 오프 전류(off current)와 약 10μA 전류 이상의 높은 리드 전류(read current)를 가질 수 도 있다.In addition, the 2-terminal thyristor-based 1T DRAM 300 induces a latch-up when the state of the first base layer 320 is high in the read state, thereby causing the memory state to be " 1", when the state of the first base layer 320 is low, causing blocking, resulting in a memory state of "0", a low off current of pA level and about 10 μA current It may have a high read current.
도 4a는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램의 에너지 밴드 다이어그램을 설명하는 도면이다.4A is a diagram illustrating an energy band diagram of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
도 4a를 참고하면, 2단자 수직형 사이리스터 기반 1T 디램의 각 층에서의 양극 전압(400)과 음극 전압(401)의 변화를 예시한다.Referring to FIG. 4A, changes in the anode voltage 400 and the cathode voltage 401 in each layer of a two-terminal vertical thyristor-based 1T DRAM are illustrated.
예를 들어, 2단자 수직형 사이리스터 기반 1T 디램의 제1 베이스층과 제2 베이스층은 그래프 가로축 상의 0.2 밀리미터와 0.3 밀리미터 사이에 위치될 수 있다.For example, the first base layer and the second base layer of the two-terminal vertical thyristor-based 1T DRAM may be located between 0.2 mm and 0.3 mm on the horizontal axis of the graph.
도 2a와 대비하면, 래치 다운 전압의 하강이 상대적으로 작으므로, 보다 높은 메모리 마진이 확보될 수 있다.Compared to FIG. 2A, since the fall of the latch-down voltage is relatively small, a higher memory margin can be secured.
도 4b는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램의 전기적 특성을 설명하는 도면이다.4B is a diagram illustrating electrical characteristics of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
보다 구체적으로, 도 4b는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램에서 300K 내지 400K의 온도 범위 변화에 기반하여 양극 전류에 따른 양극 전압의 변화에 해당하는 전기적 특성을 예시한다.More specifically, FIG. 4B illustrates electrical characteristics corresponding to a change in the anode voltage according to the anode current based on a temperature range change of 300K to 400K in a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention. .
도 2b와 도 4b를 대비할 때, 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램이 높은 온도 범위에서 양극 전압의 감소가 상대적으로 작다.2B and 4B, the reduction of the anode voltage is relatively small in the high temperature range of the 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
따라서, 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램은 종래의 2단자 수직형 사이리스터 기반 1T 디램에 대비하여 상대적으로 높은 메모리 마진을 확보할 수 있다.Accordingly, the 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention can secure a relatively high memory margin compared to the conventional 2-terminal vertical thyristor-based 1T DRAM.
즉, 본 발명은 양극 또는 음극 중 적어도 하나와 연결되는 에미터층을 쇼트키 컨택(schottky contact)을 이용하여 메탈 물질로 대체함으로써 고온에서도 메모리의 동작 안정성을 확보할 수 있다.That is, the present invention can secure the operational stability of the memory even at high temperatures by replacing the emitter layer connected to at least one of the anode or the cathode with a metal material using a Schottky contact.
도 4c는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램의 동작 온도 의존성을 설명하는 도면이다.4C is a diagram illustrating the operating temperature dependence of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
보다 구체적으로, 도 4c는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램에서 300K 내지 400K의 온도 범위 변화에 기반한 래치 업 전압(VLU)과 래치 다운 전압(VLD)의 변화를 예시한다.More specifically, FIG. 4C shows the change of the latch-up voltage (V LU ) and the latch-down voltage (V LD ) based on a temperature range change of 300K to 400K in a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention. To illustrate.
도 2c와 도 4c를 대비할 때, 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램이 높은 온도 범위에서 래치 업 전압(VLU)과 래치 다운 전압(VLD)의 감소가 상대적으로 작다.2C and 4C, the reduction of the latch-up voltage (V LU ) and the latch-down voltage (V LD ) is relatively high in the high temperature range of the 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention. small.
따라서, 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램은 종래의 2단자 수직형 사이리스터 기반 1T 디램에 대비하여 상대적으로 높은 메모리 마진을 확보할 수 있다.Accordingly, the 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention can secure a relatively high memory margin compared to the conventional 2-terminal vertical thyristor-based 1T DRAM.
즉, 본 발명은 에미터층을 쇼트키 컨택(schottky contact)을 이용하여 메탈 물질로 대체함으로써 메모리의 동작 온도 의존성을 감소시킬 수 있다.That is, the present invention can reduce the dependence of the operating temperature of the memory by replacing the emitter layer with a metal material using a Schottky contact.
도 5는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램의 제조 방법과 관련된 흐름도를 설명하는 도면이다.5 is a view for explaining a flowchart related to a method of manufacturing a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
도 5를 참고하면, 단계(501)에서 2단자 수직형 사이리스터 기반 1T 디램의 제조 방법은 제1 도전형 물질을 이용하여 제1 에미터층을 형성한다.Referring to FIG. 5, in step 501, a method of manufacturing a 2-terminal vertical thyristor-based 1T DRAM forms a first emitter layer using a first conductivity type material.
즉, 2단자 수직형 사이리스터 기반 1T 디램의 제조 방법은 제1 도전형의 불순물을 기판 상에 도핑하여 제1 에미터층을 형성할 수 있다.That is, in the method of manufacturing a two-terminal vertical thyristor-based 1T DRAM, a first emitter layer may be formed by doping impurities of a first conductivity type on a substrate.
예를 들어, 제1 에미터층은 음극으로서 동작되거나 음극에 연결될 수 있다.For example, the first emitter layer can be operated as a cathode or connected to the cathode.
단계(502)에서 2단자 수직형 사이리스터 기반 1T 디램의 제조 방법은 제2 도전형 물질을 이용하여 제1 베이스층을 형성할 수 있다.In step 502, a method of manufacturing a two-terminal vertical thyristor-based 1T DRAM may form a first base layer using a second conductive material.
즉, 2단자 수직형 사이리스터 기반 1T 디램의 제조 방법은 제1 에미터층 상에 제2 도전형의 분순물을 도핑하여 제1 베이스층을 수직 형성할 수 있다.That is, in the method of manufacturing a 2-terminal vertical thyristor-based 1T DRAM, a first base layer may be vertically formed by doping a second conductive type impurity on the first emitter layer.
단계(503)에서 2단자 수직형 사이리스터 기반 1T 디램의 제조 방법은 제1 도전형 물질을 이용하여 제2 베이스층을 형성한다.In step 503, a method of manufacturing a two-terminal vertical thyristor-based 1T DRAM forms a second base layer using a first conductivity type material.
즉, 2단자 수직형 사이리스터 기반 1T 디램의 제조 방법은 제1 베이스층 상에 제1 도전형의 분순물을 도핑하여 제2 베이스층을 수직 형성할 수 있다.That is, in the method of manufacturing a two-terminal vertical thyristor-based 1T DRAM, a second base layer may be vertically formed by doping a first conductive type impurity on the first base layer.
단계(504)에서 2단자 수직형 사이리스터 기반 1T 디램의 제조 방법은 금속물질을 이용하여 제2 에미터층을 형성할 수 있다.In step 504, a method of manufacturing a two-terminal vertical thyristor-based 1T DRAM may use a metal material to form a second emitter layer.
즉, 2단자 수직형 사이리스터 기반 1T 디램의 제조 방법은 제2 베이스(층 상에 상기 제2 베이스(base)층과 쇼트키 컨택(Schottky Contact)을 이루는 메탈 물질을 이용하여 제2 에미터층을 수직 형성할 수 있다.That is, the method of manufacturing a two-terminal vertical thyristor-based 1T DRAM uses a metal material that forms a second base (Schottky Contact with the second base layer on the layer) and vertically emits the second emitter layer. Can form.
예를 들어, 제2 에미터층은 양극으로서 동작되거나 양극에 연결될 수 있다.For example, the second emitter layer can be operated as an anode or connected to the anode.
도 6a는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램의 이중 적층 구조를 설명하는 도면이다.6A is a diagram illustrating a double-layer structure of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
보다 구체적으로, 도 6a는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램에서 이중 적층 구조를 예시한다.More specifically, FIG. 6A illustrates a double stacked structure in a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
도 6a를 참고하면, 2단자 수직형 사이리스터 기반 1T 디램(600)은 기판(610) 상에 형성될 수 있으며, 제1 에미터층(620), 제1 베이스층(630), 제2 베이스층(640), 제2 에미터층(650), 제3 베이스층(641), 제4 베이스층(631) 및 제3 에미터층(621)을 포함하여 형성될 수 있다.Referring to FIG. 6A, a two-terminal vertical thyristor-based 1T DRAM 600 may be formed on a substrate 610, and includes a first emitter layer 620, a first base layer 630, and a second base layer ( 640), a second emitter layer 650, a third base layer 641, a fourth base layer 631 and a third emitter layer 621 may be formed.
일례로, 제1 에미터층(620)은 제1 도전형 물질로 형성될 수 있으며, 고농도의 제1 불순물이 도핑될 수 있다.For example, the first emitter layer 620 may be formed of a first conductive type material, and a high concentration of first impurities may be doped.
본 발명의 일실시예에 따르면 제1 베이스층(630)은 제1 에미터층(620) 상에 제2 도전형 물질로 수직 형성될 수 있으며, 제1 에미터층(620)의 도핑 농도보다 상대적으로 낮은 농도의 제2 불순물이 도핑되어 형성될 수 있다.According to an embodiment of the present invention, the first base layer 630 may be vertically formed of a second conductive type material on the first emitter layer 620, and is relatively relatively doped than the doping concentration of the first emitter layer 620. The second impurity at a low concentration may be formed by doping.
일례로, 제2 베이스층(640)은 제1 베이스층(630) 상에 제1 도전형 물질로 수직 형성될 수 있으며, 제1 베이스층(630)의 도핑 농도와 동일한 농도의 제1 불순물이 도핑되어 형성될 수 있다.For example, the second base layer 640 may be vertically formed of a first conductive type material on the first base layer 630, and the first impurity having the same concentration as the doping concentration of the first base layer 630 may be It can be formed by doping.
예를 들어, 제2 에미터층(650)은 제2 베이스층(640) 상에 제2 베이스층(640)과 쇼트키 컨택(Schottky Contact)을 이루는 메탈 물질로 수직 형성될 수 있다. 또한, 제2 에미터층(650)은 메탈층으로도 지칭될 수 있다.For example, the second emitter layer 650 may be vertically formed of a metal material that forms a Schottky contact with the second base layer 640 on the second base layer 640. In addition, the second emitter layer 650 may also be referred to as a metal layer.
일례로, 제3 베이스층(641)은 제2 에미터층(650) 상에 제1 도전형 물질로 수직 형성될 수 있다.For example, the third base layer 641 may be vertically formed of the first conductive type material on the second emitter layer 650.
본 발명의 일실시예에 따르면 제4 베이스층(631)은 제3 베이스층(641) 상에 제2 도전형 물질로 수직 형성될 수 있다.According to an embodiment of the present invention, the fourth base layer 631 may be vertically formed of a second conductive type material on the third base layer 641.
일례로, 제3 에미터층(621)은 제4 베이스층(631) 상에 제1 도전형 물질로 수직 형성될 수 있다.For example, the third emitter layer 621 may be vertically formed of a first conductive type material on the fourth base layer 631.
예를 들어, 제2 에미터층(650)은 양극으로 동작하고, 제1 에미터층(620) 및 제3 에미터층(621)은 음극으로 동작될 수 있다.For example, the second emitter layer 650 may function as an anode, and the first emitter layer 620 and the third emitter layer 621 may act as a cathode.
도 6b는 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램의 이중 적층 구조를 설명하는 도면이다.6B is a diagram illustrating a double-layer structure of a 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention.
보다 구체적으로, 도 6b는 도 6a에서 설명된 2단자 수직형 사이리스터 기반 1T 디램의 3차원 입체도를 예시한다.More specifically, FIG. 6B illustrates a three-dimensional stereogram of the two-terminal vertical thyristor-based 1T DRAM described in FIG. 6A.
도 6b를 참고하면, 2단자 수직형 사이리스터 기반 1T 디램(600)은 기판(610) 상에 형성될 수 있으며, 제1 에미터층(620), 제1 베이스층(630), 제2 베이스층(640), 제2 에미터층(650)을 포함하고, 제2 에미터층(650) 상에 제2 베이스층(640)과 동일한 물질을 이용하여 제3 베이스층이 수직 형성되고, 제3 베이스층 상에 제1 베이스층(630)과 동일한 물질을 이용하여 제4 베이스층이 수직 형성되며, 제4 베이스층 상에 제1 에미터층(620)과 동일한 물질을 이용하여 제3 에미터층이 수직 형성될 수 있다.Referring to FIG. 6B, a two-terminal vertical thyristor-based 1T DRAM 600 may be formed on a substrate 610, and includes a first emitter layer 620, a first base layer 630, and a second base layer ( 640), including a second emitter layer 650, a third base layer is vertically formed using the same material as the second base layer 640 on the second emitter layer 650, and on the third base layer A fourth base layer is vertically formed using the same material as the first base layer 630, and a third emitter layer is vertically formed using the same material as the first emitter layer 620 on the fourth base layer. Can be.
본 발명의 일실시예에 따르면 제1 에미터층(620)과 제3 에미터층은 비트 라인에 연결되고, 제2 에미터층(650)은 워드 라인에 연결될 수 있다.According to an embodiment of the present invention, the first emitter layer 620 and the third emitter layer may be connected to a bit line, and the second emitter layer 650 may be connected to a word line.
일례로, 2단자 수직형 사이리스터 기반 1T 디램(600)은 이중 적층 구조에 기반하여 크로스 포인트(cross-point) 메모리 소자로서 동작될 수 있다.For example, the two-terminal vertical thyristor-based 1T DRAM 600 may be operated as a cross-point memory device based on a double-stacked structure.
예를 들어, 2단자 수직형 사이리스터 기반 1T 디램(600)은 3D 크로스 포인트 메모리 소자로도 지칭될 수 있다.For example, the 2-terminal vertical thyristor-based 1T DRAM 600 may also be referred to as a 3D cross-point memory device.
도 7a는 종래의 이중 적층 구조를 갖는 2단자 수직형 사이리스터 기반 1T 디램의 에너지 밴드 다이어그램을 설명하는 도면이고, 도 7b는 본 발명의 일실시예에 따른 이중 적층 구조를 갖는 2단자 수직형 사이리스터 기반 1T 디램의 에너지 밴드 다이어그램을 설명하는 도면이다.7A is a diagram illustrating an energy band diagram of a conventional 2T vertical thyristor-based 1T DRAM having a dual-stack structure, and FIG. 7B is a 2-terminal vertical thyristor-based double-stack structure according to an embodiment of the present invention. It is a diagram to explain the energy band diagram of 1T DRAM.
도 7a를 참고하면, 종래의 2단자 수직형 사이리스터 기반 1T 디램의 각 층에서의 양극 전압(700)과 음극 전압(701)의 변화를 예시한다.Referring to FIG. 7A, a change in the anode voltage 700 and the cathode voltage 701 in each layer of a conventional two-terminal vertical thyristor-based 1T DRAM is illustrated.
또한, 도 7b를 참고하면, 종래의 2단자 수직형 사이리스터 기반 1T 디램의 각 층에서의 양극 전압(710)과 음극 전압(711)의 변화를 예시한다.In addition, referring to FIG. 7B, changes in the anode voltage 710 and the cathode voltage 711 in each layer of a conventional two-terminal vertical thyristor-based 1T DRAM are illustrated.
도 7a와 도 7b에 기반하여 2단자 수직형 사이리스터 기반 1T 디램에서 0.3 내지 0.4의 접합부에서의 양극 전압(710)과 음극 전압(711)의 변화의 차이를 대비할 수 있다.Based on FIGS. 7A and 7B, it is possible to prepare for a difference between a change in the anode voltage 710 and the cathode voltage 711 at a junction of 0.3 to 0.4 in a 2-terminal vertical thyristor-based 1T DRAM.
본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램은 0.3 내지 0.4의 접합부에 베이스층과 쇼트키 컨택을 이루는 메탈층의 양극이 위치될 수 있다.In the two-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention, an anode of a metal layer forming a Schottky contact with a base layer may be positioned at a junction of 0.3 to 0.4.
도 7a와 도 7b를 대비하면, 본 발명의 일실시예에 따른 따른 2단자 수직형 사이리스터 기반 1T 디램은 래치 다운 전압의 하강이 상대적으로 작으므로, 보다 높은 메모리 마진이 확보될 수 있다.7A and 7B, the two-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention has a relatively small drop in the latch-down voltage, so a higher memory margin can be secured.
도 8a는 종래의 이중 적층 구조를 갖는 2단자 수직형 사이리스터 기반 1T 디램의 전기적 특성을 설명하는 도면이고, 도 8b는 본 발명의 일실시예에 따른 이중 적층 구조를 갖는 2단자 수직형 사이리스터 기반 1T 디램의 전기적 특성을 설명하는 도면이다.8A is a diagram for explaining electrical characteristics of a conventional 2-terminal vertical thyristor-based 1T DRAM having a dual-stacked structure, and FIG. 8B is a 2-terminal vertical thyristor-based 1T having a dual-stacked structure according to an embodiment of the present invention. This diagram explains the electrical characteristics of DRAM.
도 8a와 도 8b를 대비하면, 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램이 높은 온도 범위에서 양극 전압의 감소가 상대적으로 작다.8A and 8B, a two-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention has a relatively small decrease in anode voltage in a high temperature range.
따라서, 본 발명의 일실시예에 따른 2단자 수직형 사이리스터 기반 1T 디램은 종래의 2단자 수직형 사이리스터 기반 1T 디램에 대비하여 상대적으로 높은 메모리 마진을 확보할 수 있다.Accordingly, the 2-terminal vertical thyristor-based 1T DRAM according to an embodiment of the present invention can secure a relatively high memory margin compared to the conventional 2-terminal vertical thyristor-based 1T DRAM.
이상에서 설명된 장치는 하드웨어 구성요소, 소프트웨어 구성요소, 및/또는 하드웨어 구성요소 및 소프트웨어 구성요소의 조합으로 구현될 수 있다. 예를 들어, 실시예들에서 설명된 장치 및 구성요소는, 예를 들어, 프로세서, 콘트롤러, ALU(arithmetic logic unit), 디지털 신호 프로세서(digital signal processor), 마이크로컴퓨터, FPA(field programmable array), PLU(programmable logic unit), 마이크로프로세서, 또는 명령(instruction)을 실행하고 응답할 수 있는 다른 어떠한 장치와 같이, 하나 이상의 범용 컴퓨터 또는 특수 목적 컴퓨터를 이용하여 구현될 수 있다. 처리 장치는 운영 체제(OS) 및 상기 운영 체제 상에서 수행되는 하나 이상의 소프트웨어 애플리케이션을 수행할 수 있다. 또한, 처리 장치는 소프트웨어의 실행에 응답하여, 데이터를 접근, 저장, 조작, 처리 및 생성할 수도 있다. 이해의 편의를 위하여, 처리 장치는 하나가 사용되는 것으로 설명된 경우도 있지만, 해당 기술분야에서 통상의 지식을 가진 자는, 처리 장치가 복수 개의 처리 요소(processing element) 및/또는 복수 유형의 처리 요소를 포함할 수 있음을 알 수 있다. 예를 들어, 처리 장치는 복수 개의 프로세서 또는 하나의 프로세서 및 하나의 콘트롤러를 포함할 수 있다. 또한, 병렬 프로세서(parallel processor)와 같은, 다른 처리 구성(processing configuration)도 가능하다.The device described above may be implemented with hardware components, software components, and/or combinations of hardware components and software components. For example, the devices and components described in the embodiments include, for example, processors, controllers, arithmetic logic units (ALUs), digital signal processors (micro signal processors), microcomputers, field programmable arrays (FPAs), It may be implemented using one or more general purpose computers or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. The processing device may run an operating system (OS) and one or more software applications running on the operating system. In addition, the processing device may access, store, manipulate, process, and generate data in response to the execution of the software. For convenience of understanding, a processing device may be described as one being used, but a person having ordinary skill in the art, the processing device may include a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that may include. For example, the processing device may include a plurality of processors or a processor and a controller. In addition, other processing configurations, such as parallel processors, are possible.
실시예에 따른 방법은 다양한 컴퓨터 수단을 통하여 수행될 수 있는 프로그램 명령 형태로 구현되어 컴퓨터 판독 가능 매체에 기록될 수 있다. 상기 컴퓨터 판독 가능 매체는 프로그램 명령, 데이터 파일, 데이터 구조 등을 단독으로 또는 조합하여 포함할 수 있다. 상기 매체에 기록되는 프로그램 명령은 실시예를 위하여 특별히 설계되고 구성된 것들이거나 컴퓨터 소프트웨어 당업자에게 공지되어 사용 가능한 것일 수도 있다. 컴퓨터 판독 가능 기록 매체의 예에는 하드 디스크, 플로피 디스크 및 자기 테이프와 같은 자기 매체(magnetic media), CD-ROM, DVD와 같은 광기록 매체(optical media), 플롭티컬 디스크(floptical disk)와 같은 자기-광 매체(magneto-optical media), 및 롬(ROM), 램(RAM), 플래시 메모리 등과 같은 프로그램 명령을 저장하고 수행하도록 특별히 구성된 하드웨어 장치가 포함된다. 프로그램 명령의 예에는 컴파일러에 의해 만들어지는 것과 같은 기계어 코드뿐만 아니라 인터프리터 등을 사용해서 컴퓨터에 의해서 실행될 수 있는 고급 언어 코드를 포함한다. 상기된 하드웨어 장치는 실시예의 동작을 수행하기 위해 하나 이상의 소프트웨어 모듈로서 작동하도록 구성될 수 있으며, 그 역도 마찬가지이다.The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, or the like alone or in combination. The program instructions recorded in the medium may be specially designed and configured for the embodiments or may be known and usable by those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs, DVDs, and magnetic media such as floptical disks. -Hardware devices specifically configured to store and execute program instructions such as magneto-optical media, and ROM, RAM, flash memory, and the like. Examples of program instructions include high-level language code that can be executed by a computer using an interpreter, etc., as well as machine language codes produced by a compiler. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.
이상과 같이 실시예들이 비록 한정된 도면에 의해 설명되었으나, 해당 기술분야에서 통상의 지식을 가진 자라면 상기의 기재로부터 다양한 수정 및 변형이 가능하다. 예를 들어, 설명된 기술들이 설명된 방법과 다른 순서로 수행되거나, 및/또는 설명된 시스템, 구조, 장치, 회로 등의 구성요소들이 설명된 방법과 다른 형태로 결합 또는 조합되거나, 다른 구성요소 또는 균등물에 의하여 대치되거나 치환되더라도 적절한 결과가 달성될 수 있다.Although the embodiments have been described by the limited drawings as described above, a person skilled in the art can make various modifications and variations from the above description. For example, the described techniques are performed in a different order than the described method, and/or the components of the described system, structure, device, circuit, etc. are combined or combined in a different form from the described method, or other components Alternatively, even if replaced or substituted by equivalents, appropriate results can be achieved.
그러므로, 다른 구현들, 다른 실시예들 및 특허청구범위와 균등한 것들도 후술하는 특허청구범위의 범위에 속한다.Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (12)

  1. 제1 도전형 물질로 형성되는 제1 에미터(emitter)층;A first emitter layer formed of a first conductive type material;
    상기 제1 에미터(emitter)층 상에 제2 도전형 물질로 수직 형성되는 제1 베이스(base)층;A first base layer vertically formed of a second conductive type material on the first emitter layer;
    상기 제1 베이스(base)층 상에 상기 제1 도전형 물질로 수직 형성되는 제2 베이스(base)층; 및A second base layer vertically formed of the first conductive material on the first base layer; And
    상기 제2 베이스(base)층 상에 상기 제2 베이스(base)층과 쇼트키 컨택(Schottky Contact)을 이루는 메탈 물질로 수직 형성되는 제2 에미터(emitter)층을 포함하는And a second emitter layer vertically formed of a metal material forming a Schottky contact with the second base layer on the second base layer.
    2단자 수직형 사이리스터 기반 1T 디램.2-terminal thyristor-based 1T DRAM.
  2. 제1항에 있어서,According to claim 1,
    상기 메탈 물질은 금(Au), 코발트(Co), 구리(Cu), 철(Fe), 니켈(Ni), 팔라듐(Pd), 백금(Pt), 류테늄(Ru) 중 적어도 하나 이상을 포함하는The metal material includes at least one of gold (Au), cobalt (Co), copper (Cu), iron (Fe), nickel (Ni), palladium (Pd), platinum (Pt), and ruthenium (Ru) doing
    2단자 수직형 사이리스터 기반 1T 디램.2-terminal thyristor-based 1T DRAM.
  3. 제1항에 있어서,According to claim 1,
    상기 제1 에미터(emitter)층은 상기 제1 도전형 물질을 대체하여 상기 제1 베이스(base)층과 쇼트키 컨택(Schottky Contact)을 이루는 메탈 물질로 형성되는The first emitter layer is formed of a metal material that forms a Schottky contact with the first base layer by replacing the first conductive type material.
    2단자 수직형 사이리스터 기반 1T 디램.2-terminal thyristor-based 1T DRAM.
  4. 제1항에 있어서,According to claim 1,
    상기 제2 에미터(emitter)층은 300K 내지 400K의 온도 범위에서 1.58V 내지 2.83V의 래치 업 전압(latch up voltage)을 출력하는The second emitter layer outputs a latch up voltage of 1.58V to 2.83V in a temperature range of 300K to 400K.
    2단자 수직형 사이리스터 기반 1T 디램.2-terminal thyristor-based 1T DRAM.
  5. 제1항에 있어서,According to claim 1,
    상기 제2 에미터(emitter)층은 300K 내지 400K의 온도 범위에서 0.8V 내지 0.89V의 래치 다운 전압(latch down voltage)을 출력하는The second emitter layer outputs a latch down voltage of 0.8V to 0.89V in a temperature range of 300K to 400K.
    2단자 수직형 사이리스터 기반 1T 디램.2-terminal thyristor-based 1T DRAM.
  6. 제1항에 있어서,According to claim 1,
    상기 제1 도전형 물질은 n형 불순물을 포함하고,The first conductive type material contains n-type impurities,
    상기 제2 도전형 물질은 p형 불순물을 포함하는 The second conductivity-type material includes p-type impurities
    2단자 수직형 사이리스터 기반 1T 디램.2-terminal thyristor-based 1T DRAM.
  7. 메탈 물질로 형성되는 제1 에미터(emitter)층;A first emitter layer formed of a metal material;
    상기 제1 에미터(emitter)층 상에 상기 제1 에미터(emitter)층과 쇼트키 컨택(Schottky Contact)을 이루는 제2 도전형 물질로 수직 형성되는 제1 베이스(base)층;A first base layer vertically formed of a second conductive type material forming a Schottky Contact with the first emitter layer on the first emitter layer;
    상기 제1 베이스(base)층 상에 상기 제1 도전형 물질로 수직 형성되는 제2 베이스(base)층; 및A second base layer vertically formed of the first conductive material on the first base layer; And
    상기 제2 베이스(base)층 상에 제2 도전형 물질로 수직 형성되는 제2 에미터(emitter)층을 포함하는And a second emitter layer vertically formed of a second conductive type material on the second base layer.
    2단자 수직형 사이리스터 기반 1T 디램.2-terminal thyristor-based 1T DRAM.
  8. 제7항에 있어서,The method of claim 7,
    상기 제2 에미터(emitter)층은 상기 제2 도전형 물질을 대체하여 상기 제2 베이스(base)층과 쇼트키 컨택(Schottky Contact)을 이루는 메탈 물질로 형성되는The second emitter layer is formed of a metal material that forms a Schottky contact with the second base layer by replacing the second conductive type material.
    2단자 수직형 사이리스터 기반 1T 디램.2-terminal thyristor-based 1T DRAM.
  9. 제7항에 있어서,The method of claim 7,
    상기 메탈 물질은 금(Au), 코발트(Co), 구리(Cu), 철(Fe), 니켈(Ni), 팔라듐(Pd), 백금(Pt), 류테늄(Ru) 중 적어도 하나 이상을 포함하고,The metal material includes at least one of gold (Au), cobalt (Co), copper (Cu), iron (Fe), nickel (Ni), palladium (Pd), platinum (Pt), and ruthenium (Ru) and,
    상기 제1 도전형 물질은 n형 불순물을 포함하며,The first conductivity-type material includes an n-type impurity,
    상기 제2 도전형 물질은 p형 불순물을 포함하는 The second conductivity-type material includes p-type impurities
    2단자 수직형 사이리스터 기반 1T 디램.2-terminal thyristor-based 1T DRAM.
  10. 제1 도전형 물질로 형성되는 제1 에미터(emitter)층;A first emitter layer formed of a first conductive type material;
    상기 제1 에미터(emitter)층 상에 제2 도전형 물질로 수직 형성되는 제1 베이스(base)층;A first base layer vertically formed of a second conductive type material on the first emitter layer;
    상기 제1 베이스층 상에 상기 제1 도전형 물질로 수직 형성되는 제2 베이스(base)층;A second base layer vertically formed of the first conductivity type material on the first base layer;
    상기 제2 베이스(base)층 상에 상기 제2 베이스(base)층과 쇼트키 컨택(Schottky Contact)을 이루는 메탈 물질로 수직 형성되는 제2 에미터(emitter)층;A second emitter layer vertically formed of a metal material forming a Schottky contact with the second base layer on the second base layer;
    상기 제2 에미터(emitter)층 상에 상기 제1 도전형 물질로 수직 형성되는 제3 베이스(base)층;A third base layer vertically formed of the first conductivity type material on the second emitter layer;
    상기 제3 베이스(base)층 상에 상기 제2 도전형 물질로 수직 형성되는 제4 베이스(base)층; 및A fourth base layer vertically formed of the second conductive type material on the third base layer; And
    상기 제4 베이스(base)층 상에 상기 제1 도전형 물질로 형성되는 제3 에미터(emitter)층을 포함하는A third emitter layer formed of the first conductive type material on the fourth base layer
    2단자 수직형 사이리스터 기반 1T 디램.2-terminal thyristor-based 1T DRAM.
  11. 제10항에 있어서,The method of claim 10,
    상기 메탈 물질은 금(Au), 코발트(Co), 구리(Cu), 철(Fe), 니켈(Ni), 팔라듐(Pd), 백금(Pt), 류테늄(Ru) 중 적어도 하나 이상을 포함하고,The metal material includes at least one of gold (Au), cobalt (Co), copper (Cu), iron (Fe), nickel (Ni), palladium (Pd), platinum (Pt), and ruthenium (Ru) and,
    상기 제1 도전형 물질은 n형 불순물을 포함하며,The first conductivity-type material includes an n-type impurity,
    상기 제2 도전형 물질은 p형 불순물을 포함하는 The second conductivity-type material includes p-type impurities
    2단자 수직형 사이리스터 기반 1T 디램.2-terminal thyristor-based 1T DRAM.
  12. 제10항에 있어서,The method of claim 10,
    상기 제2 에미터(emitter)층은 300K 내지 400K의 온도 범위에서 1.58V 내지 2.83V의 래치 업 전압(latch up voltage)을 출력하고, 0.8V 내지 0.89V의 래치 다운 전압(latch down voltage)을 출력하는The second emitter layer outputs a latch up voltage of 1.58V to 2.83V in a temperature range of 300K to 400K, and a latch down voltage of 0.8V to 0.89V. Output
    2단자 수직형 사이리스터 기반 1T 디램.2-terminal thyristor-based 1T DRAM.
PCT/KR2019/014087 2018-11-27 2019-10-24 Two-terminal vertical type thyristor-based 1t dram WO2020111521A1 (en)

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