WO2020109901A1 - 半導体装置、二次電池システム - Google Patents

半導体装置、二次電池システム Download PDF

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Publication number
WO2020109901A1
WO2020109901A1 PCT/IB2019/059724 IB2019059724W WO2020109901A1 WO 2020109901 A1 WO2020109901 A1 WO 2020109901A1 IB 2019059724 W IB2019059724 W IB 2019059724W WO 2020109901 A1 WO2020109901 A1 WO 2020109901A1
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Prior art keywords
semiconductor device
transistor
insulating layer
secondary battery
semiconductor
Prior art date
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Ceased
Application number
PCT/IB2019/059724
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English (en)
French (fr)
Japanese (ja)
Inventor
松嵜隆徳
池田隆之
上妻宗広
田島亮太
井上広樹
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to US17/291,021 priority Critical patent/US12444779B2/en
Priority to JP2020557015A priority patent/JP7419258B2/ja
Publication of WO2020109901A1 publication Critical patent/WO2020109901A1/ja
Anticipated expiration legal-status Critical
Priority to JP2024001681A priority patent/JP7753410B2/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/48—Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
    • H01M10/486—Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte for measuring temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/48—Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or discharging batteries or for supplying loads from batteries
    • H02J7/80—Circuit arrangements for charging or discharging batteries or for supplying loads from batteries including monitoring or indicating arrangements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or discharging batteries or for supplying loads from batteries
    • H02J7/90—Regulation of charging or discharging current or voltage
    • H02J7/971—Regulation of charging or discharging current or voltage the charge cycle being controlled or terminated in response to non-electric parameters
    • H02J7/975—Regulation of charging or discharging current or voltage the charge cycle being controlled or terminated in response to non-electric parameters in response to temperature
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M10/00—Secondary cells; Manufacture thereof
    • H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
    • H01M10/425—Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing
    • H01M2010/4278—Systems for data transfer from batteries, e.g. transfer of battery parameters to a controller, data transferred between battery controller and main controller
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

Definitions

  • One aspect of the present invention relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • One embodiment of the present invention relates to a semiconductor device, a display device, a light emitting device, a power storage device, a lighting device, or an electronic device. Further, one embodiment of the present invention relates to a charge control method for a power storage device. Further, one embodiment of the present invention relates to a charging device.
  • a power storage device (also referred to as a “battery” or a “secondary battery”) refers to all elements and devices having a power storage function.
  • a storage battery such as a lithium ion secondary battery (also referred to as a secondary battery), a lithium ion capacitor, a nickel hydrogen battery, an all-solid-state battery, an electric double layer capacitor, or the like is included.
  • Oxide semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors (OS: Oxide Semiconductor) are attracting attention as other materials.
  • oxide semiconductors for example, not only oxides of single-element metals such as indium oxide and zinc oxide but also oxides of multi-element metals are known.
  • oxides of multi-component metals researches on In-Ga-Zn oxides (hereinafter, also referred to as IGZO) are being actively conducted.
  • Non-Patent Documents 1 to 3 As a result of research on IGZO, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are neither single crystal nor amorphous, have been found in oxide semiconductors (see Non-Patent Documents 1 to 3). ..).
  • Non-Patent Documents 1 and 2 also disclose a technique of manufacturing a transistor using an oxide semiconductor having a CAAC structure. Further, Non-Patent Document 4 and Non-Patent Document 5 show that even an oxide semiconductor having lower crystallinity than the CAAC structure and the nc structure has minute crystals.
  • Non-Patent Document 6 a transistor using IGZO as an active layer has an extremely low off-current (see Non-Patent Document 6), and an LSI and a display utilizing its characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8). ..).
  • lithium-ion secondary batteries with high output and high energy density are used for portable information terminals such as mobile phones, smartphones, and notebook personal computers, portable music players, electronic devices such as digital cameras, medical devices, and hybrid vehicles (HEV). ), electric vehicles (EVs), or next-generation clean energy vehicles such as plug-in hybrid vehicles (PHEVs), the demand for which is rapidly expanding with the development of the semiconductor industry, and modern information is available as a source of rechargeable energy. Has become indispensable to a socialized society.
  • the characteristics required of lithium ion batteries include higher energy density, improved cycle characteristics, safety in various operating environments, and improved long-term reliability.
  • Patent Document 1 As an example of a lithium ion battery, at least a positive electrode, a negative electrode, and an electrolytic solution are included (Patent Document 1).
  • Patent Document 2 discloses a battery state detection device that detects a minute short circuit of a secondary battery and a battery pack including the same.
  • JP 2012-9418 A JP, 2010-66161, A
  • An object of one embodiment of the present invention is to provide a novel semiconductor device which is highly convenient or reliable. Another object is to provide a novel secondary battery system which is highly convenient or reliable. Another object is to provide a novel semiconductor device or a novel secondary battery system.
  • a method of flowing a constant current between both electrodes until the voltage between the positive electrode and the negative electrode of the power storage device reaches a constant value is often used.
  • the optimum current value for charging the power storage device depends on the constituent materials of the positive electrode, the negative electrode, and the electrolytic solution.
  • One object of one embodiment of the present invention is to provide a semiconductor device which realizes charging in which deterioration of a power storage device does not easily occur. Another object is to provide a charging method in which deterioration of a power storage device does not easily occur. Another object is to provide a charging method in which a power storage device is not easily damaged. Another object is to provide a novel semiconductor device. Another object is to provide a new charging device. Another object is to provide a new charging method.
  • One embodiment of the present invention is a semiconductor device including a detection portion, a first storage portion, a second storage portion, and a determination portion.
  • the detection unit supplies the detection signal, and the first storage unit holds the detection signal.
  • the second storage unit holds standard data and tolerance information.
  • the determination unit compares the detection signal with the standard data, and the determination unit supplies the control signal when there is a deviation exceeding the tolerance information between the detection signal and the standard data.
  • One embodiment of the present invention is the above semiconductor device having a control portion.
  • the control unit supplies a selection signal.
  • the first memory portion includes a group of memory elements and a selection circuit, and the group of memory elements includes the memory elements.
  • the storage element holds the detection signal.
  • the selection circuit selects the storage element based on the selection signal.
  • the first storage unit can hold a plurality of detection signals obtained by, for example, sampling a plurality of times.
  • a plurality of detection signals obtained by detecting a plurality of different events such as voltage, current, and temperature can be held.
  • a detection signal that changes over time can be held together with information on the detection time.
  • the detection signal that changes with wear can be held together with information on the usage history.
  • the control signal can be supplied by detecting a deviation exceeding the tolerance information.
  • One embodiment of the present invention is the above semiconductor device, in which the selection circuit includes a switch.
  • the selection circuit includes a source follower circuit.
  • one embodiment of the present invention is the above semiconductor device in which the memory element includes a semiconductor layer and the semiconductor layer includes an oxide semiconductor.
  • the detection signal can be held.
  • the detection signal can be rewritten repeatedly.
  • deterioration of the memory element due to rewriting can be reduced.
  • a novel semiconductor device with excellent convenience or reliability can be provided.
  • one embodiment of the present invention is a semiconductor device including the first semiconductor device and the above semiconductor device.
  • the first semiconductor device has a function of supplying a predetermined current or a predetermined voltage, and the first semiconductor device is electrically connected to the second semiconductor device.
  • the first semiconductor device is supplied with the control signal, and the first semiconductor device operates based on the control signal.
  • the first semiconductor device can be feedback-controlled using the second semiconductor device.
  • a novel semiconductor device with excellent convenience or reliability can be provided.
  • one embodiment of the present invention is the above semiconductor device in which the detection unit includes a voltage detector.
  • the voltage detector measures the voltage required to supply a predetermined current.
  • the second storage unit holds standard data regarding voltage.
  • the abnormality of the first semiconductor device electrically connected to the second semiconductor device can be monitored using voltage.
  • an abnormality of the load electrically connected to the first semiconductor device can be monitored by using the voltage.
  • one embodiment of the present invention is the above semiconductor device, in which the detection unit includes a current detector.
  • the current detector measures the current required to supply a predetermined voltage.
  • the second storage unit holds standard data regarding current.
  • the abnormality of the first semiconductor device electrically connected to the second semiconductor device can be monitored using current.
  • the abnormality of the load electrically connected to the first semiconductor device can be monitored using current.
  • the detection unit includes a terminal.
  • the terminal is supplied with a detection signal relating to temperature.
  • the second storage unit holds standard data regarding temperature.
  • one embodiment of the present invention is a secondary battery system including a secondary battery and the above semiconductor device.
  • the secondary battery is electrically connected to the semiconductor device.
  • the voltage applied to the secondary battery being charged and exceeding the tolerance information can be detected.
  • the control signal can be supplied based on the tolerance information derived from the characteristics of the secondary battery.
  • one embodiment of the present invention is a secondary battery system including a secondary battery and the above semiconductor device.
  • the secondary battery includes a battery cell and a temperature detector.
  • the temperature detector is electrically connected to the terminal, and the temperature detector detects the temperature of the battery cell.
  • the magnitude of the charging current is adjusted according to the environmental temperature. Charging in a low temperature environment is performed with a small charging current. If the ambient temperature is too low or too high, stop charging. The ambient temperature is measured with a memory element including an oxide semiconductor. By using the memory element including an oxide semiconductor, the environmental temperature is measured and the temperature information is held at the same time.
  • One embodiment of the present invention includes a first memory element, a second memory element, a comparison circuit, and a current adjustment circuit, and the first memory element has a function of holding reference temperature information.
  • the second memory element has a transistor including an oxide semiconductor in a semiconductor layer, and the second memory element has a function of measuring an environmental temperature and a function of holding the environmental temperature as environmental temperature information.
  • the current adjusting circuit is a semiconductor device having a function of supplying a current to the secondary battery.
  • the semiconductor layer preferably contains at least one of indium and zinc. More preferably, it contains both indium and zinc.
  • a lithium ion secondary battery for example, a lithium ion secondary battery can be used.
  • a novel semiconductor device with excellent convenience or reliability can be provided.
  • a novel secondary battery system with excellent convenience or reliability can be provided.
  • a novel semiconductor device or a novel secondary battery system can be provided.
  • a semiconductor device which realizes charging in which deterioration of a power storage device does not easily occur can be provided.
  • a charging method in which deterioration of the power storage device does not easily occur can be provided.
  • a charging method in which the power storage device is not easily damaged can be provided.
  • a novel semiconductor device can be provided.
  • a new charging device can be provided.
  • a new charging method can be provided.
  • FIGS. 1A and 1B are diagrams illustrating a semiconductor device.
  • 2A, 2B, 2C, 2D, 2E, 2F, and 2G are diagrams illustrating circuit configuration examples of storage elements.
  • 3A and 3B are diagrams illustrating electric characteristics of a transistor.
  • FIG. 4A, FIG. 4B, and FIG. 4C are diagrams illustrating a method of charging a secondary battery.
  • FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D are diagrams illustrating a method of charging a secondary battery.
  • FIG. 6 is a flowchart illustrating the charging operation of the semiconductor device.
  • 7A and 7B are diagrams for explaining the relationship between the environmental temperature and the charging current.
  • 8A and 8B are perspective views of the semiconductor device 100.
  • FIG. 9 is a sectional view of the semiconductor device 100.
  • FIG. 10 is a sectional view of the semiconductor device 100A.
  • FIG. 11 is a sectional view of the semiconductor device 100B.
  • 12A, 12B, and 12C are diagrams illustrating an example of a transistor.
  • 13A, 13B, and 13C are diagrams illustrating an example of a transistor.
  • 14A and 14B are perspective views showing an example of a secondary battery.
  • 15A, 15B, and 15C are diagrams illustrating examples of electronic devices.
  • 16A, 16B, 16C, and 16D are diagrams illustrating examples of electronic devices.
  • FIG. 17 is a diagram illustrating a semiconductor device.
  • 18A and 18B are perspective views of the semiconductor device 700.
  • FIG. 19 is a diagram illustrating a secondary battery system and a semiconductor device.
  • a semiconductor device of one embodiment of the present invention is a semiconductor device including a detection portion, a first storage portion, a second storage portion, and a determination portion, the detection portion supplying a detection signal,
  • the first storage unit holds the detection signal
  • the second storage unit holds the standard data and the tolerance information
  • the determination unit compares the detection signal with the standard data
  • the determination unit compares the detection signal and the standard data. If there is a deviation exceeding the tolerance information, a control signal is supplied.
  • ordinal numbers such as “first” and “second” in this specification and the like are added to avoid confusion among components and do not indicate any order or order such as a process order or a stacking order. ..
  • a term without an ordinal number may be given with an ordinal number in the claims or the like in order to avoid confusion among components.
  • FIGS. 1A to 1C are diagrams illustrating a structure of a semiconductor device of one embodiment of the present invention.
  • 1A is a block diagram of a semiconductor device of one embodiment of the present invention, and
  • FIG. 1B is a part of FIG. 1A.
  • 18A and 18B are diagrams illustrating a structure of a semiconductor device of one embodiment of the present invention.
  • 18A is a perspective view of a semiconductor device of one embodiment of the present invention
  • FIG. 18B is an exploded view illustrating the stacked structure of FIG. 18A.
  • a variable having a value of an integer of 1 or more may be used as a code.
  • (p) including a variable p that takes an integer value of 1 or more is used as a part of a code that specifies any one of the maximum p components.
  • (m, n) including a variable m and a variable n that take an integer value of 1 or more may be used as a part of a code that specifies any one of the maximum m ⁇ n constituent elements.
  • the semiconductor device 700 described in this embodiment includes a detection unit 702, a storage unit 701A, a storage unit 701B, and a determination unit 703 (see FIG. 1A).
  • the detection unit 702 supplies the detection signal DS(i).
  • a voltage detector, a current detector, a temperature detector, a timer, or the like can be used for the detection unit 702.
  • a signal including information such as voltage, current, or temperature can be used as the detection signal DS(i).
  • an analog signal can be used as the detection signal DS(i).
  • the storage unit 701B holds standard data DATA and tolerance information TI.
  • standard data DATA For example, the average characteristics of electrically connected loads can be used for the standard data DATA.
  • characteristics that differ depending on the number of times of use can be used for the standard data DATA.
  • a characteristic that changes depending on the usage history can be used for the standard data DATA.
  • the characteristic detected at the time of the last use can be used as the standard data DATA.
  • a storage element having the same structure as the storage element used for the storage unit 701A can be used for the storage unit 701B.
  • the memory element described in Embodiment 2 can be used for the memory portion 701B.
  • a flash memory can be used for the storage unit 701B.
  • the determination unit 703 compares the detection signal DS(i) with the standard data DATA. Further, the determination unit 703 supplies the control signal CI1 when the detection signal DS(i) and the standard data DATA have a deviation exceeding the tolerance information TI.
  • a comparator can be used for the determination unit 703.
  • a comparison circuit having the same structure as the comparison circuit 103 described in Embodiment 2 can be used for the determination unit 703.
  • the semiconductor device 700 described in this embodiment includes the control unit 705 (see FIG. 1A).
  • Control Unit 705 supplies the selection signal CI2.
  • the storage unit 701A includes a group of storage elements 701A(1) to 701A(n) and a selection circuit SC (see FIG. 1B).
  • the group of storage elements 701A(1) to 701A(n) includes the storage element 701A(i), and the storage element 701A(i) holds the detection signal DS(i).
  • the selection circuit SC selects the storage element 701A(i) based on the selection signal CI2.
  • the first storage unit 701A can hold a plurality of detection signals DS(1) to DS(n) obtained by sampling a plurality of times, for example.
  • a plurality of detection signals DS(1) to DS(n) obtained by detecting a plurality of different events such as voltage, current, and temperature can be held.
  • a detection signal that changes over time can be held together with information on the detection time.
  • the detection signal DS(i) that changes with wear can be held together with information on the usage history.
  • the control signal CI1 can be supplied by detecting a deviation exceeding the tolerance information TI.
  • the selection circuit SC includes a switch SW.
  • a novel semiconductor device with excellent convenience or reliability can be provided.
  • the selection circuit SC includes a source follower circuit SF.
  • deterioration of the analog data DATA(i) due to the selection operation can be suppressed.
  • a novel semiconductor device with excellent convenience or reliability can be provided.
  • the memory element 701A(i) is the above semiconductor device including the semiconductor layer 260, and the semiconductor layer 260 contains an oxide semiconductor.
  • the metal oxide described in Embodiment 3 can be used for the semiconductor layer 260.
  • the detection signal DS(i) can be held.
  • the detection signal DS(i) can be rewritten repeatedly.
  • deterioration of the memory element 701A(i) due to rewriting can be reduced.
  • a novel semiconductor device with excellent convenience or reliability can be provided.
  • the semiconductor device 700 described in this embodiment includes an integrated circuit 750 and an integrated circuit 760 (see FIG. 18).
  • the integrated circuit 750 includes a determination unit 703 (see FIG. 18B).
  • Si transistors can be used in the integrated circuit 750. Accordingly, the current drive capability of the transistor used in the integrated circuit 750 can be increased. Alternatively, the operation speed can be increased.
  • the structure of the integrated circuit 150 described in Embodiment 3 can be used for the integrated circuit 750.
  • the integrated circuit 760 includes a memory element 701A(i).
  • a transistor including an oxide semiconductor can be used for the integrated circuit 760. Accordingly, a memory element that can be repeatedly rewritten can be included in the integrated circuit 760.
  • the integrated circuit 760 includes a region overlapping with the integrated circuit 750, and the integrated circuit 760 is electrically connected to the integrated circuit 750. As a result, the area occupied by the semiconductor device 700 can be reduced. Note that, for example, a structure similar to that of the integrated circuit 160 described in Embodiment 3 can be used for the integrated circuit 760.
  • This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments and the like.
  • FIG. 17 is a block diagram for explaining the semiconductor device 100.
  • the semiconductor device 100 includes a memory element 101, a memory element 102, a comparison circuit 103, a current adjustment circuit 104, a control circuit 105, and an input/output circuit 106.
  • the semiconductor device 100 is electrically connected to the secondary battery 200 and has a function of charging the secondary battery 200.
  • the memory element 101 has one or more memory elements. In this embodiment mode, the case where the memory element 101 includes three memory elements (memory element 101_1, memory element 101_2, and memory element 101_3) is shown.
  • the storage element 101 holds information (potential or charge) for changing the charging current depending on the environmental temperature during charging.
  • the storage element 101_1, the storage element 101_2, and the storage element 101_3 hold information (also referred to as “reference temperature information”) corresponding to a temperature serving as a determination reference.
  • FIGS. 2A to 2G Examples of circuit structures which can be used for the memory element 101 are shown in FIGS. 2A to 2G. 2A to 2G each function as a memory element.
  • the memory element 410 illustrated in FIG. 2A includes a transistor M1 and a capacitor CA.
  • the memory element 410 is a memory element including one transistor and one capacitor.
  • a first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to the wiring BL, a gate of the transistor M1 is connected to the wiring WL, and a back gate of the transistor M1.
  • the second terminal of the capacitor CA is connected to the wiring CAL.
  • a node at which the first terminal of the transistor M1 and the first terminal of the capacitor CA are electrically connected is called a node ND.
  • the gate and the back gate are provided so as to overlap with each other with the channel formation region of the semiconductor layer interposed therebetween. Both gates and back gates can function as gates. Therefore, one may be called a “back gate” and the other may be called a “gate” or a “front gate”. Further, one may be referred to as a "first gate” and the other may be referred to as a "second gate”.
  • the back gate may have the same potential as the gate, a ground potential, or an arbitrary potential.
  • the threshold voltage of the transistor can be changed by changing the potential of the back gate independently without interlocking with the gate.
  • the back gate and further setting the gate and the back gate to the same potential By providing the back gate and further setting the gate and the back gate to the same potential, the region in which the carriers flow in the semiconductor layer becomes larger in the film thickness direction, so that the amount of carrier movement increases. As a result, the on-current of the transistor increases and the field effect mobility increases.
  • the transistor can have a large on-state current with respect to the occupied area. That is, the area occupied by the transistor can be reduced with respect to the required on-current. Therefore, a highly integrated semiconductor device can be realized.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1.
  • the threshold voltage of the transistor M1 can be increased or decreased.
  • Data writing and reading are performed by applying a high-level potential to the wiring WL, making the transistor M1 conductive, and electrically connecting the wiring BL and the node ND.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. It is preferable to apply a fixed potential to the wiring CAL.
  • the memory element 420 illustrated in FIG. 2B is a modified example of the memory element 410.
  • the back gate of the transistor M1 is electrically connected to the wiring WL.
  • the same potential as the gate of the transistor M1 can be applied to the back gate of the transistor M1. Therefore, the current flowing through the transistor M1 can be increased when the transistor M1 is on.
  • the transistor M1 may be a single-gate transistor (a transistor that does not have a back gate).
  • the memory element 430 has a structure in which the back gate is removed from the transistors M1 of the memory elements 410 and 420. Therefore, the manufacturing process of the memory element 430 can be shorter than that of the memory element 410 and the memory element 420.
  • the memory element 410, the memory element 420, and the memory element 430 are DRAM type memory elements.
  • An oxide semiconductor which is a kind of metal oxide, is preferably used for the semiconductor layer in which the channel of the transistor M1 is formed.
  • a transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed is also referred to as an “OS transistor”.
  • an oxide semiconductor indium, an element M (the element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, A metal oxide containing any one of tantalum, tungsten, magnesium, and the like) or zinc) can be used.
  • the oxide semiconductor is preferably a metal oxide containing indium, gallium, and zinc.
  • the OS transistor has a characteristic that the off-state current is extremely small.
  • the leak current of the transistor M1 can be made extremely low. That is, the written data can be held for a long time by the transistor M1. Therefore, the frequency of refreshing the memory element can be reduced. Further, the refresh operation of the memory element can be made unnecessary.
  • the memory element 410, the memory element 420, and the memory element 430 can hold multilevel data or analog data.
  • DOSRAM Dynamic Oxide Semiconductor Random Access Memory
  • FIG. 2D shows a circuit configuration example of a gain cell type storage element including two transistors and one capacitor.
  • the memory element 440 includes a transistor M1, a transistor M2, and a capacitor CA.
  • a first terminal of the transistor M1 is connected to the first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to the wiring WBL, and a gate of the transistor M1 is connected to the wiring WWL.
  • the second terminal of the capacitor CA is connected to the wiring CAL.
  • a first terminal of the transistor M2 is connected to the wiring RBL, a second terminal of the transistor M2 is connected to the wiring RWL, and a gate of the transistor M2 is connected to a first terminal of the capacitor CA.
  • a node at which the first terminal of the transistor M1, the first terminal of the capacitor CA, and the gate of the transistor M2 are electrically connected is referred to as a node ND.
  • the bit line WBL functions as a write bit line
  • the bit line RBL functions as a read bit line
  • the word line WWL functions as a write word line
  • the word line RWL functions as a read word line.
  • the transistor M1 has a function as a switch for electrically connecting or disconnecting the node ND and the bit line WBL.
  • the off-state current of the OS transistor is extremely small; therefore, by using the OS transistor for the transistor M1, the potential written in the node ND can be held for a long time. That is, the data written in the memory element can be held for a long time.
  • transistor M2 there is no particular limitation on the transistor used for the transistor M2.
  • the transistor M2 an OS transistor, a Si transistor (a transistor in which silicon is used for a semiconductor layer), or another transistor may be used.
  • the silicon used for the semiconductor layer may be amorphous silicon, polycrystalline silicon, low temperature polysilicon (LTPS: Low Temperature Poly-Silicon), or single crystal silicon. Since the Si transistor may have higher field-effect mobility than the OS transistor, the operation speed at the time of reading can be increased by using the Si transistor as the reading transistor.
  • LTPS Low Temperature Poly-Silicon
  • the both may be stacked in different layers.
  • the OS transistor can be manufactured with a manufacturing apparatus and a process similar to those of the Si transistor. Therefore, mixed mounting (hybridization) of the OS transistor and the Si transistor is easy, and high integration is also easy.
  • the leak current at the time of non-selection can be extremely reduced, so that the reading accuracy can be improved.
  • OS transistors for both the transistor M1 and the transistor M2, the number of manufacturing steps of a semiconductor device can be reduced and productivity can be improved.
  • a semiconductor device can be manufactured at a process temperature of 400° C. or lower.
  • FIG. 2E to 2G show circuit configuration examples in the case where a transistor having a back gate (a four-terminal transistor; also referred to as a “four-terminal element”) is used for the transistor M1 and the transistor M2.
  • the memory element 450 illustrated in FIG. 2E, the memory element 460 illustrated in FIG. 2F, and the memory element 470 illustrated in FIG. 2G are modifications of the memory element 440.
  • the gate and the back gate of the transistor M1 are electrically connected.
  • the gate and the back gate of the transistor M2 are electrically connected.
  • the back gate of the transistor M1 and the back gate of the transistor M2 are electrically connected to the wiring BGL.
  • a predetermined potential can be applied to the back gates of the transistor M1 and the transistor M2 through the wiring BGL.
  • the back gate of the transistor M1 is electrically connected to the wiring WBGL and the back gate of the transistor M2 is electrically connected to the wiring RBGL.
  • the memory elements 440 to 470 are 2Tr1C type memory cells.
  • a memory device including a 2Tr1C type memory cell using an OS transistor as the transistor M1 is referred to as a NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory).
  • NOSRAM Non-volatile Oxide Semiconductor Random Access Memory
  • the memory elements 440 to 470 can amplify and read the potential of the node ND with the transistor M12.
  • the OS transistor has very low off-state current, the potential of the node ND can be held for a long time.
  • non-destructive reading in which the potential of the node ND is held even when the reading operation is performed can be performed.
  • the information held in the storage element 101 is information that is less frequently rewritten. Therefore, it is preferable to use, as the memory element 101, a NOSRAM capable of nondestructive reading of information and long-term retention.
  • transistors illustrated in FIGS. 2A, 2B, and (E) to (G) are four-terminal elements, MRAM (Magnetoresistive Random Access Memory) and ReRAM (Resistive Resistive) that use MTJ (Magnetic Tunnel Junction) characteristics are used.
  • MRAM Magneticoresistive Random Access Memory
  • ReRAM Resistive Resistive
  • MTJ Magnetic Tunnel Junction
  • the structure may change at the atomic level when information is rewritten.
  • the memory device of one embodiment of the present invention operates by charge charge or discharge through a transistor at the time of rewriting information, it has characteristics of excellent resistance to repeated rewriting and little structural change.
  • the memory element 102 As the memory element 102, a memory element similar to the memory element 101 can be used.
  • the storage element 102 is preferably DOSRAM or NOARAM.
  • FIGS. 3A and 3B show an example of the Id-Vg characteristic which is one of the electric characteristics of the transistor.
  • the Id-Vg characteristic shows changes in the drain current (Id) with respect to changes in the gate voltage (Vg).
  • the horizontal axis of FIGS. 3A and 3B represents Vg on a linear scale.
  • the vertical axes in FIGS. 3A and 3B represent Id on a log scale.
  • FIG. 3A shows the Id-Vg characteristics of the OS transistor.
  • FIG. 3B shows Id-Vg characteristics of a transistor (Si transistor) using silicon for a semiconductor layer in which a channel is formed. Note that FIGS. 3A and 3B both show Id-Vg characteristics of an n-channel transistor.
  • the off current is unlikely to increase even when operating in a high temperature environment.
  • the OS transistor can realize an on/off ratio of 10 digits or more even when the operating temperature is 125° C. or higher and 150° C. or lower.
  • the off current increases as the temperature rises.
  • Vth shifts in the positive direction as the temperature rises, and the on-current decreases.
  • the oxide semiconductor has a property that its resistance value becomes smaller as the temperature rises.
  • the ambient temperature can be converted into a potential.
  • the transistor M1 is turned on, 0 V is supplied to the wiring BL, and 0 V is written to the node ND.
  • VDD is supplied to the wiring BL and the transistor M1 is turned off after a certain period of time.
  • the resistance value of the oxide semiconductor changes with temperature. Therefore, the potential (also referred to as “environmental temperature information”) corresponding to the environmental temperature at the time of measurement is held in the node ND. Further, the higher the environmental temperature, the higher the potential held in the node ND.
  • the memory element 102 can function as a temperature sensor.
  • the oxide semiconductor By using the oxide semiconductor, the memory element 101 and the memory element 102 can be manufactured at the same time in the same step. Moreover, since it is not necessary to separately provide a temperature sensor such as a thermistor, the productivity of the semiconductor device 100 can be improved.
  • the comparison circuit 103 has a function of comparing the temperature information held in the memory element 101 with the environmental temperature held in the memory element 102 to determine the operation of the current adjustment circuit. Specifically, the potential of the node ND of the memory element 101 and the potential of the node ND of the memory element 102 are compared.
  • the comparison circuit 103 can be configured by a comparator or the like.
  • the current adjustment circuit 104 has a function of controlling a current value supplied to the secondary battery 200 by a signal supplied from the comparison circuit 103.
  • the current adjustment circuit 104 can be configured by a power transistor or the like.
  • Control circuit 105, input/output circuit 106 The control circuit 105 has a function of comprehensively controlling the operations of the memory element 101, the memory element 102, the comparison circuit 103, the current adjustment circuit 104, and the input/output circuit 106. Further, the control circuit 105 is supplied with a control signal, setting information of the memory element 101, and the like from the outside through the input/output circuit 106. Further, the control circuit 105 outputs the charging voltage of the secondary battery 200, the current value output from the current adjusting circuit 104, the environmental temperature information acquired by the storage element 102, and the like to the outside through the input/output circuit 106. Have a function.
  • the secondary battery can be charged, for example, as follows.
  • CC charging is a charging method in which a constant current is supplied to a secondary battery during the entire charging period and charging is stopped when a predetermined voltage is reached. It is assumed that the secondary battery is an equivalent circuit of the internal resistance R and the secondary battery capacity C as shown in FIG. 4A. In this case, the secondary battery voltage V B is the sum of the voltage V C applied to the voltage V R and the secondary battery capacity C according to the internal resistance R.
  • the switch is turned on and a constant current I flows through the secondary battery.
  • the voltage V C applied to the secondary battery capacity C increases with the passage of time. Therefore, the secondary battery voltage V B increases with the passage of time.
  • FIG. 4C An example of the secondary battery voltage V B and the charging current during the CC charging and after the CC charging is stopped is shown in FIG. 4C. It is shown that the secondary battery voltage V B , which has been increased during CC charging, is slightly decreased after the CC charging is stopped.
  • CCCV charging is a charging method in which CC charging is first performed to a predetermined voltage, and then CV (constant voltage) charging is performed until the amount of current flowing decreases, specifically, until the final current value is reached. ..
  • the switch of the constant current power supply is turned on and the switch of the constant voltage power supply is turned off, and a constant current I flows through the secondary battery.
  • the voltage V C applied to the secondary battery capacity C increases with the passage of time. Therefore, the secondary battery voltage V B increases with the passage of time.
  • the CC charging is switched to the CV charging.
  • a predetermined voltage for example, 4.3 V
  • the switch of the constant voltage power source is turned on, the switch of the constant current power source is turned off, and the secondary battery voltage V B becomes constant.
  • the charging is stopped.
  • a predetermined current for example, a current equivalent to 0.01 C
  • the charging is stopped.
  • the voltage V R applied to the internal resistance R by CV charging is sufficiently small, even run out of the voltage drop at the internal resistance R, the secondary battery voltage V B is hardly lowered.
  • FIG. 5D shows examples of the secondary battery voltage V B and the charging current during the CCCV charging and after the CCCV charging is stopped. It is shown that the secondary battery voltage V B hardly drops even when the CCCV charging is stopped.
  • the charging rate is a relative ratio of the charging current to the battery capacity and is expressed in the unit C.
  • the current corresponding to 1C is X[A].
  • Example of charging operation Generally, the charging condition of a secondary battery differs depending on the constituent materials of the positive electrode, the negative electrode, and the electrolytic solution contained in the secondary battery. In the present embodiment, an example will be described in which semiconductor device 100 performs CC charging on secondary battery 200 under the charging conditions shown in Table 1.
  • FIG. 6 is a flowchart illustrating the charging operation of the semiconductor device 100.
  • FIG. 7A is a diagram illustrating the relationship between the environmental temperature and the charging current. Further, FIG. 7A shows a temperature range P0 below 0° C., a temperature range P1 above 0° C. and below 10° C., a temperature range P2 below 10° C. and above 45° C., and a temperature range P3 above 45° C.
  • the environmental temperature Tp is acquired (step S501).
  • the temperature condition T1 held in the memory element 101_1 is compared with the environmental temperature Tp (step S502).
  • the environmental temperature Tp is lower than the temperature condition T1
  • the temperature condition T2 held in the storage element 101_2 is compared with the environmental temperature Tp (step S503).
  • the environmental temperature Tp is lower than the temperature condition T2
  • the current I L is supplied to the secondary battery 200 (step S511).
  • the current I L is a current corresponding to the charging rate of 0.25C. Therefore, the current I L is 750 mA.
  • the temperature condition T3 held in the storage element 101_3 is compared with the environmental temperature Tp (step S504).
  • the environmental temperature Tp is lower than the temperature condition T3, it is determined that the secondary battery 200 is in the temperature range P2, and the current I SD is supplied to the secondary battery 200 (step S512).
  • the current I SD is a current corresponding to a charging rate of 0.5C. Therefore, the current I SD is 1500 mA.
  • step S505 If the environmental temperature Tp is higher than the temperature condition T3, it is determined that the secondary battery 200 is in the temperature range P3, and charging of the secondary battery 200 is stopped (current supply is stopped) (step S505).
  • step S505 the state of step S505, step S511, or step S512 is maintained for a certain period of time (step S506).
  • step S507 When the voltage of the secondary battery 200 is equal to or higher than the charging maximum voltage, the charging operation is finished.
  • CV charging may be performed thereafter.
  • the environmental temperature is low (less than 10° C. in the present embodiment)
  • the reaction rate of the negative electrode material and Li decreases, and Li precipitation easily occurs. Li deposition may cause a decrease in battery capacity and a fire accident due to an internal short circuit. Therefore, it is preferable to reduce the charging current.
  • the environmental temperature is too low (less than 0° C. in the present embodiment)
  • the supply of charging current is stopped.
  • a temperature range P0 of less than 0° C. a temperature range P1 of 0° C. or more and less than 10° C., a temperature range P2 of 10° C. or more and less than 25° C., a temperature range P3 of 25° C. or more and less than 45° C., 45° C. or more Shows a temperature range P4.
  • the environmental temperature and the charging current may be continuously changed in a specific temperature range.
  • FIG. 7B shows an example in which the charging current is continuously changed in accordance with the environmental temperature in the temperature range P2.
  • This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments and the like.
  • the comparison circuit 103, the current adjustment circuit 104, the control circuit 105, and the input/output circuit 106 may be required to have high current driving capability and/or high speed operation. In this case, it is preferable to use Si transistors for the comparison circuit 103, the current adjustment circuit 104, the control circuit 105, and the input/output circuit 106.
  • an OS transistor is preferably used for the memory element 101 and the memory element 102.
  • the OS transistor and the Si transistor can be stacked and provided.
  • the integrated circuit 160 including the memory element 101 and the memory element 102 may be provided over the integrated circuit 150 including the comparison circuit 103, the current adjustment circuit 104, the control circuit 105, and the input/output circuit 106. ..
  • the semiconductor device 100 can be downsized. In other words, the area occupied by the semiconductor device 100 can be reduced.
  • FIG. 8A is a perspective view of the semiconductor device 100 including the integrated circuit 150 and the integrated circuit 160. Further, FIG. 8B is a diagram for easily showing the positional relationship between the integrated circuit 150 and the integrated circuit 160. FIG. 9 is a cross-sectional view of a part of the semiconductor device 100.
  • the integrated circuit 150 includes a transistor 233a, a transistor 233b, and a transistor 233c over a substrate 231.
  • FIG. 9 cross sections in the channel length direction of the transistors 233a, 233b, and 233c are shown.
  • Channels of the transistor 233a, the transistor 233b, and the transistor 233c are formed in part of the substrate 231.
  • a single crystal semiconductor substrate is preferably used as the substrate 231.
  • the transistor 233a, the transistor 233b, and the transistor 233c are electrically separated from each other by the element isolation layer 232.
  • the element isolation layer can be formed by using a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or the like.
  • an insulating layer 234, an insulating layer 235, and an insulating layer 237 are provided over the transistor 233a, the transistor 233b, and the transistor 233c, and an electrode 238 is embedded in the insulating layer 237.
  • the electrode 238 is electrically connected to one of the source and the drain of the transistor 233a through the contact plug 236.
  • the insulating layer 239, the insulating layer 240, and the insulating layer 241 are provided over the electrode 238 and the insulating layer 237, and the electrode 242 is embedded in the insulating layer 239, the insulating layer 240, and the insulating layer 241. ..
  • the electrode 242 is electrically connected to the electrode 238.
  • the insulating layer 243 and the insulating layer 244 are provided over the electrode 242 and the insulating layer 241, and the electrode 245 is embedded in the insulating layer 243 and the insulating layer 244.
  • the electrode 245 is electrically connected to the electrode 242.
  • An insulating layer 246 and an insulating layer 247 are provided over the electrode 245 and the insulating layer 244, and an electrode 249 is embedded in the insulating layer 246 and the insulating layer 247.
  • the electrode 249 is electrically connected to the electrode 245.
  • the insulating layer 248 and the insulating layer 250 are provided over the electrode 249 and the insulating layer 247, and the electrode 251 is embedded in the insulating layer 248 and the insulating layer 250.
  • the electrode 251 is electrically connected to the electrode 249.
  • the integrated circuit 160 is provided on the integrated circuit 150.
  • the integrated circuit 160 includes a transistor 210 and a capacitor 220.
  • a cross section of the transistor 210 in the channel length direction is shown.
  • the transistor 210 is a transistor having a back gate.
  • an oxide semiconductor which is a kind of metal oxide is preferably used. That is, it is preferable to use an OS transistor for the transistor 210.
  • the transistor 210 is provided over the insulating layer 361. Further, the insulating layer 362 is provided over the insulating layer 361. The back gate of the transistor 210 is embedded in the insulating layer 362. The insulating layer 371 and the insulating layer 380 are provided over the insulating layer 362. The gate of the transistor 210 is embedded in the insulating layer 380.
  • the insulating layer 374 and the insulating layer 381 are provided over the insulating layer 380.
  • the electrode 355 is embedded in the insulating layer 361, the insulating layer 362, the insulating layer 365, the insulating layer 366, the insulating layer 371, the insulating layer 380, the insulating layer 374, and the insulating layer 381.
  • the electrode 355 is electrically connected to the electrode 251.
  • the electrode 355 can function as a contact plug.
  • the electrode 152 is provided over the insulating layer 381.
  • the electrode 152 is electrically connected to the electrode 355.
  • the insulating layer 114, the insulating layer 115, and the insulating layer 130 are provided over the insulating layer 381 and the electrode 152.
  • the capacitor 220 has an electrode 110 arranged in an opening formed in the insulating layer 114 and the insulating layer 115, an insulating layer 130 over the electrode 110 and the insulating layer 115, and an electrode 120 over the insulating layer 130. .. At least a part of the electrode 110, at least a part of the insulating layer 130, and at least a part of the electrode 120 are arranged in the openings formed in the insulating layer 114 and the insulating layer 115.
  • the electrode 110 functions as a lower electrode of the capacitor 220
  • the electrode 120 functions as an upper electrode of the capacitor 220
  • the insulating layer 130 functions as a dielectric of the capacitor 220.
  • the capacitance element 220 has a structure in which the upper electrode and the lower electrode face each other across the dielectric not only in the bottom surface but also in the side surface in the openings of the insulating layers 114 and 115, and electrostatic capacitance per unit area is increased. The capacity can be increased. Therefore, the capacitance of the capacitive element 220 can be increased as the opening is deepened. By thus increasing the capacitance per unit area of the capacitive element 220, miniaturization or high integration of the semiconductor device can be promoted.
  • the shape of the openings formed in the insulating layer 114 and the insulating layer 115 when viewed from above may be a quadrangle, a polygonal shape other than the quadrangle, or a shape in which corners are curved in the polygonal shape.
  • a circular shape including an ellipse may be used.
  • the insulating layer 116 and the insulating layer 154 are provided over the insulating layer 130 and the electrode 120.
  • the electrode 112 is embedded in the insulating layer 114, the insulating layer 115, the insulating layer 130, the insulating layer 116, and the insulating layer 154.
  • the electrode 112 is electrically connected to the electrode 152.
  • the electrode 112 can function as a contact plug.
  • the electrode 153 is provided over the insulating layer 154. The electrode 153 is electrically connected to the electrode 112.
  • the insulating layer 156 is provided over the insulating layer 154 and the electrode 153.
  • FIG. 10 shows a semiconductor device 100A which is a modified example of the semiconductor device 100.
  • an integrated circuit 150A and an integrated circuit 160 are provided so as to overlap each other.
  • the integrated circuit 150A uses OS transistors as transistors such as the transistor 233a and the transistor 233b included in the integrated circuit 150.
  • the semiconductor device 100A can be a unipolar integrated circuit.
  • FIG. 11 shows a semiconductor device 100B which is a modified example of the semiconductor device 100A.
  • the integrated circuit 150A and the integrated circuit 160 can be manufactured over the substrate 231 in the same step. Therefore, the productivity of the semiconductor device can be improved. In addition, the production cost of the semiconductor device can be reduced.
  • the cooling efficiency of the semiconductor device can be higher than that when an insulating substrate or the like is used. Therefore, the reliability of the semiconductor device can be improved.
  • a substrate for example, a substrate, an insulating layer, a conductive layer, a semiconductor layer, a metal oxide, or the like can be used for a semiconductor device.
  • ⁇ substrate ⁇ There is no particular limitation on the material used as the substrate. For example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulating substrate examples include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate examples include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • a semiconductor substrate having an insulating region inside the semiconductor substrate described above, for example, an SOI (Silicon On Insulator) substrate may be used.
  • the integrated circuit when the integrated circuit is required to operate at high speed, it is preferable to use a single crystal semiconductor substrate as the substrate.
  • the conductor substrate examples include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate including a metal nitride, a substrate including a metal oxide, or the like can be given.
  • a substrate in which a conductor or a semiconductor is provided on an insulator substrate a substrate in which a conductor or an insulator is provided in a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided in a conductor substrate, and the like.
  • a substrate provided with an element may be used.
  • the elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a storage element, and the like.
  • a semiconductor substrate provided with a semiconductor element such as a strained transistor or a FIN type transistor. That is, the substrate is not limited to a simple supporting substrate, and may be a substrate on which devices such as other transistors are formed.
  • Insulating layer Materials used for the insulating layer include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides having an insulating property.
  • the insulating layer functioning as a gate insulating layer
  • parasitic capacitance generated between wirings can be reduced. Therefore, the material may be selected depending on the function of the insulating layer.
  • gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, and silicon and hafnium are given. And the like, or a nitride containing silicon and hafnium.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon-nitrogen-added silicon oxide, or Silicon oxide having holes, resin, or the like is used.
  • an OS transistor as a transistor
  • an insulating layer insulating layer 365, insulating layer 371, or the like
  • the electrical characteristics of the transistor can be improved.
  • the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium.
  • the insulator containing lanthanum, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer.
  • an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen
  • a metal oxide such as tantalum oxide, a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride can be used.
  • the insulating layer functioning as a gate insulating layer is preferably an insulator having a region containing oxygen which is released by heating.
  • an insulator having a region containing oxygen which is released by heating For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen which is released by heating is in contact with the semiconductor layer 260, oxygen vacancies in the semiconductor layer 260 can be compensated.
  • a nitride oxide refers to a compound in which the content of nitrogen is higher than that of oxygen.
  • an oxynitride refers to a compound having a higher oxygen content than nitrogen.
  • the content of each element can be measured using, for example, the Rutherford backscattering spectroscopy (RBS).
  • the hydrogen concentration in the insulating layer is determined to be 2 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less by secondary ion mass spectrometry (SIMS). It is more preferably 1 ⁇ 10 19 atoms/cm 3 or less, and further preferably 5 ⁇ 10 18 atoms/cm 3 or less. In particular, it is preferable to reduce the hydrogen concentration of the insulating layer which is in contact with the semiconductor layer.
  • the nitrogen concentration in the insulating layer is 5 ⁇ 10 19 atoms/cm 3 or less, preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less in SIMS, More preferably, it is 5 ⁇ 10 17 atoms/cm 3 or less.
  • the above-mentioned signals include the E'center observed at a g-value of 2.001.
  • the E′ center is due to the dangling bond of silicon.
  • the spin density due to the E′ center is 3 ⁇ 10 17 spins/cm 3 or less, preferably 5 ⁇ 10 16 spins/cm 3 or less.
  • a silicon oxide layer or a silicon oxynitride layer may be used.
  • signals due to nitrogen dioxide may be observed.
  • the signal is split into three signals by the nuclear spin of N, each g value is 2.037 or more and 2.039 or less (the first signal), and g value is 2.001 or more and 2.003. It is observed below (as a second signal) and at a g value of 1.964 or more and 1.966 or less (as a third signal).
  • the insulating layer it is preferable to use an insulating layer having a spin density of a signal due to nitrogen dioxide (NO 2 ) of 1 ⁇ 10 17 spins/cm 3 or more and less than 1 ⁇ 10 18 spins/cm 3 .
  • NO 2 nitrogen dioxide
  • nitrogen oxide (NO x ) containing nitrogen dioxide (NO 2 ) forms a level in the insulating layer.
  • the level is located in the energy gap of the oxide semiconductor layer. Therefore, when nitrogen oxide (NO x ) diffuses into the interface between the insulating layer and the oxide semiconductor layer, the level may trap electrons on the insulating layer side. As a result, the trapped electrons remain in the vicinity of the interface between the insulating layer and the oxide semiconductor layer, so that the threshold voltage of the transistor is shifted in the positive direction. Therefore, when the insulating layer and the film containing a small amount of nitrogen oxide are used as the insulating layer, shift of the threshold voltage of the transistor can be reduced.
  • a silicon oxynitride layer As the insulating layer from which the amount of released nitrogen oxide (NO x ) is small, for example, a silicon oxynitride layer can be used.
  • the silicon oxynitride layer is a film in which the amount of released ammonia is larger than the amount of released nitrogen oxide (NO x ) in a thermal desorption gas analysis method (TDS: Thermal Desorption Spectroscopy), and typically the amount of released ammonia is The amount of release is 1 ⁇ 10 18 /cm 3 or more and 5 ⁇ 10 19 /cm 3 or less. Note that the above-described amount of released ammonia is the total amount when the temperature of heat treatment in TDS is 50 °C to 650 °C inclusive, or 50 °C to 550 °C inclusive.
  • Nitrogen oxide (NO x ) reacts with ammonia and oxygen in heat treatment; therefore, nitrogen oxide (NO x ) is reduced by using an insulating layer in which a large amount of ammonia is released.
  • At least one of the insulating layers in contact with the oxide semiconductor layer is preferably formed using an insulating layer from which oxygen is released by heating.
  • an insulating layer from which oxygen is released by heating is 1.0. It is preferable to use an insulating layer having a density of ⁇ 10 18 atoms/cm 3 or higher, 1.0 ⁇ 10 19 atoms/cm 3 or higher, or 1.0 ⁇ 10 20 atoms/cm 3 or higher. Note that in this specification and the like, oxygen released by heating is also referred to as “excess oxygen”.
  • the insulating layer containing excess oxygen can be formed by performing treatment for adding oxygen to the insulating layer.
  • the treatment of adding oxygen can be performed by heat treatment in an oxidizing atmosphere, plasma treatment, or the like.
  • oxygen may be added by an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like.
  • the gas used for the treatment of adding oxygen include oxygen gas such as 16 O 2 or 18 O 2 , nitrous oxide gas, or gas containing oxygen such as ozone gas.
  • the treatment of adding oxygen is also referred to as “oxygen doping treatment”.
  • the oxygen doping treatment may be performed by heating the substrate.
  • a heat-resistant organic material such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, or epoxy resin can be used.
  • a low dielectric constant material low-k material
  • siloxane resin PSG (phosphorus glass), BPSG (phosphorus boron glass), or the like can be used.
  • the insulating layer may be formed by stacking a plurality of insulating layers formed of these materials.
  • the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material.
  • the siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Further, the organic group may have a fluoro group.
  • the method for forming the insulating layer is not particularly limited. Note that a baking step may be necessary depending on the material used for the insulating layer. In this case, the transistor can be efficiently manufactured by combining the baking step of the insulating layer and another heat treatment step.
  • the method for forming the insulating layer is not particularly limited. Note that a baking step may be necessary depending on the material used for the insulating layer. In this case, the transistor can be efficiently manufactured by combining the baking step of the insulating layer and another heat treatment step.
  • the conductive layer aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum. It is preferable to use a metal element selected from the above, an alloy containing the above metal element as a component, an alloy in which the above metal elements are combined, or the like.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, or the like is used.
  • tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are difficult to oxidize.
  • a conductive material or a material that maintains conductivity even when absorbing oxygen is preferable.
  • a semiconductor having high electric conductivity which is typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.
  • a plurality of conductive layers formed of the above materials may be stacked and used.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined may be used.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be used.
  • a stacked structure in which the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be used.
  • the conductive layer functioning as a gate electrode is formed by combining the above-described material containing a metal element and a conductive material containing oxygen. It is preferable to use a laminated structure.
  • a conductive material containing oxygen may be provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.
  • a conductive material containing a metal element contained in a metal oxide in which a channel is formed and oxygen as the conductive layer functioning as a gate electrode.
  • a conductive material containing the above metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide (ITO) indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc. Oxide or indium tin oxide added with silicon may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • a conductive material having a high embedding property such as tungsten or polysilicon may be used.
  • a conductive material having a high filling property and a barrier layer (diffusion prevention layer) such as a titanium layer, a titanium nitride layer, or a tantalum nitride layer may be used in combination.
  • semiconductor layer a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination.
  • semiconductor material for example, silicon or germanium can be used.
  • a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor, an organic semiconductor, or the like can be used.
  • a low molecular organic material having an aromatic ring, a ⁇ -electron conjugated conductive polymer, or the like can be used.
  • a low molecular organic material having an aromatic ring, a ⁇ -electron conjugated conductive polymer, or the like can be used.
  • rubrene, tetracene, pentacene, perylene diimide, tetracyanoquinodimethane, polythiophene, polyacetylene, polyparaphenylene vinylene and the like can be used.
  • semiconductor layers may be stacked. In the case of stacking semiconductor layers, semiconductors having different crystal states may be used, or different semiconductor materials may be used.
  • the band gap of an oxide semiconductor which is a kind of metal oxide is 2 eV or more
  • the off current per 1 ⁇ m of the channel width is less than 1 ⁇ 10 ⁇ 20 A, 1 ⁇ 10 ⁇ 22 A. Or less than 1 ⁇ 10 ⁇ 24 A. That is, the on/off ratio can be set to 20 digits or more.
  • a transistor including an oxide semiconductor for a semiconductor layer has high withstand voltage between a source and a drain. Therefore, a highly reliable transistor can be provided. Further, a transistor having a large output voltage and a high withstand voltage can be provided. Further, a highly reliable storage device or the like can be provided. In addition, a memory device with a high output voltage and a high withstand voltage can be provided.
  • Crystalline Si transistors are easier to obtain a relatively higher mobility than OS transistors.
  • an OS transistor and a crystalline Si transistor may be used in combination depending on the purpose or use.
  • the oxide semiconductor layer is preferably formed by a sputtering method.
  • the oxide semiconductor layer is formed by a sputtering method, the density of the oxide semiconductor layer can be increased, which is preferable.
  • a rare gas typically argon
  • oxygen or a mixed gas of a rare gas and oxygen may be used as a sputtering gas.
  • a gas which is highly purified to a dew point of ⁇ 60° C. or lower, preferably ⁇ 100° C. or lower is used.
  • the oxide semiconductor layer is formed by a sputtering method
  • moisture in the deposition chamber of the sputtering device be removed as much as possible.
  • it is preferable to set the partial pressure of gas molecules corresponding to H 2 O (gas molecules corresponding to m/z 18) in the deposition chamber to 1 ⁇ 10 ⁇ 4 Pa or less when the sputtering apparatus is on standby. It is more preferable that the pressure is 5 ⁇ 10 ⁇ 5 Pa or less.
  • Metal oxide By changing the composition of the elements contained in the metal oxide, a conductor, a semiconductor, and an insulator can be formed separately.
  • a metal oxide having physical properties of a conductor may be referred to as a “conductive oxide”.
  • a metal oxide having semiconductor properties may be referred to as an "oxide semiconductor”.
  • a metal oxide having an insulator physical property may be referred to as an “insulating oxide”.
  • the oxide semiconductor which is a kind of metal oxide, preferably contains indium or zinc. It is particularly preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. In addition, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be contained.
  • the oxide semiconductor contains indium, the element M, and zinc.
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • Other elements that can be applied to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium.
  • a combination of the above-mentioned elements may be used as the element M.
  • metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, the metal oxide containing nitrogen may be referred to as a metal oxynitride.
  • the oxide semiconductor (metal oxide) is divided into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor other than the single crystal oxide semiconductor.
  • a non-single-crystal oxide semiconductor for example, a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS (nanocrystal oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), And amorphous oxide semiconductors.
  • the CAAC-OS has a crystal structure having c-axis orientation and a strain in which a plurality of nanocrystals are connected in the ab plane direction.
  • the strain refers to a portion in which the orientation of the lattice arrangement is changed between a region where the lattice arrangement is uniform and another region where the lattice arrangement is uniform in the region where a plurality of nanocrystals are connected.
  • the nanocrystal is basically a hexagon, but is not limited to a regular hexagon, and may be a non-regular hexagon.
  • the strain may have a lattice arrangement such as a pentagon and a heptagon.
  • a lattice arrangement such as a pentagon and a heptagon.
  • the CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter, an In layer) and a layer containing elements M, zinc, and oxygen (hereinafter, a (M,Zn) layer) are stacked. It tends to have a structure (also called a layered structure).
  • indium and the element M can be replaced with each other, and when the element M of the (M,Zn) layer is replaced with indium, it can be expressed as an (In,M,Zn) layer.
  • the indium of the In layer is replaced with the element M, it can be expressed as an (In,M) layer.
  • CAAC-OS is a metal oxide with high crystallinity.
  • the CAAC-OS since it is difficult to confirm a clear crystal grain boundary, it can be said that the decrease in electron mobility due to the crystal grain boundary is unlikely to occur.
  • the crystallinity of a metal oxide may be reduced due to entry of impurities, generation of defects, and the like; therefore, the CAAC-OS can be referred to as a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the metal oxide having CAAC-OS has stable physical properties. Therefore, the metal oxide including the CAAC-OS is highly heat resistant and highly reliable.
  • the nc-OS has a periodic atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Moreover, in the nc-OS, no regularity is found in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.
  • In-Ga-Zn oxide which is a kind of metal oxide containing indium, gallium, and zinc, may have a stable structure by using the above-described nanocrystal. is there.
  • IGZO tends to have difficulty in crystal growth in the atmosphere, and thus a smaller crystal (for example, the above-mentioned nanocrystal) is used than a large crystal (here, a crystal of several mm or a crystal of several cm).
  • a large crystal here, a crystal of several mm or a crystal of several cm.
  • it may be structurally stable.
  • the a-like OS is a metal oxide having a structure between the nc-OS and the amorphous oxide semiconductor.
  • the a-like OS has a void or a low density region. That is, the crystallinity of the a-like OS is lower than that of the nc-OS and the CAAC-OS.
  • Oxide semiconductors have various structures and have different characteristics.
  • the oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
  • the metal oxide has a carrier density of less than 8 ⁇ 10 11 cm ⁇ 3 , preferably less than 1 ⁇ 10 11 cm ⁇ 3 , more preferably less than 1 ⁇ 10 10 cm ⁇ 3 , and 1 ⁇ 10 ⁇ 9 cm. It may be -3 or more.
  • the density of trap states may be low in some cases.
  • the charge trapped in the trap level of the metal oxide takes a long time to disappear, and may behave like a fixed charge. Therefore, electric characteristics of a transistor including a metal oxide with a high trap level density in a channel formation region might be unstable.
  • Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon and the like.
  • the metal oxide contains an alkali metal or an alkaline earth metal
  • a defect level may be formed and a carrier may be generated. Therefore, a transistor including a metal oxide containing an alkali metal or an alkaline earth metal in a channel formation region is likely to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide.
  • the concentration of alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to be water, which may cause oxygen deficiency.
  • the transistor is likely to have normally-on characteristics.
  • electrons which are carriers may be generated.
  • part of hydrogen may be bonded to oxygen which is bonded to a metal atom to generate an electron which is a carrier. Therefore, a transistor including a metal oxide containing hydrogen is likely to have normally-on characteristics.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 1 ⁇ 10 19 atoms/cm 3 , and more preferably 5 ⁇ 10 18 atoms/cm 3. It is less than 3 , and more preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • a thin film with high crystallinity is preferably used as a metal oxide used for a semiconductor of a transistor.
  • the thin film By using the thin film, stability or reliability of the transistor can be improved.
  • the thin film include a single crystal metal oxide thin film and a polycrystalline metal oxide thin film.
  • a high temperature or laser heating process is required in order to form a single crystal metal oxide thin film or a polycrystalline metal oxide thin film on a substrate. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.
  • Non-Patent Document 1 and Non-Patent Document 2 report that an In-Ga-Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was discovered in 2009. Here, it is reported that CAAC-IGZO has c-axis orientation, crystal grain boundaries are not clearly confirmed, and can be formed on a substrate at low temperature. Further, it is reported that a transistor including CAAC-IGZO has excellent electrical characteristics and reliability.
  • CAAC-IGZO In-Ga-Zn oxide having a CAAC structure
  • nc-IGZO In-Ga-Zn oxide having an nc structure was discovered (see Non-Patent Document 3).
  • nc-IGZO has a periodic atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity is observed in crystal orientation between different regions. There is.
  • Non-Patent Document 4 and Non-Patent Document 5 show the transition of the average crystal size due to the irradiation of electron beams on the thin films of CAAC-IGZO, nc-IGZO, and IGZO having low crystallinity.
  • a thin film of IGZO having low crystallinity crystalline IGZO having a crystal size of about 1 nm is observed even before being irradiated with an electron beam. Therefore, it is reported here that it was not possible to confirm the existence of a completely amorphous structure (complete amorphous structure) in IGZO.
  • the CAAC-IGZO thin film and the nc-IGZO thin film have higher stability against electron beam irradiation than the IGZO thin film having low crystallinity. Therefore, it is preferable to use a thin film of CAAC-IGZO or a thin film of nc-IGZO as a semiconductor of the transistor.
  • a transistor including a metal oxide has a very small leak current in a non-conduction state, specifically, an off-state current per 1 ⁇ m of a channel width of the transistor is on the order of yA/ ⁇ m (10 ⁇ 24 A/ ⁇ m).
  • yA/ ⁇ m 10 ⁇ 24 A/ ⁇ m.
  • Non-Patent Document 8 application of the transistor to a display device has been reported, which utilizes the characteristic that a transistor including a metal oxide has a low leakage current (see Non-Patent Document 8).
  • the displayed image is switched several tens of times per second. The number of times the image is switched per second is called the refresh rate.
  • the refresh rate may also be called the drive frequency.
  • Such high-speed screen switching which is difficult for human eyes to perceive, is considered as a cause of eye fatigue. Therefore, it has been proposed to reduce the refresh rate of the display device to reduce the number of image rewrites.
  • driving with a reduced refresh rate makes it possible to reduce power consumption of the display device.
  • IDS idling stop
  • the discovery of the CAAC structure and the nc structure contributes to improvement in electrical characteristics and reliability of a transistor including a metal oxide having a CAAC structure or an nc structure, cost reduction in a manufacturing process, and improvement in throughput. Further, application research of the transistor to a display device and an LSI, which utilizes the characteristic that the leak current of the transistor is low, is under way.
  • An insulating material for forming an insulating layer, a conductive material for forming a conductive layer, or a semiconductor material for forming a semiconductor layer is formed by a sputtering method, a spin coating method, a CVD (Chemical Vapor Deposition) method (thermal method).
  • CVD method MOCVD (Metal Organic Chemical Vapor Deposition) method, PECVD (Plasma Enhanced CVD) method, high density plasma CVD (High density plasma CVD) method, LPCVD (low pressure plasma AP) method, LPCVD (low pressure plasma AP) method, Including), ALD (Atomic Layer Deposition) method, MBE (Molecular Beam Epitaxy) method, PLD (Pulsed Laser Deposition) method, dip method, spray coating method, ink jet method, etc. (Screen printing, offset printing, etc.).
  • the plasma CVD method can obtain a high quality film at a relatively low temperature.
  • a film formation method that does not use plasma at the time of film formation such as the MOCVD method, the ALD method, or the thermal CVD method
  • the surface to be formed is less likely to be damaged.
  • a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in a memory device might be charged up by receiving electric charge from plasma. At this time, the accumulated charge may destroy wirings, electrodes, elements, and the like included in the memory device.
  • plasma damage does not occur, so that the yield of the memory device can be increased. Further, since plasma damage does not occur during film formation, a film with few defects can be obtained.
  • the ALD method utilizes the self-controllability, which is a property of atoms, and allows atoms to be deposited one layer at a time, which enables ultrathin film formation and film formation on a structure with a high aspect ratio. It is possible to form a film with few defects such as holes, form a film with excellent coverage, and form a film at a low temperature.
  • the ALD method also includes a PEALD (Plasma Enhanced ALD) method using plasma. By using plasma, film formation at a lower temperature becomes possible, which may be preferable. Note that some precursors used in the ALD method include impurities such as carbon.
  • a film formed by the ALD method may contain a large amount of impurities such as carbon as compared with a film formed by another film formation method.
  • the impurities can be quantified using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).
  • the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, the film forming method is not easily affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of the opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively low film forming rate, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the source gas.
  • a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gas.
  • This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments and the like.
  • FIG. 12A is a top view of the transistor 210A.
  • FIG. 12B is a cross-sectional view taken along the alternate long and short dash line in FIG.
  • FIG. 12C is a cross-sectional view taken along the alternate long and short dash line W1-W2 in FIG. 12A.
  • some elements are omitted for the sake of clarity.
  • the transistor 210A, the insulating layer 361, the insulating layer 362, the insulating layer 365, the insulating layer 366, the insulating layer 371, the insulating layer 380, the insulating layer 374, and the insulating layer 374 which function as interlayer insulating layers are formed.
  • Layer 381 is shown.
  • a conductive layer 340 (a conductive layer 340a and a conductive layer 340b) which is electrically connected to the transistor 210A and functions as a contact plug is illustrated.
  • the insulating layer 341 (the insulating layer 341a and the insulating layer 341b) is provided in contact with the side surface of the conductive layer 340 which functions as a contact plug.
  • interlayer insulating layer examples include silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba, Sr).
  • An insulator such as TiO 3 (BST) can be used in a single layer or a laminated layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator and used.
  • the transistor 210A includes a conductive layer 360 (a conductive layer 360a and a conductive layer 360b) which functions as a first gate electrode, a conductive layer 305 (a conductive layer 305a, and a conductive layer 305b) which function as a second gate electrode.
  • An insulating layer 349 which functions as a first gate insulating film, an insulating layer 365 and an insulating layer 366 which function as a second gate insulating layer, and a semiconductor layer 260 (a semiconductor layer 260a, a semiconductor layer having a region where a channel is formed) 260b and a semiconductor layer 260c), a conductive layer 342a which functions as one of a source and a drain, a conductive layer 342b which functions as the other of a source and a drain, and an insulating layer 371.
  • the conductive layer 305 is arranged so as to be embedded in the insulating layer 362, and the insulating layer 365 is arranged over the insulating layer 362 and the conductive layer 305.
  • the insulating layer 366 is disposed on the insulating layer 365.
  • the semiconductor layer 260 semiconductor layer 260a, semiconductor layer 260b, and semiconductor layer 260c
  • the insulating layer 349 is provided over the semiconductor layer 260, and the conductive layers 360 (the conductive layers 360a and 360b) are provided over the insulating layer 349.
  • the conductive layers 342a and 342b are provided in contact with part of the top surface of the semiconductor layer 260b, and the insulating layer 371 is part of the top surface of the insulating layer 366, the side surface of the semiconductor layer 260a, the side surface of the semiconductor layer 260b, and the conductive layer. It is arranged in contact with the side surface of the layer 342a, the upper surface of the conductive layer 342a, the side surface of the conductive layer 342b, and the upper surface of the conductive layer 342b.
  • the insulating layer 341 is provided in contact with the sidewalls of the openings formed in the insulating layer 380, the insulating layer 374, and the insulating layer 381, the first conductor of the conductive layer 340 is provided in contact with the side surface thereof, and further inside.
  • a second conductor of the conductive layer 340 is provided.
  • the height of the upper surface of the conductive layer 340 and the height of the upper surface of the insulating layer 381 can be approximately the same.
  • the transistor 210A has a structure in which the first conductor of the conductive layer 340 and the second conductor of the conductive layer 340 are stacked, the present invention is not limited to this.
  • the conductive layer 340 may have a single-layer structure or a stacked structure including three or more layers. When the structure has a laminated structure, an ordinal number may be given in the order of formation to distinguish them.
  • the semiconductor layer 260 is provided over the insulating layer 366, the semiconductor layer 260a, the semiconductor layer 260b over the semiconductor layer 260a, and the semiconductor layer 260b over at least a part of the semiconductor layer 260b. And a semiconductor layer 260c which is in contact with the top surface.
  • a semiconductor layer 260c which is in contact with the top surface.
  • the semiconductor layer 260 is preferably formed using an oxide semiconductor which is a kind of metal oxide.
  • a transistor including an oxide semiconductor for a semiconductor layer in which a channel is formed has extremely low leakage current (off current) in a non-conduction state. Therefore, a semiconductor device with reduced power consumption can be realized. Further, since the oxide semiconductor can be formed by a sputtering method or the like, a highly integrated semiconductor device can be easily realized.
  • an In-M-Zn oxide (the element M is gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium). It is preferable to use a metal oxide such as one or more selected from hafnium, tantalum, tungsten, magnesium, and the like. In particular, the element M is preferably gallium, yttrium, or tin. Alternatively, as the semiconductor layer 260, an In-M oxide, an In-Zn oxide, or an M-Zn oxide may be used.
  • a conductive layer 360 which functions as a first gate (also referred to as a top gate) electrode is formed in a self-aligned manner so as to fill an opening formed in the insulating layer 380 or the like.
  • the conductive layer 360 can be reliably arranged in the region between the conductive layers 342a and 342b without alignment.
  • the conductive layer 360 preferably includes a conductive layer 360a and a conductive layer 360b provided over the conductive layer 360a.
  • the conductive layer 360a is preferably arranged so as to cover the bottom surface and the side surface of the conductive layer 360b.
  • the top surface of the conductive layer 360 is substantially aligned with the top surface of the insulating layer 349 and the top surface of the oxide 260c.
  • the conductive layer 305 may function as a second gate (also referred to as a bottom gate) electrode in some cases.
  • the threshold voltage (Vth) of the transistor 210A can be controlled by changing the potential applied to the conductive layer 305 independently and independently of the potential applied to the conductive layer 360.
  • Vth of the transistor 210A can be higher than 0 V and off current can be reduced. Therefore, applying a negative potential to the conductive layer 305 can reduce the drain current when the potential applied to the conductive layer 360 is 0 V, as compared to the case where no potential is applied.
  • the conductive layer 305 and the conductive layer 360 are provided so as to overlap with each other with the channel formation region of the semiconductor layer 260 provided therebetween, when a voltage is applied to the conductive layer 305 and the conductive layer 360, an electric field generated from the conductive layer 360 is generated. And the electric field generated from the conductive layer 305 are connected to each other, so that the channel formation region of the semiconductor layer 260 can be covered.
  • the channel formation region can be electrically surrounded by the electric field of the conductive layer 360 having a function of the first gate electrode and the electric field of the conductive layer 305 having a function of the second gate electrode.
  • a structure of a transistor that electrically surrounds a channel formation region by electric fields of a first gate electrode and a second gate electrode is referred to as a surrounded channel (S-channel) structure.
  • the insulating layers 365 and 371 preferably have a function of suppressing diffusion of hydrogen (eg, at least one of hydrogen atoms and hydrogen molecules). Further, the insulating layers 365 and 371 preferably have a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules). For example, the insulating layer 365 and the insulating layer 371 each preferably have a function of suppressing diffusion of one or both of hydrogen and oxygen as compared with the insulating layer 366. The insulating layer 365 and the insulating layer 371 each preferably have a function of suppressing diffusion of one or both of hydrogen and oxygen as compared with the insulating layer 349. The insulating layer 365 and the insulating layer 371 each preferably have a function of suppressing diffusion of one or both of hydrogen and oxygen as compared with the insulating layer 380.
  • hydrogen eg, at least one of hydrogen atoms and hydrogen molecules
  • oxygen e.g, at least one of oxygen atoms and
  • a film having a function of suppressing diffusion of hydrogen or oxygen is referred to as a film in which hydrogen or oxygen does not easily pass, a film having low hydrogen or oxygen permeability, or a barrier property against hydrogen or oxygen.
  • the film may be referred to as a film that it has, a barrier film against hydrogen or oxygen, or the like.
  • the barrier film may be referred to as a conductive barrier film.
  • the insulating layer 371 includes side surfaces of the conductive layers 342a and 342b other than upper surfaces of the conductive layers 342a and 342b and side surfaces where the conductive layers 342a and 342b face each other.
  • the side surfaces of the semiconductor layers 260a and 260b are in contact with part of the upper surface of the insulating layer 366. Accordingly, the insulating layer 380 is separated from the insulating layer 366, the semiconductor layer 260a, and the semiconductor layer 260b by the insulating layer 371. Therefore, impurities such as hydrogen contained in the insulating layer 380 and the like can be suppressed from entering the insulating layer 366, the semiconductor layer 260a, and the semiconductor layer 260b.
  • the transistor 210A has a structure in which the insulating layer 374 is in contact with the top surfaces of the conductive layer 360, the insulating layer 349, and the semiconductor layer 260c.
  • impurities such as hydrogen contained in the insulating layer 381 and the like can be prevented from entering the insulating layer 349. Therefore, adverse effects on the electrical characteristics of the transistor and the reliability of the transistor can be suppressed.
  • a transistor with high on-state current can be provided.
  • a transistor with low off-state current can be provided.
  • FIG. 13A is a top view of the transistor 210B.
  • FIG. 13B is a cross-sectional view taken along the alternate long and short dash line in FIG.
  • FIG. 13C is a cross-sectional view taken along the alternate long and short dash line W1-W2 in FIG. 13A. Note that in the top view of FIG. 13A, some elements are omitted for clarity.
  • the transistor 210B is a modification of the transistor 210A. Therefore, in order to prevent repetition of description, points different from the transistor 210A are mainly described.
  • the conductive layer 360 functioning as the first gate electrode has a conductive layer 360a and a conductive layer 360b over the conductive layer 360a.
  • a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms.
  • a conductive material having a function of suppressing diffusion of oxygen eg, at least one of oxygen atoms and oxygen molecules is preferably used.
  • the conductive layer 360a has a function of suppressing diffusion of oxygen, the material selectivity of the conductive layer 360b can be improved. That is, by having the conductive layer 360a, oxidation of the conductive layer 360b can be suppressed and a decrease in conductivity can be prevented.
  • the insulating layer 371 is preferably provided so as to cover the top surface and the side surface of the conductive layer 360, the side surface of the insulating layer 349, and the side surface of the semiconductor layer 260c.
  • the insulating layer 371 is preferably formed using an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen.
  • impurities such as water or hydrogen and oxygen.
  • metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride can be used.
  • oxidation of the conductive layer 360 can be suppressed.
  • the presence of the insulating layer 371 can suppress diffusion of impurities such as water and hydrogen included in the insulating layer 380 to the transistor 210B.
  • the conductive layer 360 overlaps with part of the conductive layer 342a and part of the conductive layer 342b; therefore, parasitic capacitance is likely to be higher than that of the transistor 210A. Therefore, the operating frequency tends to be lower than that of the transistor 210A.
  • the productivity is higher than that of the transistor 210A.
  • This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments and the like.
  • FIG. 19 illustrates a structure of a semiconductor device of one embodiment of the present invention.
  • the semiconductor device 800 described in this embodiment includes the semiconductor device 100 and the semiconductor device 700 (see FIG. 19).
  • the semiconductor device described in Embodiment 2 can be used for the semiconductor device 100.
  • the semiconductor device described in Embodiment 1 can be used for the semiconductor device 700.
  • the semiconductor device 100 has a function of supplying a predetermined current or a predetermined voltage.
  • the semiconductor device 100 is electrically connected to the second semiconductor device 700, and the semiconductor device 100 is supplied with the control signal CI1. Further, the semiconductor device 100 operates based on the control signal CI1.
  • the semiconductor device 100 can stop the power supply based on the control signal CI1.
  • the control signal CI1 is supplied to the input/output circuit 106, and based on the control signal CI1, the control circuit 105 causes the current adjustment circuit 104 to stop supplying power (see FIG. 17).
  • the first semiconductor device 100 can be feedback-controlled using the second semiconductor device 700.
  • a novel semiconductor device with excellent convenience or reliability can be provided.
  • the detection unit 702 includes a voltage detector VD.
  • the voltage detector VD measures the voltage required to supply a predetermined current.
  • the storage unit 701B holds standard data DATA related to voltage.
  • the abnormality of the first semiconductor device 100 connected to the second semiconductor device 700 can be monitored using voltage.
  • the abnormality of the load connected to the first semiconductor device 100 can be monitored using the voltage.
  • the detection unit 702 includes a current detector CD, and the current detector CD measures the current required to supply a predetermined voltage.
  • the storage unit 701B holds standard data DATA regarding current.
  • the abnormality of the first semiconductor device 100 electrically connected to the second semiconductor device 700 can be monitored using current.
  • the abnormality of the load electrically connected to the first semiconductor device 100 can be monitored using current.
  • the detection unit 702 includes a terminal TT (see FIG. 1A). Further, the terminal TT is supplied with a detection signal regarding temperature.
  • the temperature of the first semiconductor device 100 or the load connected to the second semiconductor device 700 can be monitored for abnormality.
  • a novel semiconductor device with excellent convenience or reliability can be provided.
  • This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments and the like.
  • FIG. 19 illustrates a structure of a secondary battery system of one embodiment of the present invention.
  • the secondary battery system described in this embodiment includes a secondary battery 200 and a semiconductor device 800.
  • the semiconductor device 800 described in Embodiment 5 can be used.
  • the secondary battery 200 is electrically connected to the semiconductor device 800.
  • a voltage applied to the secondary battery 200 being charged with a constant current and exceeding the tolerance information TI can be detected.
  • the control signal can be supplied based on the tolerance information TI derived from the characteristics of the secondary battery 200.
  • the secondary battery system described in this embodiment includes a secondary battery 200 and a semiconductor device 800.
  • the secondary battery 200 is electrically connected to the semiconductor device 800.
  • the secondary battery 200 includes a battery cell and a temperature detector TD.
  • the semiconductor device 800 described in Embodiment 5 can be used.
  • the temperature detector TD is electrically connected to the terminal TT, and the temperature detector TD detects the temperature of the battery cell.
  • This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments and the like.
  • a cylindrical secondary battery 600 will be described with reference to FIGS. 14A and 14B.
  • the cylindrical secondary battery 600 has a positive electrode cap (battery lid) 601 on the upper surface and battery cans (exterior cans) 602 on the side surfaces and the bottom surface.
  • the positive electrode cap (battery lid) 601 and the battery can (outer can) 602 are insulated by a gasket (insulating packing) 610.
  • FIG. 14B is a diagram schematically showing a cross section of a cylindrical secondary battery.
  • a battery element in which a strip-shaped positive electrode 604 and a negative electrode 606 are wound with a separator 605 sandwiched therebetween is provided.
  • the battery element is wound around the center pin.
  • the battery can 602 has one end closed and the other end open.
  • a metal such as nickel, aluminum, or titanium having corrosion resistance to an electrolytic solution, or an alloy thereof or an alloy of these and another metal (for example, stainless steel) can be used. .. Further, in order to prevent corrosion due to the electrolytic solution, it is preferable to coat with nickel or aluminum.
  • the secondary battery includes a positive electrode containing an active material such as lithium cobalt oxide (LiCoO 2 ) or lithium iron phosphate (LiFePO 4 ), a negative electrode made of a carbon material such as graphite capable of absorbing and desorbing lithium ions, and ethylene. It is composed of a non-aqueous electrolytic solution in which an electrolyte composed of a lithium salt such as LiBF 4 or LiPF 6 is dissolved in an organic solvent such as carbonate or diethyl carbonate.
  • an active material such as lithium cobalt oxide (LiCoO 2 ) or lithium iron phosphate (LiFePO 4 )
  • LiFePO 4 lithium iron phosphate
  • a positive electrode terminal (positive electrode current collecting lead) 603 is connected to the positive electrode 604, and a negative electrode terminal (negative electrode current collecting lead) 607 is connected to the negative electrode 606. Both the positive electrode terminal 603 and the negative electrode terminal 607 can use a metal material such as aluminum.
  • the positive electrode terminal 603 is resistance-welded to the safety valve mechanism 612, and the negative electrode terminal 607 is resistance-welded to the bottom of the battery can 602.
  • the safety valve mechanism 612 is electrically connected to the positive electrode cap 601 via a PTC element (Positive Temperature Coefficient) 611.
  • the safety valve mechanism 612 disconnects the electrical connection between the positive electrode cap 601 and the positive electrode 604 when the increase in the internal pressure of the battery exceeds a predetermined threshold value.
  • the PTC element 611 is a PTC element whose resistance increases when the temperature rises, and limits the amount of current due to the increase in resistance to prevent abnormal heat generation.
  • barium titanate (BaTiO 3 ) based semiconductor ceramics or the like can be used.
  • a lithium-ion secondary battery using an electrolytic solution has a positive electrode, a negative electrode, a separator, an electrolytic solution, and an outer package.
  • the anode (anode) and the cathode (cathode) are switched by charging and discharging, and the oxidation reaction and the reduction reaction are switched. Therefore, the electrode with a high reaction potential is called the positive electrode, and the reaction potential is higher.
  • the electrode with a low value is called the negative electrode.
  • the positive electrode is referred to as a “positive electrode” or a “+electrode (plus electrode)”
  • the negative electrode is referred to as a “negative electrode” or a “ ⁇ electrode (whether during charging or discharging, whether it is during charging or discharging. Minus pole)”.
  • anode (anode)” and “cathode (cathode)” related to the oxidation reaction and the reduction reaction are used, the charging time and the discharging time are reversed, which may cause confusion. Therefore, the terms anode (anode) and cathode (cathode) are not used in this specification. If the terms anode (anode) and cathode (cathode) are used, indicate whether they are charging or discharging and also indicate whether they correspond to the positive electrode (positive electrode) or the negative electrode (negative electrode). To do.
  • a material containing an element A, an element X, and oxygen is used as a positive electrode material for a secondary battery without being limited to a lithium ion secondary battery.
  • the element A is preferably one or more selected from Group 1 elements and Group 2 elements.
  • the Group 1 element for example, an alkali metal such as lithium, sodium, or potassium can be used.
  • the Group 2 element for example, calcium, beryllium, magnesium, or the like can be used.
  • the element X for example, one or more selected from a metal element, silicon and phosphorus can be used.
  • the element X is preferably one or more selected from cobalt, nickel, manganese, iron, and vanadium. Typically, lithium cobalt composite oxide (LiCoO 2 ) and lithium iron phosphate (LiFePO 4 ) can be given.
  • the negative electrode has a negative electrode active material layer and a negative electrode current collector. Further, the negative electrode active material layer may have a conductive additive and a binder.
  • an element capable of performing a charge/discharge reaction by an alloying/dealloying reaction with lithium can be used.
  • a material containing at least one of silicon, tin, gallium, aluminum, germanium, lead, antimony, bismuth, silver, zinc, cadmium, indium and the like can be used.
  • Such an element has a larger capacity than carbon, and particularly silicon has a high theoretical capacity of 4200 mAh/g.
  • the secondary battery preferably has a separator.
  • the separator for example, fibers including cellulose such as paper, non-woven fabric, glass fiber, ceramics, or nylon (polyamide), vinylon (polyvinyl alcohol fiber), polyester, acryl, polyolefin, synthetic fiber using polyurethane, etc. It is possible to use those formed in.
  • This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments and the like.
  • the semiconductor device according to one embodiment of the present invention can be mounted on various electronic devices.
  • electronic devices include television devices, desktop or notebook personal computers, monitors for computers, digital signage, and large game machines such as pachinko machines.
  • electronic devices including screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, sound reproduction devices, and the like can be given.
  • moving bodies such as automobiles, two-wheeled vehicles, ships, and airplanes can be said to be electronic devices.
  • the semiconductor device according to one embodiment of the present invention can be used for a battery charge monitoring device incorporated in these electronic devices.
  • the electronic device may have an antenna. By receiving the signal with the antenna, images, information, and the like can be displayed on the display portion.
  • the antenna may be used for contactless power transmission.
  • Electronic devices include sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, It has a function of measuring flow rate, humidity, gradient, vibration, odor or infrared light).
  • Electronic devices can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of executing various software (programs), wireless communication It can have a function, a function of reading a program or data recorded in a recording medium, and the like.
  • FIG. 15 a moving object including the semiconductor device of one embodiment of the present invention and a secondary battery is illustrated.
  • the secondary battery 8024 of the automobile 8400 illustrated in FIG. 15A can not only drive the electric motor 8406 but also can supply power to a light-emitting device such as a headlight 8401 or a room light (not illustrated).
  • a battery module using a plurality of cylindrical secondary batteries 600 shown in FIGS. 14A and 14B may be used.
  • the charge monitoring device 8025 includes the semiconductor device of one embodiment of the present invention and charges the secondary battery 8024 depending on ambient temperature.
  • the automobile 8500 illustrated in FIG. 15B can be charged by being supplied with power from an external charging facility by a secondary battery included in the automobile 8500 by a plug-in method, a contactless power feeding method, or the like.
  • FIG. 15B shows a state in which a charging device 8021 installed on the ground is charging a secondary battery 8024 mounted on an automobile 8500 via a cable 8022.
  • the charging monitoring device 8025 including the semiconductor device of one embodiment of the present invention can perform charging depending on the ambient temperature. Note that a charging monitoring device including the semiconductor device of one embodiment of the present invention may be provided in the charging device 8021.
  • the charging method, the connector standard, and the like may be appropriately performed by a predetermined method such as CHAdeMO (registered trademark) or combo.
  • the charging device 8021 may be a charging station provided in a commercial facility or may be a home power source.
  • the secondary battery 8024 mounted on the automobile 8500 can be charged by external power supply. Charging can be performed by converting AC power into DC power via a converter such as an ACDC converter.
  • the power receiving device may be mounted on a moving body, and electric power may be supplied from the power transmitting device on the ground in a contactless manner to charge the mobile device.
  • this contactless power feeding method by incorporating a power transmission device on a road or an outer wall, charging can be performed not only when the vehicle is stopped but also when the vehicle is running. Moreover, you may transmit and receive electric power between moving bodies using this non-contact electric power feeding system.
  • a solar cell may be provided on the exterior of the moving body to charge the secondary battery when the vehicle is stopped or moved.
  • an electromagnetic induction method or a magnetic field resonance method can be used.
  • FIG. 15C is an example of a two-wheeled vehicle using a secondary battery.
  • the scooter 8600 illustrated in FIG. 15C includes a secondary battery 8602, a charge monitoring device 8625, a side mirror 8601, and a direction indicator light 8603.
  • the secondary battery 8602 can supply electricity to the direction indicator light 8603.
  • the charging monitoring device 8625 including the semiconductor device of one embodiment of the present invention can charge the secondary battery 8602 in accordance with the ambient temperature.
  • the scooter 8600 illustrated in FIG. 15C can store the secondary battery 8602 in the under-seat storage 8604.
  • the secondary battery 8602 can be stored in the under-seat storage 8604 even if the under-seat storage 8604 is small.
  • the semiconductor device according to one embodiment of the present invention can be applied not only to a mobile object but also to a device including a secondary battery and a wireless module.
  • FIG. 16A shows an example of a mobile phone.
  • the mobile phone 7400 includes a display portion 7402 incorporated in a housing 7401, operation buttons 7403, an external connection port 7404, a speaker 7405, a microphone 7406, and the like. Note that the mobile phone 7400 includes a power storage device 7407 and a charge monitoring device for the power storage device 7407.
  • FIG. 16B is a projection diagram illustrating an example of the outer appearance of the information processing device 1200.
  • the information processing device 1200 described in this embodiment includes an arithmetic device, an input/output device, a housing 1210, a display portion 1230, a display portion 1240, a power storage device 1250, and a charge monitoring device.
  • the information processing device 1200 has a communication unit and has a function of supplying information to the network and a function of acquiring information from the network. Further, the information distributed to the specific space may be received using the communication unit, and the image information may be generated based on the received information.
  • the information processing apparatus 1200 can function as a personal computer by setting a screen in which either the display unit 1230 or the display unit 1240 is keyboard-displayed as the touch input panel.
  • a wearable device as illustrated in FIG. 16C may be provided with the secondary battery charge monitoring device of one embodiment of the present invention.
  • the charge monitoring device may be provided in the eyeglass-type device 400 as shown in FIG. 16C.
  • the eyeglass-type device 400 includes a frame 400a, a display unit 400b, and a wireless module.
  • a power storage device, a charge monitoring device, and a wireless module may be provided on the temple portion of the curved frame 400a.
  • a power storage device, a charge monitoring device, and a wireless module can be mounted on the headset-type device 401.
  • the headset-type device 401 has at least a microphone section 401a, a flexible pipe 401b, and an earphone section 401c.
  • a power storage device, a charge monitoring device, and a wireless module can be provided in the flexible pipe 401b or the earphone unit 401c.
  • a power storage device 402b and a charge monitoring device for the power storage device can be provided in a thin housing 402a of the device 402.
  • a power storage device 403b and a charge monitoring device for the power storage device can be provided in a thin housing 403a of the device 403.
  • the wristwatch type device 405 has a display portion 405a and a belt portion 405b, and the display portion 405a or the belt portion 405b can be provided with a power storage device and a charge monitoring device for the power storage device.
  • the display unit 405a can display not only the time but also various information such as incoming mails and telephone calls.
  • the wristwatch-type device 405 is a wearable device of a type that is directly wrapped around the arm, it may be equipped with a sensor that measures a user's pulse, blood pressure, and the like. Data on the amount of exercise and health of the user can be accumulated and can be used for maintaining health.
  • the belt device 406 includes a belt portion 406a and a wireless power feeding and receiving portion 406b, and a power storage device, a charge monitoring device, and a wireless module can be mounted inside the belt portion 406a.
  • FIG. 16D is a perspective view of a device also called a cigarette-containing smoking device (electronic cigarette).
  • a cigarette-containing smoking device electronic cigarette
  • an electronic cigarette 7410 includes an atomizer 7411 including a heating element, a power storage device 7414 for supplying electric power to the atomizer, and a cartridge 7412 including a liquid supply bottle, a sensor, and the like.
  • a power storage device charge monitoring device may be electrically connected to the power storage device 7414 in order to increase safety.
  • the power storage device 7414 illustrated in FIG. 16D has an external terminal so that the power storage device 7414 can be connected to a charging device. Since the power storage device 7414 becomes a tip portion when held, it is desirable that the total length be short and the weight be light.

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  • Engineering & Computer Science (AREA)
  • General Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Secondary Cells (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
PCT/IB2019/059724 2018-11-26 2019-11-13 半導体装置、二次電池システム Ceased WO2020109901A1 (ja)

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