WO2020103672A1 - 横向双扩散金属氧化物半导体场效应管及其制备方法 - Google Patents

横向双扩散金属氧化物半导体场效应管及其制备方法

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Publication number
WO2020103672A1
WO2020103672A1 PCT/CN2019/114986 CN2019114986W WO2020103672A1 WO 2020103672 A1 WO2020103672 A1 WO 2020103672A1 CN 2019114986 W CN2019114986 W CN 2019114986W WO 2020103672 A1 WO2020103672 A1 WO 2020103672A1
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Prior art keywords
metal
gate structure
region
drift region
drain region
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PCT/CN2019/114986
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English (en)
French (fr)
Inventor
高桦
孙贵鹏
罗泽煌
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无锡华润上华科技有限公司
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Publication of WO2020103672A1 publication Critical patent/WO2020103672A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like

Definitions

  • the invention relates to the semiconductor field, in particular to a lateral double-diffused metal oxide semiconductor field effect tube and a preparation method thereof.
  • LDMOS lateral double-diffused metal oxide semiconductor field effect transistor
  • LDMOS Longeral Double-diffused MOSFET
  • a field plate is usually formed on the surface of the drift region
  • the shallow trench isolation structure in the drift region regulates the electric field below the drift region.
  • a stepped field plate or an extended field plate is generally formed.
  • Various embodiments according to the present application provide a method for manufacturing a lateral double-diffused metal oxide semiconductor field effect tube and a lateral double-diffused metal oxide semiconductor field effect tube.
  • a lateral double-diffused metal oxide semiconductor field effect tube including:
  • a drift region having a second conductivity type, formed on the surface layer of the semiconductor substrate;
  • a gate structure provided on the semiconductor substrate and covering a part of the surface of the drift region
  • the source region and the drain region, which have the second conductivity type, are formed on both sides of the gate structure, the drain region is formed in the drift region and away from the gate structure, and the source region is formed in the In the substrate and connected to the gate structure;
  • a metal silicide barrier layer formed on the drift region between the gate structure and the drain region;
  • a metal field plate is formed on the oxide layer.
  • the metal field plate includes a plurality of metal segments spaced from the gate structure toward the drain region.
  • a semiconductor substrate is provided, a drift region, a source region and a drain region are formed in the semiconductor substrate, a gate structure is formed on the semiconductor substrate, the semiconductor substrate has a first conductivity type, the drift region, The source region and the drain region have a second conductivity type, the gate structure covers a part of the surface of the drift region, the source region and the drain region are located on both sides of the gate structure, respectively, and the drain region is formed Within the drift region and away from the gate structure, the source region is formed in the substrate and is in contact with the gate structure;
  • the metal field plate is etched to form a plurality of metal segments spaced from the gate structure toward the drain region.
  • FIG. 1 is a schematic structural diagram of an LDMOS in an embodiment
  • 3a to 3f are structural diagrams corresponding to relevant steps of the LDMOS manufacturing method in an embodiment.
  • the LDMOS includes a semiconductor substrate 100, a drift region 110 is formed in the semiconductor substrate 100, a drain region 111 is formed in the drift region 110, and an active is formed outside the drift region 110 In the region 122, a gate structure 200 is formed between the source region 122 and the drain region 111.
  • the gate structure 200 is disposed on the surface of the semiconductor substrate 100 and covers a part of the surface of the drift region 110, that is, the drain region 111 is formed in the drift region 110 Inside and away from the gate structure 200, the source region 122 is formed on the other side of the gate structure 200 and is in contact with the gate structure 200, and a metal silicide is formed on the surface of the drift region between the gate structure 200 and the drain region 111
  • the barrier layer 400 is formed with an oxide layer 500 on the metal silicide barrier layer 400, and a metal field plate 600 is formed on the oxide layer 500, and the metal field plate 600 includes a plurality of metals spaced from the gate structure in the direction of the drain region segment.
  • the semiconductor substrate 100 has a first conductivity type
  • the drift region 110, the drain region 111, and the source region 122 have a second conductivity type
  • the first conductivity type and the second conductivity type have opposite conductivity properties.
  • the main area of LDMOS withstand voltage is the drift region 110.
  • the concentration and size of the drift region 110 are the main factors that determine the breakdown voltage of the device. Reducing the concentration of the drift region 110 or increasing the length of the drift region can improve the withstand voltage of the device. But this will also make other device characteristics worse, such as on-resistance, on-state characteristics (on-state characteristics) and so on.
  • the drift region 110 of the device needs to be fully depleted, that is, the surface electric field of the device needs to be optimized.
  • a field plate is provided above the drift zone, and the electric field distribution on the surface of the drift zone is regulated by the field plate.
  • the electric field distribution on the surface of the drift region is not uniform, and the drift region of the device cannot be fully depleted. If a field plate is added to the drift region, the electric field on the surface can be improved and the depletion of the drift region of the device is more adequate .
  • the size of the drift region is relatively large. Full coverage of the entire field plate on the drift region will cause the device to be depleted too quickly, resulting in a low withstand voltage of the device, so the field plate structure needs to be re-optimized. Therefore, when it is necessary to further improve the voltage resistance of the device, a slanted field plate or a stepped field plate is usually formed.
  • the oxide layer under the field plate near the main junction is thin, and the thickness of the oxide layer gradually increases toward the drain region.
  • the stronger the modulation effect of the field plate on the electric field, and the thicker the oxide layer, the weaker the modulation effect of the field plate on the electric field. Set oxide layers of different thicknesses to modulate the electric field in the drift region at different positions, so that the drift region The surface electric field distribution is more uniform, which further improves the breakdown voltage of LDMOS, but at the same time, it also increases the difficulty and cost of the LDMOS preparation process.
  • a metal silicide barrier layer 400, an oxide layer 500, and a metal field plate 600 are sequentially formed above the drift region 110, wherein the material of the metal field plate 600 can be selected from a metal with a small conductivity and good adhesion.
  • Metal-like materials such as titanium, titanium silicide, or tungsten silicide.
  • the metal silicide barrier layer 400 and the oxide layer 500 are dielectric layers. By adjusting the thickness of the dielectric layer, the metal field plate 600 can adjust the electric field of the drift region 110 to different degrees.
  • the metal field plate 600 includes a plurality of spaced metal segments, which are spaced from the gate structure 200 to the drain region 111 above the drift region, and apply different voltages to the metal segments at different positions according to the electric field distribution on the surface of the drift region 110 itself , So that different potentials are formed at different locations of the drift region 110, thereby regulating the internal electric field of the drift region 110, making the internal electric field distribution of the drift region 110 more uniform, greatly improving the breakdown voltage of the LDMOS, and the segmented metal segment is in the process It only needs one step to form, and the preparation is simple. At the same time, if it is set as a segmented metal segment, the electric field distribution on the surface of the drift region 110 can be further adjusted by adjusting its number and spacing.
  • the surface electric field of the device when the device pitch is relatively small, the surface electric field of the device can also be optimized, no buried layer is required, and it is not limited by its junction depth, and the device has a wide application voltage range.
  • the device surface electric field optimization effect of the device with a voltage of 50V to 100V is relatively good, and the device junction depth and device pitch can be relatively reduced.
  • the first conductivity type is P-type and the second conductivity type is N-type. In other embodiments, the first conductivity type may be N-type, and the second conductivity type is P-type.
  • the gate structure includes a gate oxide layer 210 and a polysilicon layer 220, and the semiconductor substrate 100 under the gate oxide layer 210 forms a channel region.
  • a body region 120 having a first conductivity type is further formed in the semiconductor substrate 100, the body region 120 and the semiconductor substrate 100 jointly form a channel region, and the source region 122 is formed in the body region 120 The doping concentration of 120 is higher than that of the semiconductor substrate 100.
  • a sidewall 300 is formed on the sidewall of the gate structure 200, that is, a sidewall 300 is formed on the sidewall of the gate oxide layer 210 and the sidewall of the polysilicon layer 220, and the sidewall 300 includes a dielectric
  • the material can further isolate the gate structure 200 from the two side structures.
  • the oxide layer 500 may be located only on the surface of the metal silicide 400, or on the surface of the metal silicide 400, the surface of the gate structure 200, the surface of the source region 122, the surface of the drift region 110, and the drain region
  • the surface of 111 is integrally formed.
  • the LDMOS further includes a top dielectric layer 700 that covers the source region 122, the gate structure 200, the drift region 110, and the drain region 111.
  • a first metal silicide 123 is formed on the surface layer of the source region 122
  • a second metal silicide 112 is formed on the surface layer of the drain region 111
  • a third metal silicide is formed on the surface layer of the gate structure 200 221, wherein the third metal silicide 221 is specifically formed on the surface layer of the polysilicon layer 220.
  • the source electrode 810 is extracted at the first metal silicide 123
  • the gate electrode (not shown in FIG. 1) is extracted at the second metal silicide 221
  • the drain electrode 830 is extracted at the third metal silicide 112.
  • the metal field plate 600 leads to contact holes, which are filled with conductive material.
  • the source electrode 810, the drain electrode 830, and the gate electrode are all connected to the metal silicide through the top dielectric layer 700.
  • metal silicide By providing metal silicide, the contact resistance between each conductive electrode and each active region can be reduced. Since the metal silicide barrier layer 400 is provided on the surface of the drift region 110, the modulation region of the drift region surface can be defined by the metal silicide barrier layer 400.
  • metal silicide is formed in the source region, the drain region and the gate structure
  • no metal silicide is formed on the top layer of the metal silicide group 400. Therefore, the metal silicide barrier layer not only has the function of modulating the electric field of the drift region but also has a definition The role of the modulation region in the drift region avoids the formation of metal silicide in the modulation region of the drift region.
  • the metal field plate 600 is located directly above the metal silicide barrier layer 400, and the coverage area of the metal field plate 600 is less than or equal to the coverage area of the metal silicide barrier layer 400.
  • the metal silicide barrier layer 400 may be located only on the surface of the drift region 110, or may be located on the surface of the drift region 110 and extend to the gate structure 200, specifically to the surface of the polysilicon 220, from the gate
  • a plurality of metal segments spaced apart in the direction of the drain region 111 of the structure 200 includes a metal segment straddling the gate structure 200 and the drift region 110 and the drift region 110 between the gate structure 200 and the drain region 111
  • the electric field modulation structure may be located only on the surface of the drift region 110 It may also be located on the surface of the drift region 110 and extend from the surface of the drift region 110 to a part of the top surface of the gate structure 200.
  • the length of the metal segment across the gate structure 200 and the drift region 110 is greater than the length of the metal segment above the drift region 110 only between the gate structure 200 and the drain region 111.
  • the metal silicide barrier layer 400 and the metal field plate 600 also cover the surface of the sidewall spacer 300.
  • the length of the metal segment near the gate structure 200 is the longest, and the metal segment near the gate structure 200 extends from the drift region 110 to the gate structure 200.
  • Contact holes are drawn on the metal field plate 600, and the contact holes are specifically connected to the metal field plate 600 covering the drift region 110.
  • the contact holes on different metal segments can be connected to different voltages to change the potential of the metal segment, which can be adjusted according to specific circumstances.
  • the material filled in the contact hole is selected to be a material suitable for the metal field plate, such as a metal or metal-like material with small conductivity and good adhesion, such as titanium, titanium silicide, or tungsten silicide.
  • the potential of the metal segment near the gate structure 200 and the potential of the remaining metal segments may be the same or different.
  • the metal segment near the gate structure 200 is grounded, or the metal segment near the gate structure 200 may also have the same potential as the gate or the source, and the potentials of the remaining metal segments are suspended.
  • a contact hole 820 is drawn across the metal segment on the gate structure 200 and the drift region 110, and the contact hole 820 is filled with a field plate material, such as a metal with a small conductivity and good adhesion Or metal-like materials, such as titanium, titanium silicide or tungsten silicide.
  • the contact hole 820 can be grounded, or connected to the source 810, or connected to the gate, and other metal segments are suspended, which can change the potential distribution on the surface of the drift region, so that a high electric field peak at the main junction is decomposed into several lower The peak value of the electric field, so that the electric field distribution on the surface of the drift region is more uniform, increasing the breakdown voltage.
  • different voltages can also be connected to each metal segment, so that the surface potential of the drift region increases stepwise. It is also possible to decompose a high electric field peak at the main junction into several lower electric field peaks, thereby making the electric field distribution on the surface of the drift region more uniform and increasing the breakdown voltage.
  • the length of the spaced metal segments gradually increases from the drain region 111 toward the gate structure 200, and the distance between the spaced metal segments gradually increases from the drain region 222 toward the gate structure 200 In this way, the surface potential of the drift region 110 can be uniformly segmented, the electric field distribution on the surface of the drift region can be uniform, and the withstand voltage of the device can be improved.
  • the device pitch of the drift region is approximately 3 ⁇ m to 4 ⁇ m, and the distance between the metal segment near the gate structure 200 and the adjacent metal segment is 0.15 ⁇ m to 0.3 ⁇ m That is, from the gate structure 200 toward the drain region 111, the distance between the first adjacent metal segments ranges from 0.15 ⁇ m to 0.3 ⁇ m.
  • the metal field plate 600 when the metal field plate 600 further includes a metal segment spanning the gate structure 200 and the drift region 110, the metal segment spanning the gate structure 200 and the drift region 110 and the adjacent metal The spacing between segments ranges from 0.15 ⁇ m to 0.3 ⁇ m.
  • the present application also relates to a method for manufacturing a lateral double-diffused metal oxide semiconductor field effect tube.
  • the method includes the following steps.
  • Step S100 providing a semiconductor substrate in which a drift region, a source region and a drain region are formed, a gate structure is formed on the semiconductor substrate, the semiconductor substrate has a first conductivity type, a drift region, a source region and a drain region With a second conductivity type, the gate structure covers part of the surface of the drift region, the source region and the drain region are located on both sides of the gate structure, the drain region is formed in the drift region and away from the gate structure, and the source region is formed in the substrate And connected with the gate structure.
  • the semiconductor substrate 100 is doped to form the drift region 110
  • the drift region 110 is doped to form the drain region 111
  • the source region 122 is formed outside the drift region.
  • a portion of the surface of the drift region 110 between the drain region 111 and the surface of the semiconductor substrate 100 forms a gate structure 200, that is, the source region 122 and the drain region 111 are located on both sides of the gate structure 200, respectively, and the gate structure 200 also covers the drift region 110
  • the drain region 111 is spaced apart from the gate structure 200, and the source region 122 is connected to the gate structure 200.
  • forming the gate structure specifically includes forming a gate oxide layer 210 and forming a polysilicon layer 220 on the gate oxide layer, and the semiconductor substrate 100 under the gate oxide layer 210 forms a channel region.
  • the source region 122 before the source region 122 is formed, it further includes doping the semiconductor substrate 100 to form a body region 120 having the first conductivity type, and the body region 120 and the semiconductor substrate 100 jointly form a channel region. Doping the body region 120 to form the source region 122, the doping concentration of the body region 120 is higher than the doping concentration of the semiconductor substrate, which is beneficial to reduce the on-resistance of the channel region.
  • a sidewall 300 is formed on the sidewall of the gate structure 200, and the sidewall 300 includes a dielectric material.
  • forming the sidewall spacer 300 specifically includes: after forming the gate structure 200, depositing a dielectric layer on the surface of the device to etch back the dielectric layer, the dielectric layer on the sidewall of the gate structure 200 is retained Down, forming a side wall 300.
  • Step S200 forming a metal silicide barrier layer on the drift region between the gate structure and the drain region.
  • a target area window is defined by photoresist and a metal silicide blocking layer 400 is deposited in the target area window.
  • the metal silicide barrier layer 400 may be located only on the surface of the drift region 110, or may be located on the surface of the drift region 110 and extend to the gate structure 200, specifically to the surface of the polysilicon 220.
  • the metal silicide barrier layer 400 also covers the surface of the spacer 300.
  • Step S300 forming an oxide layer on the metal silicide barrier layer and forming a metal field plate on the metal oxide layer.
  • the method before forming the oxide layer, further includes forming a metal silicide on the surface layer of the source region, the surface layer of the gate structure, and the surface layer of the drain region, that is, forming the oxide layer on the metal silicide barrier layer specifically includes:
  • Step S310 deposit a reactive metal layer on the side of the semiconductor structure formed in step S200 having the active region.
  • a reactive metal layer 900 is deposited on the side of the semiconductor structure formed in step S200 having an active region.
  • the metal may be cobalt metal.
  • Step S320 heat-treating the semiconductor structure formed in step S310 to react the reaction metal layer with silicon to form a metal silicide.
  • the metal in the reactive metal layer 900 will only react with silicon. Since the sidewall spacer 300 and the metal silicide barrier layer 400 are dielectric layers, they will not react with metal. As shown in FIG. 3d, when the semiconductor structure is placed in a high-temperature environment, the metal in the reactive metal layer 900 reacts with the silicon in the source region 122, the polysilicon 220, and the drain region 111 to form a metal silicide.
  • the reactive metal is removed, that is, the metal at the side wall 300 and the metal at the metal silicide barrier layer 400 are removed, a first metal silicide 123 is formed on the surface of the source region 122, and a second metal silicide is formed on the surface of the gate structure 200 At the drain 111, a third metal silicide 112 is formed.
  • Step S330 forming an oxide layer on the metal silicide barrier layer and forming a metal field plate on the oxide layer.
  • the oxide layer may be located only on the surface of the metal silicide, or may be integrally formed on the surface of the metal silicide, the surface of the gate structure, the surface of the source region, the surface of the drift region, and the surface of the drain region.
  • an oxide layer 500 is deposited on the surface of the semiconductor device formed in step 320, that is, the oxide layer 500 is formed on the upper surface of the semiconductor structure, and a layer is deposited on the oxide layer 500 Metal field plate 600.
  • Step S400 Etching the metal field plate to form a plurality of metal segments arranged at intervals in the direction from the gate structure to the drain region.
  • the metal field plate 600 is etched to form a segmented metal segment above the metal silicide.
  • the metal silicide 400 is located on the surface of the drift region and from the surface of the drift region
  • a plurality of metal segments spaced from the gate structure 200 toward the drain region 111 include metal segments spanning the gate structure 200 and the drift region 110, and located between the gate structure 200 and the drain region Multiple metal segments on the drift region 110 between 111.
  • a metal segment close to the gate structure 200 is partially located on the drift region 110 and partially extends to a part of the top surface of the gate structure 200, that is, the metal silicide barrier layer 400, the metal field plate 600, and the oxide layer interposed therebetween 500 together constitute the electric field modulation structure of the drift region 110.
  • the electric field modulation structure may be located only on the surface of the drift region 110, or may be located on the surface of the drift region 110 and extend from the surface of the drift region 110 to a part of the top surface of the gate structure 200 .
  • the LDMOS preparation method further includes depositing a top dielectric layer 700 on the semiconductor surface formed in step S400, and etching the top dielectric layer 700 to extract the source electrode 810 from the source region 122 and the gate In the electrode structure, the gate is led out and the drain 830 is led out from the drain region 111.
  • the first metal silicide 123 is formed on the surface of the source region
  • the second metal silicide 221 is formed on the surface of the gate structure
  • the third metal silicide 112 is formed on the surface of the drain region
  • each electrode has a corresponding The metal silicide in the source area is connected.
  • a metal silicide barrier layer 400, an oxide layer 500, and a metal field plate 600 are sequentially formed above the drift region 110, wherein the material of the metal field plate 600 may be a metal with a small conductivity and good adhesion Or metal-like materials, such as titanium, titanium silicide or tungsten silicide.
  • the metal silicide barrier layer 400 and the oxide layer 500 are dielectric layers. By adjusting the thickness of the dielectric layer, the metal field plate 600 can adjust the electric field of the drift region 110 to different degrees.
  • the metal field plate 600 includes a plurality of spaced metal segments, which are spaced from the gate structure 200 to the drain region 111 above the drift region, and apply different voltages to the metal segments at different positions according to the electric field distribution on the surface of the drift region 110 itself , So that different potentials are formed at different locations of the drift region 110, thereby regulating the internal electric field of the drift region 110, making the internal electric field distribution of the drift region 110 more uniform, greatly improving the breakdown voltage of the LDMOS, and the segmented metal segment is in the process
  • the above is a one-step formation and simple preparation.
  • the electric field distribution on the surface of the drift region 110 can be further adjusted by adjusting its number and spacing.
  • Contact holes are drawn on the metal field plate, and the contact holes are filled with conductive material. Different voltages can be connected to the contact hole to change the potential of different metal segments, and the potential of each metal segment can be adjusted according to the specific situation.
  • a contact hole 820 is drawn across the metal segment on the gate structure 200 and the drift region 110.
  • the contact hole 820 may be grounded or connected to the source 810 Or connected to the gate, other metal segments are suspended, which can change the potential distribution on the surface of the drift region, so that a high electric field peak at the main junction is decomposed into several lower electric field peaks, so that the electric field distribution on the surface of the drift region is more uniform. Increase breakdown voltage.
  • different voltages can also be connected to each metal segment, so that the surface potential of the drift region increases stepwise.
  • a high electric field peak at the main junction can be decomposed into several lower electric field peaks, so that the electric field distribution on the surface of the drift region is more uniform, and the breakdown voltage is improved.

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Abstract

一种LDMOS，包括：半导体衬底(100)，和形成于半导体衬底(100)表层的漂移区(110)；栅极结构(200)设置于半导体衬底(100)的表面上且覆盖漂移区(110)的部分表面；源区(122)和漏区(111)分别形成于栅极结构(200)的两侧，漏区(111)形成于远离所述栅极结构(200)的一侧的漂移区(110)中，源区(122)形成于衬底(100)中且与栅极结构(200)相接；金属硅化物阻挡层(400)形成于栅极结构(200)和漏区(111)之间的漂移区(110)上；氧化层(500)和金属场板(600)依次叠设于金属硅化物阻挡层(400)上；金属场板(600)包括自栅极结构(200)向漏区(111)方向间隔设置的多个金属段。

Description

横向双扩散金属氧化物半导体场效应管及其制备方法
相关申请
本申请要求于2018年11月19日提交中国专利局的、申请号为201811377880.9、申请名称为“横向双扩散金属氧化物半导体场效应管及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体领域，尤其涉及一种横向双扩散金属氧化物半导体场效应管及其制备方法。
背景技术
在横向双扩散金属氧化物半导体场效应管(Lateral Double-diffused MOSFET，简称LDMOS)中，为兼顾LDMOS具有较好的耐压特性和较低的导通电阻，通常在漂移区表层形成场板代替漂移区中的浅槽隔离结构对漂移区下方电场进行调控。同时，在高工作电压下，为了使漂移区表面电场分布更加均匀，一般形成阶梯场板或延展型场板。但是，为形成阶梯场板或者延展型场板，在工艺上需要进行多次光刻，由此会使得工艺更加复杂且增加工艺成本，且受限于器件表面到器件电极引出层的介质层厚度要求，故该结构常用于分立器件中。而对于BCD(Bipolar-CMOS-DMOS)工艺平台，很少采用这种结构来提高耐压和改善表面电场。
发明内容
根据本申请的各种实施例提供一种横向双扩散金属氧化物半导体场效应管和横向双扩散金属氧化物半导体场效应管的制备方法。
一种横向双扩散金属氧化物半导体场效应管，包括：
半导体衬底，具有第一导电类型；
漂移区，具有第二导电类型，形成于所述半导体衬底的表层；
栅极结构，设置于所述半导体衬底上且覆盖所述漂移区的部分表面；
源区和漏区，具有第二导电类型，分别形成于所述栅极结构的两侧，所述漏区形成于所述漂移区内且远离所述栅极结构，所述源区形成于所述衬底中且与所述栅极结构相接；
金属硅化物阻挡层，形成于所述栅极结构和所述漏区之间的漂移区上；
氧化层，形成于所述金属硅化物阻挡层上；以及
金属场板，形成于所述氧化层上，所述金属场板包括自所述栅极结构向所述漏区方向间隔设置的多个金属段。
一种横向双扩散金属氧化物半导体场效应管制备方法，包括：
提供半导体衬底，所述半导体衬底内形成有漂移区、源区和漏区，所述半导体衬底上形成有栅极结构，所述半导体衬底具有第一导电类型，所述漂移区、源区和漏区具有第二导电类型，所述栅极结构覆盖所述漂移区的部分表面，所述源区和所述漏区分别位于所述栅极结构的两侧，所述漏区形成于所述漂移区内且远离所述栅极结构，所述源区形成于所述衬底中且与所述栅极结构相接；
在所述栅极结构和所述漏区之间的漂移区上形成金属硅化物阻挡层；
在所述金属硅化物阻挡层上形成氧化层并在所述氧化层上形成金属场板；以及
刻蚀所述金属场板，在自所述栅极结构向所述漏区方向形成间隔设置的多个金属段。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些申请的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的申请、目前描述的实施例和/或示例以及目前理解的这些申请的最佳模式中的任何一者的范围的限制。
图1为一实施例中LDMOS的结构示意图；
图2为一实施例中LDMOS制备方法步骤流程图；
图3a～3f为一实施例中LDMOS制备方法相关步骤对应的结构图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
为了彻底理解本申请，将在下列的描述中提出详细步骤以及结构，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
如图1所示，在一实施例中，LDMOS包括半导体衬底100，在半导体衬底100内形成有漂移区110，在漂移区110内形成有漏区111，在漂移区110外形成有源区122，在源区122和漏区111之间形成有栅极结构200，栅极结构200设置于半导体衬底100的表面且覆盖漂移区110的部分表面，即漏区 111形成于漂移区110内且远离栅极结构200，源区122形成于栅极结构200的另一侧且与栅极结构200相接，在栅极结构200与漏区111之间的漂移区表面形成有金属硅化物阻挡层400，在金属硅化物阻挡层400上形成有氧化层500，在氧化层500上形成有金属场板600，且金属场板600包含自栅极结构向漏区方向间隔设置的多个金属段。其中，半导体衬底100具有第一导电类型，漂移区110、漏区111和源区122具有第二导电类型，第一导电类型和第二导电类型导电性能相反。
LDMOS主要承受耐压的区域是漂移区110，漂移区110中的浓度和大小是决定器件击穿电压的主要因素，降低漂移区110浓度或者增长漂移区的长度，均可以提高器件的耐压，但这也会使得器件的其他特性变差，如导通电阻、开态特性(on态特性)等。为保证器件具有较低导通电阻时，进一步提高耐压，就需要让器件的漂移区110得到充分耗尽，即需要优化器件的表面电场。目前是在漂移区上方设置场板，通过场板调控漂移区表面的电场分布。由于在不设置场板时，漂移区表面电场分布并不均匀，器件漂移区不能充分耗尽，若在漂移区上加块场板，可以改善表面的电场，使得器件漂移区的耗尽更加充分。但对于高压器件来说，漂移区的尺寸相对较大，将整块场板全覆盖在漂移区上会使得器件耗尽过快，导致器件耐压偏低，这样就需要重新优化场板结构。因此，需要进一步提高器件耐压能力时，通常形成斜场板或者阶梯场板，靠近主结处的场板下方的氧化层较薄，且氧化层厚度朝漏区方向逐渐增加，由于氧化层越薄时，场板对电场的调制作用越强，而氧化层越厚时，场板对电场的调制作用越弱，设置不同厚度的氧化层，对不同位置的漂移区电场进行调制，使得漂移区表面电场分布更加均匀，进一步提高了LDMOS的击穿电压，但是，与此同时，也相应了增加了LDMOS制备工艺的难度和成本。
在本实施例中，漂移区110上方依次形成有金属硅化物阻挡层400、氧化层500和金属场板600，其中，金属场板600的材料可选择导电系数小，粘附性好的金属或类金属材料，如钛、硅化钛或硅化钨等。金属硅化物阻挡 层400和氧化层500为介质层，通过调节介质层的厚度，金属场板600可以对漂移区110的电场进行不同程度的调控。同时，金属场板600包括间隔设置的多段金属段，在漂移区上方自栅极结构200向漏区111方向间隔设置，根据漂移区110表面本身电场分布情况对不同位置的金属段施加不同的电压，使漂移区110的不同位置处形成不同的电位，从而对漂移区110内部电场进行调控，使得漂移区110内部电场分布更加均匀，大大提高了LDMOS的击穿电压，且分段金属段在工艺上只需要一步形成，制备简单。同时，设置为分段金属段，还可以通过调节其个数和间距，进一步对漂移区110表面电场分布进行调节。
此外，本实施例在器件节距(pitch)相对较小时，也同样能够优化器件的表面电场，不需要设置埋层，且不受其结深的限制，器件的应用电压范围广。在其他实施例中，电压为50V到100V器件的器件表面电场优化效果相对好，器件结深和器件节距(pitch)相对可以缩小。
在一实施例中，第一导电类型为P型，第二导电类型为N型。在其他实施例中，第一导电类型也可为N型，第二导电类型为P型。在一实施例中，栅极结构包括栅氧层210和多晶硅层220，栅氧层210下方的半导体衬底100形成沟道区。在一实施例中，半导体衬底100内还形成有具有第一导电类型的体区120，体区120和半导体衬底100共同形成沟道区，源区122形成于体区120内，体区120的掺杂浓度高于半导体衬底100的掺杂浓度。
在一实施例中，栅极结构200的侧壁上形成有侧墙300，即在栅氧层210的侧壁和多晶硅层220的侧壁上均形成有侧墙300，侧墙300包含有介质材料，能够进一步使栅极结构200与两侧结构相互隔离。
在一实施例中，氧化层500可仅位于金属硅化物400的表面，也可在金属硅化物400的表面、栅极结构200的表面、源区122的表面、漂移区110的表面以及漏区111的表面一体成型。在一实施例中，LDMOS还包括顶层介质层700，顶层介质层700覆盖于源区122、栅极结构200、漂移区110和漏区111的上方。
在一实施例中，在源区122的表层形成有第一金属硅化物123，在漏区111的表层形成有第二金属硅化物112，在栅极结构200的表层形成有第三金属硅化物221，其中，第三金属硅化物221具体形成于多晶硅层220的表层。同时，在第一金属硅化物123处引出源极810，在第二金属硅化物221处引出栅极(图1中未示出)，在第三金属硅化物112处引出漏极830，并在金属场板600上引出接触孔，接触孔填充导电材料。源极810、漏极830、栅极均穿透顶层介质层700与金属硅化物连接。通过设置金属硅化物，可以降低各导电电极与各有源区接触的接触电阻。由于在漂移区110表面设置有金属硅化物阻挡层400，可通过金属硅化物阻挡层400定义出漂移区表面的调制区域，在工艺制程中，在源区、漏区和栅极结构形成金属硅化物时，漂移区表面由于形成有金属硅化物阻挡层400，不会在金属硅化物组400顶层处形成金属硅化物，因此，金属硅化物阻挡层既具有调制漂移区电场的作用，还具有定义漂移区调制区域的作用，避免在漂移区调制区域内形成金属硅化物。
在一实施例中，如图1所示，金属场板600位于金属硅化物阻挡层400的正上方，金属场板600的覆盖面积小于或等于金属硅化物阻挡层400的覆盖面积。在一实施例中，金属硅化物阻挡层400可仅位于漂移区110的表面上，也可位于漂移区110的表面并延伸至栅极结构200上，具体延伸至多晶硅220的表面，自栅极结构200向漏区111方向间隔设置的多个金属段包括跨设在栅极结构200与所述漂移区110上的金属段以及位于栅极结构200和所述漏区111之间的漂移区110上的多个金属段，即金属硅化物阻挡层400、金属场板600以及夹设于中间的氧化层500共同构成漂移区110电场调制结构，该电场调制结构既可以仅位于漂移区110的表面，也可以位于漂移区110的表面并自漂移区110的表面延伸至栅极结构200的部分顶面。在一实施例中，跨设在栅极结构200与漂移区110上的金属段的长度大于仅位于栅极结构200和漏区111之间的漂移区110上方的金属段的长度。当栅极结构200侧壁形成有侧墙300时，金属硅化物阻挡层400和金属场板600还覆盖于侧墙300的表面。在一实施例中，靠近栅极结构200的金属段长度最长，且该 靠近栅极结构200的金属段自漂移区110延伸至栅极结构200上。
金属场板600上引出接触孔，接触孔具体与覆盖于漂移区110上方的金属场板600连接，不同金属段上的接触孔接入不同电压可以改变该金属段的电位，可根据具体情况调节各金属段的电位。其中，接触孔内填充的材料选用适合做金属场板的材料，如选用具有导电系数小，粘附性好的金属或类金属材料，如钛、硅化钛或硅化钨等。靠近栅极结构200的金属段的电位与其余的金属段的电位可以相同，也可以不同。具体的，在一实施例中，靠近栅极结构200的金属段接地，或靠近栅极结构200的金属段也可以与栅极或者源极同电位，其余金属段的电位悬空。如图1所示，跨设在栅极结构200与漂移区110上的金属段的上方引出接触孔820，接触孔820内填充场板材料，如选用具有导电系数小，粘附性好的金属或类金属材料，如钛、硅化钛或硅化钨等。该接触孔820可接地，或者与源极810连接，或者与栅极连接，其他金属段悬空，这样可以改变漂移区表面的电势分布，使主结处的一个高电场峰值分解为几个较低的电场峰值，从而是漂移区表面电场分布更加均匀，提高击穿电压。在一实施例中，也可以在各金属段接入不同的电压，使漂移区表面电势呈台阶增加。同样可以将主结处的一个高电场峰值分解为几个较低的电场峰值，从而使漂移区表面电场分布更加均匀，提高击穿电压。在一实施例中，间隔设置的金属段的长度自漏区111向栅极结构200方向逐步增大，且间隔设置的金属段的间距自所述漏区222向栅极结构200方向逐步增大，如此可以使漂移区110表面电势分段均匀，使漂移区表面电场分布均匀，提高器件耐压。在一实施例中，对于60V器件，其漂移区的器件节距(pitch)大概为3μm至4μm，靠近栅极结构200的金属段与相邻金属段之间的间距范围为0.15μm至0.3μm，即自所述栅极结构200向所述漏区111的方向，第一个相邻金属段之间的间距范围为0.15μm至0.3μm。在一实施例中，当金属场板600还包含跨设在栅极结构200与漂移区110上的金属段时，该跨设在栅极结构200与漂移区110上的金属段与相邻金属段之间的间距范围为0.15μm至0.3μm。
本申请还涉及一种横向双扩散金属氧化物半导体场效应管制备方法，在一实施例中，如图2所示，该方法包括下述步骤。
步骤S100：提供半导体衬底，半导体衬底内形成有漂移区、源区及漏区，半导体衬底上形成有栅极结构，半导体衬底具有第一导电类型，漂移区、源区、漏区具有第二导电类型，栅极结构覆盖漂移区的部分表面，源区和漏区分别位于栅极结构的两侧，漏区形成于漂移区内且远离栅极结构，源区形成于衬底中且与栅极结构相接。
在一实施例中，如图3a所示，对半导体衬底100进行掺杂形成漂移区110，对漂移区110掺杂形成漏区111，在漂移区外部形成源区122，在源区122和漏区111之间的部分漂移区110表面和半导体衬底100表面形成栅极结构200，即源区122和漏区111分别位于栅极结构200两侧，且栅极结构200还覆盖漂移区110的部分表面，漏区111与栅极结构200间隔设置，源区122与栅极结构200相接。
在一实施例中，形成栅极结构具体包括形成栅氧层210并在栅氧层上形成多晶硅层220，栅氧层210下方的半导体衬底100形成沟道区。在一实施例中，形成源区122之前还包括对半导体衬底100掺杂形成具有第一导电类型的体区120，体区120和半导体衬底100共同形成沟道区。对体区120进行掺杂形成源区122，体区120的掺杂浓度高于半导体衬底的掺杂浓度，有利于降低沟道区的导通电阻。
在一实施例中，形成栅极结构200后，在栅极结构200的侧壁上形成侧墙300，侧墙300包含介质材料。在一实施例中，形成侧墙300具体包括：在形成栅极结构200后，在器件表面淀积一层介质层，对介质层进行回蚀，栅极结构200侧壁处的介质层被保留下来，形成侧墙300。
步骤S200：在栅极结构和漏区之间的漂移区上形成金属硅化物阻挡层。
在一实施例中，如图3b所示，通过光刻胶定义出目标区域窗口并在目标区域窗口内淀积一层金属硅化物阻挡层400。金属硅化物阻挡层400可仅位于漂移区110的表面上，也可位于漂移区110的表面并延伸至栅极结构200 上，具体延伸至多晶硅220的表面。当栅极结构200侧壁形成有侧墙300时，金属硅化物阻挡层400还覆盖于侧墙300的表面。
步骤S300：在金属硅化物阻挡层上形成氧化层并在金属氧化层上形成金属场板。
在一实施例中，在形成氧化层之前，还包括在在源区表层、栅极结构表层和漏区表层形成金属硅化物，即在金属硅化物阻挡层上形成氧化层具体包括：
步骤S310：在步骤S200形成的半导体结构具有有源区的一侧淀积一层反应金属层。
在一实施例中，如图3c所示，在步骤S200形成的半导体结构具有有源区的一侧淀积一层反应金属层900，该金属可为钴金属。
步骤S320：对步骤S310形成的半导体结构进行热处理，使反应金属层与硅发生反应形成金属硅化物。
反应金属层900中的金属只会与硅发生反应，由于侧墙300和金属硅化物阻挡层400为介质层，因此不会与金属发生反应。如图3d所示，将半导体结构置于高温环境中，反应金属层900中的金属与源区122、多晶硅220和漏区111中的硅发生反应形成金属硅化物，形成金属硅化物后将多余的反应金属除去，即将侧壁300处的金属以及金属硅化物阻挡层400处的金属去除，在源区122的表面形成第一金属硅化物123、在栅极结构200的表面形成第二金属硅化物221，在漏区111处形成第三金属硅化物112。
步骤S330：在金属硅化物阻挡层上形成氧化层并在氧化层上形成金属场板。
氧化层可仅位于金属硅化物的表面，也可在金属硅化物的表面、栅极结构的表面、源区的表面、漂移区的表面以及漏区的表面一体成型。在一实施例中，如图3e所示，在步骤320形成的半导体器件表面淀积一层氧化层500，即氧化层500形成于半导体结构的上表面，并在氧化层500上淀积一层金属场板600。
步骤S400：刻蚀金属场板，在自所述栅极结构向所述漏区方向形成间隔设置的多个金属段。
如图3f所示，通过光刻工艺定义出刻蚀窗口后对金属场板600进行刻蚀，在金属硅化物上方形成分段金属段，当金属硅化物400位于漂移区表面且自漂移区表面延伸至多晶硅部分顶面时，自栅极结构200向漏区111方向间隔设置的多个金属段包括跨设在栅极结构200与漂移区110上的金属段以及位于栅极结构200和漏区111之间的漂移区110上的多个金属段。其中，靠近栅极结构200的一个金属段部分位于漂移区110上且部分延伸至栅极结构200的部分顶面，即金属硅化物阻挡层400、金属场板600以及夹设于中间的氧化层500共同构成漂移区110的电场调制结构，该电场调制结构既可以仅位于漂移区110的表面，也可以位于漂移区110的表面并自漂移区110的表面延伸至栅极结构200的部分顶面。
在一实施例中，LDMOS制备方法还包括在步骤S400中形成的半导体表面淀积一层顶层介质层700，并对顶层介质层700进行刻蚀以从源区122中引出源极810、从栅极结构中引出栅极和从漏区111引出漏极830。在一实施例中，当在源区表层形成第一金属硅化物123、在栅极结构表面形成第二金属硅化物221和在漏区表层形成第三金属硅化物112时，各电极与对应有源区内的金属硅化物连接，通过设置金属硅化物，可以减小导电电极与有源区的接触电阻。
在本实施例中，漂移区110上方依次形成有金属硅化物阻挡层400、氧化层500和金属场板600，其中，金属场板600的材料可选择具有导电系数小，粘附性好的金属或类金属材料，如钛、硅化钛或硅化钨等。金属硅化物阻挡层400和氧化层500为介质层，通过调节介质层的厚度，金属场板600可以对漂移区110的电场进行不同程度的调控。同时，金属场板600包括间隔设置的多段金属段，在漂移区上方自栅极结构200向漏区111方向间隔设置，根据漂移区110表面本身电场分布情况对不同位置的金属段施加不同的电压，使漂移区110的不同位置处形成不同的电位，从而对漂移区110内部 电场进行调控，使得漂移区110内部电场分布更加均匀，大大提高了LDMOS的击穿电压，且分段金属段在工艺上是需要一步形成，制备简单。同时，设置为分段金属段，还可以通过调节其个数和间距，进一步对漂移区110表面电场分布进行调节。
金属场板上引出接触孔，接触孔填充导电材料。接触孔接入不同电压可以改变不同金属段的电位，可根据具体情况调节各金属段的电位。具体的，在一实施例中，如图1所示，跨设在栅极结构200与漂移区110上的金属段的上方引出接触孔820，该接触孔820可接地，或者与源极810连接，或者与栅极连接，其他金属段悬空，可以改变漂移区表面的电势分布，使主结处的一个高电场峰值分解为几个较低的电场峰值，从而是漂移区表面电场分布更加均匀，提高击穿电压。在一实施例中，也可以在各金属段接入不同的电压，使漂移区表面电势呈台阶增加。同样可以将主结处的一个高电场峰值分解为几个较低的电场峰值，从而是漂移区表面电场分布更加均匀，提高击穿电压。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种横向双扩散金属氧化物半导体场效应管，包括：
    半导体衬底，具有第一导电类型；
    漂移区，具有第二导电类型，形成于所述半导体衬底的表层；
    栅极结构，设置于所述半导体衬底上且覆盖所述漂移区的部分表面；
    源区和漏区，具有第二导电类型，分别形成于所述栅极结构的两侧，所述漏区形成于所述漂移区内且远离所述栅极结构，所述源区形成于所述衬底中且与所述栅极结构相接；
    金属硅化物阻挡层，形成于所述栅极结构和所述漏区之间的漂移区上；
    氧化层，形成于所述金属硅化物阻挡层上；以及
    金属场板，形成于所述氧化层上，所述金属场板包括自所述栅极结构向所述漏区方向间隔设置的多个金属段。
  2. 如权利要求1所述的横向双扩散金属氧化物半导体场效应管，其中，所述形成于所述栅极结构和所述漏区之间的漂移区上的金属硅化物阻挡层还延伸至所述栅极结构上；
    所述自所述栅极结构向所述漏区方向间隔设置的多个金属段包括跨设在所述栅极结构与所述漂移区上的金属段以及位于所述栅极结构和所述漏区之间的漂移区上的多个金属段。
  3. 如权利要求1或2所述的横向双扩散金属氧化物半导体场效应管，其中，所述金属场板的覆盖面积小于或等于所述金属硅化物阻挡层的覆盖面积。
  4. 如权利要求2所述的横向双扩散金属氧化物半导体场效应管，其中，所述跨设在所述栅极结构与所述漂移区上的金属段的长度大于所述位于所述栅极结构和所述漏区之间的漂移区上的金属段的长度。
  5. 如权利要求1所述的横向双扩散金属氧化物半导体场效应管，其中，所述半导体衬底内还形成有具有第一导电类型的体区，所述源区形成于所述体区内。
  6. 如权利要求1所述的横向双扩散金属氧化物半导体场效应管，其中，所述源区的表层、所述栅极结构的表层和所述漏区的表层均形成有金属硅化物。
  7. 如权利要求2所述的横向双扩散金属氧化物半导体场效应管，其中，所述跨设在所述栅极结构与所述漂移区上的金属段的上方引出接触孔。
  8. 如权利要求7所述的横向双扩散金属氧化物半导体场效应管，其中，所述接触孔内的材料与所述金属场板的材料相同。
  9. 如权利要求2所述的横向双扩散金属氧化物半导体场效应管，其中，靠近所述栅极结构的金属段接地，其余金属段的电位悬空。
  10. 如权利要求2所述的横向双扩散金属氧化物半导体场效应管，其中，靠近所述栅极结构的金属段与栅极或源极同电位，其余金属段的电位悬空。
  11. 如权利要求1所述的横向双扩散金属氧化物半导体场效应管，其中，所述间隔设置的金属段的长度自所述漏区向所述栅极结构方向逐步增大，且所述间隔设置的金属段的间距自所述漏区向所述栅极结构方向逐步增大。
  12. 如权利要求1所述的横向双扩散金属氧化物半导体场效应管，其中，所述横向双扩散金属氧化物半导体场效应管的耐压范围为50V～100V。
  13. 一种横向双扩散金属氧化物半导体场效应管制备方法，包括：
    提供半导体衬底，所述半导体衬底内形成有漂移区、源区及漏区，所述半导体衬底上形成有栅极结构，所述半导体衬底具有第一导电类型，所述漂移区、源区和漏区具有第二导电类型，所述栅极结构覆盖所述漂移区的部分表面，所述源区和所述漏区分别位于所述栅极结构的两侧，所述漏区形成于所述漂移区内且远离所述栅极结构，所述源区形成于所述衬底中且与所述栅极结构相接；
    在所述栅极结构和所述漏区之间的漂移区上形成金属硅化物阻挡层；
    在所述金属硅化物阻挡层上形成氧化层并在所述氧化层上形成金属场板；以及
    刻蚀所述金属场板，在自所述栅极结构向所述漏区方向形成间隔设置的 多个金属段。
  14. 如权利要求13所述的制备方法，其中，所述形成于所述栅极结构和所述漏区之间的漂移区上的金属硅化物阻挡层还延伸至所述栅极结构上；
    所述自所述栅极结构向所述漏区方向间隔设置的多个金属段包括跨设在所述栅极结构与所述漂移区上的金属段以及位于所述栅极结构和所述漏区之间的漂移区上的多个金属段。
  15. 如权利要求13所述的制备方法，其中，在所述栅极结构和所述漏区之间的漂移区上形成金属硅化物阻挡层之后，以及在所述金属硅化物阻挡层上形成氧化层之前，还包括：
    在所述源区表面、栅极结构表面和漏区表面以及金属硅化物阻挡层表面沉积反应金属层；
    进行热处理，使所述反应金属层与接触的源区、栅极结构和漏区发生发应，生成金属硅化物；
    去除多余的反应金属层，暴露出所述金属硅化物阻挡层。
PCT/CN2019/114986 2018-11-19 2019-11-01 横向双扩散金属氧化物半导体场效应管及其制备方法 WO2020103672A1 (zh)

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