WO2020098132A1 - 一种pgc相位解调法中相位延迟提取与补偿方法 - Google Patents

一种pgc相位解调法中相位延迟提取与补偿方法 Download PDF

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WO2020098132A1
WO2020098132A1 PCT/CN2019/070333 CN2019070333W WO2020098132A1 WO 2020098132 A1 WO2020098132 A1 WO 2020098132A1 CN 2019070333 W CN2019070333 W CN 2019070333W WO 2020098132 A1 WO2020098132 A1 WO 2020098132A1
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multiplier
phase delay
phase
output
signal
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French (fr)
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陈本永
谢建东
严利平
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浙江理工大学
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B9/00—Measuring instruments characterised by the use of optical techniques
    • G01B9/02—Interferometers
    • G01B9/02055—Reduction or prevention of errors; Testing; Calibration
    • G01B9/02062—Active error reduction, i.e. varying with time
    • G01B9/02067—Active error reduction, i.e. varying with time by electronic control systems, i.e. using feedback acting on optics or light
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/26—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B9/00—Measuring instruments characterised by the use of optical techniques
    • G01B9/02—Interferometers
    • G01B9/02001—Interferometers characterised by controlling or generating intrinsic radiation properties
    • G01B9/0201—Interferometers characterised by controlling or generating intrinsic radiation properties using temporal phase variation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B9/00—Measuring instruments characterised by the use of optical techniques
    • G01B9/02—Interferometers
    • G01B9/02055—Reduction or prevention of errors; Testing; Calibration
    • G01B9/0207—Error reduction by correction of the measurement signal based on independently determined error sources, e.g. using a reference interferometer
    • G01B9/02072—Error reduction by correction of the measurement signal based on independently determined error sources, e.g. using a reference interferometer by calibration or testing of interferometer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01B—MEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B9/00—Measuring instruments characterised by the use of optical techniques
    • G01B9/02—Interferometers
    • G01B9/02083—Interferometers characterised by particular signal processing and presentation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/26—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light
    • G01D5/32—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light
    • G01D5/34—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells
    • G01D5/353—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells influencing the transmission properties of an optical fibre
    • G01D5/35306—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light with attenuation or whole or partial obturation of beams of light the beams of light being detected by photocells influencing the transmission properties of an optical fibre using an interferometer arrangement

Definitions

  • the invention belongs to the technical field of laser interference measurement, in particular to a phase delay extraction and compensation method in a PGC phase demodulation method.
  • PGC modulation and demodulation technology is widely used in interferometric fiber optic sensors and sinusoidal phase modulation interferometers due to its advantages such as high phase sensitivity and large dynamic range.
  • PGC modulation and demodulation techniques include differential cross-multiplication algorithm (PGC-DCM) and arc tangent algorithm (PGC-Arctan).
  • PGC-DCM differential cross-multiplication algorithm
  • PSC-Arctan arc tangent algorithm
  • the PGC-DCM method obtains the phase to be measured by performing differential cross multiplication and integration on the orthogonal components. This method is easily affected by the laser light intensity, carrier phase delay, and phase modulation depth.
  • the PGC-Arctan method divides the quadrature components and the arc tangent operation to directly obtain the phase to be measured.
  • phase delay compensation is a prerequisite for modulation depth compensation.
  • the phase delay is usually adjusted to zero to achieve phase delay compensation.
  • there is a drift in the phase delay and it is difficult for the existing methods to achieve real-time compensation of the phase delay.
  • a nonlinear error will occur, which limits the improvement of the accuracy of the phase measurement.
  • part of the harmonic amplitude signal will always be equal to zero, which will cause the PGC-DCM and PGC-Arctan algorithms to calculate the phase to be measured. Therefore, accurately extracting and compensating the phase delay in the PGC phase demodulation algorithm is a key technical problem to be solved to improve the accuracy and precision of sinusoidal modulation interferometry.
  • the present invention discloses a phase delay extraction and compensation method in the PGC phase demodulation method.
  • the present invention solves the difficulty of accurately measuring the phase delay in the sinusoidal modulation interferometer and the nonlinear error caused by the phase delay Problems that are difficult to suppress in real time.
  • Step 1) Remove the DC component and high-frequency noise in the sinusoidal phase-modulated interference signal by a band-pass filter, and then convert the filtered sinusoidal phase-modulated interference signal into a digital signal S (t), which is obtained by sampling Digital interference signal S (t), where the sampling frequency is higher than 8 times the frequency of the sinusoidal modulation signal.
  • the sinusoidal modulation signal refers to the modulation signal used for sinusoidal phase modulation.
  • the digital signal S (t) is expressed as follows:
  • A represents the amplitude of the digital interference signal
  • m represents the modulation depth
  • ⁇ represents the phase delay
  • ⁇ c represents the frequency of the sinusoidal modulation signal
  • J 0 (m) represents the first order Bessel function of order
  • J 2n (m) represents the first order Bessel function of even order
  • J 2n-1 (m) represents the odd order Bessel functions of the first kind
  • Step 2 The digital interference signal S (t) is generated with the first-order quadrature reference signal (sin ( ⁇ c t), cos ( ⁇ c t)) generated by the first digital frequency synthesizer and the second digital frequency synthesizer respectively.
  • the second-order quadrature reference signal (cos (2 ⁇ c t), sin (2 ⁇ c t)), the fourth-order quadrature reference signal (cos (4 ⁇ c t), sin (4 ⁇ c t) generated by the third digital frequency synthesizer ))
  • the orthogonal down-mixing operation is completed by multiplier multiplication and low-pass filter processing.
  • the DC signal output from each filter is proportional to the amplitude of the corresponding harmonic in the digital interference signal S (t), defined as the harmonic amplitude Value signal, the same order harmonic amplitude signal is defined as the signal P i and Q i according to whether it is proportional to the cosine value of the phase delay ⁇ or proportional to the sine value of the phase delay ⁇ , that is, P i and Q i are positive Crossed, where the subscript i represents the order, the value range is 1,2,4, and three pairs of orthogonal harmonic amplitude signals are obtained, and are first-order orthogonal harmonic amplitude signals (P 1 , Q 1 ), second-order quadrature harmonic amplitude signals (P 2 , Q 2 ) and fourth-order quadrature harmonic amplitude signals (P 4 , Q 4 ), P 1 , Q 1 , P 2 , Q 2 , P 4 and Q 4 are calculated as:
  • LPF [] represents the low-pass filtering operation
  • A represents the amplitude of the digital interference signal
  • m represents the modulation depth
  • ⁇ represents the phase delay
  • J 1 (m) represents the first order Bessel function of the first kind
  • J 2 (m) represents the second order Bessel function of the first kind
  • J 4 (m) represents the fourth order first Bessel-like function
  • ⁇ c represents the frequency of the sinusoidal modulation signal
  • Step 3) Use first-order orthogonal harmonic amplitude signals (P 1 , Q 1 ), second-order orthogonal harmonic amplitude signals (P 2 , Q 2 ), and fourth-order orthogonal harmonic amplitude signals (P 4 , Q 4 ) operation to get the phase not to be measured
  • the affected phase delay amount ⁇ c is calculated as follows:
  • Step 4) The first-order quadrature harmonic amplitude signal (P 1 , Q 1 ) and the second-order quadrature harmonic amplitude signal (P 2 , Q 2 ) are added by an absolute value adder to obtain the phase at any angle
  • the absolute harmonic amplitude signal with non-zero amplitude under delay, T 1 and T 2 respectively represent the sum of the absolute values of the first-order orthogonal harmonic amplitude signals P 1 and Q 1 and the second-order orthogonal harmonic amplitude
  • the sum of the absolute values of the value signals P 2 and Q 2 is calculated as follows:
  • Step 5) Use the phase delay amount ⁇ c obtained in step 3) to calculate the first-order absolute harmonic amplitude signal phase delay correction coefficient G 1 and the second-order absolute harmonic amplitude signal phase delay correction coefficient G 2 respectively .
  • the calculation formula is as follows:
  • sign (P 1 ) and sign (P 2 ) represent the symbols of P 1 and P 2 respectively;
  • Step 6) Multiply the absolute harmonic amplitude signal by the corresponding phase delay correction coefficients G 1 and G 2 respectively to reconstruct a new harmonic amplitude signal whose amplitude is not affected by the phase delay, R 1 and R 2 respectively represent
  • the product of the reconstruction of the absolute harmonic amplitude signal T 1 phase delay correction coefficient G 1 and the product of the absolute harmonic amplitude signal T 2 phase delay correction coefficient G 2 is as follows:
  • the formula is as follows:
  • sign (R 1 ) and sign (R 2 ) represent the symbols of R 1 and R 2 respectively;
  • the calculation process of the method uses a phase processing system.
  • the phase processing system is specifically:
  • the input terminals of the first multiplier, second multiplier, fifth multiplier, sixth multiplier, seventh multiplier, and eighth multiplier are all connected to the digital interference signal S (t), and the first digital frequency synthesizer is connected to Input terminals of the first and second multipliers, a second digital frequency synthesizer is connected to the input terminals of the fifth and sixth multipliers, and a third digital frequency synthesizer is connected to the seventh and eighth multipliers
  • the input of the multiplier; the output of the first multiplier is connected to the input of the first absolute value adder and the input of the phase delay extraction module through the first low-pass filter, and the output of the second multiplier
  • the two low-pass filters are respectively connected to the input terminal of the first absolute value adder and the input terminal of the phase delay extraction module, and the output terminal of the fifth multiplier is respectively connected to the second absolute value adder via the third low-pass filter And the input of the phase delay extraction module.
  • the output of the sixth multiplier is connected to the input of the second absolute value adder and the input of the phase delay extraction module via a fourth low-pass filter.
  • the output of the seven multiplier and the eighth multiplier are connected to the input of the phase delay extraction module through the fifth low-pass filter and the sixth low-pass filter respectively; the output of the phase delay extraction module is connected to the phase delay
  • the input end of the correction coefficient calculation module, the output end of the first absolute value adder and the output end of the phase delay correction coefficient calculation module are connected to the input end of the first arc tangent operator via a third multiplier, and the second absolute value addition
  • the output terminal of the processor and the output terminal of the phase delay correction coefficient calculation module are connected to the input terminal of the first arc tangent operator through a fourth multiplier, and the output terminal of the first arc tangent operator outputs the phase to be measured.
  • the phase delay extraction module is specifically: the input end of the ninth multiplier is connected to the output ends of the first low-pass filter and the second low-pass filter respectively, and the output end of the first low-pass filter is also connected to the first
  • the input terminal of the square operator is connected, and the output terminal of the ninth multiplier is connected to the input terminal of the first adder via a multiplier
  • the output terminal of the second low-pass filter is also connected to the input terminal of the second square operator,
  • the output terminal of the second square operator and the output terminal of the first square operator are connected to the input terminal of the second adder through the first subtractor
  • the input terminal of the thirteenth multiplier is connected to the third low-pass filter
  • the output end of the sixth low-pass filter, the input end of the twelfth multiplier are respectively connected to the output ends of the fourth low-pass filter, the fifth low-pass filter, the outputs of the twelfth multiplier and the thirteenth multiplier
  • the end is connected to the input of the first adder via the second
  • the phase delay correction coefficient calculation module is specifically: the output terminal of the half multiplier after the first branch of the second arc tangent operator obtains the sine value and the cosine value through the first cosine look-up table, two values Connect the input terminal of the first symbol multiplier through the third absolute value adder and the first reciprocal operator in turn, and the first symbol multiplier passes the output value from the first reciprocal operator and the second low-pass filter through the first symbol
  • the output value obtained by the operator is operated to output the operation result;
  • the output terminal of the second branch of the second arc tangent operator obtains the sine value and the cosine value through the second cosine lookup table, and the two values are sequentially passed through the fourth absolute value
  • the adder and the second reciprocal operator are connected to the input terminal of the second symbol multiplier, and the second symbol multiplier combines the output value from the second reciprocal operator and the output value obtained by the third low-pass filter through the second symbol operator Perform calculations to output calculation results.
  • the method is applied to a sinusoidal phase modulation interferometer.
  • the sinusoidal phase modulation interferometer includes a single-frequency laser, a polarizer, a beam splitter prism, a measuring pyramid prism, an electro-optic phase modulator, a photodetector, and a high-voltage amplifier, single frequency
  • the laser emits a laser beam, which is incident on the beam splitter prism through the polarizer to reflect and transmit.
  • the reflected light of the beam splitter prism is modulated by the electro-optic phase modulator and then enters the reference cube prism, and then reflects back to the beam splitter prism through the reference cube prism.
  • the transmitted light of the prism is reflected by the measuring cube prism and then returned to the beam splitter prism for transmission.
  • the two beams of light reflected and transmitted back to the beam splitter prism are combined and reflected by the reflector to the photodetector.
  • the photodetector generates light after receiving the beam
  • the signal and the optical signal are input to the field programmable gate array signal processor FPGA through the amplifier, bandpass filter, and analog-to-digital converter in turn, and the output control signal of the field programmable gate array signal processor FPGA is sequentially passed through the digital-to-analog converter, high-voltage amplifier Then input to the control end of the electro-optical phase modulator.
  • the reference cube prism is fixed and the measuring cube prism is fixed on the object to be measured.
  • the method of the present invention uses the first-, second-, and fourth-order quadrature harmonic amplitude signals to extract the phase delay amount, which is not affected by the phase to be measured, and can realize the real-time extraction of the phase delay, thereby realizing the phase delay Real-time compensation;
  • the method of the present invention uses first-, second-, and fourth-order quadrature harmonic amplitude signals to construct an absolute harmonic amplitude signal whose amplitude is not zero at any angle of phase delay, which solves the problem that the phase delay is specific The problem that the phase to be measured cannot be measured at the angle;
  • the present invention uses the phase delay to calculate the corresponding phase delay correction coefficient to compensate for the influence of the phase delay, eliminate the nonlinear error caused by the phase delay, improve the phase measurement accuracy, and can be widely used in sinusoidal modulation interference technology field.
  • FIG. 1 is a functional block diagram of the phase delay extraction and compensation method in the PGC phase demodulation method.
  • FIG. 2 is a functional block diagram of the phase delay extraction module.
  • FIG. 3 is a functional block diagram of the phase delay correction coefficient calculation module.
  • FIG. 4 is a schematic diagram of the system of the present invention applied to a sinusoidal phase modulation interferometer.
  • FIG. 5 is a graph of simulation experiment data results of the present invention.
  • the first digital frequency synthesizer 2. The first multiplier, 3. The second multiplier, 4. The first low-pass filter, 5. The second low-pass filter, 6. The first absolute value Adder, 7, second absolute value adder, 8, third multiplier, 9, fourth multiplier, 10, first arc tangent operator, 11, third low-pass filter, 12, fifth multiplier , 13, second digital frequency synthesizer, 14, sixth multiplier, 15, fourth low-pass filter, 16, third digital frequency synthesizer, 17, seventh multiplier, 18, eighth multiplier, 19 5.
  • Fifth low-pass filter 20. Sixth low-pass filter, 21. Phase delay extraction module, 22. Phase delay correction coefficient calculation module. 23.
  • the specific implementation uses the following phase processing system: the first multiplier 2, the second multiplier 3, the fifth multiplier 12, the sixth multiplier 14, the seventh multiplier 17 and the eighth multiplier 18
  • the input terminals are connected to the digital interference signal S (t)
  • the first digital frequency synthesizer 1 is connected to the input terminals of the first multiplier 2 and the second multiplier 3
  • the second digital frequency synthesizer 13 is connected to the fifth multiplier 12 3.
  • the input terminal of the sixth multiplier 14, and the third digital frequency synthesizer 16 are connected to the input terminals of the seventh multiplier 17 and the eighth multiplier 18.
  • the output terminal of the first multiplier 2 is connected to the input terminal of the first absolute value adder 6 and the input terminal of the phase delay extraction module 21 via the first low-pass filter 4, and the output terminal of the second multiplier 3 is
  • the second low-pass filter 5 is respectively connected to the input terminal of the first absolute value adder 6 and the input terminal of the phase delay extraction module 21, and the output terminal of the fifth multiplier 12 is connected to the third low-pass filter 11 respectively
  • the input terminal of the two absolute value adder 7 and the input terminal of the phase delay extraction module 21, and the output terminal of the sixth multiplier 14 are connected to the input terminal of the second absolute value adder 7 via the fourth low-pass filter 15 and
  • the input terminals of the phase delay extraction module 21, the output terminals of the seventh multiplier 17 and the eighth multiplier 18 are connected to the phase delay extraction module 21 via the fifth low-pass filter 19 and the sixth low-pass filter 20, respectively. Input.
  • the output terminal of the phase delay extraction module 21 is connected to the input terminal of the phase delay correction coefficient calculation module 22, and the output terminal of the first absolute value adder 6 and the output terminal of the phase delay correction coefficient calculation module 22 pass through a third multiplier 8 is connected to the input terminal of the first arc tangent operator 10, the output terminal of the second absolute value adder 7 and the output terminal of the phase delay correction coefficient calculation module 22 are connected to the first arc tangent operator through a fourth multiplier 9 At the input end of 10, the output end of the first arc tangent operator 10 outputs the phase to be measured.
  • the implementation process of the present invention is:
  • the first thing to do is the orthogonal down-mixing operation, as follows: the first multiplier 2 and the second multiplier 3 combine the digital interference signal S (t) with the first digital frequency
  • the first-order orthogonal reference signal generated by the filter 1 is multiplied and filtered by the first low-pass filter 4 and the second low-pass filter 5 to obtain a first-order orthogonal harmonic amplitude signal (Q 1 , P 1 );
  • the digital interference signal S (t) is multiplied by the second-order quadrature reference signal generated by the second digital frequency synthesizer 13 through the fifth multiplier 12 and the sixth multiplier 14 and passes through the third low-pass filter 11
  • the fourth low-pass filter 14 obtains the second-order quadrature harmonic amplitude signal (P 2 , Q 2 ).
  • the digital interference signal S (t ) Is multiplied by the fourth-order quadrature reference signal generated by the third digital frequency synthesizer 16 and filtered by the fifth low-pass filter 19 and the fourth low-pass filter 20 to obtain a fourth-order quadrature harmonic amplitude signal (P 4 , Q 4 ), and the orthogonal down-mixing operation is completed, the formulas are as follows:
  • A represents the amplitude of the interference signal
  • m represents the modulation depth
  • ⁇ represents the phase delay
  • J 1 (m) represents the first order Bessel function of the first kind
  • J 2 (m) represents the second order Bessel function of the first kind
  • J 4 (m) represents the fourth order first Bessel-like functions
  • the phase delay extraction module 21 uses these three pairs of quadrature harmonic amplitude signals (Q 1 , P 1 ), (Q 2 , P 2 ) and (Q 4 , P 4 ) to extract the phase delay amount ⁇ c , the formula is as follows:
  • the phase delay correction coefficient calculation module 22 uses the extracted phase delay amount ⁇ c to calculate the first-order phase delay correction coefficient G 1 and the second-order phase delay correction coefficient G 2.
  • the formula is as follows:
  • the sum of absolute values of Q 1 and P 1 is obtained by the first absolute value adder 6 to obtain the first-order absolute harmonic signal amplitude T 1 ; similarly, the sum of Q 2 is obtained by the second absolute value adder 7
  • the sum of the absolute values of P 2 to obtain the second-order absolute harmonic signal amplitude T 2 is as follows:
  • the first inverse tangent operator 10 is used to perform a four-quadrant inverse tangent operation on the new harmonic amplitude quadrature signal (R 1 , R 2 ) after phase delay compensation to obtain the phase to be measured
  • the formula is as follows:
  • this module is a functional block diagram of the phase delay extraction module, and further illustrates the signal processing method in the phase delay extraction module 21 in FIG. 1.
  • the input terminals of the ninth multiplier 2101 are respectively connected to the output terminals of the first low-pass filter 4 and the second low-pass filter 5, and the output terminal of the first low-pass filter 4 is also connected to the input terminal of the first square calculator 2103 Connected, the output of the ninth multiplier 2101 is connected to the input of the first adder 2106 via the multiplier 2102.
  • the output terminal of the second low-pass filter 5 is also connected to the input terminal of the second square operator 2104, and the output terminal of the second square operator 2104 and the output terminal of the first square operator 2103 are connected together via the first subtractor 2105 To the input of the second adder 2107.
  • the input terminals of the thirteenth multiplier 2114 are connected to the output terminals of the third low-pass filter 11 and the sixth low-pass filter 20 respectively, and the input terminals of the twelfth multiplier 2113 are connected to the fourth low-pass filter 15 and the third
  • the output of the five low-pass filter 19 the outputs of the twelfth multiplier 2113 and the thirteenth multiplier 2114 are connected to the input of the first adder 2106 via the second subtractor 2115.
  • the input terminals of the tenth multiplier 2110 are respectively connected to the output terminals of the third low-pass filter 11 and the fifth low-pass filter 19, and the input terminals of the eleventh multiplier 2111 are respectively connected to the fourth low-pass filter 15 and the sixth
  • the output of the low-pass filter 20 the outputs of the tenth multiplier 2110 and the eleventh multiplier 2111 are connected to the input of the second adder 2107 via the third adder 2112.
  • the output terminals of the first adder 2106 and the second adder 2107 are both connected to the input terminal of the second arc tangent operator 2108.
  • the output terminal of the second arc tangent operator 2108 is divided into two, and the first branch is divided into two.
  • a multiplier 2109 outputs to the phase delay correction coefficient calculation module 22, and the second branch directly outputs the result to the phase delay correction coefficient calculation module 22.
  • the first-order quadrature harmonic amplitude signal P 1 and Q 1 are multiplied by a ninth multiplier 2101, and the product is amplified by a multiplier 2102 to obtain a signal U 1.
  • the formula is as follows:
  • the first square operator 2103 and the second square operator 2104 perform square operations on the first-order quadrature amplitude signals (P 1 , Q 1 ) respectively, and then perform the subtraction operation through the first subtractor 2105 to obtain the signal U 2 .
  • the formula is as follows:
  • the amplitudes of the signals (U 1 , U 2 ) are equal to The amplitude and the phase to be measured Relevant if and only if At time (k is any integer), the signals (U 1 , U 2 ) are all zero. At this time, the signal cannot be directly used to calculate the phase delay value. To this end, the present invention constructs another pair of signals (V 1 , V 2 ) whose amplitude is greater than zero in this case.
  • the signal P 2 and Q 4 are multiplied by the thirteenth multiplier 2114, the signal Q 2 and P 4 are multiplied by the twelfth multiplier 2113, and the product P 2 Q 4 and Q 2 P are multiplied by the second subtractor 2115 4
  • the formula is as follows:
  • the signal P 2 and P 4 are multiplied by the tenth multiplier 2110, the signal Q 2 and Q 4 are multiplied by the eleventh multiplier 2111, and the product P 2 P 4 and Q 2 are multiplied by the third adder 2112 Q 4 is added to obtain the signal V 2 , the formula is as follows:
  • the amplitude of the signal (V 1 , V 2 ) is equal to The amplitude and the phase to be measured Relevant if and only if At time (k is any integer), the signals (V 1 , V 2 ) are all zero. In this case, the formula cannot be directly used to calculate the phase delay value.
  • the amplitudes of the two pairs of signals (U 1 , U 2 ) and (V 1 , V 2 ) are affected by the phase to be measured; but when the amplitude of the signal (U 1 , U 2 ) is zero, the signal (V 1 , U 2 ) V 2 ) the amplitude is just greater than zero, otherwise when the amplitude of the signal (U 1 , U 2 ) is zero, the amplitude of the signal (V 1 , V 2 ) is just greater than zero, that is, the amplitude of the two will not be zero at the same time . Therefore, combining these two pairs of signals can construct a phase delay calculation method that is not affected by the phase to be measured.
  • phase delay signals (W 1 , W 2 ) thus obtained are always greater than zero when the phase to be measured is any value, and the arc tangent operation is performed by the second arc tangent operator 2108 to obtain the double phase delay amount 2 ⁇ c , by The half multiplier 2109 multiplies it by 0.5, and finally obtains the phase delay amount ⁇ c , the formula is as follows:
  • the numerator denominator is always greater than zero when the phase to be measured is any value, that is, it is not affected by the phase to be measured, and the phase delay value can be correctly extracted when the phase is to be measured at any angle.
  • this module is a functional block diagram of the phase delay correction coefficient calculation module, that is, the signal processing method in the phase delay correction coefficient calculation module 22 in FIG. 1 is further described.
  • the output terminal of the first branch of the second arc tangent operator 2108 obtains the sine value and the cosine value through the first cosine lookup table 2201, and the two values are sequentially connected through the third absolute value adder 2202 and the first reciprocal operator 2204.
  • the input end of the first symbol multiplier 2205, the first symbol multiplier 2205 calculates the output value from the first reciprocal operator 2204 and the output value obtained by the second low-pass filter 5 through the first symbol operator 2203 to output Operation result.
  • the output terminal of the second branch of the second arc tangent operator 2108 obtains the sine value and the cosine value through the second cosine lookup table 2206, and the two values are sequentially connected through the fourth absolute value adder 2207 and the second reciprocal operator 2209
  • the input end of the second symbol multiplier 2210, the second symbol multiplier 2210 calculates the output value from the second reciprocal operator 2209 and the output value obtained by the third low-pass filter 11 through the second symbol operator 2208 to output Operation result.
  • the sine and cosine values of the phase delay amount are obtained through the first cosine lookup table 2201, and the sine and cosine values of the phase delay amount 2 times are obtained through the second cosine lookup table 2206 (sin2 ⁇ c , cos2 ⁇ c ).
  • the sum of the absolute values of the sine and cosine values of the phase delay amount is obtained by the third absolute value adder 2202, and the double phase delay is obtained by the fourth absolute value adder 2207
  • the denominators of the correction coefficients G 1 and G 2 can be in the range of 1 to the root number 2, to avoid the situation where the reciprocal operation cannot be calculated normally when the denominator is zero.
  • the single-frequency laser 23, the polarizer 24, the beam splitter prism 25, and the measuring cube prism 29 are sequentially spaced apart along a straight line, one side of the beam splitter prism 25 is provided with a reference cube prism 26, and the other of the beam splitter prism 25
  • a mirror 30 is arranged on one side, and a photodetector 31 is arranged in sequence on one side of the mirror 30, and the photodetector 31 is in turn connected with an amplifier 32, a band-pass filter 33, an analog-to-digital converter 34, and a field programmable gate array signal processor (FPGA) 35.
  • the digital-to-analog converter 36 is connected.
  • the digital-to-analog converter 36 is connected to the electro-optical phase modulator 27 via the high-voltage amplifier 28.
  • the output wavelength of the single-frequency laser 23 is 780 nm; the highest modulation frequency of the electro-optical phase modulator 27 is 1 MHz; the bandwidth of the photodetector 31 is 10 MHz; the band-pass filter 33 of the interference signal is composed of a DC blocking filter and a A low-pass filter with a cutoff frequency of 10 MHz is connected in series; the sampling frequency of the analog-to-digital converter 34 is 125 MHz; the sampling frequency of the analog-to-digital converter is 125 MHz; FPGA 35 is a high-performance XC7K160T.
  • the laser light emitted by the single-frequency laser 23 is filtered by the polarizing plate 24 to be linearly polarized light perpendicular to the direction of the paper, and the linearly polarized light is divided into two beams by the dichroic prism 25, among which the transmitted measurement light and the reflected reference light.
  • the measuring light is reflected by the measuring cube prism 29 and returns to the beam splitter prism 25.
  • the phase of the measuring light changes. This phase change is proportional to the distance from the beam splitter 25 to the measuring cube prism 29. The amount of phase change is the phase to be measured.
  • the sinusoidal modulation signal generated by the FPGA 35 is converted into an analogue sinusoidal modulation signal by a digital-to-analog converter 36, amplified by a high-voltage amplifier 28, and finally the electro-optic modulator 27 is driven to perform sinusoidal phase modulation on the reference light, wherein the frequency of the sinusoidal modulation signal is set to 200 kHz.
  • the amplitude of the sinusoidal modulation signal determines the modulation depth.
  • the reference light after the sinusoidal phase modulation is reflected by the reference pyramid prism 26 and returns to the dichroic prism 25.
  • the measurement light and the reference light returned to the dichroic prism 25 are combined and reflected by the mirror 30 to the photodetector 31.
  • the photodetector 31 generates a sinusoidal phase modulation interference signal, which is amplified by the amplifier 32 and a band pass filter 33 After filtering, it is sampled and converted into a digital interference signal by an analog-to-digital converter 34.
  • the sinusoidal modulation signal has a certain delay from the generation to the drive of the electro-optical phase modulator 27 for phase modulation. These delays are the main source of carrier phase delay in the PGC phase demodulation algorithm.
  • the formula of the digital interference signal including the carrier phase delay is as follows:
  • the analog-to-digital converter 34 inputs the digital interference signal to the FPGA 35, and implements the phase delay measurement and compensation method in the PGC phase demodulation method shown in FIG. 1 in the FPGA 35, and finally obtains the phase to be measured accurately.
  • the same simulated sinusoidal phase modulation interference signal is generated by the signal source according to the formula of the digital interference signal S (t), where the modulation depth is set to 2.63 and the phase delay is set to 10 °,
  • the simulated sinusoidal phase modulation interference signal is transmitted to the corresponding signal processing board in FIG. 1, and the phase delay measurement and compensation method in the PGC phase demodulation method proposed by the present invention is completed in FPGA 35, and finally the experimental data shown in FIG. 5 is obtained.
  • the solid line represents the error between the data measured by the conventional PGC-Arctan phase demodulation algorithm that does not compensate for the phase delay and the reference displacement.
  • the nonlinear error changes sinusoidally with the reference displacement, and the peak-to-peak value is about 2.7 nm.
  • the dotted line shows the error between the data measured by the phase delay measurement and compensation method in the PGC phase demodulation method proposed by the present invention and the reference displacement. Obviously, there is no nonlinear error in this result, and the overall appearance is white noise with a peak-to-peak value of 0.1 nanometer .
  • the experimental data shows that the phase delay measurement and compensation method in the PGC phase demodulation method proposed by the present invention can effectively eliminate the nonlinear error caused by the modulation depth.
  • the method of the present invention fully utilizes the first-order, second-order and fourth-order quadrature harmonic amplitude signals to extract the amount of phase delay, and uses the phase delay to calculate the corresponding phase delay correction coefficient to compensate for the influence of the phase delay.
  • the non-linear error caused by the phase delay is eliminated, and the phase measurement accuracy is improved.

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Abstract

本发明公开了一种PGC相位解调法中相位延迟提取与补偿方法。正弦相位调制干涉信号在放大滤波后由模数转换器转换为数字干涉信号，对数字干涉信号同时进行一阶、二阶和四阶谐波的正交下混频，获得3对正交谐波幅值信号，运用这3对正交谐波幅值信号提取出相位延迟量，运用相位延迟量计算出对应的相位延迟修正系数，用相位延迟修正系数乘以相应的等于正交谐波幅值信号绝对值之和的绝对谐波幅值信号，获得不受相位延迟影响的新谐波幅值信号，再通过反正切运算获得待测相位。本发明解决了PGC相位解调技术中相位延迟难以准确测量以及相位延迟引起的非线性误差难以实时补偿的问题，提高了相位测量精度，广泛应用于正弦调制干涉技术领域。

Description

一种PGC相位解调法中相位延迟提取与补偿方法 技术领域
本发明属于激光干涉测量技术领域，特别是一种PGC相位解调法中相位延迟提取与补偿方法。
背景技术
相位生成载波(PGC)调制解调技术因测相灵敏度高、动态范围大等优点，被广泛应用于干涉型光纤传感器和正弦相位调制干涉仪。PGC调制解调技术包括微分交叉相乘算法(PGC-DCM)和反正切算法(PGC-Arctan)。PGC-DCM法通过对正交分量进行微分交叉相乘以及积分等运算获得待测相位，这种方法容易受激光器光强、载波相位延迟、相位调制深度的影响。PGC-Arctan法将正交分量进行除法以及反正切运算直接得到待测相位，测量结果不受光强影响，但仍然会受相位延迟与调制深度的影响。相位延迟补偿是实现调制深度补偿的前提，为了精确获得待测相位，通常将相位延迟调整为零来实现相位延迟补偿。在实际中，相位延迟存在漂移，现有方法难以实现相位延迟的实时补偿，当相位延迟偏离零时，将会出现非线性误差，这限制了测相精度的提高。此外，当相位延迟等于特定角度时，部分谐波幅值信号将恒等于零，这将导致PGC-DCM和PGC-Arctan算法均无法计算待测相位。所以，准确地提取与补偿PGC相位解调算法中的相位延迟是提高正弦调制干涉测量正确性和精度需要解决的关键技术问题。
发明内容
为了解决背景技术中存在的问题，本发明公开了一种PGC相位解调法中相位延迟提取与补偿方法，本发明解决了正弦调制干涉仪中相位延迟难以准确测量以及相位延迟引起的非线性误差难以实时抑制的问题。
本发明解决其技术问题所采用的技术方案包括以下步骤：
步骤1)通过带通滤波器去除正弦相位调制干涉信号中的直流成分与高频噪声，然后对滤波后的正弦相位调制干涉信号进行模数采样转换为数字信号S(t)，由此采样获得数字干涉信号S(t)，其中采样频率高于正弦调制信号频率的8倍，正弦调制信号是指用于正弦相位调制的调制信号，数字信号S(t)表示如下：
Figure PCTCN2019070333-appb-000001
其中，A表示数字干涉信号的幅值，m表示调制深度，θ表示相位延迟，ω c表示正弦调制信号的频率，
Figure PCTCN2019070333-appb-000002
表示待测相位，J 0(m)表示第0阶的第一类贝塞尔函数，J 2n(m)表示偶数阶的第一类贝塞尔函数，J 2n-1(m)表示奇数阶的第一类贝塞尔函数；
步骤2)数字干涉信号S(t)分别与通过第一数字频率合成器产生的一阶正交参考信号(sin(ω ct)、cos(ω ct))、第二数字频率合成器产生的二阶正交参考信号(cos(2ω ct)、sin(2ω ct))、第三数字频率合成器产生的四阶正交参考信号(cos(4ω ct)、sin(4ω ct))通过乘法器相乘以及低通滤波处理完成正交下混频运算，各滤波器输出的直流信号与数字干涉信号S(t)中对应谐波的幅值呈正比，定义为谐波幅值信号，对于同一阶谐波幅值信号按照其与相位延迟θ的余弦值呈正比还是与相位延迟θ的正弦值呈正比分别定义为信号P i与Q i，即P i与Q i是正交的，其中下标i表示阶数，取值范围为1,2,4，获得3对正交的谐波幅值信号、和，分别为一阶正交谐波幅值信号(P 1,Q 1)、二阶正交谐波幅值信号(P 2,Q 2)和四阶正交谐波幅值信号(P 4,Q 4)，,P 1、Q 1、P 2、Q 2、P 4、Q 4分别计算为：
Figure PCTCN2019070333-appb-000003
Figure PCTCN2019070333-appb-000004
Figure PCTCN2019070333-appb-000005
Figure PCTCN2019070333-appb-000006
Figure PCTCN2019070333-appb-000007
Figure PCTCN2019070333-appb-000008
其中，LPF[]表示低通滤波运算，A表示数字干涉信号的幅值，m表示调制深度，θ表示相位延迟，
Figure PCTCN2019070333-appb-000009
表示待测相位，J 1(m)表示第一阶第一类贝塞尔函数，J 2(m)表示第二阶第一类贝塞尔函数，J 4(m)表示第四阶第一类贝塞尔函数；ω c表示正弦调制信号的频率；
步骤3)运用一阶正交谐波幅值信号(P 1,Q 1)、二阶正交谐波幅值信号(P 2,Q 2)和四阶正交谐波幅值信号(P 4,Q 4)进行运算得到不受待测相位
Figure PCTCN2019070333-appb-000010
影响的相位延迟量θ c，计算公式如下：
Figure PCTCN2019070333-appb-000011
其中，假定实际相位延时取值为-π到π，运用上述公式提取的相位延迟量θ c与实际相位延迟量θ的关系为θ＝θ c+kπ。
步骤4)一阶正交谐波幅值信号(P 1,Q 1)、二阶正交谐波幅值信号(P 2,Q 2)分别经绝对值加法器相加得到在任何角度的相位延迟下幅值都不为零的绝对谐波幅值信号，T 1，T 2分别表示一阶正交谐波幅值信号P 1与Q 1的绝对值之和以及二阶正交谐波幅值信号P 2与Q 2的绝对值之和，计算公式如下：
Figure PCTCN2019070333-appb-000012
Figure PCTCN2019070333-appb-000013
步骤5)运用步骤3)得到的相位延迟量θc分别计算一阶绝对谐波幅值信号相位延迟修正系数G 1、二阶绝对谐波幅值信号相位延迟修正系数G 2，计算公式如下：
Figure PCTCN2019070333-appb-000014
Figure PCTCN2019070333-appb-000015
其中，sign(P 1)和sign(P 2)分别表示P 1与P 2的符号；
步骤6)将绝对谐波幅值信号分别乘以上述对应的相位延迟修正系数G 1与G 2，重构出幅度不受相位延迟影响的新谐波幅值信号，R 1和R 2分别表示绝对谐波幅值信号T 1相位延迟修正系数G 1的乘积以及绝对谐波幅值信号T 2相位延迟修正系数G 2的乘积，重构计算公式如下：
Figure PCTCN2019070333-appb-000016
Figure PCTCN2019070333-appb-000017
步骤7)假定调制深度m＝2.63，J 1(m)＝J 2(m)；对新谐波幅值信号进行四象限反正切运算，得到待测相位，公式如下：
Figure PCTCN2019070333-appb-000018
其中，sign(R 1)和sign(R 2)分别表示R 1与R 2的符号；
所述的方法计算过程采用相位处理系统，相位处理系统具体为：
第一乘法器、第二乘法器、第五乘法器、第六乘法器、第七乘法器和第八乘法器的输入端均连接数字干涉信号S(t)，第一数字频率合成器连接在第一乘法器和第二乘法器的输入端，第二数字频率合成器连接在第五乘法器和第六乘法器的输入端，第三数字频率合成器连接在第七乘法器和第八乘法器的输入端；第一乘法器的输出端经第一低通滤波器分别连接到第一绝对值加法器的输入端和相位延时提取模块的输入端，第二乘法器的输出端经第二低通滤波器分别连接到第一绝对值加法器的输入端和相位延时提取模块的输入端，第五乘法器的输出端经第三低通滤波器分别连接到第二绝对值加法器的输入端和相位延时提取模块的输入端，第六乘法器的输出端经第四低通滤波器分别连接到第二绝对值加法器的输入端和相位延时提取模块的输入端，第七乘法器、第八乘法器的输出端分别经第五低通滤波器、第六低通滤波器连接到相位延时提取模块的输入端；相位延时提取模块的输出端连接到相位延时修正系数计算模块的输入端，第一绝对值加法器的输出端与相位延时修正系数计算模块的输出端经第三乘法器连接到第一反正切运算器的输入端，第二绝对值加法器的输出端与相位延时修正系数计算模块的输出端经过第四乘法器连接到第一反正切运算器的输入端，第一反正切运算器的输出端输出待测相位。
所述的相位延时提取模块具体为：第九乘法器的输入端分别连接第一低通滤波器、第二低通滤波器的输出端，第一低通滤波器的输出端还与第一平方运算器的输入端相连，第九乘法器的输出端经倍乘器连接到第一加法器的输入端；第二低通滤波器的输出端还与第二平方运算器的输入端相连，第二平方运算器的输出端与第一平方运算器的输出端经第一减法器共同连接到第二加法器的输入端；第十三乘法器的输入端分别连接第三低通滤波器、第六低通滤波器的输出端，第十二乘法器的输入端分别连接第四低通滤波器、第五低通滤波器的输出端，第十二乘法器和第十三乘法器的输出端经第二减法器连接到第一加法器的输入端；第十乘法器的输入端分别连接第三低通滤波器、第五低通滤波器的输出端，第十一乘法器的输入端分别连接第四低通滤波器、第六低通滤波器的 输出端，第十乘法器与第十一乘法器的输出端经第三加法器连接到第二加法器的输入端；第一加法器与第二加法器的输出端均连接到第二反正切运算器的输入端，第二反正切运算器的输出端分两路，第一支路经二分之一乘法器输出到相位延时修正系数计算模块，第二支路直接输出结果至相位延时修正系数计算模块。
所述的相位延时修正系数计算模块具体为：第二反正切运算器第一支路后二分之一乘法器的输出端经第一余弦查找表获得正弦值和余弦值，两个值依次经第三绝对值加法器、第一倒数运算器连接第一符号乘法器的输入端，第一符号乘法器将来自第一倒数运算器的输出值与第二低通滤波器经第一符号运算器得到的输出值进行运算从而输出运算结果；第二反正切运算器的第二支路的输出端经第二余弦查找表获得正弦值和余弦值，两个值依次经第四绝对值加法器、第二倒数运算器连接第二符号乘法器的输入端，第二符号乘法器将来自第二倒数运算器的输出值与第三低通滤波器经第二符号运算器得到的输出值进行运算从而输出运算结果。
所述的方法应用于正弦相位调制干涉仪，所述的正弦相位调制干涉仪包括单频激光器、偏振片、分光棱镜、测量角锥棱镜、电光相位调制器、光电探测器和高压放大器，单频激光器发出激光光束，经偏振片入射到分光棱镜发生反射和透射，分光棱镜的反射光经电光相位调制器调制后入射到参考角锥棱镜，经参考角锥棱镜反射回到分光棱镜发生反射，分光棱镜的透射光经测量角锥棱镜反射后回到分光棱镜发生透射，回到分光棱镜发生反射和透射的两束光束合束后经反射镜反射到光电探测器，光电探测器接收光束后产生光信号，光信号依次经放大器、带通滤波器、模数转换器输入到现场可编程门阵列信号处理器FPGA，现场可编程门阵列信号处理器FPGA输出控制信号依次经数模转换器、高压放大器后输入到电光相位调制器的控制端。
参考角锥棱镜固定不动，测量角锥棱镜固定于待测物体上。
与背景技术相比，本发明具有的有益效果是：
(1)本发明方法运用一阶、二阶、四阶正交谐波幅值信号来提取出相位延迟量，不受待测相位的影响，可以实现相位延迟的实时提取，从而实现了相位延迟的实时补偿；
(2)本发明方法运用一阶、二阶、四阶正交谐波幅值信号构造在任何角度的相位延迟下幅值都不为零的绝对谐波幅值信号，解决了相位延迟在特定角度时待测相位无法测量的问题；
(3)本发明运用相位延迟计算出对应的相位延迟修正系数来补偿相位延迟带来的影响，消除了相位延迟带来的非线性误差，提高了相位测量精度，可以广泛应用于正弦调制干涉技术领域。
附图说明
图1是PGC相位解调法中相位延迟提取与补偿方法的原理框图。
图2是相位延迟提取模块的原理框图。
图3相位延迟修正系数计算模块的原理框图。
图4是本发明应用在正弦相位调制干涉仪中的系统示意图。
图5是本发明仿真实验数据结果图。
图中：1、第一数字频率合成器，2、第一乘法器，3、第二乘法器，4、第一低通滤波器，5、第二低通滤波器，6、第一绝对值加法器，7、第二绝对值加法器，8、第三乘法器，9、第四乘法器，10、第一反正切运算器，11、第三低通滤波器，12、第五乘法器，13、第二数字频率合成器，14、第六乘法器，15、第四低通滤波器，16、第三数字频率合成器，17、第七乘法器，18、第八乘法器，19、第五低通滤波器，20、第六低通滤波器，21、相位延时提取模块，22、相位延时修正系数计算模块。23、单频激光器，24、偏振片，25、分光棱镜，26、参考角锥棱镜，27、电光相位调制器，28、高压放大器，29、测量角锥棱镜，30、反射镜，31、光电探测器，32、放大器，33、带通滤波器，34、模数转换器，35、现场可编程门阵列信号处理器FPGA，36、数模转换器，2101、第九乘法器，2102、倍乘器，2103、第一平方运算器，2104、第二平方运算器，2105、第一减法器，2106、第一加法器，2107、第二加法器，2108、第二反正切运算器，2109、二分之一乘法器，2110、第十乘法器，2111、第十一乘法器，2112、第三加法器，2113、第十二乘法器，2114、第十三乘法器，2115、第二减法器，2201、第一余弦查找表，2202、第三绝对值加法器，2203、第一符号运算器，2204、第一倒数运算器，2205、第一符号乘法器，2206、第二余弦查找表，2207、第四绝对值加法器，2208、第二符号运算器，2209、第二倒数运算器，2210、第二符号乘法器。
具体实施方式
下面结合附图和实施例对本发明加以详细说明。
如图1所示，具体实施采用以下相位处理系统：第一乘法器2、第二乘法器3、第五乘法器12、第六乘法器14、第七乘法器17和第八乘法器18的输入端均连接数字干涉信号S(t)，第一数字频率合成器1连接在第一乘法器2和第二乘 法器3的输入端，第二数字频率合成器13连接在第五乘法器12、第六乘法器14的输入端，第三数字频率合成器16连接在第七乘法器17和第八乘法器18的输入端。
第一乘法器2的输出端经第一低通滤波器4分别连接到第一绝对值加法器6的输入端和相位延时提取模块21的输入端，第二乘法器3的输出端经第二低通滤波器5分别连接到第一绝对值加法器6的输入端和相位延时提取模块21的输入端，第五乘法器12的输出端经第三低通滤波器11分别连接到第二绝对值加法器7的输入端和相位延时提取模块21的输入端，第六乘法器14的输出端经第四低通滤波器15分别连接到第二绝对值加法器7的输入端和相位延时提取模块21的输入端，第七乘法器17、第八乘法器18的输出端分别经第五低通滤波器19、第六低通滤波器20连接到相位延时提取模块21的输入端。
相位延时提取模块21的输出端连接到相位延时修正系数计算模块22的输入端，第一绝对值加法器6的输出端与相位延时修正系数计算模块22的输出端经第三乘法器8连接到第一反正切运算器10的输入端，第二绝对值加法器7的输出端与相位延时修正系数计算模块22的输出端经过第四乘法器9连接到第一反正切运算器10的输入端，第一反正切运算器10的输出端输出待测相位。
本发明实施原理过程为：
在获得数字信号S(t)后，首先进行的是正交下混频运算，具体如下：通过第一乘法器2、第二乘法器3将数字干涉信号S(t)与第一数字频率合成器1产生的一阶正交参考信号相乘，经第一低通滤波器4、第二低通滤波器5滤波后，获得一阶正交谐波幅值信号(Q 1，P 1)；同理，通过第五乘法器12、第六乘法器14将数字干涉信号S(t)与第二数字频率合成器13产生的二阶正交参考信号相乘，经第三低通滤波器11、第四低通滤波器14滤波后获得二阶正交谐波幅值信号(P 2,Q 2)，同理，通过第七乘法器17、第八乘法器18将数字干涉信号S(t)与第三数字频率合成器16产生的四阶正交参考信号相乘，经第五低通滤波器19、第四低通滤波器20滤波后获得四阶正交谐波幅值信号(P 4,Q 4)，到此完成正交下混频运算，公式分别如下：
Figure PCTCN2019070333-appb-000019
Figure PCTCN2019070333-appb-000020
Figure PCTCN2019070333-appb-000021
Figure PCTCN2019070333-appb-000022
Figure PCTCN2019070333-appb-000023
Figure PCTCN2019070333-appb-000024
其中，A表示干涉信号的幅值，m表示调制深度，θ表示相位延迟，
Figure PCTCN2019070333-appb-000025
表示待测相位，J 1(m)表示第一阶第一类贝塞尔函数，J 2(m)表示第二阶第一类贝塞尔函数，J 4(m)表示第四阶第一类贝塞尔函数；
相位延迟提取模块21运用这3对正交谐波幅值信号(Q 1、P 1)、(Q 2、P 2)和(Q 4、P 4)提取出相位延迟量θ c,公式如下：
Figure PCTCN2019070333-appb-000026
相位延迟修正系数计算模块22运用已提取的相位延迟量θ c计算一阶相位延迟修正系数G 1和二阶相位延迟修正系数G 2，公式如下：
Figure PCTCN2019070333-appb-000027
Figure PCTCN2019070333-appb-000028
同时通过第一绝对值加法器6求得Q 1和P 1的绝对值之和，获得一阶绝对谐波信号幅值T 1；同理，通过第二绝对值加法器7求得Q 2和P 2的绝对值之和，获得二阶绝对谐波信号幅值T 2,公式如下：
Figure PCTCN2019070333-appb-000029
Figure PCTCN2019070333-appb-000030
用第三乘法器8、第四乘法器9将一阶、二阶相位延迟修正系数分别乘以一阶、二阶绝对谐波幅值信号幅值，获得补偿相位延迟的一阶新谐波幅值正交信号R 1和二阶新谐波幅值正交信号R 2，公式如下：
Figure PCTCN2019070333-appb-000031
Figure PCTCN2019070333-appb-000032
用第一反正切运算器10对补偿相位延迟后的新谐波幅值正交信号(R 1，R 2)进行四象限反正切运算获得待测相位
Figure PCTCN2019070333-appb-000033
公式如下：
Figure PCTCN2019070333-appb-000034
如图2所示，本模块为相位延迟提取模块的原理框图，对图1中的相位延迟提取模块21内信号处理方法进一步说明。第九乘法器2101的输入端分别连接第一低通滤波器4、第二低通滤波器5的输出端，第一低通滤波器4的输出端还与第一平方运算器2103的输入端相连，第九乘法器2101的输出端经倍乘器2102连接到第一加法器2106的输入端。
第二低通滤波器5的输出端还与第二平方运算器2104的输入端相连，第二平方运算器2104的输出端与第一平方运算器2103的输出端经第一减法器2105共同连接到第二加法器2107的输入端。
第十三乘法器2114的输入端分别连接第三低通滤波器11、第六低通滤波器20的输出端，第十二乘法器2113的输入端分别连接第四低通滤波器15、第五低通滤波器19的输出端，第十二乘法器2113和第十三乘法器2114的输出端经第二减法器2115连接到第一加法器2106的输入端。
第十乘法器2110的输入端分别连接第三低通滤波器11、第五低通滤波器19的输出端，第十一乘法器2111的输入端分别连接第四低通滤波器15、第六低通滤波器20的输出端，第十乘法器2110与第十一乘法器2111的输出端经第三加法器2112连接到第二加法器2107的输入端。
第一加法器2106与第二加法器2107的输出端均连接到第二反正切运算器2108的输入端，第二反正切运算器2108的输出端分两路，第一支路经二分之一乘法器2109输出到相位延时修正系数计算模块22，第二支路直接输出结果至相位延时修正系数计算模块22。
通过第九乘法器2101将一阶正交谐波幅值信号P 1与Q 1相乘，乘积经倍乘器2102放大2倍，得到信号U 1，公式如下：
Figure PCTCN2019070333-appb-000035
同时，第一平方运算器2103，第二平方运算器2104对一阶正交幅值信号(P 1，Q 1)分别进行平方运算，然后经第一减法器2105进行减法运算，得到信号U 2，公式如下：
Figure PCTCN2019070333-appb-000036
显然，信号(U 1,U 2)的幅值均等于
Figure PCTCN2019070333-appb-000037
该幅值与待测相位
Figure PCTCN2019070333-appb-000038
有关，当且仅当
Figure PCTCN2019070333-appb-000039
时(k为任意整数)，信号(U 1,U 2)均为零，此时该信号无法直接用于计算相位延迟值。为此，本发明构建另一对在这种情况下幅值大于零的信号(V 1,V 2)。通过第十三乘法器2114将信号P 2与Q 4相乘，通过第十二乘法器2113将信号Q 2与P 4相乘，通过第二减法器2115将乘积P 2Q 4与Q 2P 4做差，得到信号V 1，公式如下：
Figure PCTCN2019070333-appb-000040
同时，通过第十乘法器2110将信号P 2与P 4相乘，通过第十一乘法器2111将信号Q 2与Q 4相乘，通过第三加法器2112将乘积P 2P 4与Q 2Q 4相加，得到信号V 2，公式如下：
Figure PCTCN2019070333-appb-000041
显然信号(V 1,V 2)的幅值均等于
Figure PCTCN2019070333-appb-000042
该幅值与待测相位
Figure PCTCN2019070333-appb-000043
有关，当且仅当
Figure PCTCN2019070333-appb-000044
时(k为任意整数)，信号(V 1,V 2)均为零，此时该公式无法直接用于计算相位延迟值。
这两对信号(U 1,U 2)和(V 1,V 2)的幅值都会受到待测相位影响；但是当信号(U 1,U 2)幅值为零时，信号(V 1,V 2)幅值刚好大于零，反之当信号(U 1,U 2)幅值为零时，信号(V 1,V 2)幅值刚好大于零，即两者的幅值不会同时为零。因此结合这两对信号可以构建出不受待测相位影响相位延迟计算方法。通过第一加法器2106求得U 1与V 1之和，获得幅值恒大于零的相位延迟正弦信号W 1；通过第二加法器2107求得U 2与V 2之和，获得幅值恒大于零的相位延迟余弦信号W 2，公式分别如下：
Figure PCTCN2019070333-appb-000045
Figure PCTCN2019070333-appb-000046
由此获得的相位延迟信号(W 1,W 2)在待测相位为任何值时均恒大于零，通过第二反正切运算器2108进行反正切运算，获得二倍相位延迟量2θ c，通过二分之一乘法器2109将其乘以0.5，最终获得相位延迟量θ c，公式如下：
Figure PCTCN2019070333-appb-000047
在该相位延迟计算方法中，分子分母在待测相位为任何值时恒大于零，即不受待测相位影响，在任何角度待测相位时都可以正确的提取相位延迟值。假定实际相位延时取值为-π到π，运用上述公式提取的相位延迟量θ c与实际相位延迟量θ的关系为θ＝θ c±kπ(k＝-1,0,1)。
如图3所示，本模块为相位延迟修正系数计算模块的原理框图，即对图1中的相位延迟修正系数计算模块22内信号处理方法进一步说明。
第二反正切运算器2108的第一支路的输出端经第一余弦查找表2201获得正弦值和余弦值，两个值依次经第三绝对值加法器2202、第一倒数运算器2204连接第一符号乘法器2205的输入端，第一符号乘法器2205将来自第一倒数运算器2204的输出值与第二低通滤波器5经第一符号运算器2203得到的输出值进行运算从而输出运算结果。
第二反正切运算器2108的第二支路的输出端经第二余弦查找表2206获得正弦值和余弦值，两个值依次经第四绝对值加法器2207、第二倒数运算器2209连接第二符号乘法器2210的输入端，第二符号乘法器2210将来自第二倒数运算器2209的输出值与第三低通滤波器11经第二符号运算器2208得到的输出值进行运算从而输出运算结果。
观察绝对谐波幅值信号(T 1,T 2)可知，存在的相位延迟的误差项分别为|sinθ|+|cosθ|与|sin2θ|+|cos2θ|，为了补偿这个误差，运用上述计算所得的相位延迟量θ c，计算出这两个误差项的倒数值，再将其乘以对应的绝对谐波幅值信号(T 1,T 2)，就补偿了相位延迟的影响。首先通过第一余弦查找表2201获得相位延迟量的正弦值和余弦值(sinθ c,cosθ c)，通过第二余弦查找表2206获得2倍相位延迟量的正弦值和余弦值(sin2θ c,cos2θ c)。通过第三绝对值加法器2202求得相位延迟量的正弦值和余弦值的绝对值之和(|sinθ c|+|cosθ c|)，通过第四绝对值加法器 2207求得二倍相位延迟量的正弦值和余弦值的绝对值之和(|sin2θ c|+|cos2θ c|)。通过第一倒数运算器2204计算|sinθ c|+|cosθ c|的倒数，再通过第一符号乘法器2205将其与第一符号运算器2203计算所得的符号相乘，最终获得一阶绝对谐波幅值信号相位延迟修正系数G 1，公式如下：
Figure PCTCN2019070333-appb-000048
同时，通过第二倒数运算器2209计算|sin2θ c|+|cos2θ c|倒数，再通过第二符号乘法器2210将其与第二符号运算器2208计算所得的符号相乘，最终获得一阶绝对谐波幅值信号相位延迟修正系数G 2，公式如下：
Figure PCTCN2019070333-appb-000049
结合三角函数的性质，修正系数G 1，G 2的分母均取值范围为1到根号2，避免了在分母为零，倒数运算无法正常计算的情况。
如图4所示，单频激光器23、偏振片24、分光棱镜25、测量角锥棱镜29沿直线依次间隔设置，分光棱镜25的一侧设有参考角锥棱镜26，分光棱镜25的另一侧布置有反射镜30，反射镜30的一侧依次布置有光电探测器31，光电探测器31依次与放大器32、带通滤波器33、模数转换器34、现场可编程门阵列信号处理器(FPGA)35、数模转换器36连接，数模转换器36经高压放大器28连接到电光相位调制器27。
具体实施中，单频激光器23输出波长为780nm；电光相位调制器27最高调制频率为1MHz；光电探测器31的带宽为10MHz；干涉信号的带通滤波器33由1个隔直滤波器与一个截止频率为10MHz的低通滤波器串联组成；模数转换器34的采样频率为125MHz；模数转换器的采样频率为125MHz；FPGA 35为高性能的XC7K160T。
单频激光器23发出的激光经偏振片24后过滤为垂直纸面方向的线偏振光，该线偏振光经分光棱镜25后分为两束光，其中透射的测量光，反射的参考光。测量光经测量角锥棱镜29反射后返回分光棱镜25，在测量光往返过程中，测量光的相位发生了改变，这个相位改变与分光镜25到测量角锥棱镜29的距离呈正比，即该相位改变量为待测相位。FPGA35产生的正弦调制信号通过数模转换器36转换为模拟正弦调制信号后经高压放大器28放大，最后再驱动电光调制器27对参考光进行正弦相位调制，其中正弦调制信号的频率设置为200kHz。正弦调制信号的幅值决定了调制深度大小，本实例中正弦调制信号幅值经过精密 调整可以确保调制深度保持2.63弧度(此时J 1(m)＝J 2(m))，即后续处理中无需考虑调制深度带来的影响。正弦相位调制后的参考光经参考角锥棱镜26反射后返回分光棱镜25。
返回到分光棱镜25的测量光和参考光合光后经反射镜30反射到光电探测器31，光电探测器31产生正弦相位调制干涉信号，正弦相位调制干涉信号经放大器32放大，带通滤波器33滤波后再经模数转换器34进行采样转换为数字干涉信号。正弦调制信号从产生到驱动电光相位调制器27进行相位调制过程中有一定延迟，这些延迟是PGC相位解调算法中载波相位延迟的主要来源，包含载波相位延迟的数字干涉信号公式如下：
Figure PCTCN2019070333-appb-000050
然后模数转换器34将该数字干涉信号输入FPGA 35，在FPGA 35内实现图1所示的PGC相位解调法中的相位延迟测量与补偿方法，最终准确获得待测相位。
如图5所示，实际仿真中，按照数字干涉信号S(t)的公式，用信号源产生相同的仿真的正弦相位调制干涉信号，其中调制深度设置为2.63，相位延时设置为10°，将该模拟的正弦相位调制干涉信号传输给图1对应的信号处理板，在FPGA 35完成本发明提出的PGC相位解调法中相位延迟测量与补偿方法，最终得到如图5所示的实验数据。图5所示的数据中，实线表示由传统的，即未补偿相位延时的PGC-Arctan相位解调算法测量的数据与参考位移的误差。显然该非线性误差随着参考位移呈现正弦规律变化，峰峰值约为2.7纳米。虚线所示为本发明提出的PGC相位解调法中相位延迟测量与补偿方法测量得到的数据与参考位移的误差，显然该结果不存在非线性误差，整体呈现为峰峰值为0.1纳米的白噪声。该实验数据表明本发明提出的PGC相位解调法中相位延迟测量与补偿方法可以有效消除由调制深度带来的非线性误差。
综上，本发明方法充分运用1阶、2阶和4阶正交谐波幅值信号来提取出相位延迟量，运用相位延迟计算出对应的相位延迟修正系数来补偿相位延迟带来的影响，消除了相位延迟带来的非线性误差，提高了相位测量精度。
上述具体实施方式用来解释说明本发明，而不是对本发明进行限制，在本发明的精神和权利要求的保护范围内，对本发明作出的任何修改和改变，都落入本发明的保护范围。

Claims (5)

  1. 一种PGC相位解调法中相位延迟提取与补偿方法，其特征在于包括以下步骤：
    步骤1)采样获得数字干涉信号S(t)，数字信号S(t)表示如下：
    Figure PCTCN2019070333-appb-100001
    其中，A表示数字干涉信号的幅值，m表示调制深度，θ表示相位延迟，ω c表示正弦调制信号的频率，
    Figure PCTCN2019070333-appb-100002
    表示待测相位，J 0(m)表示第0阶的第一类贝塞尔函数，J 2n(m)表示偶数阶的第一类贝塞尔函数，J 2n-1(m)表示奇数阶的第一类贝塞尔函数；
    步骤2)数字干涉信号S(t)分别与通过数字频率合成器产生的一阶正交参考信号(sin(ω ct)、cos(ω ct))、二阶正交参考信号(cos(2ω ct)、sin(2ω ct))、四阶正交参考信号(cos(4ω ct)、sin(4ω ct))通过乘法器相乘以及低通滤波处理完成正交下混频运算，各滤波器输出的直流信号与数字干涉信号S(t)中对应谐波的幅值呈正比，定义为谐波幅值信号，对于同一阶谐波幅值信号按照其与相位延迟θ的余弦值呈正比还是与相位延迟θ的正弦值呈正比分别定义为信号P i与Q i，即P i与Q i是正交的，其中下标i表示阶数，取值范围为1,2,4，获得3对正交的谐波幅值信号(P 1、Q 1)、(P 2、Q 2)和(P 4、Q 4)，分别为一阶正交谐波幅值信号(P 1,Q 1)、二阶正交谐波幅值信号(P 2,Q 2)和四阶正交谐波幅值信号(P 4,Q 4)，P 1、Q 1、P 2、Q 2、P 4、Q 4分别计算为：
    Figure PCTCN2019070333-appb-100003
    Figure PCTCN2019070333-appb-100004
    Figure PCTCN2019070333-appb-100005
    Figure PCTCN2019070333-appb-100006
    Figure PCTCN2019070333-appb-100007
    Figure PCTCN2019070333-appb-100008
    其中，LPF[]表示低通滤波运算，A表示数字干涉信号的幅值，m表示调制深度，θ表示相位延迟，
    Figure PCTCN2019070333-appb-100009
    表示待测相位，J 1(m)表示第一阶第一类贝塞尔函数， J 2(m)表示第二阶第一类贝塞尔函数，J 4(m)表示第四阶第一类贝塞尔函数；ω c表示正弦调制信号的频率；
    步骤3)运用一阶正交谐波幅值信号(P 1,Q 1)、二阶正交谐波幅值信号(P 2,Q 2)和四阶正交谐波幅值信号(P 4,Q 4)进行运算得到不受待测相位
    Figure PCTCN2019070333-appb-100010
    影响的相位延迟量θ c，计算公式如下：
    Figure PCTCN2019070333-appb-100011
    步骤4)一阶正交谐波幅值信号(P 1,Q 1)、二阶正交谐波幅值信号(P 2,Q 2)分别经绝对值加法器相加得到在任何角度的相位延迟下幅值都不为零的绝对谐波幅值信号(T 1，T 2)，T 1，T 2分别表示一阶正交谐波幅值信号P 1与Q 1的绝对值之和以及二阶正交谐波幅值信号P 2与Q 2的绝对值之和，计算公式如下：
    Figure PCTCN2019070333-appb-100012
    Figure PCTCN2019070333-appb-100013
    步骤5)运用步骤3)得到的相位延迟量θc分别计算一阶绝对谐波幅值信号相位延迟修正系数G 1、二阶绝对谐波幅值信号相位延迟修正系数G 2，计算公式如下：
    Figure PCTCN2019070333-appb-100014
    Figure PCTCN2019070333-appb-100015
    其中，sign(P 1)和sign(P 2)分别表示P 1与P 2的符号；
    步骤6)将绝对谐波幅值信号(T 1，T 2)分别乘以上述对应的相位延迟修正系数G 1与G 2，重构出幅度不受相位延迟影响的新谐波幅值信号(R 1，R 2)，R 1和R 2分别表示绝对谐波幅值信号T 1与相位延迟修正系数G 1的乘积以及绝对谐波幅值信号T 2与相位延迟修正系数G 2的乘积，重构计算公式如下：
    Figure PCTCN2019070333-appb-100016
    Figure PCTCN2019070333-appb-100017
    步骤7)对新谐波幅值信号(R 1，R 2)进行四象限反正切运算，得到待测相 位，公式如下：
    Figure PCTCN2019070333-appb-100018
    其中，sign(R 1)和sign(R 2)分别表示R 1与R 2的符号。
  2. 根据权利要求1所述的一种PGC相位解调法中相位延迟提取与补偿方法，其特征在于：所述的方法计算过程采用相位处理系统，相位处理系统具体为：第一乘法器(2)、第二乘法器(3)、第五乘法器(12)、第六乘法器(14)、第七乘法器(17)和第八乘法器(18)的输入端均连接数字干涉信号S(t)，第一数字频率合成器(1)连接在第一乘法器(2)和第二乘法器(3)的输入端，第二数字频率合成器(13)连接在第五乘法器(12)和第六乘法器(14)的输入端，第三数字频率合成器(16)连接在第七乘法器(17)和第八乘法器(18)的输入端；第一乘法器(2)的输出端经第一低通滤波器(4)分别连接到第一绝对值加法器(6)的输入端和相位延时提取模块(21)的输入端，第二乘法器(3)的输出端经第二低通滤波器(5)分别连接到第一绝对值加法器(6)的输入端和相位延时提取模块(21)的输入端，第五乘法器(12)的输出端经第三低通滤波器(11)分别连接到第二绝对值加法器(7)的输入端和相位延时提取模块(21)的输入端，第六乘法器(14)的输出端经第四低通滤波器(15)分别连接到第二绝对值加法器(7)的输入端和相位延时提取模块(21)的输入端，第七乘法器(17)、第八乘法器(18)的输出端分别经第五低通滤波器(19)、第六低通滤波器(20)连接到相位延时提取模块(21)的输入端；相位延时提取模块(21)的输出端连接到相位延时修正系数计算模块(22)的输入端，第一绝对值加法器(6)的输出端与相位延时修正系数计算模块(22)的输出端经第三乘法器(8)连接到第一反正切运算器(10)的输入端，第二绝对值加法器(7)的输出端与相位延时修正系数计算模块(22)的输出端经过第四乘法器(9)连接到第一反正切运算器(10)的输入端，第一反正切运算器(10)的输出端输出待测相位。
  3. 根据权利要求2所述的一种PGC相位解调法中相位延迟提取与补偿方法，其特征在于：所述的相位延时提取模块(21)具体为：第九乘法器(2101)的输入端分别连接第一低通滤波器(4)、第二低通滤波器(5)的输出端，第一低通滤波器(4)的输出端还与第一平方运算器(2103)的输入端相连，第九 乘法器(2101)的输出端经倍乘器(2102)连接到第一加法器(2106)的输入端；第二低通滤波器(5)的输出端还与第二平方运算器(2104)的输入端相连，第二平方运算器(2104)的输出端与第一平方运算器(2103)的输出端经第一减法器(2105)共同连接到第二加法器(2107)的输入端；第十三乘法器(2114)的输入端分别连接第三低通滤波器(11)、第六低通滤波器(20)的输出端，第十二乘法器(2113)的输入端分别连接第四低通滤波器(15)、第五低通滤波器(19)的输出端，第十二乘法器(2113)和第十三乘法器(2114)的输出端经第二减法器(2115)连接到第一加法器(2106)的输入端；第十乘法器(2110)的输入端分别连接第三低通滤波器(11)、第五低通滤波器(19)的输出端，第十一乘法器(2111)的输入端分别连接第四低通滤波器(15)、第六低通滤波器(20)的输出端，第十乘法器(2110)与第十一乘法器(2111)的输出端经第三加法器(2112)连接到第二加法器(2107)的输入端；第一加法器(2106)与第二加法器(2107)的输出端均连接到第二反正切运算器(2108)的输入端，第二反正切运算器(2108)的输出端分两路，第一支路经二分之一乘法器(2109)输出到相位延时修正系数计算模块(22)，第二支路直接输出结果至相位延时修正系数计算模块(22)。
  4. 根据权利要求2所述的一种PGC相位解调法中相位延迟提取与补偿方法，其特征在于：所述的相位延时修正系数计算模块(22)具体为：第二反正切运算器(2108)第一支路后二分之一乘法器(2109)的输出端经第一余弦查找表(2201)获得正弦值和余弦值，两个值依次经第三绝对值加法器(2202)、第一倒数运算器(2204)连接第一符号乘法器(2205)的输入端，第一符号乘法器(2205)将来自第一倒数运算器(2204)的输出值与第二低通滤波器(5)经第一符号运算器(2203)得到的输出值进行运算从而输出运算结果；第二反正切运算器(2108)的第二支路的输出端经第二余弦查找表(2206)获得正弦值和余弦值，两个值依次经第四绝对值加法器(2207)、第二倒数运算器(2209)连接第二符号乘法器(2210)的输入端，第二符号乘法器(2210)将来自第二倒数运算器(2209)的输出值与第三低通滤波器(11)经第二符号运算器(2208)得到的输出值进行运算从而输出运算结果。
  5. 根据权利要求1所述的一种PGC相位解调法中相位延迟提取与补偿方法，其特征在于：所述的方法应用于正弦相位调制干涉仪，所述的正弦相位调制干涉仪包括单频激光器(23)、偏振片(24)、分光棱镜(25)、测量角锥棱镜(29)、电光相位调制器(27)、光电探测器(31)和高压放大器(28)，单频激光器(23)发出激光光束，经偏振片(24)入射到分光棱镜(25)发生 反射和透射，分光棱镜(25)的反射光经电光相位调制器(27)调制后入射到参考角锥棱镜(26)，经参考角锥棱镜(26)反射回到分光棱镜(25)发生反射，分光棱镜(25)的透射光经测量角锥棱镜(29)反射后回到分光棱镜(25)发生透射，回到分光棱镜(25)发生反射和透射的两束光束合束后经反射镜(31)反射到光电探测器(31)，光电探测器(31)接收光束后产生光信号，光信号依次经放大器(32)、带通滤波器(33)、模数转换器(34)输入到现场可编程门阵列信号处理器FPGA(35)，现场可编程门阵列信号处理器FPGA(35)输出控制信号依次经数模转换器(36)、高压放大器(28)后输入到电光相位调制器(27)的控制端。
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