WO2020098048A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2020098048A1
WO2020098048A1 PCT/CN2018/121480 CN2018121480W WO2020098048A1 WO 2020098048 A1 WO2020098048 A1 WO 2020098048A1 CN 2018121480 W CN2018121480 W CN 2018121480W WO 2020098048 A1 WO2020098048 A1 WO 2020098048A1
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Prior art keywords
thin film
film transistor
display panel
drain
source
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PCT/CN2018/121480
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English (en)
French (fr)
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吴川
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惠科股份有限公司
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Publication of WO2020098048A1 publication Critical patent/WO2020098048A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a display device.
  • Micro LED display is to thin, miniaturize and array the LED structure design, batch transfer Micro LED to the circuit substrate, integrate high-density micro LED array as display pixels, and carry on the substrate Packaging, complete a Micro LED display device.
  • the minimum size of micro LED can be 1 ⁇ 10 microns.
  • Micro LED displays are organic light-emitting diode (Organic Light-Emitting Diode, OLED) displays that are self-luminous displays, but micro LED displays have the advantages of better material stability, longer life, and no image imprinting than OLED displays. Compared with LCD (Liquid Crystal Display), it has higher transmittance.
  • TFT Thin Film Transistor
  • a-Si Amorphous Silicon
  • IGZO Indium Gallium Zinc Oxide
  • LTPS Low Temperature Poly-silicon, low-temperature polysilicon
  • the electron mobility of a-si is only about 0.5 cm 2 / Vs, and its mobility is not enough to provide a large on-state current for current driving.
  • the electron mobility of IGZO can reach 10 ⁇ 50cm 2 / Vs, but the stability of IGZO's compressive stress is poor, so its stability needs to be improved.
  • the electron mobility of LTPS can reach 100cm 2 / Vs, but the complex structure and uniformity of its TFT device limit its application in next generation panels. Therefore, if a TFT device based on a-Si can be developed to drive micro LEDs, the mass productivity of micro LED displays will be greatly improved.
  • An object of the present application is to provide a display panel, including but not limited to making thin film transistors meet the driving current requirements of micro light-emitting diodes, and at the same time take into account its stability and suitable for mass production.
  • a display panel including:
  • the array is arranged on the substrate base layer;
  • the sub-pixel unit includes a switching thin film transistor, a driving thin film transistor, a detecting thin film transistor and a micro light emitting diode;
  • the driving thin film transistor includes a first gate, a first active layer, a first source, and a first drain, the first gate is connected to the switching thin film transistor, and the first source is connected to a high potential End, the first drain is connected to the micro light emitting diode and the detection thin film transistor;
  • the first source electrode includes a plurality of curved bars connected side by side, and the first drain includes a plurality of spaced straight bars and connection bars connecting the plurality of straight bars; the straight bars Inserted into the opening of the curved strip in a one-to-one correspondence, a zigzag gap is formed between the first source electrode and the first drain electrode, and a portion of the first active layer corresponding to the gap forms a conductive channel.
  • Another object of this application is to provide a display panel, including:
  • the array is arranged on the substrate base layer;
  • the sub-pixel unit includes a switching thin film transistor, a driving thin film transistor, a detecting thin film transistor and a micro light emitting diode;
  • the driving thin film transistor includes a first gate, a first active layer, a first source, and a first drain, the first gate is connected to the switching thin film transistor, and the first source is connected to a high potential End, the first drain is connected to the micro light emitting diode and the detection thin film transistor;
  • the first source electrode includes a plurality of curved bars connected side by side, and the first drain includes a plurality of spaced straight bars and connection bars connecting the plurality of straight bars; the straight bars Inserted into the opening of the curved strip in a one-to-one correspondence, a zigzag gap is formed between the first source electrode and the first drain electrode, and a portion of the first active layer corresponding to the gap forms a conductive channel;
  • the conductive channel includes a first channel corresponding to a curved shape between the curved bar and the straight bar, and the width-to-length ratio of the first channel is 2-10.
  • Another object of the present application is to provide a display device, including a display panel and a packaging layer provided on the light exit side of the display panel; the display panel includes:
  • the array is arranged on the substrate base layer;
  • the sub-pixel unit includes a switching thin film transistor, a driving thin film transistor, a detecting thin film transistor and a micro light emitting diode;
  • the driving thin film transistor includes a first gate, a first active layer, a first source, and a first drain, the first gate is connected to the switching thin film transistor, and the first source is connected to a high potential End, the first drain is connected to the micro light emitting diode and the detection thin film transistor;
  • the first source electrode includes a plurality of curved bars connected side by side, and the first drain includes a plurality of spaced straight bars and connection bars connecting the plurality of straight bars; the straight bars Inserted into the opening of the curved strip in a one-to-one correspondence, a zigzag gap is formed between the first source electrode and the first drain electrode, and a portion of the first active layer corresponding to the gap forms a conductive channel.
  • a plurality of sub-pixel units are provided on the substrate base layer.
  • the sub-pixel units include a switching thin film transistor, a driving thin film transistor, a detection thin film transistor, and a micro light-emitting diode
  • the driving thin film transistor includes a first gate , A first source and a first drain, the first gate is connected to the switching thin film transistor, the first source is connected to the high potential terminal, the first drain is connected to the micro light emitting diode and the detection thin film transistor, the first source includes A plurality of curved strips connected side by side, a drain includes a plurality of straight strips arranged at intervals, and a connecting strip connecting the multiple straight strips, the straight strips are correspondingly inserted into the openings of the curved strips one by one, the first source A zigzag gap is formed between the electrode and the first drain, and the first active layer corresponds to the gap to form a conductive channel, thereby significantly improving the width-to-length ratio of the conductive channel
  • Allowing a larger driving current to pass between the first drains can meet the driving current requirements of the micro light-emitting diode, reduce the manufacturing cost of the driving thin-film transistor, and use the micro-light emitting diode to form the sub-pixel unit, and also has high penetration Rate and service life, thereby reducing energy consumption and increasing the service life of the display panel.
  • the display panel of the present application uses switching thin film transistors, driving thin film transistors, and detecting thin film transistors to drive the micro light-emitting diodes to emit light and display, which can ensure the stability of the display effect of the micro light-emitting diodes and has a good display effect.
  • the display panel and the display device can meet the driving current requirements of the micro light-emitting diode, reduce the manufacturing cost of the driving thin film transistor, and use the micro-light emitting diode to form the sub-pixel unit, and also have high transmittance and service life, thereby reducing energy It consumes and improves the service life of the display panel; the switching thin film transistor, the driving thin film transistor and the detecting thin film transistor are used to drive the micro light-emitting diodes to emit light and display, which can ensure the stability of the micro-light emitting diode display effect and have a good display effect .
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a longitudinal section of a display panel provided by an embodiment of the present application.
  • FIG. 3 is another schematic structural view of a longitudinal section of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a pixel driving circuit in a display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic circuit diagram of a sub-pixel unit in a display panel provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a single horseshoe structure in a display panel provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a conductive channel for driving a thin film transistor in a display panel provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a connection of a horseshoe structure in a display panel provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of the aspect ratio of the driving thin film transistor in the display panel provided by the embodiment of the present application.
  • FIG. 10 is another schematic diagram of the connection of the horseshoe structure in the display panel provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a channel of a switching thin film transistor in a display panel provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a control circuit of a display device provided by an embodiment of the present application.
  • the present application first provides a display panel 100 including a substrate base layer 9 and a plurality of pixel units arranged in an array on the substrate base layer 9, each pixel unit includes a plurality of sub-pixel units 90 of different colors .
  • Each sub-pixel unit 90 includes a switching thin film transistor 2, a driving thin film transistor 1, a capacitive element 4, a micro light emitting diode 5, and a detection thin film transistor 3.
  • the switching thin film transistor 2, the driving thin film transistor 1, the capacitive element 4, and the detection thin film transistor 3 constitute a pixel driving circuit of the sub-pixel unit 90, which is used to drive the micro light-emitting diode 5 to emit light.
  • the light emitting colors of the micro light emitting diodes 5 are different.
  • the sub-pixel units 90 are a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit respectively.
  • the red sub-pixel unit, the green sub-pixel unit, and the blue sub-pixel unit include red micro-pixels, respectively.
  • the pixel unit may also include a yellow sub-pixel unit or a white sub-pixel unit, or be composed of sub-pixel units of other colors, which is not limited.
  • the micro light-emitting diode 5 includes a wafer, and the semiconductor material in the wafer emits light under the action of the current between the positive pin and the negative pin. Depending on the semiconductor material, different colors of light are emitted.
  • the semiconductor material is a compound containing gallium (Ga), arsenic (As), phosphorus (P), nitrogen (N), etc.
  • the red micro-LEDs included in the red sub-pixel unit use gallium arsenide material; the green micro-diodes included in the green sub-pixel unit use gallium phosphide material, and the blue micro-luminescence included in the blue sub-pixel unit
  • the diode uses gallium nitride material.
  • the side length of the micro light-emitting diode 5 is 1-100 microns, and the area is 5-800 square micrometers.
  • the side length of the micro-light emitting diode 5 can be at least 1-10 microns.
  • the side length of the sub-pixel unit 90 is 5 to 500 microns, and its area may be 10 to 1000 square microns.
  • the micro light emitting diode 5 occupies a certain area in the sub-pixel unit 90, except for the area of the micro light emitting diode 5, the other is occupied by the pixel driving circuit.
  • micro-light-emitting diodes 5 of corresponding sizes may be used.
  • a plurality of scanning lines 6 and a plurality of data lines 7 are also formed on the substrate base layer 9, and the sub-pixel unit 90 is disposed between the scanning lines 6 and the data lines 7.
  • the driving thin film transistor 1 includes a first gate 11 provided on the substrate base layer 9, a gate insulating layer 901 formed on the first gate 11, and a gate formed on the gate
  • the switching thin film transistor 2 includes a second gate 21 provided on the substrate base layer 9, a gate insulating layer 901 formed on the second gate 21, a second active layer 22 formed on the gate insulating layer 901, and The second source electrode 23 and the second drain electrode 24 connected to the two ends of the second active layer 22 respectively.
  • the detection thin film transistor 3 includes a third gate 31 disposed on the substrate base layer 9, a gate insulating layer 901 formed on the third gate 31, and a third active layer 32 formed on the gate insulating layer 901 And the third source electrode 33 and the third drain electrode 34 connected to the two ends of the third active layer 32 respectively.
  • the parts filled with the same pattern represent the same layer, and the parts filled with the two patterns represent electrical connection or the formation of a capacitor.
  • the first active layer 12, the second active layer 22, and the third active layer 32 are omitted in FIG.
  • the first gate electrode 11, the second gate electrode 21 and the third gate electrode 31 are arranged in the same layer and are simultaneously formed by a photomask process.
  • the second drain electrode 24, the third source electrode 33 and the third drain electrode 34 are arranged in the same layer and formed simultaneously by a photomask process.
  • the second drain 24 is connected to the first gate 11 through the first via 106 penetrating the gate insulating layer 901.
  • the second gate 21 is connected to the scan line 6, and the second source 23 is connected to the data line 7.
  • the scan signal Scan on the scan line 6 causes the switching thin film transistor 2 to turn on
  • the data line 7 The above data signal Data can be transmitted to the second drain 24.
  • the first source electrode 13 is connected to the high potential terminal (Vdd in FIG. 4), and the first drain electrode 14 is connected to the positive pin of the micro light-emitting diode 5.
  • the data signal Data causes the driving thin film transistor 1 to turn on
  • the current from the high potential terminal can
  • the first source electrode 13 and the first gate electrode 11 reach the negative pin of the micro-light emitting diode 5 and flow to the low potential end (Vss in FIG. 4), so that the micro-light emitting diode 5 can emit light.
  • the lower electrode plate 42 and the second drain 24 of the capacitive element 4 are arranged in the same layer, and are connected between the second drain 24 and the first gate 11, and the upper electrode plate 41 is connected to the positive pin of the micro light-emitting diode 5 and Between the first drains 14, a sustain voltage is provided for driving the thin film transistor 1 on.
  • a passivation layer 902 is provided above the driving thin film transistor 1 and the switching thin film transistor 2, and the upper electrode plate 41 of the capacitor element 4 is provided on the passivation layer 902.
  • a protective layer 903 is further provided on the passivation layer 902 to protect the upper electrode plate 41 of the capacitor element 4, and the protective layer 903 is provided with an opening defining area 904 corresponding to the micro light-emitting diode 5.
  • the micro LED 5 is provided in the opening definition area 904.
  • the connection between the micro LED 5 and the first drain 14 penetrates the passivation layer 902.
  • the micro-light-emitting diode 5 is disposed on the protective layer 903, and the connection between the micro-light-emitting diode 5 and the first drain 14 simultaneously penetrates the passivation layer 902 and the protective layer 903.
  • the third gate 31 of the detection thin-film transistor 3 is connected to the detection signal line 81.
  • the detection signal line 81 and the scanning line 6 are in the same layer but spaced apart, and are provided to provide the detection signal Sense to the third gate 31.
  • the third source electrode 33 is connected to the micro light emitting diode 5 through the second via hole 107 penetrating the passivation layer 902 or both the passivation layer 902 and the protective layer 903.
  • the third drain 34 is connected to the detection control line 82, and the detection control line 82 is configured to input the detection control signal Monitor to the third drain 34, as shown in FIGS. 4 and 5.
  • the driving thin film transistor 1 is an a-Si TFT, and its first active layer 12 includes a first intrinsic semiconductor layer and an ohmic contact layer formed on both sides of the first intrinsic semiconductor layer (not Icon).
  • the material of the first intrinsic semiconductor layer is amorphous silicon
  • the ohmic contact layer is amorphous silicon doped with n-type ions, such as nitrogen (N), phosphorus (P), and arsenic (As) elements.
  • the switching thin film transistor 2 and the detecting thin film transistor 3 can also be n-type a-Si TFTs, so that the second active layer 22 and the third active layer 32 can be in the same process as the first active layer 12 of the driving thin film transistor 1 Formed in order to improve the production efficiency; it can also be other types of thin film transistors, which will not be described in detail.
  • the first source electrode 13 of the driving thin film transistor 1 includes a plurality of curved bars 131 connected side by side, and the opening direction of each curved bar 131 faces the first drain 14.
  • the first drain 14 of the driving thin film transistor 1 is in a comb shape, and includes a plurality of straight bars 141 arranged at intervals and a connecting bar 142 connecting the plurality of straight bars 141, and the straight bars 141 are inserted into the curved bars one by one In the opening of 131 (for convenience of description, a curved bar 131 and a straight bar 141 are referred to as a horseshoe structure hereinafter), thereby forming a curved first gap between the curved bar 131 and the straight bar 141 Between the curved strip 131 and the connecting strip 142, a straight strip-shaped second gap is formed, a plurality of first gaps and a plurality of second gaps are sequentially connected to form a zigzag gap, the second active layer 22
  • the portion corresponding to the tortuous gap is set to form a conductive channel 120, and the conductive channel 120 includes a first channel 121 corresponding to the first gap portion and a second channel 122 corresponding to the second gap portion, see FIG. 7.
  • a zigzag gap is formed between the first source electrode 13 and the first drain electrode 14, and when a voltage is applied to the first gate electrode 11, the first source electrode 13 flows toward the first drain electrode 14 Current flows in the direction of, the first active layer 12 corresponds to the gap to form a conductive channel 120, and in the direction of the current, the width of the gap is the length L of the conductive channel 120, in a direction perpendicular to the current, The total length of the gap is the width W of the conductive channel 120, whereby the width-to-length ratio W / L of the conductive channel 120 of the driving thin film transistor 1 can be improved, and the first source electrode 13 and the first drain of the driving thin film transistor 1 Between 14 allows a larger drive current, so that the micro-light-emitting diode 5 can be driven to emit light.
  • FIG. 6 to FIG. 9 Please refer to FIG. 6 to FIG. 9 to take a horseshoe structure as an example for specific description.
  • the curved bar 131 includes a semi-circular arc portion 1311 in a semi-circular arc shape, and an extension portion 1312 connected to both ends of the semi-circular arc portion 1311 and extending toward the connecting bar 142, and the straight bar 141 includes a rectangle connected to the connecting bar 142 The portion 1412 and the semicircular portion 1411 provided at the tip of the rectangular portion 1412.
  • the extensions 1312 are located on both sides of the straight bar 141 respectively, and the semicircle 1411 corresponds to the semicircular arc 1311, thereby forming a semicircular arc channel 1211 of uniform width between the semicircle 1411 and the semicircular arc 1311, extending A strip-shaped channel 1212 with a uniform width is formed between the portion 1312 and the rectangular portion 1412.
  • the semi-circular arc-shaped channel 1211 is connected to the two strip-shaped channels 1212 to form a first channel 121, and the width of the semi-circular arc-shaped channel 1211 and the width of the strip-shaped channel 1212 are also equal.
  • the straight bars 141 and the connecting bars 142 are vertically connected, and the curved bars 131 are sequentially connected and arranged along the direction parallel to the connecting bars 142.
  • the extending portion 1312 is vertically connected to both ends of the semi-circular arc portion 1311.
  • the width of the gap (that is, the length of the channel) be L
  • the length of the extending portion 1312 toward the first drain 14 be c
  • the width-to-length ratio of one second channel 122 is roughly the ratio of the sum of the widths of the two extensions 1312 and the distance between the extension 1312 and the connecting body 142, that is
  • the width-to-length ratio W / L of the conductive channel 120 of the driving thin film transistor 1 is the sum of multiple W / L (1) and multiple W / L (2), which can greatly increase the width of the conductive channel 120 Aspect ratio.
  • a is 2-50 microns
  • b is 5-55 microns
  • c is 1-50 microns.
  • the range of L is 3 to 53 microns.
  • the number of the first channels 121 that is, the number of the curved strips 131 of the first source electrode 13 may be multiple, optionally, may be more than 10, such as 15 or more, 20 or more, etc., depending on W / L ( 1) and the drive current requirements of the micro light emitting diode 5 are not limited.
  • the width-to-length ratio W / L of the conductive channel 120 of the driving thin film transistor 1 is greater than or equal to 30.
  • width-to-length ratio W / L of the conductive channel 120 is less than or equal to 200, limited by the area of the sub-pixel unit 90 and based on meeting the driving current requirement of the micro light-emitting diode 5.
  • FIG. 10 is another connection method of the curved bar 131.
  • An extension 1312 is shared between two adjacent curved bars 131. Since W / L (2) ⁇ W / L (1), such a design can reduce the number of second channels 122, so that more first channels 121 can be formed in each driving thin film transistor 1, further improving the driving film
  • the width-to-length ratio of the conductive channel 120 of the transistor 1 is W / L.
  • the conductive channel 120 is mainly composed of the first channel 121, and the second channel 122 can be ignored. Simply consider the connection of multiple first channels 121 to derive the width-to-length ratio of the conductive channel 120.
  • the second source electrode 23 and the second drain electrode 24 of the switching thin film transistor 2 are arranged parallel to each other, the channel of the switching thin film transistor 2 is strip-shaped, and the length L ′ of the channel is The distance between the second source electrode 23 and the second drain electrode 24 and the width W ′ of the channel are the width of the second active layer 22 perpendicular to the current direction. The current flows from the second source electrode 23 to the second drain electrode 24 vertically.
  • the detection thin film transistor 3 may also use the same horseshoe structure as the driving thin film transistor 1, such as one horseshoe structure shown in FIG. 5, or two or more horseshoe structures connected in sequence, which is not limited.
  • the switching thin film transistor 2, the capacitive element 4 and the detection thin film transistor 3 are located on one side in a sub-pixel unit 90, and the switching thin film transistor 2 and the detection thin film transistor 3 may be provided on two sides of the capacitive element 4 respectively On the side, the micro light emitting diode 5 and the driving thin film transistor 1 are located on the other side in one sub-pixel unit 90.
  • the detection control line 82 is provided in the same layer as the third source electrode 33 and the third drain electrode 34, but the detection thin film transistor 3 and the detection control line 82 are separated by a capacitor element 4 and other structures.
  • a plurality of transition connection lines 105 are also formed on the substrate base layer 9, and the transition connection lines 105 are parallel to the scanning line 6, which is convenient for manufacturing.
  • the third source electrode 33 is first connected to the transition connection line 105 through the third via 108 penetrating through the gate insulating layer 901, and then the transition connection line 105 passes through the fourth via 109 penetrating through the gate insulating layer 901 and the detection control line 82 connection.
  • the pixel driving circuit can also be arranged in other positions, which is not limited.
  • the present application also provides a display device, as shown in FIG. 12, including the above-mentioned display panel 100 and an encapsulation layer 300 provided above the display panel 100.
  • the encapsulation layer 300 is a transparent layer, such as a glass layer or a transparent plastic layer. The light emitted by the micro light-emitting diode 5 is emitted upward through the encapsulation layer 300 to form a screen for display.
  • the display device further includes a control circuit.
  • the control circuit includes a timing controller 92 and a source driver 93, a gate driver 94 and a reference voltage output circuit 95 respectively connected to the timing controller 92.
  • the timing controller 92 controls the source driver 93 to output the data signal Data to each data line 7, controls the gate driver 94 to output the scan signal Scan to each scan line 6, and controls the reference voltage output circuit 95 to provide at the high potential end and the low potential end The corresponding potential signal.
  • the process of detecting the drift of the threshold voltage of the driving thin film transistor 1 is as follows:
  • the low potential end is adjusted to the first potential, which is greater than the potential of the detection control signal Monitor.
  • Both the scan signal and the Scan and detection signal Sense provide high potentials, the switching thin film transistor 2 and the detection thin film transistor 3 are both turned on, and the detection control signal Monitor and the data signal Data respectively charge both sides of the capacitor element 4.
  • the potential at the connection between the upper electrode plate 41 of the capacitive element 4 and the micro light-emitting diode 5 is equal to the difference between the potential of the data signal Data and the threshold voltage of the thin film transistor 1.
  • the micro LED 5 Since the first potential of the low potential end is greater than the potential of the detection control signal Monitor at this time, the micro LED 5 is in the reverse bias state, which can reduce the influence of the leakage current of the micro LED 5 on the detection of the threshold voltage of the driving thin film transistor 1 At the same time, the built-in electric field of the micro light-emitting diode 5 is eliminated, and the service life is extended. Then, the scan signal Scan provides a low potential, the detection signal Sense remains high, and the detection thin film transistor 3 remains on.
  • the analog-to-digital converter 96 Analog-to-Digital Converter, ADC
  • ADC Analog-to-Digital Converter
  • the process of detecting the drift amount of the threshold voltage of the micro LED 5 is as follows:
  • the low potential end is adjusted to a second potential, which is less than the potential of the detection control signal Monitor.
  • Scan signal and Scan and detection signal Sense provide high potential, the switching thin film transistor 2 and the detection thin film transistor 3 are turned on, the detection control signal Monitor and the data signal Data respectively charge the capacitor element 4 on both sides, and the detection control The potentials of the signal Monitor and the data signal Data are equal, so as to ensure that the driving thin film transistor 1 is in an off state, so as to avoid the leakage current from affecting the detection of the threshold voltage of the micro LED 5.
  • the current flowing through the micro LED 5 is detected and transmitted to the detection chip 91, and converted into a digital signal by the analog-to-digital converter 96 in the detection chip 91, and then the current of the micro LED 5 is preset by searching -A voltage display look-up table to obtain the drift amount of the threshold voltage of the micro light-emitting diode 5.
  • the process of compensating the threshold voltage of the driving thin film transistor 1 is:
  • the detection chip 91 transmits the detected threshold voltage drift amount of the driving thin film transistor 1 to the timing controller 92, the timing controller 92 calculates the compensation voltage according to the drift amount, and then outputs the source driving signal to the source according to the compensation voltage
  • the electrode driver 93 adjusts the magnitude of the data voltage output by the source driver 93 to compensate the threshold voltage of the thin film transistor 1.
  • the timing controller 92 can also output a high reference voltage to high according to the compensation voltage through the reference voltage output circuit 95 The potential terminal and / or the low reference voltage to the low potential terminal, by adjusting the voltage of the high potential terminal and / or the low potential terminal to adjust the gate-source voltage of the driving thin film transistor 1, the threshold voltage of the driving thin film transistor 1 can also be compensated At the same time, the threshold voltage of the micro light-emitting diode 5 is compensated.
  • the drift of the threshold voltages of the driving thin-film transistor 1 and the micro light-emitting diode 5 of each sub-pixel unit 90 can be compensated, which ensures that the driving thin-film transistor 1 always works in the saturation region and avoids the first source 13 and the A voltage drop is caused between the first drain 14 and the positive and negative electrodes of the micro light-emitting diode 5 to ensure light emission and display effects.

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Abstract

一种显示面板(100)，包括衬底基层(9)以及设于衬底基层(9)上的多个子像素单元(90)，子像素单元(90)包括开关薄膜晶体管(2)、驱动薄膜晶体管(1)和侦测薄膜晶体管(3)，驱动薄膜晶体管(1)的第一源极(13)包括多个并排连接的曲形条(131)，第一漏极(14)包括多个间隔排列的直形条(141)，直形条(141)一一对应插入曲形条(131)的开口内，在曲形条(131)与直形条(141)、连接条(142)之间形成曲折的间隙，第一有源层(12)对应间隙形成导电沟道(120)。

Description

显示面板和显示装置
本申请要求于2018年11月12日提交中国专利局，申请号为201811339330.8，发明名称为“显示面板和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板和显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
微发光二极管(Micro LED)显示器是将LED结构设计进行薄膜化、微小化、阵列化后，将Micro LED批量式转移至电路基板上，集成高密度的微LED阵列作为显示像素，进行上基板的封装，完成一Micro LED显示器件。微LED的尺寸最小可以做到1～10微米。微LED显示器和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器一样属于自发光显示器，但微LED显示器相比OLED显示器还具有材料稳定性更好、寿命更长、无影像烙印等优点，相比于LCD(Liquid Crystal Display,液晶显示器)具有更高的穿透率。
相比于OLED，微发光二极管发光时需要较大电流驱动。根据使用的半导体材料的不同，TFT(Thin Film Transistor，薄膜晶体管)可以分为a-Si(Amorphous Silicon,非晶硅)、IGZO(Indium Gallium Zinc Oxide,铟镓锌氧化物)和LTPS(Low Temperature Poly-silicon,低温多晶硅)三种。a-si的电子迁移率大概只有0.5cm 2/Vs，其迁移率不足以提供较大开态电流进行电流驱动。IGZO的电子迁移率可达10～50cm 2/Vs，但是IGZO的压应力稳定性较差，故其稳定性还有待提升。LTPS的电子迁移率可达100cm 2/Vs，但是其TFT器件复杂 的结构和膜层均一性限制了其在世代面板的应用。所以若能开发出基于a-Si的TFT器件设置为驱动微发光二极管，将大大提升微发光二极管显示器的量产性。
申请内容
本申请一目的在于提供一种显示面板，包括但不限于使薄膜晶体管满足微发光二极管的驱动电流要求以及同时兼顾其稳定性和适于量产。
本申请实施例采用的技术方案是：一种显示面板，包括：
衬底基层；以及
多个子像素单元，阵列排布于所述衬底基层上；
其中，所述子像素单元包括开关薄膜晶体管、驱动薄膜晶体管、侦测薄膜晶体管和微发光二极管；
所述驱动薄膜晶体管包括第一栅极、第一有源层、第一源极和第一漏极，所述第一栅极连接至所述开关薄膜晶体管，所述第一源极连接至高电位端，所述第一漏极连接至所述微发光二极管以及所述侦测薄膜晶体管；
所述第一源极包括多个并排连接的曲形条，所述第一漏极包括多个间隔排列的直形条以及将多个所述直形条连接的连接条；所述直形条一一对应插入所述曲形条的开口内，所述第一源极与第一漏极之间形成曲折的间隙，所述第一有源层对应所述间隙的部分形成导电沟道。
本申请的另一目的在于提供一种显示面板，包括：
衬底基层；以及
多个子像素单元，阵列排布于所述衬底基层上；
其中，所述子像素单元包括开关薄膜晶体管、驱动薄膜晶体管、侦测薄膜晶体管和微发光二极管；
所述驱动薄膜晶体管包括第一栅极、第一有源层、第一源极和第一漏极，所述第一栅极连接至所述开关薄膜晶体管，所述第一源极连接至高电位端，所述第一漏极连接至所述微发光二极管以及所述侦测薄膜晶体管；
所述第一源极包括多个并排连接的曲形条，所述第一漏极包括多个间隔排列的直形条以及将多个所述直形条连接的连接条；所述直形条一一对应插入所述曲形条的开口内，所述第一源极与第一漏极之间形成曲折的间隙，所述第一有源层对应所述间隙的部分形成导电沟道；
所述导电沟道包括对应所述曲形条和直形条之间呈弯曲形的第一沟道，所述第一沟道的宽长比为2～10。
本申请的又一目的在于提供一种显示装置，包括显示面板以及设于所述显示面板的出光侧的封装层；所述显示面板包括：
衬底基层；以及
多个子像素单元，阵列排布于所述衬底基层上；
其中，所述子像素单元包括开关薄膜晶体管、驱动薄膜晶体管、侦测薄膜晶体管和微发光二极管；
所述驱动薄膜晶体管包括第一栅极、第一有源层、第一源极和第一漏极，所述第一栅极连接至所述开关薄膜晶体管，所述第一源极连接至高电位端，所述第一漏极连接至所述微发光二极管以及所述侦测薄膜晶体管；
所述第一源极包括多个并排连接的曲形条，所述第一漏极包括多个间隔排列的直形条以及将多个所述直形条连接的连接条；所述直形条一一对应插入所述曲形条的开口内，所述第一源极与第一漏极之间形成曲折的间隙，所述第一有源层对应所述间隙的部分形成导电沟道。
本申请实施例提供的显示面板，其衬底基层上设有多个子像素单元，子像素单元包括开关薄膜晶体管、驱动薄膜晶体管、侦测薄膜晶体管和微发光二极管，驱动薄膜晶体管包括第一栅极、第一源极和第一漏极，第一栅极连接至开关薄膜晶体管，第一源极连接至高电位端，第一漏极连接至微发光二极管以及侦测薄膜晶体管，第一源极包括多个并排连接的曲形条，一漏极包括多个间隔排列的直形条以及将多个直形条连接的连接条，直形条一一对应插入曲形条的开口内，第一源极与第一漏极之间形成曲折的间隙，第一有源层对应该间隙形 成导电沟道，由此，显著地提高了驱动薄膜晶体管的导电沟道的宽长比，第一源极和第一漏极之间允许更大的驱动电流通过，能够满足微发光二极管的驱动电流要求，降低了驱动薄膜晶体管的制作成本，且使用微发光二极管来形成子像素单元，还具有高的穿透率和使用寿命，从而降低能耗并提高了显示面板的使用寿命。此外，本申请的显示面板采用开关薄膜晶体管、驱动薄膜晶体管和侦测薄膜晶体管来驱动微发光二极管进行发光和显示，能够保证微发光二极管的显示效果的稳定性，具有良好的显示效果。显示面板和显示装置，能够满足微发光二极管的驱动电流要求，降低了驱动薄膜晶体管的制作成本，且使用微发光二极管来形成子像素单元，还具有高的穿透率和使用寿命，从而降低能耗并提高了显示面板的使用寿命；采用开关薄膜晶体管、驱动薄膜晶体管和侦测薄膜晶体管来驱动微发光二极管进行发光和显示，能够保证微发光二极管的显示效果的稳定性，具有良好的显示效果。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或示范性的技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是本申请实施例提供的显示面板的结构示意图；
图2是本申请实施例提供的显示面板的纵截面的示意图；
图3是本申请实施例提供的显示面板的纵截面的另一结构示意图；
图4是本申请实施例提供的显示面板中像素驱动电路的示意图；
图5是本申请实施例提供的显示面板中子像素单元的电路示意图；
图6是本申请实施例提供的显示面板中的单个马蹄结构的示意图；
图7是本申请实施例提供的显示面板中驱动薄膜晶体管的导电沟道的示意图；
图8是本申请实施例提供的显示面板中马蹄结构的一种连接示意图；
图9是本申请实施例提供的显示面板中驱动薄膜晶体管的宽长比的示意图；
图10是本申请实施例提供的显示面板中马蹄结构的另一连接示意图；
图11是本申请实施例提供的显示面板中开关薄膜晶体管的沟道示意图；
图12是本申请实施例提供的显示装置的结构示意图；
图13是本申请实施例提供的显示装置的控制电路示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以直接在另一个部件上或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本专利的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所述的技术方案，以下结合具体附图及实施例进行详细说明。
请参阅图1，本申请首先提供一种显示面板100，包括衬底基层9以及阵列排布于衬底基层9上的多个像素单元，每一像素单元包括多个不同颜色的子像素单元90。
每一子像素单元90均包括一开关薄膜晶体管2、驱动薄膜晶体管1、电容元 件4、微发光二极管5以及侦测薄膜晶体管3。开关薄膜晶体管2、驱动薄膜晶体管1、电容元件4和侦测薄膜晶体管3构成子像素单元90的像素驱动电路，用于驱动微发光二极管5发光。
对于不同颜色的子像素单元90，微发光二极管5的发光颜色不同。在一实施例中，子像素单元90分别为红色子像素单元、绿色子像素单元和蓝色子像素单元，对应地，红色子像素单元、绿色子像素单元和蓝色子像素单元分别包括红色微发光二极管、绿色微发光二极管和蓝色微发光二极管。当然，像素单元还可包括如黄色子像素单元或白色子像素单元，或者由其他多种颜色的子像素单元构成，对此不作限制。
微发光二极管5包括晶片，晶片中的半导体材料在正引脚和负引脚之间电流的作用下发光。根据半导体材料的不同，发出不同颜色的光。半导体材料为含镓(Ga)、砷(As)、磷(P)、氮(N)等的化合物，具体如，发红色光的铝砷化镓、砷化镓、砷化镓磷化物、磷化铟镓、铝磷化镓(掺杂氧化锌)，发绿色光的铝磷化镓、铟氮化镓/氮化镓、磷化镓、磷化铟镓铝、铝磷化镓，发黄色(橘红色、橙色)光的磷化铝铟、镓砷化镓、磷化铟镓铝、磷化镓、碳化硅，发蓝色光的氮化镓、硒化锌等。
在一具体实施例中，红色子像素单元包括的红色微发光二极管采用砷化镓材料；绿色子像素单元包括的绿色微二极管发采用磷化镓材料，蓝色子像素单元包括的蓝色微发光二极管采用氮化镓材料。
在一实施例中，微发光二极管5的边长尺寸在1～100微米，面积在5～800平方微米，微发光二极管5的边长最小可为1～10微米。
子像素单元90的边长尺寸在5～500微米，其面积可为10～1000平方微米。微发光二极管5在子像素单元90中占据一定面积，除去该微发光二极管5的面积，其他为像素驱动电路所占用。
根据显示面板100的规格、分辨率等可以使用相应尺寸的微发光二极管5。
如图1和图4所示，衬底基层9上还形成有多条扫描线6和多条数据线7，子 像素单元90设置于该些扫描线6和数据线7之间。
具体如图2、图3和图5所示，驱动薄膜晶体管1包括设置于衬底基层9上的第一栅极11、形成于第一栅极11上的栅极绝缘层901、形成于栅极绝缘层901上的第一有源层12以及分别连接于第一有源层12两端的第一源极13和第一漏极14。
开关薄膜晶体管2包括设置于衬底基层9上的第二栅极21、形成于第二栅极21上的栅极绝缘层901、形成于栅极绝缘层901上的第二有源层22以及分别连接于第二有源层22两端的第二源极23和第二漏极24。
侦测薄膜晶体管3包括设置于衬底基层9上的第三栅极31、形成于第三栅极31上的栅极绝缘层901、形成于栅极绝缘层901上的第三有源层32以及分别连接于第三有源层32两端的第三源极33和第三漏极34。
图5中以相同图案填充的部分表示位于同一层，被两种图案填充的部分表示电性连接或形成电容。图5中省略了第一有源层12、第二有源层22和第三有源层32。
具体地，第一栅极11、第二栅极21和第三栅极31同层设置且由一道光罩制程同时形成，第一源极13、第一漏极14、第二源极23、第二漏极24、第三源极33和第三漏极34同层设置且由一道光罩制程同时形成。第二漏极24通过贯穿栅极绝缘层901的第一过孔106与第一栅极11连接。
请参阅图4和图5，第二栅极21连接至扫描线6，第二源极23连接至数据线7，当扫描线6上的扫描信号Scan使得开关薄膜晶体管2打开时，数据线7上的数据信号Data能够传输至第二漏极24。
第一源极13连接至高电位端(图4中Vdd)，第一漏极14连接至微发光二极管5的正引脚，当数据信号Data使得驱动薄膜晶体管1打开时，来自高电位端的电流能够通过第一源极13和第一栅极11到达微发光二极管5的负引脚，并流向低电位端(图4中Vss)，从而微发光二极管5能够发光。
电容元件4的下电极板42与第二漏极24同层设置，并连接至第二漏极24与 第一栅极11之间，上电极板41连接至微发光二极管5的正引脚与第一漏极14之间，为驱动薄膜晶体管1的打开提供维持电压。
如图2和图3所示，在驱动薄膜晶体管1和开关薄膜晶体管2的上方设有一层钝化层902，电容元件4的上电极板41设于钝化层902上。
如图3所示，在钝化层902上还设有一层保护层903，以将电容元件4的上电极板41保护起来，该保护层903对应微发光二极管5设有开口定义区904，该开口定义区904内设置微发光二极管5。微发光二极管5与第一漏极14之间的连接贯穿钝化层902。或者，如图2所示，微发光二极管5设于保护层903之上，微发光二极管5与第一漏极14之间的连接同时贯穿钝化层902和保护层903。
图5中，侦测薄膜晶体管3的第三栅极31连接至侦测信号线81，侦测信号线81与扫描线6同层但间隔设置，设置为提供侦测信号Sense至第三栅极31。
第三源极33通过贯穿钝化层902或者同时贯穿钝化层902和保护层903的第二过孔107连接至微发光二极管5。
第三漏极34连接至侦测控制线82，侦测控制线82设置为向第三漏极34输入侦测控制信号Monitor，如图4和图5所示。
在本实施例中，驱动薄膜晶体管1为a-Si TFT，其第一有源层12包括一层第一本征半导体层以及形成于第一本征半导体层两侧上方的欧姆接触层(未图示)。第一本征半导体层的材料为非晶硅，欧姆接触层为掺杂n型离子的非晶硅，如掺杂氮(N)、磷(P)、砷(As)元素。
开关薄膜晶体管2和侦测薄膜晶体管3也可以为n型a-Si TFT，这样第二有源层22、第三有源层32可以和驱动薄膜晶体管1的第一有源层12在同一制程中形成，提高制作效率；也可以是其他类型的薄膜晶体管，不再赘述。
请参阅图5至图8，驱动薄膜晶体管1的第一源极13包括多个并排连接的曲形条131，每一曲形条131的开口方向朝向第一漏极14。
驱动薄膜晶体管1的第一漏极14呈头梳状，包括多个间隔排列的直形条141以及将多个直形条141连接的连接条142，直形条141一一对应插入曲形条131 的开口内(为描述方便，下文将一个曲形条131和一个直形条141称为一个马蹄结构)，从而在曲形条131与直形条141之间形成呈弯曲形的第一间隙部，在曲形条131与和连接条142之间形成直条状的第二间隙部，多个第一间隙部和多个第二间隙部依次连接，形成曲折的间隙，第二有源层22对应该曲折的间隙的部分设置为形成导电沟道120，导电沟道120包括对应第一间隙部的第一沟道121以及对应第二间隙部的第二沟道122，参见图7。
本申请的驱动薄膜晶体管1中，第一源极13与第一漏极14之间形成曲折的间隙，当在第一栅极11上施加电压，从第一源极13向第一漏极14的方向有电流流过，第一有源层12对应该间隙形成导电沟道120，沿着电流的方向上，间隙的宽度即为导电沟道120的长度L，在垂直于电流的方向上，间隙的总长度为导电沟道120的宽度W，由此，驱动薄膜晶体管1的导电沟道120的宽长比W/L能够提高，驱动薄膜晶体管1的第一源极13和第一漏极14之间允许通过更大的驱动电流，从而可以驱动微发光二极管5发光。
请参阅图6至图9，以一个马蹄结构为例具体进行说明。
曲形条131包括呈半圆弧状的半圆弧部1311，以及连接于半圆弧部1311的两端并朝向连接条142方向延伸的延伸部1312，直形条141包括连接于连接条142的矩形部1412以及设置于矩形部1412的顶端的半圆部1411。延伸部1312分别位于直形条141的两侧，半圆部1411与半圆弧部1311对应，从而在半圆部1411与半圆弧部1311之间形成宽度均一的半圆弧形沟道1211，在延伸部1312与矩形部1412之间形成宽度均一的条形沟道1212。半圆弧形沟道1211与两个条形沟道1212连接形成第一沟道121，且半圆弧形沟道1211的宽度与条形沟道1212的宽度也相等。
可选地，直形条141与连接条142之间为垂直连接，曲形条131沿着与连接条142平行的方向依次连接排列。延伸部1312垂直连接于半圆弧部1311的两端。
如图9所示，设半圆部1411的半径为a，间隙的宽度(也即沟道的长度)为L，延伸部1312朝向第一漏极14延伸的长度为c，半圆部1411的圆心至延伸部1312 靠近半圆部1411的一侧的距离为b(b＝a+L)，则在第一间隙部的范围内，一个第一沟道121的宽长比W/L(1)计算公式为：
Figure PCTCN2018121480-appb-000001
在第二间隙部的范围内而言，一个第二沟道122的宽长比大体为两个延伸部1312的宽度之和与延伸部1312至连接体142之间的距离的比值，即
Figure PCTCN2018121480-appb-000002
由于多个第一沟道121和第二沟道122均对导电沟道120的宽度做出贡献，不改变导电沟道120的长度，因此，多个第一沟道121和第二沟道122连接后，驱动薄膜晶体管1的导电沟道120的宽长比W/L为多个W/L(1)与多个W/L(2)的和，能够极大地高导电沟道120的宽长比。
在一实施例中，a为2～50微米，b为5～55微米，c为1～50微米。L的范围为3～53微米。
在一实施例中，对于一个第一沟道121而言，2≤W/L(1)≤10。
第一沟道121的数量也即第一源极13的曲形条131的数量可为多个，可选地，可为10个以上，如15以上、20个以上等，视W/L(1)以及微发光二极管5的驱动电流要求而定，对此不作限制。
在一实施例中，驱动薄膜晶体管1的导电沟道120的宽长比W/L大于或等于30。
进一步地，受限于子像素单元90的面积以及基于满足微发光二极管5的驱动电流要求，导电沟道120的宽长比W/L小于或等于200。
请参阅图10，为曲形条131的另一种连接方式，相邻两个曲形条131之间共用一个延伸部1312。由于W/L(2)<W/L(1)，这样的设计可以减少第二沟道122 的数量，从而各个驱动薄膜晶体管1中可以形成更多个第一沟道121，进一步提高驱动薄膜晶体管1的导电沟道120的宽长比W/L。
在图8和图10中，当延伸部1312和半圆弧部1311的宽度足够小时，导电沟道120主要由第一沟道121构成，第二沟道122可以忽略不计，此时，可以更简单地考虑多个第一沟道121的连接以得出导电沟道120的宽长比。
在一实施例中，请参阅图11，开关薄膜晶体管2的第二源极23和第二漏极24呈相互平行设置，开关薄膜晶体管2的沟道为条状，沟道的长度L’为第二源极23和第二漏极24之间的距离，沟道的宽度W’为垂直于电流方向上的第二有源层22的宽度。电流由第二源极23垂直地流向第二漏极24。
在一实施例中，侦测薄膜晶体管3也可以采用与驱动薄膜晶体管1相同的马蹄结构，如图5所示的1个马蹄结构，或者2个以上依次连接的马蹄结构，对此不作限制。
如图5所示，开关薄膜晶体管2、电容元件4和侦测薄膜晶体管3在一个子像素单元90中位于一侧，开关薄膜晶体管2和侦测薄膜晶体管3可以分别设于电容元件4的两侧，微发光二极管5和驱动薄膜晶体管1在一个子像素单元90中位于另一侧。在图5中，侦测控制线82与第三源极33、第三漏极34同层设置，但侦测薄膜晶体管3与侦测控制线82之间间隔了电容元件4等结构，为便于第三漏极34与侦测控制线82之间的连接，在衬底基层9上还形成了多条过渡连接线105，过渡连接线105与扫描线6平行，这样便于工艺制作。第三源极33先通过贯穿栅极绝缘层901的第三过孔108与过渡连接线105连接，然后过渡连接线105通过贯穿栅极绝缘层901的第四过孔109与侦测控制线82连接。当然，像素驱动电路也可以有其他位置排布方式，对此不作限制。
本申请还提供一种显示装置，如图12所示，包括上述所说的显示面板100，以及设于显示面板100上方的封装层300。封装层300为透明层，如玻璃层、透明塑料层等。微发光二极管5发出的光线向上经封装层300出射，形成画面予以显示。
请参阅图13，显示装置还包括控制电路，控制电路包括时序控制器92以及分别与时序控制器92连接的源极驱动器93、栅极驱动器94和参考电压输出电路95。时序控制器92控制源极驱动器93向各数据线7输出数据信号Data，控制栅极驱动器94向各扫描线6输出扫描信号Scan，以及控制参考电压输出电路95在高电位端和低电位端提供相应的电位信号。
请结合参阅图4，对驱动薄膜晶体管1的阈值电压的漂移量进行侦测的过程为：
将低电位端调整至第一电位，该第一电位为大于侦测控制信号Monitor的电位。扫描信号和Scan和侦测信号Sense均提供高电位，开关薄膜晶体管2和侦测薄膜晶体管3均打开，侦测控制信号Monitor和数据信号Data分别对电容元件4的两侧进行充电。当驱动薄膜晶体管1进入饱和模式，电容元件4的上电极板41与微发光二极管5连接处的电位等于数据信号Data的电位与驱动薄膜晶体管1的阈值电压的差值。由于此时低电位端的第一电位大于侦测控制信号Monitor的电位，微发光二极管5处于反向偏置状态，可以减少微发光二极管5的漏电流对驱动薄膜晶体管1的阈值电压侦测的影响，同时消除微发光二极管5的内建电场，延长寿命。然后，扫描信号Scan提供低电位，侦测信号Sense仍保持高电位，侦测薄膜晶体管3保持打开，此时，侦测电容元件4的上电极板41与微发光二极管5连接处的电位并传输至侦测芯片91，经侦测芯片91内的模数转换器96(Analog-to-Digital Converter,ADC)转换成数字信号储存在侦测芯片91的存储器中，从而可以得出驱动薄膜晶体管1阈值电压或其阈值电压的漂移量。
对微发光二极管5的阈值电压的漂移量进行侦测的过程为：
将低电位端调整至第二电位，该第二电位为小于侦测控制信号Monitor的电位。扫描信号和Scan和侦测信号Sense均提供高电位，开关薄膜晶体管2和侦测薄膜晶体管3均打开，侦测控制信号Monitor和数据信号Data分别对电容元件4两侧进行充电，并且侦测控制信号Monitor和数据信号Data的电位相等，从而保证驱动薄膜晶体管1为关闭状态，避免产生漏电流影响微发光二极管5的阈值 电压的侦测。然后，侦测流过微发光二极管5的电流并传输给侦测芯片91，并且通过侦测芯片91内的模数转换器96转换成数字信号，再通过查找预先设定微发光二极管5的电流-电压显示查找表，得到微发光二极管5的阈值电压的漂移量。
对驱动薄膜晶体管1的阈值电压进行补偿的过程为：
侦测芯片91将侦测到的驱动薄膜晶体管1的阈值电压漂移量传输至时序控制器92，时序控制器92根据该漂移量计算出补偿电压，然后，根据补偿电压输出源极驱动信号至源极驱动器93，以调整源极驱动器93输出的数据电压的大小，补偿驱动薄膜晶体管1的阈值电压。
对微发光二极管5的阈值电压进行补偿时，以及当补偿电压超出源极驱动器93允许输出的数据电压范围时，时序控制器92根据补偿电压还可以通过参考电压输出电路95来输出高参考电压至高电位端和/或低参考电压至低电位端，通过调整高电位端和/或低电位端的电压来调整驱动薄膜晶体管1的栅源极电压，也可以实现补偿驱动薄膜晶体管1的阈值电压，并同时实现补偿微发光二极管5的阈值电压。
本实施例中，每一子像素单元90的驱动薄膜晶体管1和微发光二极管5的阈值电压的漂移均能够补偿，保证了驱动薄膜晶体管1始终工作于饱和区，避免在第一源极13和第一漏极14之间以及微发光二极管5的正负极之间造成压降，保证发光和显示效果。
以上仅为本申请的可选实施例而已，并不设置为限制本申请。对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (20)

  1. 一种显示面板，包括：
    衬底基层；以及
    多个子像素单元，阵列排布于所述衬底基层上；
    其中，所述子像素单元包括开关薄膜晶体管、驱动薄膜晶体管、侦测薄膜晶体管和微发光二极管；
    所述驱动薄膜晶体管包括第一栅极、第一有源层、第一源极和第一漏极，所述第一栅极连接至所述开关薄膜晶体管，所述第一源极连接至高电位端，所述第一漏极连接至所述微发光二极管以及所述侦测薄膜晶体管；
    所述第一源极包括多个并排连接的曲形条，所述第一漏极包括多个间隔排列的直形条以及将多个所述直形条连接的连接条；所述直形条一一对应插入所述曲形条的开口内，所述第一源极与第一漏极之间形成曲折的间隙，所述第一有源层对应所述间隙的部分形成导电沟道。
  2. 如权利要求1所述的显示面板，其中，所述第一有源层包括第一本征半导体层以及形成于所述第一本征半导体层两侧上方的欧姆接触层；所述本征半导体层的材料为非晶硅，所述欧姆接触层的材料为掺杂n型元素的非晶硅。
  3. 如权利要求1所述的显示面板，其中，所述曲形条包括呈半圆弧状的半圆弧部以及连接于所述半圆弧部两端的延伸部。
  4. 如权利要求3所述的显示面板，其中，相邻两个所述曲形条之间共用一个所述延伸部。
  5. 如权利要求3所述的显示面板，其中，所述延伸部朝向所述第一漏极延伸的长度为1～50微米。
  6. 如权利要求1所述的显示面板，其中，所述直形条包括连接于所述连接条的矩形部以及设置于所述矩形部的顶端的半圆部。
  7. 如权利要求6所述的显示面板，其中，所述半圆部的半径为2～50微米，所述导电沟道的长度为3～53微米。
  8. 如权利要求1所述的显示面板，其中，所述导电沟道的宽长比大于或等于30。
  9. 如权利要求8所述的显示面板，其中，所述导电沟道的宽长比小于或等于200。
  10. 如权利要求1所述的显示面板，其中，所述子像素单元的边长为5～500微米，所述微发光二极管的边长为1～10微米。
  11. 如权利要求1所述的显示面板，其中，所述侦测薄膜晶体管包括第三栅极、第三源极和第三漏极，所述第三栅极设置为连接侦测扫描线以接收侦测信号，所述第三源极连接至所述第一漏极与所述微发光二极管之间，所述第三漏极设置为连接侦测控制线以接收侦测控制信号。
  12. 如权利要求11所述的显示面板，其中，所述开关薄膜晶体管包括第二栅极、第二有源层、第二源极和第二漏极；所述第二漏极连接至所述第一栅极。
  13. 如权利要求12所述的显示面板，其中，所述显示面板还包括设于所述衬底基层上的多条扫描线和多条数据线；所述第二栅极连接至所述扫描线，所述第二源极连接至所述数据线。
  14. 如权利要求12所述的显示面板，其中，所述第一栅极、第二栅极和第三栅极同层设置，所述第一源极、第一漏极、第二源极、第二漏极、第三源极和第三漏极同层设置。
  15. 如权利要求12所述的显示面板，其中，所述第一有源层、第二有源层和第三有源层的材料相同。
  16. 如权利要求1所述的显示面板，其中，所述开关薄膜晶体管、驱动薄膜晶体管、侦测薄膜晶体管的上方还设有钝化层，所述微发光二极管与所述第一漏极的连接贯穿所述钝化层。
  17. 一种显示面板，包括：
    衬底基层；以及
    多个子像素单元，阵列排布于所述衬底基层上；
    其中，所述子像素单元包括开关薄膜晶体管、驱动薄膜晶体管、侦测薄膜晶体管和微发光二极管；
    所述驱动薄膜晶体管包括第一栅极、第一有源层、第一源极和第一漏极，所述第一栅极连接至所述开关薄膜晶体管，所述第一源极连接至高电位端，所述第一漏极连接至所述微发光二极管以及所述侦测薄膜晶体管；
    所述第一源极包括多个并排连接的曲形条，所述第一漏极包括多个间隔排列的直形条以及将多个所述直形条连接的连接条；所述直形条一一对应插入所述曲形条的开口内，所述第一源极与第一漏极之间形成曲折的间隙，所述第一有源层对应所述间隙的部分形成导电沟道；
    所述导电沟道包括对应所述曲形条和直形条之间呈弯曲形的第一沟道，所述第一沟道的宽长比为2～10。
  18. 如权利要求17所述的显示面板，其中，所述导电沟道还包括对应于所述曲形条和连接条之间呈直条状的第二沟道，多个所述第一沟道和第二沟道依次连接。
  19. 一种显示装置，包括显示面板以及设于所述显示面板的出光侧的封装层；所述显示面板包括：
    衬底基层；以及
    多个子像素单元，阵列排布于所述衬底基层上；
    其中，所述子像素单元包括开关薄膜晶体管、驱动薄膜晶体管、侦测薄膜晶体管和微发光二极管；
    所述驱动薄膜晶体管包括第一栅极、第一有源层、第一源极和第一漏极，所述第一栅极连接至所述开关薄膜晶体管，所述第一源极连接至高电位端，所述第一漏极连接至所述微发光二极管以及所述侦测薄膜晶体管；
    所述第一源极包括多个并排连接的曲形条，所述第一漏极包括多个间隔排列的直形条以及将多个所述直形条连接的连接条；所述直形条一一对应插入所述曲形条的开口内，所述第一源极与第一漏极之间形成曲折的间隙，所述第一有源层对应所述间隙的部分形成导电沟道。
  20. 如权利要求19所述的显示装置，其中，还包括控制电路，所述控制电路包括时序控制器、源极驱动器和侦测芯片；
    所述侦测芯片向所述侦测薄膜晶体管提供侦测控制信号，设置为侦测所述驱动薄膜晶体管的阈值电压，所述时序控制器根据所述侦测芯片侦测的驱动薄膜晶体管的阈值电压控制所述源极驱动器调整输出的数据电压的大小，以补偿所述驱动薄膜晶体管的阈值电压。
PCT/CN2018/121480 2018-11-12 2018-12-17 显示面板和显示装置 WO2020098048A1 (zh)

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