WO2024114113A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2024114113A1
WO2024114113A1 PCT/CN2023/123771 CN2023123771W WO2024114113A1 WO 2024114113 A1 WO2024114113 A1 WO 2024114113A1 CN 2023123771 W CN2023123771 W CN 2023123771W WO 2024114113 A1 WO2024114113 A1 WO 2024114113A1
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WO
WIPO (PCT)
Prior art keywords
sub
microns
marking pattern
area
display panel
Prior art date
Application number
PCT/CN2023/123771
Other languages
English (en)
French (fr)
Inventor
王欣欣
周洋
屈忆
刘松
初志文
何磊
白露
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Publication of WO2024114113A1 publication Critical patent/WO2024114113A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display panel and a display device.
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • PDP plasma display panel
  • FED Field Emission Display
  • an embodiment of the present disclosure provides a display panel, comprising a display area and a border area located around the display area, wherein the display area comprises a plurality of data lines and a plurality of sub-pixels, and the plurality of data lines and the plurality of sub-pixels are electrically connected; the border area comprises a crack detection line and a plurality of detection control units, wherein the crack detection line is electrically connected to at least one of the plurality of data lines through the plurality of detection control units, and the crack detection line comprises at least one marking pattern, and the at least one marking pattern is configured as an alignment mark used in the process.
  • the crack detection line includes a plurality of winding segments, the plurality of winding segments include a second winding segment and a first winding segment arranged at intervals in a direction away from the display area, and the first winding segment includes the at least one marking pattern.
  • the border area includes a first border area surrounding the display area and a second border area located on a side of the first border area away from the display area, the first border area includes a first sub-border area located between the display area and the second border area and a second sub-border area located on the other side of the display area, the crack detection line is located in the first sub-border area and the second sub-border area, the marking graphic includes a first sub-marking graphic and a second sub-marking graphic, the first sub-marking graphic is located in the second sub-border area, and the second sub-marking graphic is located in the first sub-border area.
  • the first winding segment of the crack detection line of the second sub-border area includes a first sub-winding segment extending along a second direction, the first sub-winding segment is bent and provided with a first sub-marking pattern, the first sub-marking pattern extends along a first direction away from the display area, and the first direction intersects with the second direction.
  • the first sub-mark pattern is configured as a trapezoidal protrusion
  • the trapezoidal protrusion includes two waist edges and a bottom edge extending along the second direction, the two waist edges are respectively connected to two ends of the bottom edge.
  • the length of the bottom edge is 200 micrometers to 300 micrometers, and the distance between the bottom edge and the second winding segment is 10 micrometers to 30 micrometers.
  • a plurality of the first sub-mark patterns are arranged at intervals along the second direction to form a first sub-mark pattern group, and the first sub-mark patterns in the first sub-mark pattern group are connected in sequence.
  • a distance between a bottom edge of a first sub-mark pattern in the first sub-mark pattern group located on one side in the second direction and a bottom edge of a first sub-mark pattern in the first sub-mark pattern group located on the other side in the second direction is 200 microns to 300 microns.
  • the angle formed by the waist edge and a direction perpendicular to the bottom edge is 30 degrees to 60 degrees.
  • the crack detection line of the first sub-border area includes a third sub-winding segment extending along a first direction, the third sub-winding segment includes a second sub-marking pattern, the second sub-marking pattern is arranged along a second direction away from the display area, and the first direction intersects with the second direction.
  • the second sub-mark pattern is configured as a boss-shaped protrusion, and the boss-shaped protrusion
  • the length of the protrusion in the first direction is 70 microns to 90 microns, and the length of the boss-shaped protrusion in the second direction is 60 microns to 80 microns; or, the second sub-mark pattern is set as a step-shaped protrusion, the length of the step-shaped protrusion in the first direction is 60 microns to 80 microns, and the length of the step-shaped protrusion in the second direction is 60 microns to 80 microns; or, the second sub-mark pattern is set as a triangular protrusion, the length of the triangular protrusion in the first direction is 60 microns to 90 microns, and the length of the triangular protrusion in the second direction is 60 microns to 80 microns; or, the second sub-mark pattern is set as a diamond protrusion, the length of the diamond protrusion in the first direction is 60 microns
  • the length of the protrusion in the second direction is 60 microns to 80 microns; or, the length of the diamond protrusion in the first direction is 30 microns to 60 microns, and the length of the diamond protrusion in the second direction is 60 microns to 80 microns; or, the second sub-mark pattern is set as a hexagonal protrusion, the length of the hexagonal protrusion in the first direction is 120 microns to 130 microns, and the length of the hexagonal protrusion in the second direction is 40 microns to 60 microns; or, the second sub-mark pattern includes a first part and a second part connected to each other, the first part is located on the side of the second part close to the display area, the first part and the second part are both set as triangles, and the corner of the first part is connected to the corner of the second part.
  • the frame area includes a plurality of crack detection lines, the plurality of crack detection lines are symmetrically arranged about a center line of the display area, and the marking pattern is symmetrically arranged about the center line of the display area.
  • the marking pattern and the crack detection line are located in different film layers, and the marking pattern is connected to the crack detection line through a via hole.
  • the border area also includes a gate drive circuit, a power signal line and an isolation dam, and the gate drive circuit, the power signal line and the isolation dam are arranged in sequence in a direction away from the display area, and the crack detection line is located between the power signal line and the isolation dam.
  • an embodiment of the present disclosure provides a display device, comprising any of the display panels described above.
  • FIG1 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG2 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.
  • FIG3 is a first schematic diagram of wiring of a display panel according to an embodiment of the present disclosure.
  • FIG4a is a first schematic diagram of a first sub-marking pattern in a display panel according to an embodiment of the present disclosure
  • FIG4 b is a second schematic diagram of a first sub-marking pattern in a display panel according to an embodiment of the present disclosure
  • FIG4c is a third schematic diagram of a first sub-marking pattern in a display panel according to an embodiment of the present disclosure.
  • FIG5a is a first schematic diagram of a second sub-marking pattern in a display panel according to an embodiment of the present disclosure
  • FIG5 b is a second schematic diagram of a second sub-marking pattern in a display panel according to an embodiment of the present disclosure
  • FIG5c is a third schematic diagram of a second sub-marking pattern in a display panel according to an embodiment of the present disclosure.
  • FIG5d is a fourth schematic diagram of a second sub-marking pattern in a display panel according to an embodiment of the present disclosure.
  • FIG5e is a fifth schematic diagram of a second sub-marking pattern in a display panel according to an embodiment of the present disclosure.
  • FIG5f is a sixth schematic diagram of a second sub-marking pattern in a display panel according to an embodiment of the present disclosure.
  • FIG6 is a second wiring diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of wiring of a display panel in the related art.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • electrical connection includes the case where components are connected together through an element having some electrical function.
  • element having some electrical function There is no particular limitation on the "element having some electrical function” as long as it can transmit electrical signals between connected components. Examples of “element having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.
  • a transistor refers to an element including at least three terminals: a gate, a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source.
  • a channel region refers to a region where current mainly flows.
  • one electrode is called the first electrode and the other electrode is called the second electrode.
  • the first electrode can be the source or the drain
  • the second electrode can be The drain or source
  • the gate of the transistor is called the control electrode.
  • parallel means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.
  • triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.
  • each process stage will have its own process detection function to prevent defective products in this process stage from being missed and flowing into the next process stage, resulting in waste of materials and resource costs. Therefore, during the manufacturing process of the display panel, it is required to perform effective and rapid detection on each process stage as much as possible, so as to effectively control production costs and improve the yield of the display panel.
  • FIG7 is a schematic diagram of the wiring of a display panel of the related art.
  • the display panel of the related art may include: a display area 10 and a frame area located around the display area 10.
  • the frame area may include: a first frame area 21 surrounding the display area 10 and a second frame area 22 located on one side of the display area 10.
  • the first frame area 21 may include a crack detection line 31 and a marking graphic 60', the marking graphic 60' is located on the side of the crack detection line 31 away from the display area 10, and is arranged at intervals with the crack detection line 31 in a direction away from the display area 10. Since both the crack detection line 31 and the marking graphic 60' will occupy a part of the space of the frame area, the requirement of a narrow frame cannot be met.
  • the present embodiment provides a display panel, comprising a display area and a frame area located around the display area, wherein the display area comprises a plurality of data lines and a plurality of sub-pixels, wherein the plurality of data lines and the plurality of sub-pixels are electrically connected; the frame area comprises a crack detection line and a plurality of detection control units, wherein the crack detection line is connected to at least one of the plurality of data lines through the plurality of detection control units.
  • a data line is electrically connected, and the crack detection line includes at least one mark pattern, and the at least one mark pattern is configured as an alignment mark in the process.
  • the crack detection line of the display panel provided in this embodiment can receive a detection signal.
  • crack detection of the frame area can be achieved to determine whether the display panel is qualified. In this way, fast and effective crack detection can be achieved, the quality of the display panel can be improved, and production costs can be reduced.
  • the display panel of the embodiment of the present disclosure sets a marking pattern on the crack detection line to achieve an identification effect through the marking pattern, thereby saving space in the border area. For example, 50 to 100 um of space can be saved to achieve a narrow border effect.
  • FIG1 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel may include: a display area 10 and a frame area located around the display area 10.
  • the frame area may include: a first frame area 21 surrounding the display area 10 and a second frame area 22 located on a side of the first frame area 21 away from the display area 10.
  • the second frame area 22 may be located on a side of the first frame area 21 away from the display area 10.
  • a portion of the first frame area 21 may be located between the display area 10 and the second frame area 22.
  • the display area 10 may be a flat area including a plurality of sub-pixels Px constituting a pixel array, the plurality of sub-pixels Px may be configured to display a dynamic image or a still image, and the display area 10 may be referred to as an active area (AA).
  • the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as curling, bending, folding, or rolling up.
  • the display area 10 may be a rectangle. However, this embodiment is not limited to this.
  • the display area 10 may be a circle, an ellipse or other shapes.
  • the second frame area 22 may include a bending area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area 10.
  • the fan-out area is connected to the first frame area 21, and at least includes a data fan-out line, and a plurality of data fan-out lines are configured to connect the data signal lines of the display area 10 in a fan-out routing manner.
  • the bending area is connected to the fan-out area, and may include a composite insulating layer provided with a groove, which is configured to bend the driver chip area and the binding pin area to the back of the display area 10.
  • the driver chip area may be provided with a corresponding integrated circuit (IC, Integrated Circuit), for example, a display driver integrated circuit (DDI, Display Driver Integration) or It can be a touch and display driver integrated circuit (TDDI, Touch and Display Driver Integration).
  • IC integrated circuit
  • the integrated circuit can be configured to be connected to multiple data fan-out lines.
  • the binding pin area can include multiple binding pins, and the multiple binding pins can be configured to be bound and connected to an external flexible printed circuit (FPC, Flexible Printed Circuit), so that multiple signal leads (for example, drive control lines, power signal lines, etc.) are connected to an external control device through multiple binding pins.
  • FPC Flexible Printed Circuit
  • the display area 10 may include: a substrate, a display structure layer and an encapsulation structure layer disposed on the substrate.
  • the display structure layer may include a plurality of display units (i.e., sub-pixels), a plurality of gate lines and a plurality of data lines.
  • the plurality of data lines may extend along a first direction D1, and the plurality of gate lines may extend along a second direction D2.
  • the positive projections of the plurality of gate lines and the plurality of data lines on the substrate may intersect to form a plurality of sub-pixel regions.
  • a sub-pixel is disposed in a sub-pixel region.
  • the plurality of data lines are electrically connected to the plurality of sub-pixels, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels.
  • the plurality of gate lines are electrically connected to the plurality of sub-pixels, and the plurality of gate lines are configured to provide gate drive signals to the plurality of sub-pixels.
  • the first direction D1 intersects with the second direction D2, for example, the first direction D1 may be perpendicular to the second direction D2.
  • three sub-pixels in the display area can form a pixel unit, and the three sub-pixels are red sub-pixels, green sub-pixels, and blue sub-pixels.
  • the three sub-pixels can be arranged horizontally, vertically, or in a triangle.
  • this embodiment is not limited to this.
  • four sub-pixels can form a pixel unit, and the four sub-pixels are red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels.
  • the four sub-pixels can be arranged horizontally, vertically, or in a square.
  • At least one sub-pixel may include a pixel circuit and a light-emitting element.
  • the pixel circuit may be configured to drive the connected light-emitting element.
  • the pixel circuit may include multiple transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • T in the above circuit structure refers to a thin film transistor
  • C refers to a capacitor
  • the number before T represents the number of thin film transistors in the circuit
  • the number before C represents the number of capacitors in the circuit.
  • the multiple transistors in the pixel circuit may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In other examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.
  • multiple transistors in the pixel circuit can be made of low-temperature polysilicon thin-film crystals. Tubes, or oxide thin film transistors can be used, or low-temperature polysilicon thin film transistors and oxide thin film transistors can be used.
  • the active layer of the low-temperature polysilicon thin film transistor uses low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor uses oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • oxide thin film transistor uses oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display panel that is, LTPS+Oxide (LTPO for short) display panel, can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.
  • LTPS+Oxide LTPO for short
  • the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc.
  • the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element may be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • the display panel may also integrate a touch structure.
  • the display area of the display panel may also include: a touch structure layer located on the side of the packaging structure layer away from the substrate.
  • the touch structure layer may be arranged on the packaging structure layer of the display panel to form a touch structure on thin film packaging (Touch on Thin Film Encapsulation, referred to as Touch on TFE) structure.
  • Touch on TFE thin film packaging
  • the Touch on TFE structure mainly includes a flexible multi-layer covering surface type (Flexible Multi-Layer On Cell, referred to as FMLOC) structure and a flexible single-layer covering surface type (Flexible Single-Layer On Cell, referred to as FSLOC) structure.
  • FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode.
  • the integrated circuit (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode.
  • the FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode.
  • the integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.
  • the touch structure layer may include a plurality of touch units. At least one touch unit may include at least one touch electrode.
  • the orthographic projection of at least one touch electrode on the substrate may include Orthographic projections of multiple sub-pixels on the substrate.
  • the touch unit includes multiple touch electrodes, the multiple touch electrodes can be arranged at intervals, and adjacent touch electrodes can be connected to each other through a connecting portion.
  • the touch electrode and the connecting portion can be a same-layer structure.
  • the touch electrode can have a rhombus shape, for example, a regular rhombus, a horizontally long rhombus, or a vertically long rhombus. However, this embodiment is not limited to this.
  • the touch electrode can have any one or more of a triangle, a square, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons.
  • the touch electrodes in the display panel may be in the form of a metal grid
  • the metal grid is formed by interweaving a plurality of metal wires
  • the metal grid includes a plurality of grid patterns
  • the grid pattern is a polygon surrounded by a plurality of metal wires
  • the touch electrodes in the form of a metal grid have the advantages of low resistance, small thickness, and fast response speed, etc.
  • this embodiment is not limited to this.
  • FIG2 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.
  • FIG2 may be a partial cross-sectional schematic diagram along the R-R' direction in FIG1.
  • the display area 10 may include: a substrate 41, a driving circuit layer 42, a light-emitting element 43, a packaging structure layer 44, and a touch structure layer 45, which are sequentially arranged on the substrate 41.
  • FIG2 only takes the structure of one sub-pixel as an example for illustration.
  • the substrate 41 may be a flexible substrate.
  • the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked.
  • the materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET) or a surface-treated polymer soft film
  • the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate
  • the material of the semiconductor layer may be amorphous silicon (a-si).
  • this embodiment is not limited to this.
  • the driving circuit layer 42 may include a plurality of transistors forming a pixel circuit and at least one storage capacitor.
  • FIG. 2 illustrates a first transistor 401 and a first storage capacitor 402 as an example.
  • the driving circuit layer 42 of the display area 10 may include: a semiconductor layer disposed on a substrate 41, a first insulating layer 51 covering the semiconductor layer, a first gate metal layer disposed on the first insulating layer 51, a second insulating layer 52 covering the first gate metal layer, a second gate metal layer disposed on the second insulating layer 52, a third insulating layer 53 covering the second gate metal layer, and a first source-drain metal layer disposed on the third insulating layer 53.
  • the semiconductor layer may include at least a first active layer, a first gate
  • the metal layer may include at least a first gate electrode and a first capacitor electrode
  • the second gate metal layer may include at least a second capacitor electrode
  • the first source-drain metal layer may include at least a first source electrode and a first drain electrode.
  • the first active layer, the first gate electrode, the first source electrode, and the first drain electrode may constitute a first transistor 401
  • the first capacitor electrode and the second capacitor electrode may constitute a first storage capacitor 402.
  • the driving circuit layer may further include a sixth insulating layer and a second source-drain metal layer located on a side of the first source-drain metal layer away from the substrate.
  • this embodiment is not limited to this.
  • the light emitting element 43 may include a first electrode 431, a pixel definition layer 434, an organic light emitting layer 432, and a second electrode 433.
  • the first electrode 431 is disposed on the fifth insulating layer 55, and is connected to the first drain electrode of the first transistor 401 through vias provided on the fourth insulating layer 54 and the fifth insulating layer 55.
  • the pixel definition layer 434 may be disposed on the first electrode 431 and the fifth insulating layer 55, and a pixel opening may be provided on the pixel definition layer 434, and the pixel opening may expose a portion of the surface of the first electrode 431.
  • the organic light emitting layer 432 is at least partially disposed in the pixel opening, and the organic light emitting layer 432 is connected to the first electrode 431.
  • the second electrode 433 is disposed on the organic light emitting layer 432, and the second electrode 433 is connected to the organic light emitting layer 432.
  • the organic light-emitting layer 432 of the light-emitting element 43 may include a light-emitting layer (EML, Emitting Layer), and one or more film layers including a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole blocking layer (HBL, Hole Block Layer), an electron blocking layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer).
  • HIL hole injection layer
  • HTL Hole Transport Layer
  • HBL Hole Block Layer
  • EBL Electron Block Layer
  • EIL Electron Injection Layer
  • ETL Electron Transport Layer
  • the light-emitting layers of light-emitting elements of different colors are different.
  • a red light-emitting element includes a red light-emitting layer
  • a green light-emitting element includes a green light-emitting layer
  • a blue light-emitting element includes a blue light-emitting layer.
  • the hole injection layer and the hole transport layer on one side of the light-emitting layer can use a common layer
  • the electron injection layer and the electron transport layer on the other side of the light-emitting layer can use a common layer.
  • any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation can be achieved by means of a surface step difference of the formed film layer or by surface treatment.
  • any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be made by a single evaporation process or a single inkjet printing process.
  • One or more layers may be isolated.
  • the organic light emitting layer may be formed by evaporation using a fine metal mask (FMM) or an open mask, or may be formed by an inkjet process.
  • FMM fine metal mask
  • the encapsulation structure layer 44 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials
  • the second encapsulation layer may be made of organic materials
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting element 43.
  • this embodiment is not limited to this.
  • the encapsulation layer may adopt a five-layer stacked structure of inorganic/organic/inorganic/organic/inorganic.
  • the touch structure layer 45 may include: a first touch insulating layer 451 disposed on a side of the encapsulation structure layer 44 away from the substrate 41, a touch electrode layer 452 disposed on a side of the first touch insulating layer 451 away from the substrate 41, and a touch protection layer 455 disposed on a side of the touch electrode layer 452 away from the substrate 41.
  • the touch structure layer of this example is illustrated by taking the FSLOC structure as an example. However, this embodiment is not limited to this.
  • Fig. 3 is a schematic diagram of wiring of a display panel according to an embodiment of the present disclosure.
  • Fig. 3 takes several data lines in the display area and several crack detection lines in the frame area as examples, and omits other wiring lines.
  • the display area 10 may include: a plurality of data lines 11. Each data line 11 may extend along the second direction D2, and the plurality of data lines 11 may be arranged at intervals along the first direction D1. Each data line 11 may be electrically connected to a plurality of display units Px arranged along the second direction D2, and configured to provide data signals to the plurality of display units Px. For example, the data line 11 may be configured to be electrically connected to a display unit emitting light of the same color, such as the data line 11 may be configured to be electrically connected to a plurality of display units emitting green light. However, this embodiment is not limited to this.
  • the first direction D1 intersects the second direction D2, for example, the first direction D1 may be perpendicular to the second direction D2.
  • the frame area may include: a plurality of detection control units 35 and a detection control line 34.
  • the plurality of detection control units may be located in the first frame area 21.
  • the plurality of detection control units may be arranged at intervals along the first direction D1, and the plurality of detection control units may be located between the display area 10 and the second frame area 22.
  • the detection control line 34 may be located in the first frame area 21 and between the display area 10 and the second frame area 22.
  • the detection control line 34 is electrically connected to the detection control unit 35.
  • this embodiment is not limited to this.
  • the plurality of detection control units may be arranged at intervals along the first direction D1, and the plurality of detection control units may be located between the display area 10 and the second frame area 22.
  • the unit may be located in the second border area.
  • one crack detection line 31 may be electrically connected to one detection control unit 35 , and one detection control unit 35 may be electrically connected to at least one data line 11 .
  • One crack detection line 31 may be electrically connected to at least one data line 11 through one detection control unit 35 .
  • the crack detection line 31 may be a serpentine line.
  • a serpentine line is a meandering curve. For example, after one end of the line extends a distance in one direction, it bends and twists and extends a distance in the opposite direction of the direction, bends and twists again and extends in the direction, and bends and twists repeatedly several times to form a serpentine line.
  • the crack detection line 31 may be wound along the direction in which the first frame area 21 is away from the display area 10.
  • the second frame region 22 may include a first signal pin 51 and a second signal pin 52.
  • the first end of the crack detection line 31 may be electrically connected to the detection control unit 35, and the second end of the crack detection line 31 may be connected to the first signal pin 51 on the second frame region 22.
  • the first signal pin 51 may be used as a test pin. For example, by providing a test signal through the first signal pin 51, crack detection may be performed on the crack detection line.
  • the detection control unit 35 may include: a detection transistor.
  • the gate of the detection transistor may be electrically connected to the detection control line 34
  • the first electrode of the detection transistor may be electrically connected to the first end of the crack detection line
  • the second electrode of the detection transistor may be electrically connected to the data line 11 of the display area 10.
  • One end of the detection control line 34 may be electrically connected to the second signal pin 52 of the second frame area 22.
  • the detection control line 34 may provide a detection control signal through the second signal pin 52, and is configured to turn on or off multiple detection control units.
  • the detection control signal provided by the detection control line 34 can turn on the detection transistor, thereby turning on the detection control unit 35.
  • the crack detection line 31 can receive a test signal through the first signal pin 51, and the test signal is transmitted to the display unit of the display area 10 through the data line 11 of the display area 10.
  • the test signal drives the display unit to display, and whether the display unit displays is determined to determine whether the crack detection line 31 connected thereto is broken.
  • the crack detection line 31 may include a plurality of winding segments, the plurality of winding segments are arranged at intervals in a direction away from the display area 10, and the winding segment 311 located on the side away from the display area 10 among the plurality of winding segments includes a marking pattern 60, and the marking pattern 60 extends in a direction away from the display area 10.
  • at least one marking pattern 60 is configured as an alignment mark in the process, and the marking pattern 60 is a marking pattern.
  • the marking pattern 60 can be used for precision detection and identification of alignment in each process section (such as cutting, bonding, second frame area bending, etc.).
  • the crack detection line 31 may include a second winding segment 312, a first winding segment 311, and a connecting segment 313 that connects the second winding segment 312 and the end of the first winding segment 311, which are arranged at intervals in a direction away from the display area 100.
  • the connecting segment 313 may be in an arc shape.
  • the first winding segment 311 is located on a side of the second winding segment 312 away from the display area 100, and the first winding segment 311 includes at least one marking pattern 60.
  • the marking pattern 60 is clearly distinguished from other routing lines in the border area in shape, which is easy to identify.
  • the marking pattern 60 can be set to a shape formed by a triangle, rectangle, trapezoid, rhombus, polygon or a combination of polygons.
  • the display panel of the embodiment of the present disclosure sets a marking pattern on the crack detection line to achieve an identification effect through the marking pattern, thereby saving space in the border area. For example, 50 to 100 um of space can be saved to achieve a narrow border effect.
  • the first frame area 21 may include a first sub-frame area 211 located between the display area 10 and the second frame area 22 and a second sub-frame area 212 located on the other side of the display area 10.
  • the display area 10 is rectangular
  • the first frame area 21 may be a rectangular ring
  • the first frame area 21 includes a first sub-frame area 211 and three second sub-frame areas 212
  • the first sub-frame area 211 is located between the display area 10 and the second frame area 22, and the three second sub-frame areas 212 are located on the other side of the display area 10.
  • the first sub-frame area 211 and the three second sub-frame areas 212 form a rectangular ring-shaped first frame area 21.
  • the crack detection line 31 may be located in the first sub-frame area 211 and the second sub-frame area 212.
  • the marking pattern 60 includes a first sub-marking pattern 61 and a second sub-marking pattern 62, wherein the first sub-marking pattern 61 is located in the second sub-frame area 212, and the second sub-marking pattern 62 is located in the first sub-frame area 211.
  • the first sub-marking pattern 61 is used for precision detection after cutting the display panel
  • the second sub-marking pattern 62 is used for precision detection after cutting the display panel and alignment of the binding process of the second frame area 22.
  • FIG4a is a schematic diagram of a first sub-marking pattern in a display panel according to an embodiment of the present disclosure.
  • the first winding segment 311 of the crack detection line 31 of the second sub-frame area 212 may include a first sub-winding segment 3111 extending along the second direction D2
  • the second sub-frame area 212 may include a first sub-winding segment 3111 extending along the second direction D2.
  • the second winding segment 312 of the crack detection line 31 may include a second sub-winding segment 3112 extending along the second direction D2, the first sub-winding segment 3111 and the second sub-winding segment 3112 are arranged alternately along the first direction D1, and the first sub-winding segment 3111 is located on the side of the second sub-winding segment 3112 away from the display area 10.
  • the first sub-winding segment 3111 includes at least one first sub-marking pattern 61, the first sub-marking pattern 61 extends along the first direction D1 away from the display area 10, and the first sub-marking pattern 61 is set as a trapezoidal protrusion.
  • the trapezoidal protrusion includes two waist edges 612 and a bottom edge 611 extending along the second direction D2, the two waist edges 612 respectively connect the two ends of the bottom edge 611 with the first sub-winding segment 3111, and the two waist edges 612 form an obtuse angle with the bottom edge 611.
  • the first sub-mark pattern may also be a protrusion in other shapes, such as a triangle, a diamond, a rectangle, a hexagon, or a step.
  • the length a of the bottom edge 611 in the second direction D2 is 200 microns to 300 microns, for example, the length a of the bottom edge 611 in the second direction D2 is 220 microns to 260 microns.
  • the spacing b between the bottom edge 611 and the second sub-winding segment 3112 is 10 microns to 30 microns, for example, the spacing b between the bottom edge 611 and the second sub-winding segment 3112 is 15 microns to 20 microns.
  • FIG. 4b is a second schematic diagram of a first sub-marking pattern in a display panel according to an embodiment of the present disclosure
  • FIG. 4c is a third schematic diagram of a first sub-marking pattern in a display panel according to an embodiment of the present disclosure.
  • a plurality of first sub-marking patterns 61 are arranged at intervals along the second direction D2 to form a first sub-marking pattern group, and each first sub-marking pattern 61 in the first sub-marking pattern group is connected in sequence.
  • three first sub-marking patterns 61 are arranged at intervals along the second direction D2 to form a first sub-marking pattern group, and the three first sub-marking patterns 61 are connected in sequence, and the three first sub-marking patterns 61 are all trapezoidal protrusions, as shown in FIG. 4b.
  • two first sub-marking patterns 61 are arranged at intervals along the second direction D2 to form a first sub-marking pattern group, and the two first sub-marking patterns 61 are connected in sequence, and the two first sub-marking patterns 61 are all trapezoidal protrusions, as shown in FIG. 4c.
  • a distance L between a bottom edge of the first sub-mark pattern 61 on one side of the first sub-mark pattern group in the second direction D2 and a bottom edge of the first sub-mark pattern 61 on the other side of the first sub-mark pattern group in the second direction D2 is 200 ⁇ m to 300 ⁇ m.
  • three first sub-mark patterns 61 are arranged at intervals along the second direction D2 to form a first sub-mark pattern group, and the length a of the bottom edge 611 in each first sub-mark pattern 61 in the second direction D2 is 80 microns, and the spacing c between adjacent first sub-mark patterns 61 is 10 micrometers, and a distance L between a bottom edge of the first sub-mark pattern 61 on one side of the first sub-mark pattern group in the second direction D2 and a bottom edge of the first sub-mark pattern 61 on the other side of the first sub-mark pattern group in the second direction D2 is 260 micrometers.
  • two first sub-marking patterns 61 are arranged at intervals along the second direction D2 to form a first sub-marking pattern group, the length a of the bottom edge 611 in each first sub-marking pattern 61 in the second direction D2 is 120 microns, the spacing c between adjacent first sub-marking patterns 61 is 10 microns, and the distance L between the bottom edge of one first sub-marking pattern 61 to the bottom edge of another first sub-marking pattern 61 is 260 microns.
  • the angle d formed by the waist edge 612 of the first sub-marking graphic 61 and the first direction D1 perpendicular to the bottom edge 611 is 30 degrees to 60 degrees.
  • the angle d formed by the waist edge 612 of the first sub-marking graphic 61 and the first direction D1 perpendicular to the bottom edge 611 is 45 degrees to 55 degrees.
  • FIG5a is a schematic diagram of a second sub-marking pattern in a display panel according to an embodiment of the present disclosure.
  • the crack detection line 31 of the first sub-frame region 211 may include two third sub-winding segments 312c and a fourth sub-winding segment 312d extending along the first direction D1, the third sub-winding segment 312c and the fourth sub-winding segment 312d are arranged at intervals along the second direction D2, and the third sub-winding segment 312c is located on the side of the fourth sub-winding segment 312d away from the display region 10.
  • the third sub-winding segment 312c may be connected to the first sub-winding segment 3111, and the fourth sub-winding segment 312d may be connected to the first winding segment 311.
  • the third sub-winding segment 312c is bent and provided with a second sub-marking pattern 62, the second sub-marking pattern 62 extends along the first direction D1 away from the display region 10, and the second sub-marking pattern 62 is provided as a boss-shaped protrusion.
  • the length e of the platform-shaped protrusion in the first direction D1 is 50 micrometers to 100 micrometers, for example, the length e of the platform-shaped protrusion in the first direction D1 is 70 micrometers to 90 micrometers.
  • the length f of the platform-shaped protrusion in the second direction D2 is 40 micrometers to 100 micrometers, for example, the length f of the platform-shaped protrusion in the second direction D2 is 60 micrometers to 80 micrometers.
  • the length e in the first direction D1 is the distance between the edge of the second sub-mark pattern 62 on one side in the first direction D1 and the edge of the second sub-mark pattern 62 on the other side in the first direction D1; the length f in the second direction D2 is the distance between the edge of the second sub-mark pattern 62 on one side in the second direction D2 and the edge of the second sub-mark pattern 62 on the other side in the second direction D2.
  • FIG5b is a second schematic diagram of a second sub-mark pattern in a display panel according to an embodiment of the present disclosure.
  • the second sub-mark pattern 62 is configured as a stepped protrusion.
  • the length e of the first direction D1 is 40 to 100 microns, for example, the length e of the step-shaped protrusion in the first direction D1 is 60 to 80 microns.
  • the length f of the step-shaped protrusion in the second direction D2 is 40 to 100 microns, for example, the length f of the step-shaped protrusion in the second direction D2 is 60 to 80 microns.
  • FIG5c is a third schematic diagram of a second sub-marking pattern in a display panel according to an embodiment of the present disclosure.
  • the second sub-marking pattern 62 is set as a triangular protrusion.
  • the corners of the triangular protrusion are rounded.
  • the length e of the triangular protrusion in the first direction D1 is 40 microns to 100 microns, for example, the length e of the triangular protrusion in the first direction D1 is 60 microns to 90 microns.
  • the length f of the triangular protrusion in the second direction D2 is 40 microns to 100 microns, for example, the length f of the triangular protrusion in the second direction D2 is 60 microns to 80 microns.
  • FIG5d is a fourth schematic diagram of a second sub-mark pattern in a display panel according to an embodiment of the present disclosure.
  • the second sub-mark pattern 62 is configured as a diamond-shaped protrusion.
  • the length e of the diamond-shaped protrusion in the first direction D1 is 60 microns to 80 microns
  • the length f of the diamond-shaped protrusion in the second direction D2 is 60 microns to 80 microns.
  • the length e of the diamond-shaped protrusion in the first direction D1 is 30 microns to 60 microns
  • the length f of the diamond-shaped protrusion in the second direction D2 is 60 microns to 80 microns.
  • FIG5e is a fifth schematic diagram of a second sub-mark pattern in a display panel according to an embodiment of the present disclosure.
  • the second sub-mark pattern 62 is set as a hexagonal protrusion.
  • the length e of the hexagonal protrusion in the first direction D1 is 100 microns to 150 microns, for example, the length e of the hexagonal protrusion in the first direction D1 is 120 microns to 130 microns.
  • the length f of the hexagonal protrusion in the second direction D2 is 20 microns to 80 microns. For example, the length f of the hexagonal protrusion in the second direction D2 is 40 microns to 60 microns.
  • FIG5f is a sixth schematic diagram of a second sub-mark pattern in a display panel according to an embodiment of the present disclosure.
  • the second sub-mark pattern 62 includes a first portion 71 and a second portion 72 connected to each other, the first portion 71 is located on a side of the second portion 72 close to the display area 10, the first portion 71 and the second portion 72 are both triangular, and the corner of the first portion 71 is connected to the corner of the second portion 72.
  • the length e of the second sub-mark pattern 62 in the first direction D1 is 10 microns to 60 microns, for example, the length e of the second sub-mark pattern 62 in the first direction D1 is 30 microns to 50 microns.
  • the length f of the second sub-mark pattern 62 in the second direction D2 is 20 microns to 80 microns. For example, the length f of the second sub-mark pattern 62 in the second direction D2 is 40 microns to 60 microns.
  • the marking pattern on the crack detection line can be set in the same layer as the crack detection line (such as the winding segment and the connecting segment) and formed as one piece.
  • the winding segment, the connecting segment and the marking pattern of the crack detection line are all set in the same layer as the second gate metal layer of the driving circuit layer in the display area.
  • the marking pattern on the crack detection line can be located in a different film layer from the crack detection line (eg, the winding segment and the connecting segment).
  • the marking pattern can be connected to the winding segment of the crack detection line through a via, thereby increasing the recognition of the marking pattern.
  • FIG6 is a second wiring diagram of the display panel of the embodiment of the present disclosure.
  • the first sub-frame area 212 also includes a gate drive circuit (GOA circuit) 71, a power signal line 72 and an isolation dam 73, and the gate drive circuit (GOA circuit) 71, the power signal line 72 and the isolation dam 73 are all arranged around the periphery of the display area 10, and the gate drive circuit (GOA circuit) 71, the power signal line 72 and the isolation dam 73 are arranged in sequence in a direction away from the display area 10, and the crack detection line 31 is located between the power signal line 72 and the isolation dam 73, and the marking pattern 60 of the crack detection line 31 is located between the power signal line 72 and the isolation dam 73, and the marking pattern 60 extends in a direction close to the isolation dam 73, and a gap is set between the isolation dam 73.
  • GOA circuit gate drive circuit
  • the power signal line 72 and the isolation dam 73 are all arranged around the periphery of the display area 10
  • the frame area may include a plurality of crack detection lines 31, the plurality of crack detection lines 31 are substantially symmetrical with the center line A of the display area in the second direction D2 as an axis, and the marking pattern 60 is substantially symmetrical with the center line A of the display area in the second direction D2 as an axis.
  • the first frame area 21 may include two crack detection lines 31, and the two crack detection lines 31 may be substantially symmetrical about the center line A of the display panel along the second direction D2.
  • One crack detection line 31 may be located in the left half of the first frame area 21, and one crack detection line 31 may be located in the right half of the first frame area 21; the marking patterns 60 on the two crack detection lines 31 are substantially symmetrical with the center line A of the display area in the second direction D2 as an axis, the marking pattern 60 on one crack detection line 31 may be located in the left half of the first frame area 21, and the marking pattern 60 on one crack detection line 31 may be located in the right half of the first frame area 21.
  • the embodiment of the present invention further provides a display device, including any of the display panels described above.
  • the display device includes a mobile phone, a tablet computer, a smart wearable product (such as a smart watch, a bracelet, etc.), a personal digital assistant (PDA), a car computer, etc.
  • PDA personal digital assistant
  • the embodiment of the present application does not impose any special restrictions on the specific form of the above display device.

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Abstract

提供一种显示面板和显示装置，显示面板包括显示区域(10)以及位于显示区域(10)周边的边框区域，显示区域(10)包括多条数据线(11) 和多个子像素(PX)，多条数据线(11)和多个子像素(PX)电连接；边框区域包括裂纹检测线(31)和多个检测控制单元(35)，裂纹检测线(31)通过多个检测控制单元(35)与多条数据线(11)中的至少一条数据线(11)电连接，裂纹检测线(31)包括至少一个标记图形(60)，至少一个标记图形(60)被配置为用于工艺中的对位标记。

Description

显示面板和显示装置
本申请要求于2022年11月29日提交中国专利局、申请号为202211511955.4、发明名称为“显示面板和显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，具体涉及一种显示面板和显示装置。
背景技术
随着显示技术的不断发展，显示产品的种类越来越多，例如，液晶显示器(LCD，Liquid Crystal Di splay)、有机发光二极管(OLED，Organic Light-Emitting Diode)显示器、等离子体显示面板(PDP，Plasma Display Panel)、场发射显示器(FED，Field Emission Display)等。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供了一种显示面板，包括显示区域以及位于所述显示区域周边的边框区域，所述显示区域包括多条数据线和多个子像素，所述多条数据线和所述多个子像素电连接；所述边框区域包括裂纹检测线和多个检测控制单元，所述裂纹检测线通过所述多个检测控制单元与所述多条数据线中的至少一条数据线电连接，所述裂纹检测线包括至少一个标记图形，所述至少一个标记图形被配置为用于工艺中的对位标记。
在一些示例中，所述裂纹检测线包括多条绕线段，所述多条绕线段包括沿着远离所述显示区域的方向间隔排布的第二绕线段和第一绕线段，所述第一绕线段包括所述至少一个标记图形。
在一些示例中，所述边框区域包括围绕所述显示区域的第一边框区域以及位于所述第一边框区域远离所述显示区域一侧的第二边框区域，所述第一边框区域包括位于所述显示区域和所述第二边框区域之间的第一子边框区域以及位于所述显示区域其他侧的第二子边框区域，所述裂纹检测线位于所述第一子边框区域和所述第二子边框区域，所述标记图形包括第一子标记图形和第二子标记图形，所述第一子标记图形位于所述第二子边框区域，所述第二子标记图形位于所述第一子边框区域。
在一些示例中，所述第二子边框区域的裂纹检测线的第一绕线段包括沿着第二方向延伸的第一子绕线段，所述第一子绕线段弯曲设置有第一子标记图形，所述第一子标记图形沿着远离所述显示区域的第一方向延伸，所述第一方向与所述第二方向交叉。
在一些示例中，所述第一子标记图形设置为梯形凸起，所述梯形凸起包括两个腰边以及沿着所述第二方向延伸的底边，所述两个腰边分别与所述底边的两端连接。
在一些示例中，所述底边的长度为200微米至300微米，所述底边与所述第二绕线段之间的间距为10微米至30微米。
在一些示例中，多个所述第一子标记图形沿着所述第二方向间隔排布形成第一子标记图形组，所述第一子标记图形组中的第一子标记图形依次连接。
在一些示例中，所述第一子标记图形组中位于所述第二方向上一侧的第一子标记图形的底边边缘至所述第一子标记图形组中位于所述第二方向上另一侧的第一子标记图形的底边边缘之间的距离为200微米至300微米。
在一些示例中，所述腰边与垂直于所述底边的方向形成的夹角为30度至60度。
在一些示例中，所述第一子边框区域的裂纹检测线包括沿着第一方向延伸的第三子绕线段，所述第三子绕线段包括第二子标记图形，所述第二子标记图形沿着远离所述显示区域的第二方向设置，所述第一方向与所述第二方向交叉。
在一些示例中，所述第二子标记图形设置为凸台状凸起，所述凸台状凸 起在所述第一方向的长度为70微米至90微米，所述凸台状凸起在所述第二方向的长度为60微米至80微米；或者，所述第二子标记图形设置为台阶状凸起，所述台阶状凸起在所述第一方向的长度为60微米至80微米，所述台阶状凸起在所述第二方向的长度为60微米至80微米；或者，所述第二子标记图形设置为三角形凸起，所述三角形凸起在所述第一方向的长度为60微米至90微米，所述三角形凸起在所述第二方向的长度为60微米至80微米；或者，所述第二子标记图形设置为菱形凸起，所述菱形凸起在所述第一方向的长度为60微米至80微米，所述菱形凸起在所述第二方向的长度为60微米至80微米；或者，所述菱形凸起在所述第一方向的长度为30微米至60微米，所述菱形凸起在所述第二方向的长度为60微米至80微米；或者，所述第二子标记图形设置为六边形凸起，所述六边形凸起在所述第一方向的长度为120微米至130微米，所述六边形凸起在所述第二方向的长度为40微米至60微米；或者，所述第二子标记图形包括互相连接的第一部分和第二部分，所述第一部分位于所述第二部分靠近所述显示区域一侧，所述第一部分和所述第二部分均设置为三角形，所述第一部分的角部与所述第二部分的角部连接。
在一些示例中，所述边框区域包括多条裂纹检测线，所述多条裂纹检测线以所述显示区域的中心线为轴对称设置，且所述标记图形以所述显示区域的中心线为轴对称设置。
在一些示例中，所述标记图形与所述裂纹检测线位于不同膜层，所述标记图形通过过孔与所述裂纹检测线连接。
在一些示例中，所述边框区域还包括栅极驱动电路、电源信号线和隔离坝，所述栅极驱动电路、电源信号线和隔离坝沿着远离所述显示区域的方向依次间隔排布，所述裂纹检测线位于所述电源信号线与所述隔离坝之间。
第二方面，本公开实施例提供了一种显示装置，包括前面任一所述的显示面板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为本公开实施例显示面板的示意图；
图2为本公开实施例显示面板的剖视图；
图3为本公开实施例显示面板的走线示意图一；
图4a为本公开实施例显示面板中第一子标记图形的示意图一；
图4b为本公开实施例显示面板中第一子标记图形的示意图二；
图4c为本公开实施例显示面板中第一子标记图形的示意图三；
图5a为本公开实施例显示面板中第二子标记图形的示意图一；
图5b为本公开实施例显示面板中第二子标记图形的示意图二；
图5c为本公开实施例显示面板中第二子标记图形的示意图三；
图5d为本公开实施例显示面板中第二子标记图形的示意图四；
图5e为本公开实施例显示面板中第二子标记图形的示意图五；
图5f为本公开实施例显示面板中第二子标记图形的示意图六；
图6为本公开实施例显示面板的走线示意图二；
图7为相关技术显示面板的走线示意图。
具体实施方式
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、 层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，为区分晶体管除栅极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极或者漏极，第二极可以为 漏极或源极，另外，将晶体管的栅极称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本说明书中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本说明书中，“大致相同”是指数值相差10％以内的情况。
在一些实现方式中，在显示面板的制备过程中，每个工艺阶段都会有自身工艺的检测功能，以防止本工艺阶段的次品漏检流入下一个工艺阶段，造成材料和资材成本的浪费。因此，在显示面板的制备过程中要求尽可能对每个工艺阶段进行有效快速的检测，以此来有效控制生产成本，提高显示面板的良率。
图7为相关技术显示面板的走线示意图。如图7所示，相关技术显示面板可以包括：显示区域10以及位于显示区域10周边的边框区域。边框区域可以包括：围绕显示区域10的第一边框区域21以及位于显示区域10一侧的第二边框区域22。第一边框区域21可以包括裂纹检测线31以及标记图形60’，标记图形60’位于裂纹检测线31远离显示区域10一侧，且与裂纹检测线31沿着远离显示区域10方向间隔排布。由于裂纹检测线31和标记图形60’均会占据边框区域的一部分空间，导致无法满足窄边框的要求。
本实施例提供一种显示面板，包括显示区域以及位于所述显示区域周边的边框区域，所述显示区域包括多条数据线和多个子像素，所述多条数据线和所述多个子像素电连接；所述边框区域包括裂纹检测线和多个检测控制单元，所述裂纹检测线通过所述多个检测控制单元与所述多条数据线中的至少 一条数据线电连接，所述裂纹检测线包括至少一个标记图形，所述至少一个标记图形被配置为用于工艺中的对位标记。
本实施例提供的显示面板的裂纹检测线可以接收检测信号，通过利用检测信号对裂纹检测线进行裂纹检测，实现对边框区域的裂纹进行检测，以确定显示面板是否合格，如此一来，可以实现快速有效的裂纹检测，可以提升显示面板的品质，并降低生产成本。
本公开实施例显示面板通过在裂纹检测线上设置标记图形，通过标记图形实现识别的效果，从而节省边框区域的空间，例如，可以节省50～100um的空间，实现窄边框的效果。
下面通过一些示例对本实施例的方案进行举例说明。
图1为本公开实施例显示面板的示意图。在一些示例中，如图1所示，显示面板可以包括：显示区域10以及位于显示区域10周边的边框区域。边框区域可以包括：围绕显示区域10的第一边框区域21以及位于第一边框区域21远离显示区域10一侧的第二边框区域22。第二边框区域22可以位于第一边框区域21远离显示区域10的一侧。在第二方向D2上，第一边框区域21的部分区域可以位于显示区域10和第二边框区域22之间。
在一些示例中，显示区域10可以是平坦的区域，包括组成像素阵列的多个子像素Px，多个子像素Px可以被配置为显示动态图片或静止图像，显示区域10可以称为有效区域(AA)。在一些示例中，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在一些示例中，如图1所示，显示区域10可以为矩形。然而，本实施例对此并不限定。例如，显示区域10可以为圆形、或者椭圆形等其它形状。
在一些示例性实施例中，第二边框区域22可以包括沿着远离显示区域10的方向依次设置的弯折区、驱动芯片区和绑定引脚区。扇出区连接到第一边框区域21，至少包括数据扇出线，多条数据扇出线被配置为以扇出走线方式连接显示区域10的数据信号线。弯折区连接到扇出区，可以包括设置有凹槽的复合绝缘层，被配置为使驱动芯片区和绑定引脚区弯折到显示区域10的背面。驱动芯片区可以设置相应的集成电路(IC，Integrated Circuit)，例如可以为显示驱动器集成电路(DDI，Display Driver Integration)或者 可以为触控与显示驱动器集成电路(TDDI，Touch and Display Driver Integration)。集成电路可以被配置为与多条数据扇出线连接。绑定引脚区可以包括多个绑定引脚，多个绑定引脚可以被配置为与外部的柔性线路板(FPC，Flexible Printed Circuit)绑定连接，使得多条信号引线(例如，驱动控制线、电源信号线等)通过多个绑定引脚与外部控制装置连接。
在一些示例中，显示区域10可以包括：衬底、设置在衬底上的显示结构层和封装结构层。显示结构层可以包括多个显示单元(即子像素)、多条栅线以及多条数据线。多条数据线可以沿第一方向D1延伸，多条栅线可以沿第二方向D2延伸。多条栅线和多条数据线在衬底上的正投影可以交叉形成多个子像素区域。一个子像素设置在一个子像素区域内。多条数据线与多个子像素电连接，多条数据线配置为向多个子像素提供数据信号。多条栅线与多个子像素电连接，多条栅线配置为向多个子像素提供栅极驱动信号。其中，第一方向D1与第二方向D2交叉，例如第一方向D1可以垂直于第二方向D2。
在一些示例中，显示区域的三个子像素可以形成一个像素单元，三个子像素分别为红色子像素、绿色子像素和蓝色子像素。三个子像素可以采用水平并列、竖直并列或品字方式排列。然而，本实施例对此并不限定。在另一些示例中，四个子像素可以形成一个像素单元，四个子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素。四个子像素可以采用水平并列、竖直并列或正方形方式排列。
在一些示例中，至少一个子像素可以包括像素电路和发光元件。像素电路可以配置为驱动所连接的发光元件。例如，像素电路可以包括多个晶体管和至少一个电容。例如，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。在一些示例中，像素电路中的多个晶体管可以是P型晶体管，或者可以是N型晶体管。像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在另一些示例中，像素电路中的多个晶体管可以包括P型晶体管和N型晶体管。
在一些示例中，像素电路中的多个晶体管可以采用低温多晶硅薄膜晶体 管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(LTPS，Low Temperature Poly-Silicon)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示面板上，即LTPS+Oxide(简称LTPO)显示面板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diodes)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在其对应的像素电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
在一些示例中，显示面板还可以集成触控结构。显示面板的显示区域还可以包括：位于封装结构层远离衬底一侧的触控结构层。触控结构层可以设置在显示面板的封装结构层上，形成触控结构在薄膜封装上(Touch on Thin Film Encapsulation，简称Touch on TFE)的结构，显示结构和触控结构集成在一起，具有轻薄、可折叠等优点，可以满足柔性折叠、窄边框等产品需求。Touch on TFE结构主要包括柔性多层覆盖表面式(Flexible Multi-Layer On Cell，简称FMLOC)结构和柔性单层覆盖表面式(Flexible Single-Layer On Cell，简称FSLOC)结构。FMLOC结构是基于互容检测的工作原理，一般采用两层金属形成驱动(Tx)电极和感应(Rx)电极，集成电路(IC)通过检测驱动电极和感应电极间的互容来实现触控动作。FSLOC结构是基于自容(或电压)检测的工作原理，一般采用单层金属形成触控电极，集成电路通过检测触控电极自容(或电压)来实现触控动作。
在一些示例中，触控结构层可以包括多个触控单元。至少一个触控单元可以包括至少一个触控电极。至少一个触控电极在衬底上的正投影可以包含 多个子像素在衬底上的正投影。当触控单元包括多个触控电极，多个触控电极可以间隔设置，且相邻的触控电极之间可以通过连接部彼此连接。触控电极和连接部可以为同层结构。在一些示例中，触控电极可以具有菱形状，例如可以是正菱形，或者是横长的菱形，或者是纵长的菱形。然而，本实施例对此并不限定。在一些示例中，触控电极可以具有三角形、正方形、梯形、平行四边形、五边形、六边形和其它多边形中的任意一种或多种。
在一些示例中，显示面板中的触控电极可以是金属网格形式，金属网格由多条金属线交织形成，金属网格包括多个网格图案，网格图案是由多条金属线围成的多边形，金属网格形式的触控电极具有电阻小、厚度小和反应速度快等优点。然而，本实施例对此并不限定。
图2为本公开实施例显示面板的剖视图。其中，图2可以为图1中沿R-R’方向的局部剖面示意图。在一些示例中，如图1和图2所示，在垂直于显示面板的方向上，显示区域10可以包括：衬底41、依次设置在衬底41上的驱动电路层42、发光元件43、封装结构层44以及触控结构层45。图2中仅以一个子像素的结构为例进行示意。
在一些示例中，衬底41可以是柔性基底。柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。其中，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高衬底基板的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。然而，本实施例对此并不限定。
在一些示例中，如图2所示，驱动电路层42可以包括形成像素电路的多个晶体管和至少一个存储电容。图2中以一个第一晶体管401和一个第一存储电容402为例进行示意。显示区域10的驱动电路层42可以包括：设置在衬底41上的半导体层、覆盖半导体层的第一绝缘层51、设置在第一绝缘层51上的第一栅金属层、覆盖第一栅金属层的第二绝缘层52、设置在第二绝缘层52上的第二栅金属层、覆盖第二栅金属层的第三绝缘层53、设置在第三绝缘层53上的第一源漏金属层。半导体层可以至少包括第一有源层，第一栅 金属层可以至少包括第一栅电极和第一电容电极，第二栅金属层可以至少包括第二电容电极，第一源漏金属层可以至少包括第一源电极和第一漏电极。第一有源层、第一栅电极、第一源电极和第一漏电极可以组成第一晶体管401，第一电容电极和第二电容电极可以组成第一存储电容402。在另一些示例中，驱动电路层还可以包括位于第一源漏金属层远离衬底一侧的第六绝缘层和第二源漏金属层。然而，本实施例对此并不限定。
在一些示例中，如图2所示，发光元件43可以包括第一电极431、像素定义层434、有机发光层432和第二电极433。第一电极431设置在第五绝缘层55上，通过第四绝缘层54和第五绝缘层55上开设的过孔与第一晶体管401的第一漏电极连接。像素定义层434可以设置在第一电极431和第五绝缘层55上，像素定义层434上可以设置有像素开口，像素开口可以暴露出第一电极431的部分表面。有机发光层432至少部分设置在像素开口内，有机发光层432与第一电极431连接。第二电极433设置在有机发光层432上，第二电极433与有机发光层432连接。
在一些示例中，如图2所示，发光元件43的有机发光层432可以包括发光层(EML，Emitting Layer)，以及包括空穴注入层(HIL，Hole Injection Layer)、空穴传输层(HTL，Hole Transport Layer)、空穴阻挡层(HBL，Hole Block Layer)、电子阻挡层(EBL，Electron Block Layer)、电子注入层(EIL，Electron Injection Layer)、电子传输层(ETL，Electron Transport Layer)中的一个或多个膜层。在第一电极431和第二电极433的电压驱动下，利用有机材料的发光特性根据需要的灰度发光。在一些示例中，不同颜色的发光元件的发光层不同。例如，红色发光元件包括红色发光层，绿色发光元件包括绿色发光层，蓝色发光元件包括蓝色发光层。为了降低工艺难度和提升良率，位于发光层一侧的空穴注入层和空穴传输层可以采用共通层，位于发光层另一侧的电子注入层和电子传输层可以采用共通层。在一些示例中，空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以通过一次工艺(一次蒸镀工艺或一次喷墨打印工艺)制作，并通过形成的膜层表面段差或者通过表面处理等手段实现隔离。例如，相邻子像素对应的空穴注入层、空穴传输层、电子注入层和电子传输层中的任意 一层或多层可以是隔离的。在一些示例中，有机发光层可以通过采用精细金属掩模版(FMM，Fine Metal Mask)或者开放式掩膜版(Open Mask)蒸镀制备形成，或者采用喷墨工艺制备形成。
在一些示例中，如图2所示，封装结构层44可以包括叠设的第一封装层、第二封装层和第三封装层。其中，第一封装层和第三封装层可采用无机材料，第二封装层可采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光元件43。然而，本实施例对此并不限定。例如，封装层可以采用无机/有机/无机/有机/无机的五层叠设结构。
在一些示例中，如图2所示，触控结构层45可以包括：设置在封装结构层44远离衬底41一侧的第一触控绝缘层451、设置在第一触控绝缘层451远离衬底41一侧的触控电极层452以及设置在触控电极层452远离衬底41一侧的触控保护层455。本示例的触控结构层以FSLOC结构为例进行示意。然而，本实施例对此并不限定。
图3为本公开实施例显示面板的走线示意图一。图3中以显示区域的若干条数据线和边框区域的若干条裂纹检测线为例进行示意，省略示意了其他走线。
在一些示例中，如图3所示，显示区域10可以包括：多条数据线11。每条数据线11可以沿第二方向D2延伸，多条数据线11可以沿第一方向D1间隔排布。每条数据线11可以与沿第二方向D2排布的多个显示单元Px电连接，配置为给多个显示单元Px提供数据信号。例如，数据线11可以配置为与出射相同颜色光的显示单元电连接，比如数据线11可以配置为与出射绿光的多个显示单元电连接。然而，本实施例对此并不限定。其中，第一方向D1与第二方向D2交叉，例如第一方向D1可以垂直于第二方向D2。
在一些示例中，如图3所示，边框区域可以包括：多个检测控制单元35以及检测控制线34。多个检测控制单元可以位于第一边框区域21，例如，多个检测控制单元可以沿着第一方向D1间隔排布，多个检测控制单元位于显示区域10与第二边框区域22之间。检测控制线34可以位于第一边框区域21，并位于显示区域10与第二边框区域22之间，检测控制线34与检测控制单元35电连接。然而，本实施例对此并不限定。在另一些示例中，多个检测控制 单元可以位于第二边框区域。
在一些示例中，如图3所示，一条裂纹检测线31可以与一个检测控制单元35电连接，一个检测控制单元35可以与至少一条数据线11电连接。一条裂纹检测线31可以通过一个检测控制单元35与至少一条数据线11电连接。
在一些示例中，如图3所示，裂纹检测线31可以为蛇形走线。蛇形走线是一种弯折曲线。例如，走线一端沿一个方向延伸一段距离后，弯折迂回并向与该方向的相反方向延伸一段距离，再次弯折迂回而向该方向延伸，如此反复弯折迂回若干次，形成蛇形走线。在本示例中，裂纹检测线31可以沿着第一边框区域21远离显示区域10的方向进行绕线。
在一些示例中，如图3所示，第二边框区域22可以包括第一信号引脚51和第二信号引脚52。裂纹检测线31的第一端可以与检测控制单元35电连接，裂纹检测线31的第二端可以与第二边框区域22上的第一信号引脚51连接。第一信号引脚51可以作为测试引脚。例如，通过第一信号引脚51提供测试信号，可以对裂纹检测线进行裂纹检测。
在一些示例中，如图3所示，检测控制单元35可以包括：检测晶体管。检测晶体管的栅极可以与检测控制线34电连接，检测晶体管的第一极可以与裂纹检测线的第一端电连接，检测晶体管的第二极可以与显示区域10的数据线11电连接。检测控制线34的一端可以与第二边框区域22的第二信号引脚52电连接，在本示例中，检测控制线34可以通过第二信号引脚52提供检测控制信号，配置为导通或断开多个检测控制单元。
在裂纹检测过程中，检测控制线34提供的检测控制信号可以使得检测晶体管导通，从而使得检测控制单元35导通。裂纹检测线31可以通过第一信号引脚51接收测试信号，测试信号通过显示区域10的数据线11传递至显示区域10的显示单元，测试信号驱动显示单元进行显示，通过显示单元是否显示来判断与其连接的裂纹检测线31是否断裂。
在一些示例中，如图3所示，裂纹检测线31可以包括多条绕线段，多条绕线段沿着远离显示区域10的方向间隔排布，多条绕线段中位于远离显示区域10一侧的绕线段311包括标记图形60，标记图形60沿着远离显示区域10方向延伸。其中，至少一个标记图形60被配置为用于工艺中的对位标记，标 记图形60可以用于各工艺段(例如切割、贴合、第二边框区域弯折等工艺段)的精度检测和识别对位。
在一些示例中，如图3所示，裂纹检测线31可以包括沿着远离显示区域100的方向间隔排布的第二绕线段312、第一绕线段311以及将第二绕线段312和第一绕线段311的端部连接的连接段313。连接段313的形状可以为弧形。第一绕线段311位于第二绕线段312远离显示区域100一侧，第一绕线段311包括至少一个标记图形60。
标记图形60与边框区域中的其他走线在形状上有明显区分，便于识别。例如，标记图形60可以设置为三角形、矩形、梯形、菱形、多边形或多边形组合形成的形状。
本公开实施例显示面板通过在裂纹检测线上设置标记图形，通过标记图形实现识别的效果，从而节省边框区域的空间，例如，可以节省50～100um的空间，实现窄边框的效果。
在一些示例中，如图3所示，第一边框区域21可以包括位于显示区域10和第二边框区域22之间的第一子边框区域211以及位于显示区域10其他侧的第二子边框区域212。例如，显示区域10为矩形，第一边框区域21可以为矩形环状，第一边框区域21包括一个第一子边框区域211以及三个第二子边框区域212，第一子边框区域211位于显示区域10和第二边框区域22之间，三个第二子边框区域212位于显示区域10的其他侧。第一子边框区域211和三个第二子边框区域212围成矩形环状的第一边框区域21。
在一些示例中，如图3所示，裂纹检测线31可以位于第一子边框区域211和第二子边框区域212。标记图形60包括第一子标记图形61和第二子标记图形62，第一子标记图形61位于第二子边框区域212，第二子标记图形62位于第一子边框区域211。其中，第一子标记图形61用于切割显示面板后的精度检测，第二子标记图形62用于切割显示面板后的精度检测以及第二边框区域22绑定工艺的对位。
图4a为本公开实施例显示面板中第一子标记图形的示意图一。在一些示例中，如图4a所示，第二子边框区域212的裂纹检测线31的第一绕线段311可以包括沿着第二方向D2延伸的第一子绕线段3111，第二子边框区域212 的裂纹检测线31的第二绕线段312可以包括沿着第二方向D2延伸的第二子绕线段3112，第一子绕线段3111和第二子绕线段3112沿着第一方向D1间隔排布，第一子绕线段3111位于第二子绕线段3112远离显示区域10一侧。第一子绕线段3111包括至少一个第一子标记图形61，第一子标记图形61沿着远离显示区域10的第一方向D1延伸，第一子标记图形61设置为梯形凸起。梯形凸起包括两个腰边612以及一个沿着第二方向D2延伸的底边611，两个腰边612分别将底边611的两端与第一子绕线段3111连接，且两个腰边612分别与底边611形成钝角。
在一些实施例中，第一子标记图形也可以采用其他形状的凸起，例如，三角形、菱形、矩形、六边形以及台阶状。
在一些示例中，如图4a所示，底边611在第二方向D2的长度a为200微米至300微米，例如，底边611在第二方向D2的长度a为220微米至260微米。底边611与第二子绕线段3112之间的间距b为10微米至30微米，例如，底边611与第二子绕线段3112之间的间距b为15微米至20微米。
图4b为本公开实施例显示面板中第一子标记图形的示意图二；图4c为本公开实施例显示面板中第一子标记图形的示意图三。在一些示例中，多个第一子标记图形61沿着第二方向D2间隔排布形成第一子标记图形组，第一子标记图形组中的各第一子标记图形61依次连接。例如，三个第一子标记图形61沿着第二方向D2间隔排布形成一个第一子标记图形组，三个第一子标记图形61依次连接，且三个第一子标记图形61均为梯形凸起，如图4b所示。或者，两个第一子标记图形61沿着第二方向D2间隔排布形成一个第一子标记图形组，两个第一子标记图形61依次连接，且两个第一子标记图形61均为梯形凸起，如图4c所示。
在一些示例中，第一子标记图形组中位于第二方向D2上一侧的第一子标记图形61的底边边缘至第一子标记图形组中位于第二方向D2上另一侧的第一子标记图形61的底边边缘之间的距离L为200微米至300微米。
示例的，如图4b所示，三个第一子标记图形61沿着第二方向D2间隔排布形成一个第一子标记图形组，每个第一子标记图形61中的底边611在第二方向D2的长度a均为80微米，相邻第一子标记图形61之间的间距c为10 微米，第一子标记图形组中位于第二方向D2上一侧的第一子标记图形61的底边边缘至第一子标记图形组中位于第二方向D2上另一侧的第一子标记图形61的底边边缘之间的距离L为260微米。
示例的，如图4c所示，两个第一子标记图形61沿着第二方向D2间隔排布形成一个第一子标记图形组，每个第一子标记图形61中的底边611在第二方向D2的长度a均为120微米，相邻第一子标记图形61之间的间距c为10微米，一个第一子标记图形61的底边边缘至另一个第一子标记图形61的底边边缘之间的距离L为260微米。
在一些示例中，如图4b和图4c所示，第一子标记图形61的腰边612与垂直于底边611的第一方向D1形成的夹角d为30度至60度，示例的，第一子标记图形61的腰边612与垂直于底边611的第一方向D1形成的夹角d为45度至55度。
图5a为本公开实施例显示面板中第二子标记图形的示意图一。在一些示例中，如图5a所示，第一子边框区域211的裂纹检测线31可以包括两条沿着第一方向D1延伸的第三子绕线段312c和第四子绕线段312d，第三子绕线段312c和第四子绕线段312d沿着第二方向D2间隔排布，第三子绕线段312c位于第四子绕线段312d远离显示区域10一侧。第三子绕线段312c可以与第一子绕线段3111连接，第四子绕线段312d可以与第一绕线段311连接。第三子绕线段312c弯曲设置有第二子标记图形62，第二子标记图形62沿着远离显示区域10的第一方向D1延伸，第二子标记图形62设置为凸台状凸起。凸台状凸起在第一方向D1的长度e为50微米至100微米，例如，凸台状凸起在第一方向D1的长度e为70微米至90微米。凸台状凸起在第二方向D2的长度f为40微米至100微米，例如，凸台状凸起在第二方向D2的长度f为60微米至80微米。其中，第一方向D1的长度e为第二子标记图形62在第一方向D1一侧边缘至第二子标记图形62在第一方向D1另一侧边缘之间的距离；在第二方向D2的长度f为第二子标记图形62在第二方向D2一侧的边缘至第二子标记图形62在第二方向D2另一侧的边缘之间的距离。
图5b为本公开实施例显示面板中第二子标记图形的示意图二。在一些示例中，如图5b所示，第二子标记图形62设置为台阶状凸起。台阶状凸起在 第一方向D1的长度e为40微米至100微米，例如，台阶状凸起在第一方向D1的长度e为60微米至80微米。台阶状凸起在第二方向D2的长度f为40微米至100微米，例如，台阶状凸起在第二方向D2的长度f为60微米至80微米。
图5c为本公开实施例显示面板中第二子标记图形的示意图三。在一些示例中，如图5c所示，第二子标记图形62设置为三角形凸起。三角形凸起的角部为圆角。三角形凸起在第一方向D1的长度e为40微米至100微米，例如，三角形凸起在第一方向D1的长度e为60微米至90微米。三角形凸起在第二方向D2的长度f为40微米至100微米，例如，三角形凸起在第二方向D2的长度f为60微米至80微米。
图5d为本公开实施例显示面板中第二子标记图形的示意图四。在一些示例中，如图5d所示，第二子标记图形62设置为菱形凸起。菱形凸起在第一方向D1的长度e为60微米至80微米，菱形凸起在第二方向D2的长度f为60微米至80微米。或者，菱形凸起在第一方向D1的长度e为30微米至60微米，菱形凸起在第二方向D2的长度f为60微米至80微米。
图5e为本公开实施例显示面板中第二子标记图形的示意图五。在一些示例中，如图5e所示，第二子标记图形62设置为六边形凸起。六边形凸起在第一方向D1的长度e为100微米至150微米，例如，六边形凸起在第一方向D1的长度e为120微米至130微米。六边形凸起在第二方向D2的长度f为20微米至80微米。例如，六边形凸起在第二方向D2的长度f为40微米至60微米。
图5f为本公开实施例显示面板中第二子标记图形的示意图六。在一些示例中，如图5f所示，第二子标记图形62包括互相连接的第一部分71和第二部分72，第一部分71位于第二部分72靠近显示区域10一侧，第一部分71和第二部分72均为三角形，且第一部分71的角部与第二部分72的角部连接。第二子标记图形62在第一方向D1的长度e为10微米至60微米，例如，第二子标记图形62在第一方向D1的长度e为30微米至50微米。第二子标记图形62在第二方向D2的长度f为20微米至80微米。例如，第二子标记图形62在第二方向D2的长度f为40微米至60微米。
在一些示例中，裂纹检测线上的标记图形可以与裂纹检测线(例如绕线段和连接段)同层设置，并一体成型，例如，裂纹检测线的绕线段、连接段以及标记图形均与显示区域中驱动电路层的第二栅金属层同层设置。
在一些实施例中，裂纹检测线上的标记图形可以与裂纹检测线(例如绕线段和连接段)位于不同膜层。标记图形可以通过过孔与裂纹检测线的绕线段连接，从而增加标记图形的辨识度。
图6为本公开实施例显示面板的走线示意图二。如图6所示，第一子边框区域212还包括栅极驱动电路(GOA电路)71、电源信号线72和隔离坝73，栅极驱动电路(GOA电路)71、电源信号线72和隔离坝73均围绕显示区域10的周边设置，栅极驱动电路(GOA电路)71、电源信号线72和隔离坝73沿着远离显示区域10的方向依次间隔排布，裂纹检测线31位于电源信号线72与隔离坝73之间，裂纹检测线31的标记图形60位于位于电源信号线72与隔离坝73之间，且标记图形60沿着靠近隔离坝73的方向延伸，并与隔离坝73之间设置有间隔。
在一些示例中，如图6所示，边框区域可以包括多条裂纹检测线31，多条裂纹检测线31以显示区域在第二方向D2的中心线A为轴大致对称，且标记图形60以显示区域在第二方向D2的中心线A为轴大致对称。例如，第一边框区域21可以包括两条裂纹检测线31，两条裂纹检测线31可以关于显示面板沿第二方向D2的中心线A大致对称。一条裂纹检测线31可以位于第一边框区域21的左半区域，一条裂纹检测线31可以位于第一边框区域21的右半区域；两条裂纹检测线31上的标记图形60以显示区域在第二方向D2的中心线A为轴大致对称，一条裂纹检测线31上的标记图形60可以位于第一边框区域21的左半区域，一条裂纹检测线31上的标记图形60可以位于第一边框区域21的右半区域。
本发明实施例还提供了一种显示装置，包括前面任一所述的显示面板。该显示装置包括手机、平板电脑、智能穿戴产品(例如智能手表、手环等)、个人数字助理(personal digital assistant，PDA)、车载电脑等。本申请实施例对上述显示装置的具体形式不做特殊限制。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。 在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (15)

  1. 一种显示面板，包括显示区域以及位于所述显示区域周边的边框区域，所述显示区域包括多条数据线和多个子像素，所述多条数据线和所述多个子像素电连接；所述边框区域包括裂纹检测线和多个检测控制单元，所述裂纹检测线通过所述多个检测控制单元与所述多条数据线中的至少一条数据线电连接，所述裂纹检测线包括至少一个标记图形，所述至少一个标记图形被配置为用于工艺中的对位标记。
  2. 根据权利要求1所述的显示面板，其中，所述裂纹检测线包括多条绕线段，所述多条绕线段包括沿着远离所述显示区域的方向间隔排布的第二绕线段和第一绕线段，所述第一绕线段包括所述至少一个标记图形。
  3. 根据权利要求2所述的显示面板，其中，所述边框区域包括围绕所述显示区域的第一边框区域以及位于所述第一边框区域远离所述显示区域一侧的第二边框区域，所述第一边框区域包括位于所述显示区域和所述第二边框区域之间的第一子边框区域以及位于所述显示区域其他侧的第二子边框区域，所述裂纹检测线位于所述第一子边框区域和所述第二子边框区域，所述标记图形包括第一子标记图形和第二子标记图形，所述第一子标记图形位于所述第二子边框区域，所述第二子标记图形位于所述第一子边框区域。
  4. 根据权利要求3所述的显示面板，其中，所述第二子边框区域的裂纹检测线的第一绕线段包括沿着第二方向延伸的第一子绕线段，所述第一子绕线段弯曲设置有第一子标记图形，所述第一子标记图形沿着远离所述显示区域的第一方向延伸，所述第一方向与所述第二方向交叉。
  5. 根据权利要求4所述的显示面板，其中，所述第一子标记图形设置为梯形凸起，所述梯形凸起包括两个腰边以及沿着所述第二方向延伸的底边，所述两个腰边分别与所述底边的两端连接。
  6. 根据权利要求5所述的显示面板，其中，所述底边的长度为200微米至300微米，所述底边与所述第二绕线段之间的间距为10微米至30微米。
  7. 根据权利要求5所述的显示面板，其中，多个所述第一子标记图形沿着所述第二方向间隔排布形成第一子标记图形组，所述第一子标记图形组 中的第一子标记图形依次连接。
  8. 根据权利要求7所述的显示面板，其中，所述第一子标记图形组中位于所述第二方向上一侧的第一子标记图形的底边边缘至所述第一子标记图形组中位于所述第二方向上另一侧的第一子标记图形的底边边缘之间的距离为200微米至300微米。
  9. 根据权利要求5所述的显示面板，其中，所述腰边与垂直于所述底边的方向形成的夹角为30度至60度。
  10. 根据权利要求3所述的显示面板，其中，所述第一子边框区域的裂纹检测线包括沿着第一方向延伸的第三子绕线段，所述第三子绕线段包括第二子标记图形，所述第二子标记图形沿着远离所述显示区域的第二方向设置，所述第一方向与所述第二方向交叉。
  11. 根据权利要求10所述的显示面板，其中，所述第二子标记图形设置为凸台状凸起，所述凸台状凸起在所述第一方向的长度为70微米至90微米，所述凸台状凸起在所述第二方向的长度为60微米至80微米；或者，所述第二子标记图形设置为台阶状凸起，所述台阶状凸起在所述第一方向的长度为60微米至80微米，所述台阶状凸起在所述第二方向的长度为60微米至80微米；或者，所述第二子标记图形设置为三角形凸起，所述三角形凸起在所述第一方向的长度为60微米至90微米，所述三角形凸起在所述第二方向的长度为60微米至80微米；或者，所述第二子标记图形设置为菱形凸起，所述菱形凸起在所述第一方向的长度为60微米至80微米，所述菱形凸起在所述第二方向的长度为60微米至80微米；或者，所述菱形凸起在所述第一方向的长度为30微米至60微米，所述菱形凸起在所述第二方向的长度为60微米至80微米；或者，所述第二子标记图形设置为六边形凸起，所述六边形凸起在所述第一方向的长度为120微米至130微米，所述六边形凸起在所述第二方向的长度为40微米至60微米；或者，所述第二子标记图形包括互相连接的第一部分和第二部分，所述第一部分位于所述第二部分靠近所述显示区域一侧，所述第一部分和所述第二部分均设置为三角形，所述第一部分的角部与所述第二部分的角部连接。
  12. 根据权利要求1至11任一所述的显示面板，其中，所述边框区域包 括多条裂纹检测线，所述多条裂纹检测线以所述显示区域的中心线为轴对称设置，且所述标记图形以所述显示区域的中心线为轴对称设置。
  13. 根据权利要求1至11任一所述的显示面板，其中，所述标记图形与所述裂纹检测线位于不同膜层，所述标记图形通过过孔与所述裂纹检测线连接。
  14. 根据权利要求1至11任一所述的显示面板，其中，所述边框区域还包括栅极驱动电路、电源信号线和隔离坝，所述栅极驱动电路、电源信号线和隔离坝沿着远离所述显示区域的方向依次间隔排布，所述裂纹检测线位于所述电源信号线与所述隔离坝之间。
  15. 一种显示装置，包括权利要求1至14任一所述的显示面板。
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