WO2021212421A1 - 防腐蚀电路、阵列基板和电子装置 - Google Patents

防腐蚀电路、阵列基板和电子装置 Download PDF

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Publication number
WO2021212421A1
WO2021212421A1 PCT/CN2020/086443 CN2020086443W WO2021212421A1 WO 2021212421 A1 WO2021212421 A1 WO 2021212421A1 CN 2020086443 W CN2020086443 W CN 2020086443W WO 2021212421 A1 WO2021212421 A1 WO 2021212421A1
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Prior art keywords
signal line
sub
circuit
metal layer
electrically connected
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PCT/CN2020/086443
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English (en)
French (fr)
Inventor
张波
董向丹
王俊喜
魏玉龙
王蓉
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP20930655.4A priority Critical patent/EP4141943A4/en
Priority to CN202080000588.4A priority patent/CN113841251A/zh
Priority to US17/433,481 priority patent/US20220344439A1/en
Priority to PCT/CN2020/086443 priority patent/WO2021212421A1/zh
Publication of WO2021212421A1 publication Critical patent/WO2021212421A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the embodiments of the present disclosure relate to an anti-corrosion circuit, an array substrate, and an electronic device.
  • OLED Organic Light-Emitting Diode
  • OLED Organic Light-Emitting Diode
  • Similar active light-emitting elements include quantum dot light-emitting diodes and so on.
  • At least one embodiment of the present disclosure provides an array substrate, which includes: a base substrate including a display area and a peripheral area at least on one side of the display area; a plurality of sub-pixels located in the display area; a plurality of source signals Lines, located in the display area and electrically connected to the plurality of sub-pixels, and configured to provide data signals to the plurality of sub-pixels, wherein the plurality of source signal lines extend in a first direction and extend in different directions.
  • the plurality of first sub-signal lines and the plurality of second sub-signal lines extend along the second direction and are alternately arranged along the first direction, and the main body portion of the first power bus is connected to a first
  • the sub-signal lines are adjacent, and the electrical properties of the first power bus are the same as the electrical properties of the one first sub-signal line.
  • the electrostatic discharge protection circuit includes a plurality of switch groups, and each switch group includes a first switch and a second switch sharing the same electrode, and the first switch and the second switch are electrically connected through the same electrode.
  • the same source signal line is connected, and different switch groups are electrically connected to different source signal lines.
  • the main body part of the first power bus is a first signal line
  • the one first sub-signal line adjacent to the main body part is a second signal line and is connected to the second signal line.
  • the adjacent second sub-signal line is a third signal line
  • the first switch includes a first input terminal and a first output terminal, the first input terminal is electrically connected to the same source signal line, and the first switch An output terminal is electrically connected to the second signal line
  • the second switch includes a second input terminal and a second output terminal, the second input terminal is electrically connected to the third signal line, and the second The output terminal is electrically connected to the same source signal line.
  • the first switch is a first transistor, the first transistor includes a first gate, a first electrode, and a second electrode, the first electrode serves as the first input terminal, and the second electrode is electrically connected. Is connected to the first gate and serves as the first output terminal; the second switch is a second transistor, and the second transistor includes a second gate, a third electrode, and a fourth electrode, the third electrode As the second input terminal, the fourth electrode is electrically connected to the second gate and serves as the second output terminal.
  • the absolute value of the voltage difference between the first signal line and the second signal line is smaller than the absolute value of the voltage difference between the first signal line and the third signal line.
  • both the first signal line and the second signal line have positive electrical properties
  • the third signal line has negative electrical properties
  • both the first signal line and the second signal line have negative electrical properties
  • the third signal line has positive electrical properties
  • the voltage of the first signal line, the voltage of the second signal line, and the voltage of the third signal line are all constant voltages.
  • the first signal line, the second signal line, and the third signal line are located side by side on the same surface.
  • the plurality of source signal lines includes a signal line group sequentially arranged along the second direction, and each signal line group includes a first source signal line and a second source signal line sequentially arranged along the second direction.
  • the plurality of switch groups included in the electrostatic discharge protection circuit include a first switch group and a second switch group arranged in sequence along the first direction , A third switch group and a fourth switch group, the first switch group is electrically connected to the first source signal line, the second switch group is electrically connected to the second source signal line, and the third switch The group is electrically connected to the third source signal line, and the fourth switch group is electrically connected to the fourth source signal line.
  • the array substrate includes a first gate metal layer, a second gate metal layer, and a source-drain metal layer sequentially located on the base substrate, and the first gate metal layer includes the plurality of source signal lines.
  • the second gate metal layer includes another part of the plurality of source signal lines, and the source drain metal layer includes the main body part of the first power bus line, the plurality of sub power lines, The plurality of first sub-signal lines and the plurality of second sub-signal lines.
  • At least one of the plurality of sub-pixels includes a plurality of pixel switches, and each pixel switch includes a gate, a first pole, and a second pole; the gate is located on the first gate metal layer or the second gate. In the gate metal layer, the first electrode and the second electrode are located in the source and drain metal layer.
  • the material of at least one of the main body portion of the first power bus and the one first sub-signal line includes aluminum metal.
  • At least one of the main body portion of the first power bus and the one first sub-signal line has a multilayer film structure, and the multilayer film structure includes a first metal layer and a second metal layer that are sequentially stacked.
  • the metal activity of the second metal layer is greater than the metal activity of the first metal layer and the third metal layer.
  • the voltages of the main part of the first power bus and the one first sub-signal line are both constant voltages.
  • the size of the gap between the main body portion of the first power bus and the one first sub-signal line in the first direction is less than or equal to 300 microns.
  • At least one embodiment of the present disclosure provides an anti-corrosion circuit, which includes a first signal line, a second signal line, and a third signal line that are sequentially arranged along a first direction; the first signal line and the second signal line And the third signal line extend in a second direction, the second direction is different from the first direction; the first signal line and the third signal line are adjacent to the second signal line .
  • the second signal line and the first signal line have the same electrical properties, and the second signal line and the third signal line have different electrical properties.
  • the absolute value of the voltage difference between the first signal line and the second signal line is smaller than the absolute value of the voltage difference between the first signal line and the third signal line.
  • both the first signal line and the second signal line have positive electrical properties
  • the third signal line has negative electrical properties
  • both the first signal line and the second signal line have negative electrical properties
  • the third signal line has positive electrical properties
  • the voltage of the first signal line, the voltage of the second signal line, and the voltage of the third signal line are all constant voltages.
  • the first signal line, the second signal line, and the third signal line are located side by side on the same surface.
  • the material of at least one of the first signal line and the second signal line includes an aluminum metal layer.
  • the first signal line and the second signal line has a multilayer film structure
  • the multilayer film structure includes a first metal layer, a second metal layer, and a third metal layer that are sequentially stacked,
  • the metal activity of the second metal layer is greater than the metal activity of the first metal layer and the third metal layer.
  • the anti-corrosion circuit includes a first sub-circuit and a second sub-circuit spaced apart from each other, one of the first signal line and the second signal line belongs to the first sub-circuit, the The other of the first signal line and the second signal line belongs to the second sub-circuit.
  • the second sub-circuit is an electrostatic discharge protection circuit
  • the electrostatic discharge protection circuit includes the other of the first signal line and the second signal line, and the third signal line.
  • the electrostatic discharge protection circuit includes a first bus signal line and a second bus signal line arranged in sequence; the electrostatic discharge protection circuit further includes a plurality of first sub signal lines and a plurality of second sub signal lines arranged in sequence , The plurality of first sub-signal lines are electrically connected to the first bus signal line, the plurality of second sub-signal lines are electrically connected to the second bus signal line; and the first signal line and the first signal line The other of the two signal lines belongs to the first bus signal line, the second bus signal line, the plurality of first sub signal lines, or the plurality of second sub signal lines.
  • the anti-corrosion circuit includes a protected signal line that is electrically connected to the electrostatic discharge protection circuit;
  • the electrostatic discharge protection circuit includes a first switch and a second switch;
  • the first switch includes A first input terminal and a first output terminal.
  • the first input terminal is electrically connected to the protected signal line, and the first output terminal is connected to all of the first signal line and the second signal line.
  • the other one is electrically connected;
  • the second switch includes a second input terminal and a second output terminal, the second input terminal is electrically connected to the third signal line, and the second output terminal is connected to the Protect the electrical connection of the signal line.
  • the first switch is a first transistor, the first transistor includes a first gate, a first electrode, and a second electrode, the first electrode serves as the first input terminal, and the second electrode is electrically connected. Is connected to the first gate and serves as the first output terminal; the second switch is a second transistor, and the second transistor includes a second gate, a third electrode, and a fourth electrode, the third electrode As the second input terminal, the fourth electrode is electrically connected to the second gate and serves as the second output terminal.
  • the electrostatic discharge protection circuit includes the second signal line and the third signal line, the second signal line is one of the plurality of first sub-signal lines, and the third signal line is One of the plurality of second sub-signal lines.
  • the size of the gap between the first signal line and the second signal line in the first direction is less than or equal to 300 micrometers.
  • the size of the gap between the first signal line and the second signal line in the first direction is less than or equal to 60 microns.
  • At least one embodiment of the present disclosure further provides an electronic device, which includes the array substrate described in any one of the above embodiments or the anti-corrosion circuit described in any one of the above embodiments.
  • the electronic device includes: a pixel substrate, which includes a plurality of sub-pixels, and a circuit board, which is connected to one side of the pixel substrate.
  • the circuit board is configured to provide signals to the first signal line, the second signal line, and the third signal line, and the anti-corrosion
  • the second signal line and the third signal line of the circuit are located between the circuit board and the pixel substrate, and the first signal line of the anti-corrosion circuit is located on the side facing the second signal line. Said one side of the pixel substrate.
  • FIG. 1 is a simplified schematic diagram of the positional relationship of the first signal line, the second signal line, and the third signal line in the anti-corrosion circuit provided by an embodiment of the disclosure.
  • FIG. 2 is a schematic diagram of a multilayer film structure of a signal line in an anti-corrosion circuit provided by an embodiment of the disclosure.
  • FIG. 3 is a schematic diagram of the anti-corrosion circuit provided by an embodiment of the disclosure including a first sub-circuit and a second sub-circuit.
  • 4A and 4B are simplified schematic diagrams of the bus signal line and the sub signal line included in the electrostatic discharge protection circuit in the anti-corrosion circuit provided by the embodiment of the disclosure.
  • FIG. 5A is an equivalent circuit diagram of an electrostatic discharge protection circuit in an anti-corrosion circuit provided by an embodiment of the disclosure.
  • FIG. 5B is a schematic diagram of the electrostatic discharge protection circuit shown in FIG. 5A for releasing positive charges.
  • FIG. 5C is a schematic diagram of the electrostatic discharge protection circuit shown in FIG. 5A for releasing negative charges.
  • FIG. 6 is another equivalent circuit diagram of the electrostatic discharge protection circuit in the anti-corrosion circuit provided by the embodiment of the disclosure.
  • FIG. 7 is a schematic top view 1 of an anti-corrosion circuit provided by an embodiment of the disclosure.
  • FIG. 8A is a schematic top view of a semiconductor layer included in the anti-corrosion circuit shown in FIG. 7.
  • FIG. 8B is a schematic top view of the semiconductor layer and the first gate metal layer included in the anti-corrosion circuit shown in FIG. 7.
  • FIG. 8C is a schematic top view of the semiconductor layer, the first gate metal layer, and the second gate metal layer included in the anti-corrosion circuit shown in FIG. 7.
  • FIG. 9A is a partial enlarged schematic diagram of the anti-corrosion circuit shown in FIG. 7.
  • Fig. 9B is a schematic cross-sectional view taken along the line A-A in Fig. 9A.
  • FIG. 10A is a second schematic top view of the anti-corrosion circuit provided by the embodiment of the disclosure.
  • Fig. 10B is a partial enlarged schematic diagram of area A in Fig. 10A.
  • Fig. 10C is a partial enlarged schematic diagram of area C in Fig. 10B.
  • Fig. 10D is a partial enlarged schematic diagram of area B in Fig. 10A.
  • FIG. 11A and 11B are schematic top views of an electronic device provided by an embodiment of the disclosure.
  • FIG. 12 is a schematic diagram of forming a conductive layer in a method for manufacturing an anti-corrosion circuit provided by an embodiment of the disclosure.
  • FIG. 13 is a schematic top view of an array substrate provided by an embodiment of the disclosure.
  • FIG. 14 is a schematic partial cross-sectional view of an array substrate in a display area provided by an embodiment of the disclosure.
  • the inventor of the present application has discovered in research that one of the reasons for the partial short circuit or open circuit of the current OLED display product circuit is that there is a large electric field between some adjacent traces in the circuit, and it is under high temperature and high humidity conditions. These traces are prone to electrochemical corrosion.
  • the inventor of the present application proposes an anti-corrosion circuit and a manufacturing method thereof, an array substrate, and an electronic device including the anti-corrosion circuit or the array substrate.
  • FIG. 1 is a simplified schematic diagram of the positional relationship of the first signal line, the second signal line, and the third signal line in the anti-corrosion circuit provided by an embodiment of the disclosure.
  • the first signal line, the second signal line, and the third signal line belong to the electrostatic discharge protection circuit, see the embodiment shown in FIG. 7 and FIG. 13; or the first signal line, the second signal line, and the third signal line belong to the detection circuit.
  • the circuit see the embodiment shown in Figure 10A.
  • an embodiment of the present disclosure provides an anti-corrosion circuit AC.
  • the anti-corrosion circuit AC includes a first signal line L1 and a second signal line located on the same side of the surface S.
  • the first signal line L1, the second signal line L2, and the third signal line L3 are arranged in sequence along the first direction and all extend substantially along the second direction ("substantially” refers to ignoring the manufacturing process caused
  • the second direction is different from the first direction; both the first signal line L1 and the third signal line L3 are adjacent to the second signal line L2, that is, the signal line closest to the side of the second signal line L2
  • the signal line that is the first signal line L1 and is closest to the other side of the second signal line L2 is the third signal line L3 (that is, each of the first signal line L1 and the third signal line L3 and the second signal line L3 No other signal lines are provided between the signal lines L2).
  • the second signal line L2 and the first signal line L1 have the same electrical properties, and the second signal line L2 and the third signal line L3 have different electrical properties.
  • the first signal line L1 For the first signal line L1, the second signal line L2, and the third signal line L3 that have a given voltage and are arranged in sequence, if the first signal line L1 is adjacent to the third signal line L3, the The electrical properties of the line L1 and the third signal line L3 are different, causing electrochemical corrosion to easily occur between the first signal line L1 and the third signal line L3.
  • the first signal line L1 is adjacent to the second signal line L2; on this basis, the same electrical property of the first signal line L1 and the second signal line L2 is different from that of the third signal line L3
  • the embodiments of the present disclosure are beneficial to avoid electrochemistry between the first signal line L1 and the second signal line L2. Corrosion (especially under high temperature and high humidity conditions) is beneficial to avoid corrosion of the first signal line L1 and the second signal line L2.
  • the distance between the first signal line L1 and the second signal line L2 can be designed to be smaller.
  • the frame (for example, the lower frame) of the panel is narrowed to increase the screen-to-body ratio. Therefore, some embodiments of the present disclosure can improve the local short circuit or open circuit while realizing the narrow frame design.
  • the second signal line L2 and the first signal line L1 have the same electrical properties
  • the second signal line L2 and the third signal line L2 have the same electrical properties
  • the absolute value of the voltage difference between the first signal line L1 and the second signal line L2 is smaller than the absolute value of the voltage difference between the first signal line L1 and the third signal line L3 value.
  • FIGS. 1, 7, 10A, and 13 take the second direction perpendicular to the first direction as an example for description; in other embodiments, the first direction and the second direction may not be perpendicular.
  • that one signal line is adjacent to another signal line means that the one signal line and the other signal line extend in the same direction, and the two signal lines are not arranged along the same direction. Other signal lines extending in the direction.
  • the voltage of the second signal line L2 is different from that of the third signal line L3.
  • the voltage of the third signal line L3, the voltage of the first signal line L1 and the voltage of the second signal line L2 are both greater than or less than the voltage of the third signal line L3 (it should be noted that the positive voltage is greater than the negative voltage).
  • the voltage of the first signal line L1 is greater than the voltage of the second signal line L2, and the voltage of the second signal line L2 is greater than the voltage of the third signal line L3; or, the voltage of the first signal line L1 is less than the voltage of the second signal line L2
  • the voltage of the second signal line L2 is less than the voltage of the third signal line L3.
  • the voltage relationship between the first signal line L1, the second signal line L2, and the third signal line L3 includes but is not limited to the listed embodiments.
  • the first signal line L1 and the second signal line L1 have different electrical properties.
  • the lines L2 all have positive electrical properties, and the third signal line L3 has negative electrical properties.
  • the voltage of the first signal line L1 and the voltage of the second signal line L2 are both positive voltages, and the voltage of the third signal line L3 is negative voltage; or, the voltage of the first signal line L1 and the voltage of the second signal line L2 are both positive.
  • the voltages are all negative voltages, and the voltage of the third signal line L3 is positive voltages.
  • the voltage of the first signal line L1 is a positive voltage
  • the voltage of the second signal line L2 is a positive voltage
  • the voltage of the third signal line L3 is a negative voltage
  • the voltage of the first signal line L1 is a negative voltage
  • the voltage of the second signal line L2 is a negative voltage
  • the voltage of the third signal line L3 is a positive voltage
  • the voltage of the first signal line L1, the voltage of the second signal line L2, and the voltage of the third signal line L3 are all constant voltages.
  • the inventor of the present application found that electrochemical corrosion is likely to occur when a constant voltage is applied to adjacent signal lines. Compared with the arrangement in which the first signal line L1 and the third signal line L3 are adjacent to each other, even if the voltage of the first signal line L1, the voltage of the second signal line L2, and the voltage of the third signal line L3 in the embodiment of the present disclosure are all It is a constant voltage. Since the first signal line L1 and the second signal line L2 have the same electrical properties, electrochemical corrosion is not prone to occur between the first signal line L1 and the second signal line L2.
  • the first signal line L1, the second signal line L2, and the third signal line L3 are located side by side on the same surface S, that is, the first signal line L1, the second signal line L2, and the third signal line L3 directly contact the same carrier.
  • Surface S The inventor of the present application found that electrochemical corrosion is likely to occur when adjacent signal lines are located side by side on the same surface.
  • the embodiment of the present disclosure exchanges the positions of the second signal line L2 and the third signal line L3. After the exchange, the adjacent first signal line L1 and the second signal line L2 have the same electrical properties. Therefore, even if the first signal line L1, the second signal line L2, and the third signal line L3 are located side by side on the same surface S, After the exchange, the adjacent first signal line L1 and the second signal line L2 are not prone to electrochemical corrosion.
  • the first signal line L1, the second signal line L2, and the third signal line L3 can be formed by forming a conductive layer on the surface S, and then patterning the conductive layer to form side by side on the surface S The first signal line L1, the second signal line L2 and the third signal line L3.
  • the material of at least one of the first signal line L1 and the second signal line L2 includes an aluminum metal layer.
  • the aforementioned conductive layer used to form the first signal line L1, the second signal line L2, and the third signal line L3 has an aluminum metal layer.
  • the first signal line L1, the second signal line L2, and the The materials of the three signal lines L3 all include an aluminum metal layer. The inventor of the present application discovered that aluminum metal is prone to electrochemical corrosion due to its relatively strong metal activity.
  • the first signal line L1 and the second signal line L2 have the same electrical property, since the first signal line L1 and the second signal line L2 have the same electrical property, the first signal line L1 and the second signal line L2 have the same electrical properties. Electrochemical corrosion is not prone to occur between the signal line L1 and the second signal line L2.
  • FIG. 2 is a schematic diagram of a multilayer film structure of a signal line in an anti-corrosion circuit provided by an embodiment of the disclosure.
  • the first signal line L1 and the second signal line L2 has a multilayer film structure including a first metal layer that is sequentially stacked in a direction perpendicular to the surface S.
  • the layer M1, the second metal layer M2 and the third metal layer M3, and the metal activity of the second metal layer M2 is greater than the metal activity of the first metal layer M1 and the third metal layer M3.
  • the aforementioned conductive layer used to form the first signal line L1, the second signal line L2, and the third signal line L3 has this multilayer film structure.
  • the first signal line L1, the second signal line L2 Both and the third signal line L3 have a multilayer film structure.
  • the first metal layer M1 is a titanium metal layer
  • the second metal layer M2 is an aluminum metal layer
  • the third metal layer M3 is a titanium metal layer.
  • the use of a multilayer film structure to fabricate the first signal line L1, the second signal line L2, and the third signal line L3 is beneficial to making these signal lines have better electrical performance.
  • FIG. 3 is a schematic diagram of the anti-corrosion circuit provided by an embodiment of the disclosure including a first sub-circuit and a second sub-circuit.
  • the anti-corrosion circuit AC provided by at least one embodiment of the present disclosure includes a first sub-circuit C1 and a second sub-circuit C2 spaced apart from each other.
  • the other of the first signal line L1 and the second signal line L2 belongs to the second sub-circuit C2.
  • the first signal line L1 belongs to the first sub-circuit C1
  • the second signal line L2 belongs to the second sub-circuit C2.
  • the first sub-circuit C1 and the second sub-circuit C2 can be arranged relatively closely, which is conducive to the realization of a narrow frame design .
  • the second sub-circuit C2 is an electrostatic discharge protection circuit ESD for discharging static electricity
  • the electrostatic discharge protection circuit ESD includes the other one of the first signal line L1 and the second signal line L2, and The third signal line L3.
  • FIG. 3 illustrates an example in which the electrostatic discharge protection circuit ESD includes the second signal line L2 and the third signal line L3.
  • the electrostatic discharge protection circuit ESD includes a first signal line L1 and a third signal line L3.
  • the second sub-circuit C2 may not be an electrostatic discharge protection circuit.
  • FIGS. 4A and 4B are simplified schematic diagrams of the bus signal line and the sub signal line included in the electrostatic discharge protection circuit in the anti-corrosion circuit provided by the embodiment of the present disclosure.
  • the bus signal line and the sub-signal line in the embodiment shown in FIG. 4A can be referred to the embodiment shown in Figure 13 when applied to the array substrate, and the embodiment shown in Figure 4B can be referred to Figure 10A and Figures when applied to the detection circuit The embodiment shown in 10B.
  • the electrostatic discharge protection circuit ESD includes a plurality of first sub-signal lines Su1 (see, for example, VGH in FIGS.
  • FIG. 13 only schematically shows Two VGHs but do not reflect the actual size
  • a plurality of second sub-signal lines Su2 see, for example, the VGL in FIGS. 7, 13 and 10A-10B, FIG. 13 only schematically shows two VGLs but Does not reflect the actual size
  • the plurality of first sub-signal lines Su1 and the plurality of second sub-signal lines Su2 are alternately arranged, for example, there is a second sub-signal line Su2 between adjacent first sub-signal lines Su1, And there is a first sub-signal line Su1 between adjacent second sub-signal lines Su2.
  • the plurality of first sub-signal lines Su1 and the plurality of second sub-signal lines Su2 are sequentially arranged along the first direction and both extend along the second direction; or, as As shown in FIGS. 4B and 10A-10B, the plurality of first sub-signal lines Su1 and the plurality of second sub-signal lines Su2 are sequentially arranged along the second direction and both extend along the first direction.
  • the electrostatic discharge protection circuit ESD includes a first bus signal line B1 and a second bus signal line B2 arranged in sequence.
  • the arrangement direction of the sub signal lines is different from The arrangement direction of the above-mentioned bus signal line;
  • the plurality of first sub signal lines Su1 are electrically connected to the first bus signal line B1, for example, the end of the first sub signal line Su1 is electrically connected to the first bus signal line B1 (as shown in Figures 4A and 13) or the part between the two ends of the first sub signal line Su1 is electrically connected to the first bus signal line B1 (as shown in Figures 4B and 10A-10B, the black dots in Figure 4B indicate electrical connections );
  • the plurality of second sub signal lines Su2 are electrically connected to the second bus signal line B2, for example, the end of the second sub signal line Su2 is electrically connected to the second bus signal line B2 (as shown in FIG.
  • the part between the two ends of the two sub signal lines Su2 is electrically connected to the second bus signal line B2 (as shown in FIGS. 4B and 10A-10B).
  • the other of the first signal line L1 and the second signal line L2 included in the second sub-circuit C2 belongs to the first bus signal line B1, the second bus signal line B2, and the plurality of second signal lines One sub-signal line Su1 or multiple second sub-signal lines Su2.
  • the electrostatic discharge protection circuit ESD includes a second signal line L2 and a third signal line L3.
  • the second signal line L2 is one of a plurality of first sub signal lines Su1
  • the line L3 is one of a plurality of second sub-signal lines Su2.
  • the outermost first sub-signal line Su1 is the second signal line L2
  • the second sub-signal line Su2 adjacent to the first sub-signal line Su1 is the third signal line L3.
  • the first signal line L1 (not shown in FIG. 4A) is located on the side of the first sub-signal line Su1/L2 away from the second sub-signal line Su2/L3.
  • the outermost first sub-signal line Su1 is the second signal line L2
  • the second sub-signal line Su2 adjacent to the first sub-signal line Su1 is the third signal line L3
  • the first signal The gap between the orthographic projection of the line L1 on the surface S and the orthographic projection of the second signal line L2 on the surface S is in the arrangement direction of the first signal line L1 and the second signal line L2 (that is, the above-mentioned first direction)
  • the size is less than or equal to 300 microns.
  • the size is less than or equal to 200 microns.
  • the size is less than or equal to 100 microns.
  • the electrostatic discharge protection circuit ESD includes a first signal line L1 and a third signal line L3, the first signal line L1 is the first bus signal line B1, and the third signal line L3 is the first signal line L3.
  • the second signal line L2 (not shown in FIG. 4B) is located between the first bus signal line B1/L1 and the second bus signal line B2/L3.
  • the orthographic projection of the first signal line L1 on the surface S and the second signal line is less than or equal to 60 microns.
  • the size is greater than or equal to 50 microns and less than or equal to 60 microns.
  • FIG. 5A is an equivalent circuit diagram of the electrostatic discharge protection circuit in the anti-corrosion circuit provided by an embodiment of the disclosure
  • FIG. 5B is a schematic diagram of the electrostatic discharge protection circuit shown in FIG. 5A releasing positive charges
  • FIG. 5C is the electrostatic discharge protection shown in FIG. 5A Schematic diagram of the circuit releasing negative charge.
  • the anti-corrosion circuit includes a protected signal line SL and an electrostatic discharge protection circuit ESD (not shown in FIG. 5A) electrically connected to the protected circuit.
  • the electrostatic discharge includes a circuit ESD including a switch group.
  • the group includes a first switch T1 and a second switch T2;
  • the first switch T1 includes a first input terminal Vi1 and a first output terminal Vo1, the first input terminal Vi1 is electrically connected to the protected signal line SL, and the first output terminal Vo1 is electrically connected Connected to the first signal line L1 or the second signal line L2;
  • the second switch T2 includes a second input terminal Vi2 and a second output terminal Vo2, the second input terminal Vi2 is electrically connected to the third signal line L3, and the second output terminal Vo2 It is electrically connected to the protected signal line SL.
  • the static electricity on the protected signal line SL can be discharged through the first switch T1, the second switch T2, the first signal line L1/the second signal line L2, and the third signal line L3 to avoid accumulation on the protected signal line SL More static electricity.
  • the working principle of the electrostatic discharge protection circuit ESD is as follows: when the static charge on the protected signal line SL is positive and the static electricity on the protected signal line SL is too large, the first switch T1 is opened, so that the positive charge will be It is released through the first signal line L1 or the second signal line L2, as shown in Figure 5B (the arrow in the figure indicates the direction of current flow); when the static charge on the protected signal line SL is negative and the protected signal line SL When the static electricity is too large, the second switch T2 is opened, so that the negative charge will be released through the third signal line L3, as shown in FIG. 5C (the arrow in the figure indicates the current flow direction).
  • FIG. 6 is another equivalent circuit diagram of the electrostatic discharge protection circuit in the anti-corrosion circuit provided by the embodiment of the disclosure.
  • the first switch T1 is a first transistor.
  • the first transistor includes a first gate G1, a first electrode S1, and a second electrode D1.
  • the first electrode S1 serves as the first input terminal Vi1, and the second transistor
  • the electrode D1 is electrically connected to the first gate G1 and serves as the first output terminal Vo1
  • the second switch T2 is a second transistor, and the second transistor includes a second gate G2, a third electrode S2, and a fourth electrode D2.
  • the third electrode S2 As the second input terminal Vi2, the fourth electrode D2 is electrically connected to the second gate G2 and serves as the second output terminal Vo2.
  • both the first transistor and the second transistor are P-type transistors.
  • FIG. 7 is a schematic top view 1 of an anti-corrosion circuit provided by an embodiment of the present disclosure
  • FIG. 8A is a schematic top view of a semiconductor layer included in the anti-corrosion circuit shown in FIG. 7
  • FIG. 8B is a semiconductor layer and a semiconductor layer included in the anti-corrosion circuit shown in FIG.
  • FIG. 8C is a schematic top view of the semiconductor layer, the first gate metal layer, and the second gate metal layer included in the anti-corrosion circuit shown in FIG. 7.
  • the electrostatic discharge protection circuit ESD includes a plurality of switch groups T0, and each switch group T0 includes a first switch T1 and a second switch T2 that share the same electrode (the electrical connection relationship between T1 and T2 is detailed above Related description in the text), the first switch T1 and the second switch T2 are electrically connected to the same source signal line SL through the same electrode, so that the source signal line SL discharges static electricity through the switch group T0 connected to it, and is different
  • the switch group T0 is electrically connected to different source signal lines SL.
  • the multiple source signal lines SL in the anti-corrosion circuit AC include signal line groups sequentially arranged along the second direction, and each signal line group includes first source electrodes sequentially arranged along the second direction.
  • the electrostatic discharge protection circuit ESD includes a plurality of switch groups T0 including first The switch group T01, the second switch group T02, the third switch group T03, and the fourth switch group T04.
  • the first switch group T01 is electrically connected to the first source signal line SL1 to discharge static electricity on the first source signal line SL1.
  • the second switch group T02 is adjacent to the first switch group T01 and is electrically connected to the second source signal line SL2 to discharge static electricity on the second source signal line SL2.
  • the third switch group T03 is adjacent to and electrically connected to the second switch group T02.
  • the third source signal line SL3 is connected to discharge the static electricity on the third source signal line SL3
  • the fourth switch group T04 is adjacent to the third switch group T03 and is electrically connected to the fourth source signal line SL4 to discharge the fourth source. Static electricity on signal line SL4.
  • the switch groups T01-T04 included in the electrostatic discharge protection circuit ESD are periodically repeated; accordingly, the first source signal line SL1 to the fourth source signal line SL4 are also periodically repeated.
  • the anti-corrosion circuit AC provided by at least one embodiment of the present disclosure includes a semiconductor layer SM, a first gate metal layer GM1, a second gate metal layer GM2, and a source-drain metal layer SD.
  • the semiconductor layer SM includes a plurality of spaced apart semiconductor lines SML, and the plurality of semiconductor lines SML all extend in the first direction and are sequentially arranged in the second direction. As shown in FIG. 7 and FIG.
  • the first gate metal layer GM1 includes a plurality of gate groups, and each gate group includes a first gate G1 and a second gate G2 sequentially arranged along a first direction, and the same gate The first gate G1 and the second gate G2 included in the group overlap the same semiconductor line SML; the first gate metal layer GM1 also includes a part of the plurality of source signal lines SL, for example, the first gate metal layer GM1 includes The plurality of second source signal lines SL2 and the plurality of fourth source signal lines SL4, the plurality of second source signal lines SL2 and the plurality of fourth source signal lines SL4 all extend along the first direction and along the first direction The two directions are arranged in sequence. As shown in FIGS.
  • the source-drain metal layer SD includes a first high-voltage signal line VDD, a plurality of second high-voltage signal lines VGH (see VGH1-VGH3), and a plurality of low-voltage signal lines VGL (see VGL1-VGL2) ,
  • the signal lines are arranged in sequence along the first direction and all extend along the second direction, the plurality of second high voltage signal lines VGH and the plurality of low voltage signal lines VGL are alternately arranged, and the adjacent second high voltage signal lines
  • a gate group is provided between VGH and the low-voltage signal line VGL.
  • each second high-voltage signal line VGH includes a main body extending in the second direction and branches extending from the main body and extending toward the low-voltage signal line VGL, and each branch overlaps one semiconductor line SML and is electrically connected. Connect (the black dots in Figure 7 indicate vias for electrical connections).
  • the "high voltage” involved in the first high voltage signal line VDD and the second high voltage signal line VGH refers to the voltage of these two signal lines being higher than the voltage of the low voltage signal line VGL; the low voltage signal line The “low voltage” referred to VGL means that the voltage of the low voltage signal line VGL is lower than the voltages of the first high voltage signal line VDD and the second high voltage signal line VGH.
  • the first sub-circuit C1 includes a first high-voltage signal line VDD
  • the second sub-circuit C2 includes a second high-voltage signal line VGH1-VGH3, and a low-voltage signal line VGL1-VGL2.
  • the first high voltage signal line VDD is an example of the first signal line L1
  • the second high voltage signal line VGH1 is an example of the second signal line L2
  • the low voltage signal line VGL1 is one of the third signal lines L3.
  • the first source signal line SL1 electrically connected to the second signal line L2 and the third signal line L3 is an example of the above-mentioned protected signal line SL
  • the plurality of second high-voltage signal lines VGH are the above-mentioned plurality of first signal lines.
  • An example of the sub-signal lines, the plurality of low-voltage signal lines is an example of the above-mentioned plurality of second sub-signal lines.
  • the dimension d of the gap between the first signal line L1 and the second signal line L2 in the first direction is less than or equal to 300 micrometers.
  • the dimension d is less than or equal to 200 microns.
  • the dimension d is less than or equal to 100 microns.
  • Fig. 9A is a partial enlarged schematic diagram of the anti-corrosion circuit shown in Fig. 7;
  • Fig. 9B is a schematic cross-sectional view taken along the line A-A in Fig. 9A.
  • a semiconductor layer SM, a first gate metal layer GM1, an insulating layer ILD, and a source-drain metal layer are sequentially disposed on the base substrate BS. SD.
  • the source-drain metal layer SD is covered by the planarization insulating layer PLN and the pixel definition layer PDL.
  • FIGS. 9A is a partial enlarged schematic diagram of the anti-corrosion circuit shown in Fig. 7
  • Fig. 9B is a schematic cross-sectional view taken along the line A-A in Fig. 9A.
  • a semiconductor layer SM, a first gate metal layer GM1, an insulating layer ILD, and a source-drain metal layer are sequentially disposed on the base substrate BS. SD.
  • the semiconductor line SML in the semiconductor layer SM includes a first channel CH1 and a second channel CH2.
  • the first gate metal layer GM1 includes a first gate G1 and a second gate G2 located side by side on the semiconductor layer SM.
  • the source-drain metal layer SD includes a first signal line L1 (see the first high-voltage signal line VDD), a second signal line L2 (see the second high-voltage signal line VGH1), and a third signal line L1 (see the first high-voltage signal line VDD) side by side on the surface S of the insulating layer ILD.
  • Signal line L3 see low voltage signal line VGL1.
  • the first switch T1 includes a first gate G1, a first pole S1, a second pole D1, and a first channel CH1 located between the first pole S1 and the second pole D1.
  • the second switch T2 includes a second gate G2, a third pole S2, a fourth pole D2, and a second channel CH2 located between the third pole S2 and the fourth pole D2.
  • the insulating layer ILD is sequentially provided with first via holes V1 to fifth via holes V5;
  • the second signal line L2 includes The branch protruding to the third signal line L3 is electrically connected to the semiconductor line SML through the first via hole V1, the branch serves as the second pole D1 of the first switch T1, and the second pole D1 is electrically connected to the second pole through the second via hole V2.
  • a gate G1; the first gate G1 is directly electrically connected to the semiconductor line SML at the second via hole V2 (that is, not electrically connected through the via hole);
  • the above-mentioned adapter SD2 serves as the first pole S1 of the first switch T1 and serves as The fourth pole D2 of the second switch T2 (that is, the adapter SD2 is the electrode shared by the first switch T1 and the second switch T2), the first pole S1 and the fourth pole D2 are electrically connected at the third via hole V3
  • the semiconductor line SML, and the transfer SD2 is electrically connected to the second gate G2 at the fourth via hole V4;
  • the second gate G2 is directly electrically connected to the semiconductor line at the fourth via hole V4 (that is, not electrically connected through the via hole) SML;
  • the third signal line L3 serves as the third pole S2 of the second switch T2.
  • the material of the source and drain metal layer SD includes an aluminum metal layer.
  • the material of the source and drain metal layers includes the first metal layer M1, the second metal layer M2, and the third metal layer M3 as described above.
  • the first metal layer M1, the second metal layer M2, and the third metal layer M3 are respectively a titanium metal layer, an aluminum metal layer, and a titanium metal layer. Since the source-drain metal layer SD includes the first high-voltage signal line VDD, the second high-voltage signal line VGH, the low-voltage signal line VGL and the adapter SD, the materials of these signal lines and adapters are the same as those of the source-drain metal layer. The above materials are the same, so I won't repeat them here.
  • Fig. 10A is a schematic top view of the anti-corrosion circuit provided by an embodiment of the present disclosure
  • Fig. 10B is a partial enlarged schematic diagram of area A in Fig. 10A
  • Fig. 10C is a partial enlarged schematic diagram of area C in Fig. 10B
  • Fig. 10D is an area in Fig. 10A
  • the anti-corrosion circuit AC provided by at least one embodiment of the present disclosure includes a high voltage signal line VGH, a reset voltage signal line Vinit, and a low voltage signal that are sequentially arranged along a first direction and extend along a second direction.
  • Line VGL these signal lines are all input with a constant voltage during operation, the voltage of the high-voltage signal line VGH is greater than the voltage of the low-voltage signal line VGL, and the voltage of the reset voltage signal line Vinit is greater than the voltage of the low-voltage signal line VGL.
  • the first sub-circuit C1 includes a reset voltage signal line Vinit
  • the second sub-circuit C2 includes a high voltage signal line VGH and a low voltage signal line VGL;
  • a high voltage signal line VGH is an example of the foregoing first signal line L1
  • the reset voltage signal line Vinit is an example of the foregoing second signal line L2
  • the low voltage signal line VGL is an example of the foregoing third signal line L3.
  • the “high voltage” related to the high-voltage signal line VGH refers to the voltage of the high-voltage signal line VGH being higher than the voltage of the low-voltage signal line VGL; the “low voltage” related to the low-voltage signal line VGL refers to The voltage of the low-voltage signal line VGL is lower than the voltage of the high-voltage signal line VGH.
  • the anti-corrosion circuit AC further includes a plurality of detection signal lines ET sequentially arranged along the first direction and extending along the second direction.
  • the detection signal lines ET are inputted with a change signal, such as a square wave, during operation. Signal; the high-voltage signal line VGH is adjacent to one detection signal line ET, and the low-voltage signal line VGL is adjacent to the other detection signal line ET.
  • the anti-corrosion circuit AC further includes an electrostatic discharge protection circuit ESD for protecting the detection signal line ET, and the high voltage signal line VGH, the low voltage signal line VGL, and the detection signal line ET are all electrically connected to the electrostatic discharge protection circuit ESD.
  • the electrostatic discharge protection circuit ESD includes a plurality of sub-high voltage signal lines VGH1-VGH2 and a plurality of sub-low voltage signal lines VGL1-VGL2 alternately arranged, and these signal lines all extend in the first direction and Arranged in sequence along the second direction; the plurality of sub high voltage signal lines VGH1-VGH2 are electrically connected to the high voltage signal line VGH through, for example, a plurality of via holes V (see the black dots in FIG. 10C), and the plurality of sub low voltage signal lines VGL1-VGL2 are electrically connected to the low-voltage signal line VGH through a plurality of via holes V, for example.
  • the high-voltage signal line VGH is an example of the above-mentioned first bus signal line
  • the low-voltage signal line VGL is an example of the above-mentioned second bus signal line.
  • the sub-high-voltage signal lines VGH1-VGH2 are an example of the foregoing multiple first sub-signal lines
  • the multiple low-voltage signal lines VGL1-VGL2 are an example of the foregoing multiple second sub-signal lines.
  • the "high voltage” involved in the sub-high voltage signal lines VGH1-VGH2 refers to the voltage of these signal lines being higher than the voltage of the sub-low voltage signal lines VGL1-VGL2; the sub-low voltage signal lines VGL1-VGL2 are involved "Low voltage” means that the voltage of these signal lines is lower than the voltage of the sub-high voltage signal lines VGH1-VGH2.
  • the electrostatic discharge protection circuit ESD includes a first switch T1, a protected detection signal line ET (an example of the above-mentioned protected signal line), and a second switch T2.
  • the detection signal line ET includes a first portion ET1 extending in the first direction and a second portion ET2 extending in the second direction.
  • the first portion ET1 and the second portion ET2 are directly connected, that is, the detection signal line ET is an integrated structure.
  • the first switch T1 is a first transistor, and the first transistor includes a first gate G1, a first electrode S1, and a second electrode D1.
  • the second switch T2 is a second transistor, and the second transistor includes a second gate G2, a third electrode S2, and a fourth electrode D2.
  • the second pole D1 of the first switch T1 is electrically connected to the sub-high voltage signal line (see VGH1) and the first gate G1; the first part ET1 of the detection signal line ET serves as the first pole S1 of the first switch T1 and serves as the first pole S1 of the first switch T1.
  • the fourth pole D2 of the second switch T2; the third pole S2 of the second switch T2 is electrically connected to the sub-low voltage signal line (see VGL1).
  • both the first transistor and the second transistor are P-type transistors.
  • the positive charge static electricity on the detection signal line ET can be discharged to the sub-high voltage signal lines VGH1-VGH2 through the first switch T1, and then discharged through the sub-high voltage signal lines VGH1-VGH2; the detection signal line
  • the negative charge static electricity on the ET can be discharged to the sub-low voltage signal lines VGL1-VGL2 through the second switch T2, and then discharged through the sub-low voltage signal lines VGL1-VGL2.
  • the high voltage signal line VGH, the reset voltage signal line Vinit, the low voltage signal line VGH, and the detection signal line ET all belong to the source-drain metal layer, and these signal lines are located side by side on the same surface.
  • the material of the source and drain metal layers includes an aluminum metal layer.
  • the material of the source and drain metal layers includes the first metal layer M1, the second metal layer M2, and the third metal layer M3 as described above.
  • the sub-high voltage signal lines VGH1-VGH2 and the sub-low voltage signal lines VGL1-VGL2 all belong to the gate metal layer (for example, the aforementioned first gate metal layer GM1).
  • the high voltage signal line VGH (an example of the first signal line L1) and the reset voltage signal line Vinit (an example of the second signal line L2) between the orthographic projections on the same surface
  • the dimension h of the gap in the first direction is less than or equal to 60 microns.
  • the size h is less than or equal to 60 microns and greater than or equal to 50 microns. Since the distance between the high-voltage signal line VGH and the reset voltage signal line Vinit can be made smaller, the structure of the anti-corrosion circuit is compact and space-saving.
  • An embodiment of the present disclosure also provides an electronic device, which includes the anti-corrosion circuit described in any of the above embodiments.
  • the electronic device provided by at least one embodiment of the present disclosure includes a pixel substrate AR, a first power bus VDD (that is, the first high-voltage signal line in the embodiment shown in FIG. 7), and more A sub-power supply line VDD0 (only three sub-power supply lines are schematically drawn in the figure), a second power supply bus VSS, an electrostatic discharge protection circuit ESD, a driving circuit IC, and a circuit board PC.
  • the pixel substrate AR includes a plurality of sub-pixels (for example, the sub-pixels include light-emitting elements), and the plurality of sub-pixels are arranged in a matrix.
  • the plurality of sub-pixels includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B.
  • the first power bus VDD is electrically connected to the sub-power line VDD0 to provide a first power signal to the sub-pixels (such as light-emitting elements) through the sub-power line VDD0
  • the second power bus VSS is used to provide the second power signal to the sub-pixels.
  • the pixel can work under the action of the first power signal and the second power signal.
  • the first power bus VDD provides the first power signal to the anode of the light-emitting element in the sub-pixel
  • the second power bus VSS provides the second power signal to the cathode of the light-emitting element in the sub-pixel.
  • the constant voltage is greater than the constant voltage of the second power bus VSS.
  • a circuit board PC (which is, for example, a flexible printed circuit board) is connected to one side of the pixel substrate AR, and the circuit board PC is configured to provide signals to the first power bus VDD and the second power bus VSS.
  • an electrostatic discharge protection circuit ESD (hereinafter referred to as a first electrostatic discharge protection circuit) included in the electronic device is located between the pixel substrate AR and the circuit board PC.
  • the first electrostatic discharge protection circuit ESD is adjacent to the first power bus VDD.
  • the first electrostatic discharge protection circuit ESD is an electrostatic discharge protection circuit as shown in FIG. 7, that is, the first electrostatic discharge protection circuit ESD includes a plurality of second sub-high voltage signal lines VGH1-VGH3 and a plurality of low voltage signal lines VGL1-VGL2.
  • the plurality of second sub-high voltage signal lines VGH1-VGH3 are electrically connected to the high voltage signal line VGH0 (an example of the above-mentioned first bus signal line B1), and the plurality of low voltage signal lines VGL1-VGL2 are electrically connected to the low voltage signal line VGL0 (An example of the above-mentioned second bus signal line B2).
  • the circuit board PC is used to provide signals to the high voltage signal line VGH0 and the low voltage signal line VGL0 to respectively provide the plurality of second sub-high voltage signal lines VGH1-VGH3 and the plurality of low voltage signal lines of the first electrostatic discharge protection circuit ESD VGL1-VGL2 provide signals.
  • the “high voltage” related to the high-voltage signal line VGH0 refers to the voltage of the high-voltage signal line VGH0 being higher than the voltage of the low-voltage signal line VGL0; the “low voltage” related to the low-voltage signal line VGL0 refers to The voltage of the low-voltage signal line VGL0 is lower than the voltage of the high-voltage signal line VGH0.
  • the anti-corrosion circuit AC includes a first power bus VDD, a high-voltage signal line VGH0, a low-voltage signal line VGL0, and a first electrostatic discharge protection circuit ESD.
  • the first power bus VDD is an example of the first signal line L1
  • the high-voltage signal line VGH0 is an example of the first bus signal line B1
  • the low-voltage signal line VGL0 is the second bus signal.
  • the second high voltage signal line VGH1 adjacent to the first power supply bus VDD is an example of the second signal line L2
  • the low voltage signal line VGL1 adjacent to the second high voltage signal line VGH1 is An example of the third signal line L3.
  • the second signal line L2 and the third signal line L3 are located between the circuit board PC and the pixel substrate AR, and the first signal line L1 is located on the side of the second signal line L2 facing the pixel substrate AR, that is, the first signal line L2.
  • the signal line L1 is located between the pixel substrate AR and the second signal line L2.
  • the electronic device provided by at least one embodiment of the present disclosure further includes a detection circuit ETC, which is located on the side of the circuit board PC away from the pixel substrate AR, that is, the circuit board PC is located between the detection circuit ETC and the pixel substrate AR. between.
  • the detection circuit ETC is an anti-corrosion circuit as shown in FIGS. 10A to 10D, that is, the detection circuit ETC is an example of the aforementioned anti-corrosion circuit AC.
  • the detection circuit ETC includes a high voltage signal line VGH, a reset voltage signal line Vinit, a low voltage signal line VGL, a detection signal line ET, and an electrostatic discharge protection circuit (hereinafter referred to as It is the second electrostatic discharge protection circuit) ESD.
  • the second electrostatic discharge protection circuit ESD refers to the relevant description in the embodiment of the anti-corrosion circuit shown in FIGS.
  • the high voltage signal line VGH is the first signal line An example of L1
  • the reset voltage signal line Vinit is an example of the second signal line L2
  • the low voltage signal line VGL is an example of the third signal line L3
  • the first signal line L1 and the third signal line L3 are located on the circuit board A side of the PC away from the pixel substrate AR
  • the reset voltage signal line Vinit is used to electrically connect with the light emitting element included in the pixel substrate AR to provide a reset voltage.
  • the electronic device provided by the embodiments of the present disclosure may be an active light-emitting element panel (for example, an OLED panel or a quantum dot panel) or other types of electronic devices including the above-mentioned anti-corrosion circuit.
  • an active light-emitting element panel for example, an OLED panel or a quantum dot panel
  • other types of electronic devices including the above-mentioned anti-corrosion circuit.
  • the electronic device as an active light-emitting element panel (in this case, the light-emitting element is an OLED light-emitting element or a quantum dot light-emitting element) as an example
  • the detection circuit ETC as shown in FIG. Electrical testing, and cutting along the cutting line in FIG. 11B after the electrical testing is completed to remove the detection circuit ETC, thereby obtaining the electronic device as shown in FIG. 11A.
  • the electronic device is an OLED panel that includes a plurality of sub-pixels, and each sub-pixel includes a light-emitting element and a driving circuit that drives the light-emitting element to emit light.
  • the driving circuit may adopt a 6T1C or 7T1C or similar circuit structure, where T refers to a thin film transistor (TFT), and C refers to a capacitor (Capacitor).
  • T refers to a thin film transistor (TFT)
  • C refers to a capacitor (Capacitor).
  • the first electrostatic discharge protection circuit ESD is the electrostatic discharge protection circuit shown in FIG. 7
  • the first power bus VDD is used to provide a signal to a TFT included in the driving circuit, and the source signal line in FIG.
  • the SL (see SL1-SL4) is electrically connected to another TFT included in the driving circuit, and the first electrostatic discharge protection circuit is used to discharge the static electricity on the source signal line SL.
  • the detection circuit ETC is an anti-corrosion circuit as shown in FIGS. 10A to 10D
  • the reset voltage signal line Vinit is used to provide a signal to a TFT included in the driving circuit
  • the detection signal line ET and the driving circuit include The other TFT is electrically connected
  • the second electrostatic discharge protection circuit is used to discharge the static electricity on the detection signal line ET.
  • the display device may be: OLED panel, quantum dot panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc., any product or component with display function.
  • the embodiment of the present disclosure also provides a method for manufacturing an anti-corrosion circuit, which includes: as shown in FIG. 12, forming a conductive layer CL on the surface S; and patterning the conductive layer CL to form the edge as shown in FIG.
  • the first signal line L1, the second signal line L2, and the third signal line L3 are arranged in the first direction.
  • the first signal line L1, the second signal line L2, and the third signal line L3 all extend in the second direction.
  • the direction is different from the first direction.
  • Both the first signal line L1 and the third signal line L3 are adjacent to the second signal line L2.
  • the first signal line L1 and the second signal line L2 have the same electrical properties and the second signal line L2 It has a different electrical property from the third signal line L3.
  • the patterning process includes: coating a photoresist layer on the conductive layer CL; exposing the photoresist layer using a mask; developing the exposed photoresist layer to form a photoresist pattern; , The conductive layer CL is etched using the photoresist pattern to obtain the first signal line L1, the second signal line L2, and the third signal line L3.
  • the material of the conductive layer CL includes an aluminum metal layer.
  • the material of the conductive layer C1 includes a multilayer film structure.
  • the multilayer film structure includes the first metal layer M1, the second metal layer M2, and the third metal layer M3 as described above.
  • the multilayer film structure includes two stacked titanium metal layers and an aluminum metal layer sandwiched between the two.
  • FIG. 13 is a schematic top view of an array substrate provided by an embodiment of the disclosure.
  • the array substrate provided by at least one embodiment of the present disclosure includes a base substrate BS, a plurality of sub-pixels P, a plurality of source signal lines SL, a first power bus VDD, a plurality of sub power lines VDD0, and electrostatic discharge protection Circuit ESD.
  • the base substrate BS includes a display area AA and a peripheral area PA at least on one side of the display area AA.
  • the plurality of sub-pixels P are located in the display area AA.
  • the plurality of source signal lines SL are located in the display area AA, extend along a first direction and are sequentially arranged along a second direction different from the first direction, the plurality of source signal lines SL are electrically connected to the plurality of sub-pixels P, and It is configured to provide data signals to a plurality of sub-pixels P.
  • each source signal line SL is electrically connected to a column of sub-pixels P to provide data signals to the column of sub-pixels P.
  • the array substrate further includes a plurality of transfer lines TL located in the peripheral area PA, and the plurality of transfer lines TL are electrically connected to the plurality of source signal lines SL in a one-to-one correspondence, so that the plurality of source signal lines SL are respectively
  • the electrostatic discharge protection circuit ESD is electrically connected through the corresponding transfer line TL, so as to discharge static electricity through the electrostatic discharge protection circuit ESD.
  • the first power supply bus VDD is located in the peripheral area PA and includes a main body portion extending in the second direction.
  • the first power bus VDD further includes an extension portion extending from both ends of the main body portion and extending in the first direction.
  • the plurality of sub-power supply lines VDD0 are located in the display area AA and are electrically connected to the plurality of sub-pixels P, respectively, and are configured to provide the plurality of sub-pixels P with a first power signal.
  • each sub-power supply line VDD0 is electrically connected to a column of sub-pixels P to provide a first power signal to the column of sub-pixels P.
  • the first power bus VDD is electrically connected to the plurality of sub power lines VDD0 to provide a first power signal to the sub pixels P through the plurality of sub power lines VDD0.
  • the first power bus VDD0 provides the first power signal to the plurality of sub power lines VDD0
  • the plurality of sub power lines VDD0 provides the first power signal to the plurality of sub-pixels P.
  • the electrostatic discharge protection circuit ESD is located on the side of the main body part of the first power bus VDD away from the display area AA (that is, the main body part is located between the display area AA and the electrostatic discharge protection circuit ESD), and the electrostatic discharge protection circuit ESD is connected to multiple sources.
  • the polar signal line SL is electrically connected and includes a plurality of first sub-signal lines VGH ( Figure 13 shows VGH1 and VGH2 for illustration) and a plurality of second sub-signal lines VGL ( Figure 13 shows VGL1 and VGL2 for example Description), the plurality of first sub-signal lines VGH and the plurality of second sub-signal lines VGL extend along the second direction and are alternately arranged along the first direction, and the main part of the first power bus VDD is connected to one first sub-signal line VGH1 is adjacent, and the electrical properties of the first power bus VDD (that is, the main part of the first power bus VDD) are the same as the electrical properties of a first sub-signal line (see VGH1).
  • the array substrate provided by at least one embodiment of the present disclosure further includes a second power bus VSS.
  • the second power bus VSS is located in the peripheral area PA and is configured to provide a second power signal to a plurality of sub-pixels P.
  • the sub-pixel P includes a light-emitting element
  • the light-emitting element includes a positive electrode and a negative electrode
  • the first power bus VDD is configured to apply a first power signal to the positive electrode of the light-emitting element
  • the second power bus VSS is configured to apply a first power signal to the light-emitting element.
  • the negative pole applies the second power signal.
  • the array substrate further includes a circuit board PC (such as a printed circuit board), such as a flexible circuit board FPC, which is configured to provide a first power signal to the first power bus VDD and a second power signal to the second power bus VSS.
  • a circuit board PC such as a printed circuit board
  • FPC flexible circuit board
  • the main body portion of the first power bus VDD is adjacent to the first sub-signal line VGH1 means that the main body portion and the first sub-signal line VGH1 extend in the same direction, and the main body There is no other signal line extending in the same direction between the part and the first sub-signal line VGH1.
  • the first sub-signal line VGH1 and the second sub-signal line VGL1 adjacent to the first sub-signal line VGH1 have opposite electrical properties. That is, when the first sub signal line VGH1 and the second sub signal line VGL1 are electrically opposite to each other, the first sub signal line VGH1 having the same electrical property as that of the first power bus VDD is set to be the same as the first sub signal line VGH1.
  • the power bus VDD is adjacent.
  • the main part of the first power bus VDD extending in the second direction is the first signal line L1
  • the first sub-signal line VGH1 adjacent to the main part is the second signal line L2, which is connected to the first signal line L1.
  • the second sub-signal line VGL1 adjacent to the line VGH1 is the aforementioned third signal line L3.
  • the absolute value of the voltage difference between the first signal line L1 and the second signal line L2 is smaller than the absolute value of the voltage difference between the first signal line L1 and the third signal line L3.
  • the absolute value of the voltage difference between the first signal line L1 and the second signal line L2 is made smaller than the first signal line L1 and the first signal line L1 and the second signal line L2.
  • the absolute value of the voltage difference between the three signal lines L3 is beneficial to further avoid electrochemical corrosion between the main part of the first power bus VDD and the adjacent first sub-signal line VGH1.
  • the voltage of the first signal line L1, the voltage of the second signal line L2, and the voltage of the third signal line L3 are all constant voltages.
  • first signal line L1, the second signal line L2, and the third signal line L3 are located side by side on the same surface S, as shown in FIG. 1.
  • both the first signal line L1 and the second signal line L2 have positive electrical properties
  • the third signal line L3 has negative electrical properties
  • both the first signal line L1 and the second signal line L2 have negative electrical properties
  • the third signal line L3 has positive electrical properties
  • the material of at least one of the body portion of the first power bus VDD extending in the second direction and the first sub-signal line VGH1 adjacent thereto includes an aluminum metal layer.
  • At least one of the main body portion of the first power bus VDD and the first sub-signal line VGH1 has a multilayer film structure, as shown in FIG.
  • the metal layer M2 and the third metal layer M3, and the metal activity of the second metal layer M2 is greater than the metal activity of the first metal layer M1 and the third metal layer M3.
  • the size of the gap between the main body portion of the first power bus VDD and the first sub-signal line VGH1 in the first direction is less than or equal to 300 microns.
  • the electrostatic discharge protection circuit ESD also includes a first bus signal line B1 and a second bus signal line B2.
  • the signal lines (see VGL1-VGL2) are electrically connected to the second bus signal line B2.
  • the first bus signal line B1 and the second bus signal line B2 respectively receive different signals from the circuit board PC.
  • the first bus signal line B1 and the second bus signal line B2 are the high voltage signal line VGH0 and the low voltage signal line VGL0 in the embodiment shown in FIGS. 11A and 11B, respectively.
  • the electrostatic discharge protection circuit ESD includes a plurality of switch groups T0, each switch group T0 includes a first switch T1 and a second switch T2 sharing the same electrode, and the first switch T1 and the second switch T2 are electrically connected through the same electrode.
  • the same source signal line SL is used to discharge the static electricity on the power signal line SL, and different switch groups TO are electrically connected to different source signal lines SL.
  • the connection relationship between the first switch T1 and the second switch T2 please refer to the description of FIGS. 5A to 6.
  • the first switch T1 includes a first input terminal Vi1 and a first output terminal Vo1, the first input terminal Vi1 is electrically connected to the same source signal line SL, and the first output terminal Vo1 is electrically connected to the second signal line L2;
  • the second switch T2 includes a second input terminal Vi2 and a second output terminal Vo2.
  • the second input terminal Vi2 is electrically connected to the third signal line L1, and the second output terminal Vo2 is electrically connected to the same source signal line SL.
  • the first switch T1 is a first transistor, the first transistor includes a first gate G1, a first electrode S1, and a second electrode D1.
  • the first electrode S1 serves as the first input terminal Vi1, and the second electrode D1 is electrically connected to the first
  • the gate G1 serves as the first output terminal Vo1;
  • the second switch T2 is a second transistor, the second transistor includes a second gate G2, a third pole S2, and a fourth pole D2, and the third pole S2 serves as a second input terminal Vi2
  • the fourth electrode D2 is electrically connected to the second gate G2 and serves as the second output terminal Vo2.
  • the source signal line SL and the electrostatic discharge protection circuit ESD may adopt the embodiment shown in FIG. 7.
  • the main part of the first power bus VDD is the first high voltage in the embodiment shown in FIG.
  • the signal line VDD is the first high voltage in the embodiment shown in FIG.
  • the plurality of source signal lines SL includes signal line groups sequentially arranged along the second direction, and each signal line group includes first source signal lines SL1 and second source signal lines SL1 and second The source signal line SL2, the third source signal line SL2, and the fourth source signal line SL4;
  • the electrostatic discharge protection circuit ESD includes a plurality of switch groups T0 including a first switch group T01 and a second switch group T01 and The switch group T02, the third switch group T03, and the fourth switch group T04.
  • the first switch group T01 is electrically connected to the first source signal line SL1 to discharge static electricity on the first source signal line SL1.
  • the second switch group T02 is connected to the first source signal line SL1.
  • a switch group T01 is adjacent to and electrically connected to the second source signal line SL2 to discharge static electricity on the second source signal line SL2, and a third switch group T03 is adjacent to the second switch group T02 and electrically connected to the third source signal Line SL3 to discharge the static electricity on the third source signal line SL3, the fourth switch group T04 is adjacent to the third switch group T03 and electrically connected to the fourth source signal line SL4 to discharge the static electricity on the fourth source signal line SL4 .
  • the schematic partial cross-sectional view of each layer structure of the array substrate in the display area may refer to FIG. 14, and the schematic top view of each layer structure of the array substrate in the peripheral area PA may refer to FIG. 7 to FIG. 8C.
  • the array substrate includes a first gate metal layer GM1, a second gate metal layer GM2, and a source-drain metal layer SD sequentially located on a base substrate BS.
  • the first gate metal layer GM1 includes a part of a plurality of source signal lines SL (for example, includes a plurality of second source signal lines SL2 and a plurality of fourth source signal lines SL4 as shown in FIGS.
  • the second gate metal layer includes another part of the plurality of source signal lines SL (for example, includes a plurality of first source signal lines SL1 and a plurality of third source signal lines SL3 as shown in FIGS. 7 and 8C);
  • the source drain metal layer SD includes a main body portion of the first power bus VDD extending in the second direction, a plurality of sub power lines VDD0, a plurality of first sub signal lines VGH (see VGH1-VGH2), and a plurality of second sub signal lines VGL (See VGL1-VGL 2).
  • the source-drain metal layer SD does not include the transfer line TL, that is, the transfer line TL is located outside the source-drain metal layer SD, so as to prevent the transfer line TL from being electrically connected to the main part of the first power bus VDD.
  • the transfer line TL is located in the first gate metal layer GM1 or the second gate metal layer GM2.
  • At least one sub-pixel of the array substrate provided by at least one embodiment of the present disclosure includes a plurality of pixel switches PT (FIG. 14 only shows one pixel switch PT for illustration), and each sub-pixel has more than one pixel switch PT.
  • a pixel switch PT is electrically connected to the light-emitting element in the sub-pixel, and each pixel switch PT includes an active layer AL, a gate G, a first electrode E1 and a second electrode E2, one of the first electrode E1 and the second electrode E2 One is the source and the other is the drain.
  • the first pole E1 and the second pole E2 of the pixel switch PT are located on the insulating layer ILD and are sequentially covered by the passivation insulating layer PVX and the planarizing insulating layer PLN.
  • the light emitting member L includes an anode AN, a light emitting layer EL, and a cathode CA, and the anode AN of the light emitting member L is electrically connected to the first electrode E1 of the pixel switch PT.
  • the anode AN of the light-emitting element L is electrically connected to the first electrode E1 of the pixel switch PT through a via hole penetrating the passivation insulating layer PVX and the planarization insulating layer PLN.
  • adjacent light-emitting elements L are separated by a pixel definition layer PDL.
  • the pixel definition layer PDL is further provided with an organic layer PS including a plurality of spacers to better separate adjacent light-emitting elements L.
  • the array substrate provided by at least one embodiment of the present disclosure further includes an encapsulation layer for encapsulating the light emitting element L.
  • the encapsulation layer includes inorganic encapsulation layers IEP1 and IEP2 and an organic encapsulation layer OEP located between the inorganic encapsulation layers IEP1 and IEP2.
  • the encapsulation layer may include a plurality of organic encapsulation layers and a plurality of inorganic encapsulation layers, and the plurality of organic encapsulation layers and the plurality of inorganic encapsulation layers are alternately arranged.
  • the anti-corrosion circuit and the manufacturing method thereof, the array substrate and the electronic device provided in the embodiments of the present disclosure can have the same arrangement of the same components in the embodiments.

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Abstract

一种防腐蚀电路、阵列基板和电子装置，该阵列基板包括：多个源极信号线，位于显示区、沿第一方向延伸且沿第二方向依次排列；第一电源总线，位于周边区且包括沿第二方向延伸的主体部分；静电释放保护电路，位于第一电源总线的主体部分远离显示区的一侧，与多个源极信号线电连接，并且包括多个第一子信号线和多个第二子信号线。多个第一子信号线和多个第二子信号线沿第二方向延伸且沿第一方向交替排列，第一电源总线的主体部分与一个第一子信号线相邻，并且第一电源总线的电性与该一个第一子信号线的电性相同。该阵列基板可以防止电化学腐蚀。

Description

防腐蚀电路、阵列基板和电子装置 技术领域
本公开的实施例涉及一种防腐蚀电路、阵列基板和电子装置。
背景技术
有机电致发光二极管(OLED，Organic Light-Emitting Diode)是将电能直接转换成光能的全固体器件，因其具有薄而轻、高对比度、快速响应、宽视角、宽工作温度范围等优点而引起人们的极大关注。类似的主动发光元件还有量子点发光二极管等。
发明内容
本公开至少一个实施例提供一种阵列基板，其包括：衬底基板，包括显示区和至少位于所述显示区一侧的周边区；多个子像素，位于所述显示区；多个源极信号线，位于所述显示区且分别与所述多个子像素电连接，并且被配置为向所述多个子像素提供数据信号，其中，所述多个源极信号线沿第一方向延伸且沿不同于所述第一方向的第二方向依次排列；第一电源总线，位于所述周边区并且包括沿所述第二方向延伸的主体部分；多个子电源线，位于所述显示区且分别与所述多个子像素电连接，并且被配置为向所述多个子像素提供第一电源信号，其中，所述第一电源总线与所述多个子电源线电连接；静电释放保护电路，位于所述第一电源总线的所述主体部分远离所述显示区的一侧，与所述多个源极信号线电连接，并且包括多个第一子信号线和多个第二子信号线，其中，所述多个第一子信号线和所述多个第二子信号线沿所述第二方向延伸且沿所述第一方向交替排列，所述第一电源总线的所述主体部分与一个第一子信号线相邻，并且所述第一电源总线的电性与所述一个第一子信号线的电性相同。
例如，所述静电释放保护电路还包括第一母信号线和第二母信号线，所述多个第一子信号线电连接所述第一母信号线，所述多个第二子信号线电连接所述第二母信号线。
例如，所述静电释放保护电路包括多个开关组，每个开关组包括共用同一电极的第一开关和第二开关，所述第一开关和所述第二开关通过所述共用的同一电极电连接同一源极信号线，并且不同的开关组电连接不同的源极信号线。
例如，所述第一电源总线的所述主体部分为第一信号线，与所述主体部分相邻的所述一个第一子信号线为第二信号线，并且与所述第二信号线相邻的第二子信号线为第三信号线；所述第一开关包括第一输入端和第一输出端，所述第一输入端与所述同一源极信号线电连接，并且所述第一输出端与所述第二信号线电连接；所述第二开关包括第二输入端和第二输出端，所述第二输入端与所述第三信号线电连接，并且所述第二输出端与所述同一源极信号线电连接。
例如，所述第一开关为第一晶体管，所述第一晶体管包括第一栅极、第一极和第二极， 所述第一极作为所述第一输入端，所述第二极电连接所述第一栅极且作为所述第一输出端；所述第二开关为第二晶体管，所述第二晶体管包括第二栅极、第三极和第四极，所述第三极作为所述第二输入端，所述第四极电连接所述第二栅极且作为所述第二输出端。
例如，所述第一信号线与所述第二信号线之间的电压差的绝对值小于所述第一信号线与所述第三信号线之间的电压差的绝对值。
例如，所述第一信号线和所述第二信号线都具有正电性，并且所述第三信号线具有负电性。
例如，所述第一信号线和所述第二信号线都具有负电性，并且所述第三信号线具有正电性。
例如，所述第一信号线的电压、所述第二信号线的电压和所述第三信号线的电压都为恒定电压。
例如，所述第一信号线、所述第二信号线和所述第三信号线并排位于同一表面上。
例如，所述多个源极信号线包括沿所述第二方向依次排列的信号线组，每个信号线组包括沿所述第二方向依次排列的第一源极信号线、第二源极信号线、第三源极信号线和第四源极信号线；所述静电释放保护电路包括的所述多个开关组包括沿所述第一方向依次排列的第一开关组、第二开关组、第三开关组和第四开关组，所述第一开关组电连接所述第一源极信号线，所述第二开关组电连接所述第二源极信号线，所述第三开关组电连接所述第三源极信号线，所述第四开关组电连接所述第四源极信号线。
例如，所述阵列基板包括依次位于所述衬底基板上的第一栅金属层、第二栅金属层和源漏金属层，所述第一栅金属层包括所述多个源极信号线中的一部分，所述第二栅金属层包括所述多个源极信号线中的另一部分，所述源漏金属层包括所述第一电源总线的所述主体部分、所述多个子电源线、所述多个第一子信号线和所述多个第二子信号线。
例如，所述多个子像素中的至少一个包括多个像素开关，每个像素开关包括栅极、第一极和第二极；所述栅极位于所述第一栅金属层或所述第二栅金属层中，所述第一极和所述第二极位于源漏金属层中。
例如，所述第一电源总线的所述主体部分和所述一个第一子信号线中的至少一个的材料包括铝金属。
例如，所述第一电源总线的所述主体部分和所述一个第一子信号线中的至少一个为多层膜结构，所述多层膜结构包括依次层叠的第一金属层、第二金属层和第三金属层，所述第二金属层的金属活泼性大于所述第一金属层和所述第三金属层的金属活泼性。
例如，所述第一电源总线的所述主体部分和所述一个第一子信号线的电压都为恒定电压。
例如，所述第一电源总线的所述主体部分和所述一个第一子信号线之间的间隙在所述第一方向上的尺寸小于或等于300微米。
例如，所述的阵列基板还包括第二电源总线，所述第二电源总线位于所述周边区并且被配置为向所述多个子像素提供第二电源信号。
本公开至少一个实施例提供一种防腐蚀电路，其包括沿第一方向依次排列的第一信号线、第二信号线和第三信号线；所述第一信号线、所述第二信号线和所述第三信号线都沿第二方向延伸，所述第二方向不同于所述第一方向；所述第一信号线和所述第三信号线都与所述第二信号线相邻。所述第二信号线与所述第一信号线具有相同的电性，并且所述第二信号线与所述第三信号线具有不同的电性。
例如，所述第一信号线与所述第二信号线之间的电压差的绝对值小于所述第一信号线与所述第三信号线之间的电压差的绝对值。
例如，所述第一信号线和所述第二信号线都具有正电性，并且所述第三信号线具有负电性。
例如，所述第一信号线和所述第二信号线都具有负电性，并且所述第三信号线具有正电性。
例如，所述第一信号线的电压、所述第二信号线的电压和所述第三信号线的电压都为恒定电压。
例如，所述第一信号线、所述第二信号线和所述第三信号线并排位于同一表面上。
例如，所述第一信号线和所述第二信号线中的至少一个的材料包括铝金属层。
例如，所述第一信号线和所述第二信号线中的至少一个为多层膜结构，所述多层膜结构包括依次层叠的第一金属层、第二金属层和第三金属层，所述第二金属层的金属活泼性大于所述第一金属层和所述第三金属层的金属活泼性。
例如，所述的防腐蚀电路包括彼此间隔开的第一子电路和第二子电路，所述第一信号线和所述第二信号线中的一者属于所述第一子电路，所述第一信号线和所述第二信号线中的另一者属于所述第二子电路。
例如，所述第二子电路为静电释放保护电路，所述静电释放保护电路包括所述第一信号线和所述第二信号线中的所述另一者以及所述第三信号线。
例如，所述静电释放保护电路包括依次排列的第一母信号线和第二母信号线；所述静电释放保护电路还包括依次排列的多个第一子信号线和多个第二子信号线，所述多个第一子信号线电连接所述第一母信号线，所述多个第二子信号线电连接所述第二母信号线；并且所述第一信号线和所述第二信号线中的所述另一者属于所述第一母信号线、所述第二母信号线、所述多个第一子信号线或者所述多个第二子信号线。
例如，所述防腐蚀电路包括被保护信号线，所述被保护信号线与所述静电释放保护电路电连接；所述静电释放保护电路包括第一开关和第二开关；所述第一开关包括第一输入端和第一输出端，所述第一输入端与所述被保护信号线电连接，并且所述第一输出端与所述第一信号线和所述第二信号线中的所述另一者电连接；所述第二开关包括第二输入端和第二输出端，所述第二输入端与所述第三信号线电连接，并且所述第二输出端与所述被保护信号线电连接。
例如，所述第一开关为第一晶体管，所述第一晶体管包括第一栅极、第一极和第二极，所述第一极作为所述第一输入端，所述第二极电连接所述第一栅极且作为所述第一输出 端；所述第二开关为第二晶体管，所述第二晶体管包括第二栅极、第三极和第四极，所述第三极作为所述第二输入端，所述第四极电连接所述第二栅极且作为所述第二输出端。
例如，所述静电释放保护电路包括所述第二信号线以及所述第三信号线，所述第二信号线为所述多个第一子信号线之一，并且所述第三信号线为所述多个第二子信号线之一。
例如，所述第一信号线与所述第二信号线之间的间隙在所述第一方向上的尺寸小于或等于300微米。
例如，所述静电释放保护电路包括所述第一信号线以及所述第三信号线，所述第一信号线为所述第一母信号线，并且所述第三信号线为所述第二母信号线。
例如，所述第一信号线和所述第二信号线之间的间隙在所述第一方向上的尺寸小于或等于60微米。
本公开至少一个实施例还提供一种电子装置，其包括以上任一项实施例所述的阵列基板或以上任一项实施例所述的防腐蚀电路。
例如，所述的电子装置包括：像素基板，其包括多个子像素；电路板，其与所述像素基板的一侧连接。在所述电子装置包括所述防腐蚀电路的情况下，所述电路板被配置为向所述第一信号线、所述第二信号线和所述第三信号线提供信号，所述防腐蚀电路的所述第二信号线和所述第三信号线位于所述电路板与所述像素基板之间，所述防腐蚀电路的所述第一信号线位于所述第二信号线的面向所述像素基板的一侧。
例如，所述的电子装置包括：像素基板，其包括多个子像素；电路板，其与所述像素基板的一侧连接；以及检测电路，其位于所述电路板的远离所述像素基板的一侧。所述检测电路为所述防腐蚀电路，所述防腐蚀电路的所述第一信号线和所述第三信号线位于所述电路板的远离所述像素基板的一侧，所述第二信号线被配置为向所述多个子像素提供重置信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开实施例提供的防腐蚀电路中第一信号线、第二信号线和第三信号线的位置关系简化示意图。
图2为本公开实施例提供的防腐蚀电路中信号线的多层膜结构示意图。
图3为本公开实施例提供的防腐蚀电路包括第一子电路和第二子电路的示意图。
图4A和图4B为本公开实施例提供的防腐蚀电路中静电释放保护电路包括的母信号线和子信号线的简化示意图。
图5A为本公开实施例提供的防腐蚀电路中静电释放保护电路的等效电路图。
图5B为图5A所示静电释放保护电路释放正电荷的原理图。
图5C为图5A所示静电释放保护电路释放负电荷的原理图。
图6为本公开实施例提供的防腐蚀电路中的静电释放保护电路的另一种等效电路图。
图7为本公开实施例提供的防腐蚀电路的俯视示意图一。
图8A为图7所示防腐蚀电路包括的半导体层的俯视示意图。
图8B为图7所示防腐蚀电路包括的半导体层和第一栅金属层的俯视示意图。
图8C为图7所示防腐蚀电路包括的半导体层、第一栅金属层和第二栅金属层的俯视示意图。
图9A为图7所示防腐蚀电路的局部放大示意图。
图9B为沿图9A中的A-A线的剖视示意图。
图10A为本公开实施例提供的防腐蚀电路的俯视示意图二。
图10B为图10A中区域A的局部放大示意图。
图10C为图10B中区域C的局部放大示意图。
图10D为图10A中区域B的局部放大示意图。
图11A和图11B为本公开实施例提供的电子装置的俯视示意图。
图12为本公开实施例提供的防腐蚀电路的制作方法中形成导电层的示意图；
图13为本公开实施例提供的阵列基板的俯视示意图；
图14为本公开实施例提供的阵列基板在显示区的局部剖视示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在显示行业，随着技术的不断发展，OLED显示产品尤其是柔性OLED显示产品的市场越来越大。为了在未来的市场竞争中占有一定的比重，企业对OLED显示产品良率的提升越发地看重；而且，企业越来越追求较小的下边框(即“窄下巴”)，以实现屏占比更大的显示产品。在这样的背景下，目前的OLED显示产品的电路具有的不同功能模块之间被设置得较之前更加紧密，走线之间的空间被极大的压缩。然而，目前的OLED显示产品的电路容易出现局部短路或开路现象。
本申请的发明人在研究中发现，目前的OLED显示产品的电路出现局部短路或开路 的原因之一是：电路中某些相邻走线之间存在较大的电场，在高温高湿的条件下这些走线容易发生电化学腐蚀。
针对上述发现，本申请的发明人提出一种防腐蚀电路及其制作方法、阵列基板、以及包括该防腐蚀电路或阵列基板的电子装置。
图1为本公开实施例提供的防腐蚀电路中第一信号线、第二信号线和第三信号线的位置关系简化示意图。例如，第一信号线、第二信号线和第三信号线属于静电释放保护电路，参见图7和图13所示实施例；或者第一信号线、第二信号线和第三信号线属于检测电路，参见图10A所示实施例。如图1、图7、图10A和图13所示，本公开实施例提供一种防腐蚀电路AC，该防腐蚀电路AC包括位于表面S的同一侧的第一信号线L1、第二信号线L2和第三信号线L3，第一信号线L1、第二信号线L2和第三信号线L3沿第一方向依次排列且都大致沿第二方向延伸(“大致”指的是忽略制作工艺导致的误差的影响)，第二方向不同于第一方向；第一信号线L1和第三信号线L3都与第二信号线L2相邻，即距离第二信号线L2的一侧最近的信号线为第一信号线L1且距离第二信号线L2的另一侧最近的信号线为第三信号线L3(也就是说，第一信号线L1和第三信号线L3中的每个与第二信号线L2之间都未设置其它信号线)。第二信号线L2与第一信号线L1具有相同的电性，并且第二信号线L2与第三信号线L3具有不同的电性。
需要说明的是，相同的电性指的是都为正电性或者都为负电性或者都为0；不同的电性指的是其中一者为正电性且另一者为负电性或0，或者其中一者为负电性且另一者为正电性或0。
对于具有给定电压且依次排列的第一信号线L1、第二信号线L2和第三信号线L3来说，如果将第一信号线L1与第三信号线L3相邻，则由于第一信号线L1与第三信号线L3具有不同的电性导致第一信号线L1与第三信号线L3之间容易发生电化学腐蚀。在本公开实施例中，第一信号线L1与第二信号线L2相邻；在此基础上，在第一信号线L1与第二信号线L2具有的相同电性不同于第三信号线L3的电性的情况下，与将第一信号线L1与第三信号线L3相邻的方式相比，本公开实施例有利于避免第一信号线L1与第二信号线L2之间发生电化学腐蚀(尤其是在高温高湿条件下)，即有利于避免第一信号线L1和第二信号线L2被腐蚀。在一些实施例中，由于第一信号线L1与第二信号线L2之间不容易发生电化学腐蚀，因此第一信号线L1与第二信号线L2之间的距离可以设计得更小，以窄化面板的边框(例如下边框)，从而提高屏占比，因此本公开一些实施例可以在实现窄边框设计的同时改善局部短路或开路。
例如，为了进一步避免第一信号线L1和第二信号线L2之间发生电化学腐蚀，在第二信号线L2与第一信号线L1具有相同的电性，并且第二信号线L2与第三信号线L3具有不同的电性的基础上，第一信号线L1与第二信号线L2之间的电压差的绝对值小于第一信号线L1与第三信号线L3之间的电压差的绝对值。
需要说明的是，图1、图7、图10A和图13以第二方向与第一方向垂直为例进行说明；在其他实施例中，第一方向与第二方向也可以不垂直。另外，在本公开实施例中，一 个信号线与另一个信号线相邻是指，该一个信号线与该另一个信号线沿同一方向延伸，并且这两个信号线之间未设置沿该同一方向延伸的其它信号线。
例如，在本公开一些实施例中，根据第一信号线L1与第二信号线L2具有的相同电性不同于第三信号线L3的电性可以得出：第二信号线L2的电压不同于第三信号线L3的电压，并且第一信号线L1的电压和第二信号线L2的电压都大于或者都小于第三信号线L3的电压(需要说明的是，正电压大于负电压)。例如，第一信号线L1的电压大于第二信号线L2的电压，并且第二信号线L2的电压大于第三信号线L3的电压；或者，第一信号线L1的电压小于第二信号线L2的电压，并且第二信号线L2的电压小于第三信号线L3的电压。第一信号线L1、第二信号线L2和第三信号线L3之间的电压关系包括但不限于所列举的这些实施例。
例如，在第二信号线L2与第一信号线L1具有相同的电性，并且第二信号线L2与第三信号线L3具有不同的电性的情况下，第一信号线L1和第二信号线L2都具有正电性，并且第三信号线L3具有负电性。例如，第一信号线L1的电压与第二信号线L2的电压都为正电压，并且第三信号线L3的电压为负电压；或者，第一信号线L1的电压与第二信号线L2的电压都为负电压，并且第三信号线L3的电压为正电压。
例如，第一信号线L1的电压为正电压，第二信号线L2的电压为正电压，并且第三信号线L3的电压为负电压；或者，第一信号线L1的电压为负电压，第二信号线L2的电压为负电压，并且第三信号线L3的电压为正电压。
例如，第一信号线L1的电压、第二信号线L2的电压和第三信号线L3的电压都为恒定电压。本申请的发明人发现，电化学腐蚀现象容易发生在相邻的信号线都被施加恒定电压的情况下。与第一信号线L1与第三信号线L3相邻的设置方式相比，即使本公开实施例中第一信号线L1的电压、第二信号线L2的电压和第三信号线L3的电压都为恒定电压，由于第一信号线L1与第二信号线L2具有相同的电性，第一信号线L1与第二信号线L2之间也不容易发生电化学腐蚀。
例如，第一信号线L1、第二信号线L2和第三信号线L3并排位于同一表面S上，即第一信号线L1、第二信号线L2和第三信号线L3直接接触承载其的同一表面S。本申请的发明人发现，电化学腐蚀现象容易发生在相邻的信号线并排位于同一表面的情况下。与第一信号线L1、第三信号线L3和第二信号线L2依次并排位于同一表面上的设置方式相比，本公开实施例由于交换了第二信号线L2和第三信号线L3的位置，交换后相邻的第一信号线L1与第二信号线L2具有相同的电性，因此，即使第一信号线L1、第二信号线L2和第三信号线L3并排位于同一表面S上，交换后相邻的第一信号线L1与第二信号线L2之间也不容易发生电化学腐蚀。
例如，第一信号线L1、第二信号线L2和第三信号线L3可以通过这样的方式形成：在表面S上形成导电层，之后对该导电层进行图案化处理以形成并排位于表面S上的第一信号线L1、第二信号线L2和第三信号线L3。
例如，第一信号线L1和第二信号线L2中的至少一个的材料包括铝金属层。例如， 用于形成第一信号线L1、第二信号线L2和第三信号线L3的上述导电层具有铝金属层，在这种情况下，第一信号线L1、第二信号线L2和第三信号线L3的材料都包括铝金属层。本申请的发明人发现，铝金属由于金属活泼性比较强从而容易发生电化学腐蚀。在本公开实施例中，即使第一信号线L1和第二信号线L2中的至少一个的材料包括铝金属层，由于第一信号线L1与第二信号线L2具有相同的电性，第一信号线L1与第二信号线L2之间也不容易发生电化学腐蚀。
图2为本公开实施例提供的防腐蚀电路中信号线的多层膜结构示意图。例如，如图2所示，第一信号线L1和第二信号线L2中的至少一个为多层膜结构，该多层膜结构包括在垂直于上述表面S的方向上依次层叠的第一金属层M1、第二金属层M2和第三金属层M3，并且第二金属层M2的金属活泼性大于第一金属层M1和第三金属层M3的金属活泼性。例如，用于形成第一信号线L1、第二信号线L2和第三信号线L3的上述导电层具有该多层膜结构，在这种情况下，第一信号线L1、第二信号线L2和第三信号线L3都具有多层膜结构。例如，第一金属层M1为钛金属层，第二金属层M2为铝金属层，第三金属层M3为钛金属层。采用多层膜结构制作第一信号线L1、第二信号线L2和第三信号线L3，有利于使这些信号线具有较好的电学性能。
图3为本公开实施例提供的防腐蚀电路包括第一子电路和第二子电路的示意图。例如，如图3所示，本公开至少一个实施例提供的防腐蚀电路AC包括彼此间隔开的第一子电路C1和第二子电路C2，第一信号线L1和第二信号线L2中的一者属于第一子电路C1，第一信号线L1和第二信号线L2中的另一者属于第二子电路C2。例如，如图3所示，第一信号线L1属于第一子电路C1，第二信号线L2属于第二子电路C2。在本公开实施例中，由于第一信号线L1和第二信号线L2中的一者属于第一子电路C1，第一信号线L1和第二信号线L2中的另一者属于第二子电路C2，并且由于第一信号线L1和第二信号线L2之间不容易产生电化学腐蚀，因此第一子电路C1与第二子电路C2可以排列得比较紧密，这有利于实现窄边框设计。
例如，如图3所示，第二子电路C2为用于释放静电的静电释放保护电路ESD，静电释放保护电路ESD包括第一信号线L1和第二信号线L2中的所述另一者以及第三信号线L3。图3以静电释放保护电路ESD包括第二信号线L2和第三信号线L3为例进行说明。在另一些实施例中，静电释放保护电路ESD包括第一信号线L1和第三信号线L3。在其他实施例中，第二子电路C2也可以不是静电释放保护电路。
图4A和图4B为本公开实施例提供的防腐蚀电路中静电释放保护电路包括的母信号线和子信号线的简化示意图，图4A所示实施例中的子信号线的设置方式可以参考图7所示实施例；图4A所示实施例中的母信号线和子信号线应用于阵列基板时可以参考图13所示实施例，图4B所示实施例应用于检测电路时可以参考图10A和图10B所示实施例。例如，如图4A和图4B所示，静电释放保护电路ESD包括多个第一子信号线Su1(例如参见图7、图13和图10A-10B中的VGH，图13仅示意性地示出了两个VGH但并不反映真实尺寸)和多个第二子信号线Su2(例如参见图7、图13和图10A-10B中的VGL，图 13仅示意性地示出了两个VGL但并不反映真实尺寸)，该多个第一子信号线Su1与该多个第二子信号线Su2交替设置，例如相邻的第一子信号线Su1之间有一个第二子信号线Su2，并且相邻的第二子信号线Su2之间有一个第一子信号线Su1。例如，如图4A、图7和图13所示，该多个第一子信号线Su1和该多个第二子信号线Su2沿第一方向依次排列且都沿第二方向延伸；或者，如图4B和图10A-10B所示，该多个第一子信号线Su1和该多个第二子信号线Su2沿第二方向依次排列且都沿第一方向延伸。
例如，如图4A-4B、图13和图10A-10B所示，静电释放保护电路ESD包括依次排列的第一母信号线B1和第二母信号线B2，例如子信号线的排列方向不同于上述母信号线的排列方向；该多个第一子信号线Su1电连接第一母信号线B1，例如第一子信号线Su1的端部电连接第一母信号线B1(如图4A和图13所示)或者第一子信号线Su1的两个端部之间的部分电连接第一母信号线B1(如图4B和图10A-10B所示，图4B中的黑色圆点表示电连接)；该多个第二子信号线Su2电连接第二母信号线B2，例如第二子信号线Su2的端部电连接第二母信号线B2(如图4A和图13所示)或者第二子信号线Su2的两个端部之间的部分电连接第二母信号线B2(如图4B和图10A-10B所示)。第二子电路C2(如图3所示)包括的第一信号线L1和第二信号线L2中的所述另一者属于第一母信号线B1、第二母信号线B2、多个第一子信号线Su1或者多个第二子信号线Su2。
例如，第一母信号线B1被配置为向所述多个第一子信号线Su1施加第一恒定电压，第二母信号线B2被配置为向所述多个第二子信号线Su2施加不同于第一恒定电压的第二恒定电压。例如，第一恒定电压大于第二恒定电压。也就是说，第一母信号线B1、第一子信号线Su1、第二母信号线B2和第二子信号线Su2在工作时都被施加恒定电压，并且第一母信号线B1的恒定电压大于第二母信号线B2的恒定电压，从而第一子信号线Su1的恒定电压大于第二子信号线Su2的恒定电压。
例如，如图4A和图13所示，静电释放保护电路ESD包括第二信号线L2以及第三信号线L3，第二信号线L2为多个第一子信号线Su1之一，并且第三信号线L3为多个第二子信号线Su2之一。例如，在图4A中，最外侧的第一子信号线Su1为第二信号线L2，并且与该第一子信号线Su1相邻的第二子信号线Su2为第三信号线L3，在这种情况下，第一信号线L1(图4A中未示出)位于该第一子信号线Su1/L2的远离第二子信号线Su2/L3的一侧。
例如，在最外侧的第一子信号线Su1为第二信号线L2，并且与该第一子信号线Su1相邻的第二子信号线Su2为第三信号线L3的情况下，第一信号线L1在表面S上的正投影与第二信号线L2在表面S上的正投影之间的间隙在第一信号线L1和第二信号线L2的排列方向(即上述第一方向)上的尺寸小于或等于300微米。例如，该尺寸小于或等于200微米。例如，该尺寸小于或等于100微米。与第一信号线L1与第三信号线L3相邻的设置方式相比，本公开实施例中相邻的第一信号线L1与第二信号线L2之间的距离较小，从而有利于窄边框设计。
例如，如图4B和图10A所示，静电释放保护电路ESD包括第一信号线L1以及第三 信号线L3，第一信号线L1为第一母信号线B1，并且第三信号线L3为第二母信号线B2。在这种情况下，第二信号线L2(图4B中未示出)位于第一母信号线B1/L1与第二母信号线B2/L3之间。
例如，在第一信号线L1为第一母信号线B1，并且第三信号线L3为第二母信号线B2的情况下，第一信号线L1在表面S上的正投影和第二信号线L2在表面S上的正投影之间的间隙在第一信号线L1和第二信号线L2的排列方向(即上述第一方向)上的尺寸小于或等于60微米。例如，该尺寸大于或等于50微米并且小于或等于60微米。
图5A为本公开实施例提供的防腐蚀电路中静电释放保护电路的等效电路图；图5B为图5A所示静电释放保护电路释放正电荷的原理图；图5C为图5A所示静电释放保护电路释放负电荷的原理图。例如，如图5A所示，防腐蚀电路包括被保护信号线SL和与被保护电路电连接的静电释放保护电路ESD(图5A中未标出)，静电释放包括电路ESD包括开关组，该开关组包括第一开关T1和第二开关T2；第一开关T1包括第一输入端Vi1和第一输出端Vo1，第一输入端Vi1与被保护信号线SL电连接，并且第一输出端Vo1电连接第一信号线L1或第二信号线L2；第二开关T2包括第二输入端Vi2和第二输出端Vo2，第二输入端Vi2与第三信号线L3电连接，并且第二输出端Vo2与被保护信号线SL电连接。被保护信号线SL上的静电可以通过第一开关T1、第二开关T2、第一信号线L1/第二信号线L2、以及第三信号线L3释放出去，以避免被保护信号线SL上积累较多的静电。
例如，该静电释放保护电路ESD的工作原理如下：当被保护信号线SL上的静电荷为正电荷且被保护信号线SL上的静电过大时，第一开关T1打开，这样正电荷就会通过第一信号线L1或第二信号线L2释放出去，如图5B所示(图中的箭头表示电流流向)；当被保护信号线SL上的静电荷为负电荷且被保护信号线SL上的静电过大时，第二开关T2打开，这样负电荷就会通过第三信号线L3释放出去，如图5C所示(图中的箭头表示电流流向)。
图6为本公开实施例提供的防腐蚀电路中的静电释放保护电路的另一种等效电路图。例如，如图6所示，第一开关T1为第一晶体管，第一晶体管包括第一栅极G1、第一极S1和第二极D1，第一极S1作为第一输入端Vi1，第二极D1电连接第一栅极G1且作为第一输出端Vo1；第二开关T2为第二晶体管，第二晶体管包括第二栅极G2、第三极S2和第四极D2，第三极S2作为第二输入端Vi2，第四极D2电连接第二栅极G2且作为第二输出端Vo2。例如，第一晶体管和第二晶体管都为P型晶体管。
图7为本公开实施例提供的防腐蚀电路的俯视示意图一；图8A为图7所示防腐蚀电路包括的半导体层的俯视示意图；图8B为图7所示防腐蚀电路包括的半导体层和第一栅金属层的俯视示意图；图8C为图7所示防腐蚀电路包括的半导体层、第一栅金属层和第二栅金属层的俯视示意图。
例如，如图7所示，静电释放保护电路ESD包括多个开关组T0，每个开关组T0包括共用同一电极的第一开关T1和第二开关T2(T1与T2的电连接关系详见上文中的相关描述)，第一开关T1和第二开关T2通过共用的同一电极电连接同一源极信号线SL，从 而该源极信号线SL通过与其对应连接的开关组T0释放静电，并且不同的开关组T0电连接不同的源极信号线SL。
例如，如图7所示，防腐蚀电路AC中的多个源极信号线SL包括沿第二方向依次排列的信号线组，每个信号线组包括沿第二方向依次排列的第一源极信号线SL1、第二源极信号线SL2、第二源极信号线SL2和第四源极信号线SL4；静电释放保护电路ESD包括的多个开关组T0包括沿第一方向依次排列的第一开关组T01、第二开关组T02、第三开关组T03和第四开关组T04，第一开关组T01电连接第一源极信号线SL1以释放第一源极信号线SL1上的静电，第二开关组T02与第一开关组T01相邻并且电连接第二源极信号线SL2以释放第二源极信号线SL2上的静电，第三开关组T03与第二开关组T02相邻并且电连接第三源极信号线SL3以释放第三源极信号线SL3上的静电，第四开关组T04与第三开关组T03相邻并且电连接第四源极信号线SL4以释放第四源极信号线SL4上的静电。例如，静电释放保护电路ESD包括的开关组T01-T04周期性地重复；相应地，第一源极信号线SL1至第四源极信号线SL4也周期性地重复。
例如，如图7所示，本公开至少一个实施例提供的防腐蚀电路AC包括半导体层SM、第一栅金属层GM1、第二栅金属层GM2和源漏金属层SD。如图7和图8A，半导体层SM包括间隔开的多个半导体线SML，该多个半导体线SML都沿第一方向延伸并且沿第二方向依次排列。如图7和图8B所示，第一栅金属层GM1包括多个栅极组，每个栅极组包括沿第一方向依次排列的第一栅极G1和第二栅极G2，同一栅极组包括的第一栅极G1和第二栅极G2与同一半导体线SML交叠；第一栅金属层GM1还包括多个源极信号线SL中的一部分，例如，第一栅金属层GM1包括多个第二源极信号线SL2和多个第四源极信号线SL4，该多个第二源极信号线SL2和该多个第四源极信号线SL4都沿第一方向延伸且沿第二方向依次排列。如图7和图8C所示，第二栅金属层GM2包括多个源极信号线SL中的另一部分，例如，第二栅金属层GM2包括多个第一源极信号线SL1和多个第三源极信号线SL3，该多个第一源极信号线SL1和该多个第三源极信号线SL3沿第二方向依次排列且沿第一方向延伸。如图7所示，源漏金属层SD包括一个第一高电压信号线VDD、多个第二高电压信号线VGH(参见VGH1-VGH3)以及多个低电压信号线VGL(参见VGL1-VGL2)，这些信号线沿第一方向依次排列并且都沿第二方向延伸，该多个第二高电压信号线VGH与该多个低电压信号线VGL交替设置，并且相邻的第二高电压信号线VGH与低电压信号线VGL之间设置有栅极组。例如，第一高电压信号线VDD的电压、第二高电压信号线VGH的电压以及低电压信号线VGL的电压都为恒定电压，并且第一高电压信号线VDD的电压和第二高电压信号线VGH的电压都大于低电压信号线VGL的电压。例如，每个第二高电压信号线VGH都包括沿第二方向延伸的主体以及从该主体伸出且伸向低电压信号线VGL的分支，每个分支都与一个半导体线SML交叠且电连接(图7中的黑色圆点表示用于电连接的过孔)。源漏金属层SD还包括多个间隔开的转接件SD2，每个转接件SD2都位于相邻的第二高电压信号线VGH和低电压信号线VGL之间，该转接件SD2的一端电连接一个源极信号线(即上述多个第一源极信号线SL1 至上述多个第四源极信号线SL中的一个)，该转接件SD2的另一端与一个半导体信号线SML交叠且电连接，并且该另一端与一个第二栅极G2交叠且电连接。例如，转接件SD2的平面形状为L形。
需要说明的是，第一高电压信号线VDD和第二高电压信号线VGH涉及的“高电压”指的是这两种信号线的电压比低电压信号线VGL的电压高；低电压信号线VGL涉及的“低电压”指的是该低电压信号线VGL的电压比第一高电压信号线VDD和第二高电压信号线VGH的电压低。
在图7所示的防腐蚀电路中，上述第一子电路C1包括第一高电压信号线VDD，上述第二子电路C2包括第二高电压信号线VGH1-VGH3、低电压信号线VGL1-VGL2、转接件SD2、源极信号线SL1-SL4、半导体线SML以及栅极组。第一高电压信号线VDD为上述第一信号线L1的一个示例，第二高电压信号线VGH1为上述第二信号线L2的一个示例，低电压信号线VGL1为上述第三信号线L3的一个示例，与第二信号线L2和第三信号线L3电连接的第一源极信号线SL1为上述被保护信号线SL的一个示例，多个第二高电压信号线VGH为上述多个第一子信号线的一个示例，多个低电压信号线为上述多个第二子信号线的一个示例。
例如，如图7所示，第一信号线L1与第二信号线L2之间的间隙在第一方向上的尺寸d小于或等于300微米。例如，该尺寸d小于或等于200微米。例如，该尺寸d小于或等于100微米。在本公开如图7所示的实施例中，由于第一信号线L1与第二信号线L2之间的距离较小，因此有利于实现窄边框设计，尤其是“窄下巴”设计。
图9A为图7所示防腐蚀电路的局部放大示意图；图9B为沿图9A中的A-A线的剖视示意图。如图9A和图9B所示，在本公开至少一个实施例提供的防腐蚀电路中，衬底基板BS上依次设置有半导体层SM、第一栅金属层GM1、绝缘层ILD和源漏金属层SD。例如，如图9B所示，源漏金属层SD被平坦化绝缘层PLN和像素定义层PDL覆盖。例如，如图9A和图9B所示，半导体层SM中的半导体线SML包括第一沟道CH1和第二沟道CH2。第一栅金属层GM1包括并排位于半导体层SM上的第一栅极G1和第二栅极G2。源漏金属层SD包括并排位于绝缘层ILD的表面S上的第一信号线L1(参见第一高电压信号线VDD)、第二信号线L2(参见第二高电压信号线VGH1)和第三信号线L3(参见低电压信号线VGL1)。第一开关T1包括第一栅极G1、第一极S1、第二极D1、以及位于第一极S1和第二极D1之间的第一沟道CH1。第二开关T2包括第二栅极G2、第三极S2、第四极D2、以及位于第三极S2和第四极D2之间的第二沟道CH2。在从第一信号线L1到第三信号线L3的方向上(如箭头A-A所示方向)，绝缘层ILD中依次设置有第一过孔V1至第五过孔V5；第二信号线L2包括的凸向第三信号线L3的分支通过第一过孔V1电连接半导体线SML，该分支作为第一开关T1的第二极D1，并且该第二极D1通过第二过孔V2电连接第一栅极G1；第一栅极G1在第二过孔V2处直接电连接(即未通过过孔电连接)半导体线SML；上述转接件SD2作为第一开关T1的第一极S1并且作为第二开关T2的第四极D2(即转接件SD2为上述第一开关T1和第二开关T2共 用的电极)，该第一极S1和第四极D2在第三过孔V3处电连接半导体线SML，并且该转接SD2在第四过孔V4处电连接第二栅极G2；第二栅极G2在第四过孔V4处直接电连接(即未通过过孔电连接)半导体线SML；第三信号线L3作为第二开关T2的第三极S2。
例如，源漏金属层SD的材料包括铝金属层。例如，源漏金属层的材料包括如上所述的第一金属层M1、第二金属层M2和第三金属层M3。例如，第一金属层M1、第二金属层M2和第三金属层M3分别为钛金属层、铝金属层和钛金属层。由于源漏金属层SD包括第一高电压信号线VDD、第二高电压信号线VGH、低电压信号线VGL和转接件SD，因此这些信号线和转接件的材质与源漏金属层的上述材质相同，这里不再赘述。
图10A为本公开实施例提供的防腐蚀电路的俯视示意图二；图10B为图10A中区域A的局部放大示意图；图10C为图10B中区域C的局部放大示意图；图10D为图10A中区域B的局部放大示意图。
例如，如图10A所示，本公开至少一个实施例提供的防腐蚀电路AC包括沿第一方向依次排列且沿第二方向延伸的高电压信号线VGH、重置电压信号线Vinit和低电压信号线VGL，这些信号线在工作时都被输入恒定电压，高电压信号线VGH的电压大于低电压信号线VGL的电压，并且重置电压信号线Vinit的电压大于低电压信号线VGL的电压。在如图10A所示的防腐蚀电路AC中，上述第一子电路C1包括重置电压信号线Vinit，上述第二子电路C2包括高电压信号线VGH和低电压信号线VGL；高电压信号线VGH为上述第一信号线L1的一个示例，重置电压信号线Vinit为上述第二信号线L2的一个示例，低电压信号线VGL为上述第三信号线L3的一个示例。需要说明的是，高电压信号线VGH涉及的“高电压”指的是该高电压信号线VGH的电压比低电压信号线VGL的电压高；低电压信号线VGL涉及的“低电压”指的是该低电压信号线VGL的电压比高电压信号线VGH的电压低。
例如，如图10A所示，该防腐蚀电路AC还包括沿第一方向依次排列且沿第二方向延伸的多个检测信号线ET，检测信号线ET在工作时被输入变化信号，例如方波信号；高电压信号线VGH与一个检测信号线ET相邻，且低电压信号线VGL与另一个检测信号线ET相邻。该防腐蚀电路AC还包括用于保护检测信号线ET的静电释放保护电路ESD，并且高电压信号线VGH、低电压信号线VGL和检测信号线ET都电连接静电释放保护电路ESD。
例如，如图10A至图10C所示，静电释放保护电路ESD包括交替设置的多个子高电压信号线VGH1-VGH2以及多个子低电压信号线VGL1-VGL2，这些信号线都沿第一方向延伸且沿第二方向依次排列；该多个子高电压信号线VGH1-VGH2通过如多个过孔V(参见图10C中的黑色圆点)电连接高电压信号线VGH，并且该多个子低电压信号线VGL1-VGL2通过如多个过孔V电连接低电压信号线VGH。在如图10A至图10C所示的静电释放保护电路ESD中，高电压信号线VGH为上述第一母信号线的一个示例，低电压信号线VGL为上述第二母信号线的一个示例，多个子高电压信号线VGH1-VGH2为上述多个第一子信号线的一个示例，多个低电压信号线VGL1-VGL2为上述多个第二子信号线 的一个示例。需要说明的是，子高电压信号线VGH1-VGH2涉及的“高电压”指的是这些信号线的电压比子低电压信号线VGL1-VGL2的电压高；子低电压信号线VGL1-VGL2涉及的“低电压”指的是这些信号线的电压比子高电压信号线VGH1-VGH2的电压低。
例如，如图10A和图10D所示，静电释放保护电路ESD包括第一开关T1、被保护的检测信号线ET(上述被保护信号线的一个示例)和第二开关T2。检测信号线ET包括沿第一方向延伸的第一部分ET1和沿第二方向延伸的第二部分ET2，第一部分ET1和第二部分ET2直接连接，即检测信号线ET为一体化结构。第一开关T1为第一晶体管，第一晶体管包括第一栅极G1、第一极S1和第二极D1。第二开关T2为第二晶体管，第二晶体管包括第二栅极G2、第三极S2和第四极D2。第一开关T1的第二极D1电连接子高电压信号线(参见VGH1)且电连接第一栅极G1；检测信号线ET的第一部分ET1作为第一开关T1的第一极S1且作为第二开关T2的第四极D2；第二开关T2的第三极S2与子低电压信号线(参见VGL1)电连接。例如，第一晶体管和第二晶体管都为P型晶体管。在本公开实施例中，检测信号线ET上的正电荷静电可以通过第一开关T1释放到子高电压信号线VGH1-VGH2上，进而通过子高电压信号线VGH1-VGH2释放出去；检测信号线ET上的负电荷静电可以通过第二开关T2释放到子低电压信号线VGL1-VGL2上，进而通过子低电压信号线VGL1-VGL2释放出去。关于静电释放保护电路的工作原理，请参见以上相关描述，这里不再赘述。
例如，高电压信号线VGH、重置电压信号线Vinit、低电压信号线VGH和检测信号线ET都属于源漏金属层，并且这些信号线都并排位于同一表面上。例如，源漏金属层的材料包括铝金属层。例如，源漏金属层的材料包括如上所述的第一金属层M1、第二金属层M2和第三金属层M3。例如，子高电压信号线VGH1-VGH2以及子低电压信号线VGL1-VGL2都属于栅金属层(例如上述第一栅金属层GM1)。
例如，如图10A所示，高电压信号线VGH(第一信号线L1的一个示例)和重置电压信号线Vinit(第二信号线L2的一个示例)在同一表面上的正投影之间的间隙在第一方向上的尺寸h小于或等于60微米。例如，尺寸h小于或等于60微米且大于或等于50微米。由于高电压信号线VGH和重置电压信号线Vinit之间的距离可以制作得较小，因此防腐蚀电路的结构紧凑，节省空间。
本公开实施例还提供一种电子装置，其包括以上任一实施例所述的防腐蚀电路。
图11A和图11B为本公开实施例提供的电子装置的俯视示意图。例如，如图11A和图11B所示，本公开至少一个实施例提供的电子装置包括像素基板AR、第一电源总线VDD(即图7所示实施例中的第一高电压信号线)、多个子电源线VDD0(图中仅示意性地画出三条子电源线)、第二电源总线VSS、静电释放保护电路ESD、驱动电路IC和电路板PC。像素基板AR包括多个子像素(例如子像素包括发光件)，该多个子像素呈矩阵排列，例如该多个子像素包括红色子像素R、绿色子像素G和蓝色子像素B，这些子像素位于像素基板AR的显示区AA中，用于实现显示功能。第一电源总线VDD与子电源线VDD0电连接，以通过子电源线VDD0向子像素(例如发光件)提供第一电源信号， 第二电源总线VSS用于向子像素提供第二电源信号，子像素可以在第一电源信号和第二电源信号的作用下工作。例如，第一电源总线VDD向子像素中的发光件的正极提供第一电源信号，第二电源总线VSS向子像素中的发光件的负极提供第二电源信号，此时第一电源总线VDD的恒定电压大于第二电源总线VSS的恒定电压。电路板PC(其例如为柔性印刷电路板)与像素基板AR的一侧连接，电路板PC被配置为向第一电源总线VDD和第二电源总线VSS提供信号。
例如，如图11A和图11B所示，电子装置包括的静电释放保护电路ESD(以下称为第一静电释放保护电路)位于像素基板AR和电路板PC之间。该第一静电释放保护电路ESD与第一电源总线VDD相邻。例如，该第一静电释放保护电路ESD为如图7所示的静电释放保护电路，即第一静电释放保护电路ESD包括多个第二子高电压信号线VGH1-VGH3和多个低电压信号线VGL1-VGL2。该多个第二子高电压信号线VGH1-VGH3电连接高电压信号线VGH0(上述第一母信号线B1的一个示例)，该多个低电压信号线VGL1-VGL2电连接低电压信号线VGL0(上述第二母信号线B2的一个示例)。电路板PC用于向高电压信号线VGH0和低电压信号线VGL0提供信号，以分别向第一静电释放保护电路ESD的多个第二子高电压信号线VGH1-VGH3和多个低电压信号线VGL1-VGL2提供信号。需要说明的是，高电压信号线VGH0涉及的“高电压”指的是该高电压信号线VGH0的电压比低电压信号线VGL0的电压高；低电压信号线VGL0涉及的“低电压”指的是该低电压信号线VGL0的电压比高电压信号线VGH0的电压低。
在图11A所示实施例中，防腐蚀电路AC包括第一电源总线VDD、高电压信号线VGH0、低电压信号线VGL0和第一静电释放保护电路ESD。在这种情况下，第一电源总线VDD为上述第一信号线L1的一个示例，高电压信号线VGH0为上述第一母信号线B1的一个示例，低电压信号线VGL0为上述第二母信号线B2的一个示例，与第一电源总线VDD相邻的第二高电压信号线VGH1为第二信号线L2的一个示例，与该第二高电压信号线VGH1相邻的低电压信号线VGL1为第三信号线L3的一个示例。在图11A中，第二信号线L2和第三信号线L3位于电路板PC与像素基板AR之间，第一信号线L1位于第二信号线L2的面向像素基板AR的一侧，即第一信号线L1位于像素基板AR与第二信号线L2之间。
例如，如图11B所示，本公开至少一个实施例提供的电子装置还包括检测电路ETC，其位于电路板PC的远离像素基板AR的一侧，即电路板PC位于检测电路ETC与像素基板AR之间。例如，该检测电路ETC为如图10A至图10D所示的防腐蚀电路，即该检测电路ETC为上述防腐蚀电路AC的一个示例。在这种情况下，该检测电路ETC包括如图10A至10D所示的高电压信号线VGH、重置电压信号线Vinit、低电压信号线VGL、检测信号线ET以及静电释放保护电路(以下称为第二静电释放保护电路)ESD，关于第二静电释放保护电路ESD的设置方式参见图10A至图10D所示防腐蚀电路的实施例中的相关描述；高电压信号线VGH为第一信号线L1的一个示例，重置电压信号线Vinit为第二信号线L2的一个示例，低电压信号线VGL为第三信号线L3的一个示例，第一信号线 L1和第三信号线L3位于电路板PC的远离像素基板AR的一侧，并且重置电压信号线Vinit用于与像素基板AR包括的发光件电连接以提供重置电压。
本公开实施例提供的电子装置可以为主动发光元件面板(例如OLED面板或者量子点面板)或者其它类型的包括上述防腐蚀电路的电子装置中。
以电子装置为主动发光元件面板(此时发光件为OLED发光件或量子点发光件)为例，在制作该电子装置的过程中，可以利用如图11B中的检测电路ETC对像素基板AR进行电学测试，并且在完成该电学测试后沿图11B中的切割线进行切割以去除检测电路ETC，从而得到如图11A所示的电子装置。
例如，本公开至少一个实施例提供的电子装置为OLED面板，该OLED面板包括多个子像素，每个子像素包括发光件以及驱动该发光件发光的驱动电路。例如，该驱动电路可以采用6T1C或7T1C或类似电路结构，其中，T指的是薄膜晶体管(Thin Film Transistor，缩写为TFT)，C指的是电容器(Capacitor)。例如，在第一静电释放保护电路ESD为如图7所示的静电释放保护电路的情况下，第一电源总线VDD用于向驱动电路包括的一个TFT提供信号，图7中的源极信号线SL(参见SL1-SL4)与驱动电路包括的另一个TFT电连接，并且第一静电释放保护电路用于释放该源极信号线SL上的静电。例如，在检测电路ETC为如图10A至图10D所示的防腐蚀电路的情况下，重置电压信号线Vinit用于向驱动电路包括的一个TFT提供信号，检测信号线ET与驱动电路包括的另一个TFT电连接，并且第二静电释放保护电路用于释放该检测信号线ET上的静电。
例如，本公开实施例提供的显示装置可以为：OLED面板、量子点面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例还提供一种防腐蚀电路的制作方法，其包括：如图12所示，在表面S上形成导电层CL；对导电层CL进行图案化处理以形成如图1所示的沿第一方向依次排列的第一信号线L1、第二信号线L2和第三信号线L3，第一信号线L1、第二信号线L2和第三信号线L3都沿第二方向延伸，第二方向不同于第一方向，第一信号线L1和第三信号线L3都与第二信号线L2相邻，第一信号线L1与第二信号线L2具有相同的电性且第二信号线L2与第三信号线L3具有不同的电性。
例如，图案化处理包括：在导电层CL上涂覆光刻胶层；利用掩膜板对光刻胶层进行曝光；对曝光后的光刻胶层进行显影处理以形成光刻胶图案；之后，利用光刻胶图案对导电层CL进行刻蚀处理以得到第一信号线L1、第二信号线L2和第三信号线L3。
例如，导电层CL的材料包括铝金属层。例如，导电层Cl的材料包括多层膜结构。例如，该多层膜结构包括如上所述的第一金属层M1、第二金属层M2和第三金属层M3。例如，该多层膜结构包括层叠的两层钛金属层以及夹置于二者之间的铝金属层。
本公开至少一个实施例还提供一种阵列基板。图13为本公开实施例提供的阵列基板的俯视示意图。如图13所示，本公开至少一个实施例提供的阵列基板包括衬底基板BS、多个子像素P、多个源极信号线SL、第一电源总线VDD、多个子电源线VDD0以及静电 释放保护电路ESD。衬底基板BS包括显示区AA和至少位于显示区AA一侧的周边区PA。该多个子像素P位于显示区AA。该多个源极信号线SL位于显示区AA、沿第一方向延伸且沿不同于第一方向的第二方向依次排列，该多个源极信号线SL分别与多个子像素P电连接，并且被配置为向多个子像素P提供数据信号。例如，每个源极信号线SL与一列子像素P电连接以向该列子像素P提供数据信号。例如，阵列基板还包括位于周边区PA中的多个转接线TL，该多个转接线TL与该多个源极信号线SL一一对应地电连接，从而该多个源极信号线SL分别通过对应的转接线TL电连接静电释放保护电路ESD，以通过静电释放保护电路ESD释放静电。第一电源总线VDD位于周边区PA并且包括沿第二方向延伸的主体部分。例如，第一电源总线VDD还包括从主体部分两端伸出且沿第一方向延伸的延伸部分。多个子电源线VDD0位于显示区AA且分别与多个子像素P电连接，并且被配置为向多个子像素P提供第一电源信号。例如，每个子电源线VDD0电连接一列子像素P以向该列子像素P提供第一电源信号。第一电源总线VDD与该多个子电源线VDD0电连接，以通过该多个子电源线VDD0向子像素P提供第一电源信号。也就是说，第一电源总线VDD0向该多个子电源线VDD0提供第一电源信号，进而该多个子电源线VDD0将该第一电源信号提供至所述多个子像素P。静电释放保护电路ESD位于第一电源总线VDD的主体部分的远离显示区AA的一侧(即该主体部分位于显示区AA与静电释放保护电路ESD之间)，静电释放保护电路ESD与多个源极信号线SL电连接，并且包括多个第一子信号线VGH(图13示出了VGH1和VGH2进行举例说明)和多个第二子信号线VGL(图13示出了VGL1和VGL2进行举例说明)，该多个第一子信号线VGH和该多个第二子信号线VGL沿第二方向延伸且沿第一方向交替排列，第一电源总线VDD的主体部分与一个第一子信号线VGH1相邻，并且第一电源总线VDD的电性(即第一电源总线VDD的主体部分)与一个第一子信号线(参见VGH1)的电性相同。
例如，如图13所示，本公开的至少一个实施例提供的阵列基板还包括第二电源总线VSS，第二电源总线VSS位于周边区PA并且被配置为向多个子像素P提供第二电源信号。例如，子像素P包括发光件，该发光件包括正极和负极，第一电源总线VDD被配置为向该发光件的正极施加第一电源信号，第二电源总线VSS被配置为向该发光件的负极施加第二电源信号。
例如，阵列基板还包括电路板PC(例如印刷电路板)，例如柔性电路板FPC，其被配置为向第一电源总线VDD提供第一电源信号并且向第二电源总线VSS提供第二电源信号。
在本公开实施例中，第一电源总线VDD的主体部分与第一子信号线VGH1相邻并且电性相同，这样有利于避免第一电源总线VDD的主体部分与和其相邻的第一子信号线VGH1之间发生电化学腐蚀(尤其是在高温高湿条件下)。在一些实施例中，由于第一电源总线VDD的主体部分与和其相邻的第一子信号线VGH1之间不容易发生电化学腐蚀，因此第一电源总线VDD的主体部分与和其相邻的第一子信号线VGH1之间的距离可以设计得更小，以窄化面板的边框(例如下边框)，从而提高屏占比，因此本公开一些实施例 可以在实现窄边框设计的同时改善局部短路或开路。
需要说明的是，在本公开实施例中，第一电源总线VDD的主体部分与第一子信号线VGH1相邻是指，该主体部分与该第一子信号线VGH1沿同一方向延伸，并且主体部分与该第一子信号线VGH1之间未设置沿该同一方向延伸的其它信号线。
例如，第一子信号线VGH1和与该第一子信号线VGH1相邻的第二子信号线VGL1的电性相反。也就是说，在第一子信号线VGH1和第二子信号线VGL1电性相反的情况下，将电性与第一电源总线VDD的电性相同的第一子信号线VGH1设置为与第一电源总线VDD相邻。
例如，第一电源总线VDD的沿第二方向延伸的主体部分为上述第一信号线L1，与该主体部分相邻的第一子信号线VGH1为上述第二信号线L2，与第一子信号线VGH1相邻的第二子信号线VGL1为上述第三信号线L3。例如，第一信号线L1与第二信号线L2之间的电压差的绝对值小于第一信号线L1与第三信号线L3之间的电压差的绝对值。在使第一信号线L1与第二信号线L2的电性相同的情况下，通过使第一信号线L1与第二信号线L2之间的电压差的绝对值小于第一信号线L1与第三信号线L3之间的电压差的绝对值，有利于进一步避免第一电源总线VDD的主体部分与和其相邻的第一子信号线VGH1之间发生电化学腐蚀。
例如，第一信号线L1的电压、第二信号线L2的电压和第三信号线L3的电压都为恒定电压。
例如，第一信号线L1、第二信号线L2和第三信号线L3并排位于同一表面S上，如图1所示。
例如，第一信号线L1和第二信号线L2都具有正电性，并且第三信号线L3具有负电性。或者，例如，第一信号线L1和第二信号线L2都具有负电性，并且第三信号线L3具有正电性。
例如，第一电源总线VDD的沿第二方向延伸的主体部分和与其相邻的第一子信号线VGH1中的至少一个的材料包括铝金属层。
例如，第一电源总线VDD的主体部分和第一子信号线VGH1中的至少一个为多层膜结构，如图2所示，该多层膜结构包括依次层叠的第一金属层M1、第二金属层M2和第三金属层M3，第二金属层M2的金属活泼性大于第一金属层M1和第三金属层M3的金属活泼性。
例如，第一电源总线VDD的主体部分和第一子信号线VGH1之间的间隙在第一方向上的尺寸小于或等于300微米。
例如，静电释放保护电路ESD还包括第一母信号线B1和第二母信号线B2，多个第一子信号线(参见VGH1-VGH2)电连接第一母信号线B1，多个第二子信号线(参见VGL1-VGL2)电连接第二母信号线B2。例如，第一母信号线B1和第二母信号线B2分别接收来自电路板PC的不同信号。例如，第一母信号线B1和第二母信号线B2分别为图11A和图11B所示实施例中的高电压信号线VGH0和低电压信号线VGL0。
例如，静电释放保护电路ESD包括多个开关组T0，每个开关组T0包括共用同一电极的第一开关T1和第二开关T2，第一开关T1和第二开关T2通过共用的同一电极电连接同一源极信号线SL以释放该电源信号线SL上的静电，并且不同的开关组T0电连接不同的源极信号线SL。例如，关于第一开关T1和第二开关T2的连接关系请参见关于图5A至图6的描述。
例如，第一开关T1包括第一输入端Vi1和第一输出端Vo1，第一输入端Vi1与同一源极信号线SL电连接，并且第一输出端Vo1与第二信号线L2电连接；第二开关T2包括第二输入端Vi2和第二输出端Vo2，第二输入端Vi2与第三信号线L1电连接，并且第二输出端Vo2与同一源极信号线SL电连接。
例如，第一开关T1为第一晶体管，第一晶体管包括第一栅极G1、第一极S1和第二极D1，第一极S1作为第一输入端Vi1，第二极D1电连接第一栅极G1且作为第一输出端Vo1；第二开关T2为第二晶体管，第二晶体管包括第二栅极G2、第三极S2和第四极D2，第三极S2作为第二输入端Vi2，第四极D2电连接第二栅极G2且作为第二输出端Vo2。
例如，源极信号线SL和静电释放保护电路ESD可以采用如图7所示实施例，在这种情况下，第一电源总线VDD的主体部分为图7所示实施例中的第一高电压信号线VDD。
例如，如图7所示，多个源极信号线SL包括沿第二方向依次排列的信号线组，每个信号线组包括沿第二方向依次排列的第一源极信号线SL1、第二源极信号线SL2、第三源极信号线SL2和第四源极信号线SL4；静电释放保护电路ESD包括的多个开关组T0包括沿第一方向依次排列的第一开关组T01、第二开关组T02、第三开关组T03和第四开关组T04，第一开关组T01电连接第一源极信号线SL1以释放第一源极信号线SL1上的静电，第二开关组T02与第一开关组T01相邻并且电连接第二源极信号线SL2以释放第二源极信号线SL2上的静电，第三开关组T03与第二开关组T02相邻并且电连接第三源极信号线SL3以释放第三源极信号线SL3上的静电，第四开关组T04与第三开关组T03相邻并且电连接第四源极信号线SL4以释放第四源极信号线SL4上的静电。
例如，阵列基板在显示区的各层结构的局部剖视示意图可以参考图14，并且阵列基板在周边区PA的各层结构的俯视示意图可以参考图7至图8C。例如图7和图14所示，阵列基板包括依次位于衬底基板BS上的第一栅金属层GM1、第二栅金属层GM2和源漏金属层SD。第一栅金属层GM1包括多个源极信号线SL中的一部分(例如包括如图7和图8B所示的多个第二源极信号线SL2和多个第四源极信号线SL4)；第二栅金属层包括多个源极信号线SL中的另一部分(例如包括如图7和图8C所示的多个第一源极信号线SL1和多个第三源极信号线SL3)；源漏金属层SD包括第一电源总线VDD的沿第二方向延伸的主体部分、多个子电源线VDD0、多个第一子信号线VGH(参见VGH1-VGH2)和多个第二子信号线VGL(参见VGL1-VGL 2)。例如，源漏金属层SD不包括转接线TL，即转接线TL位于源漏金属层SD之外，以避免转接线TL电连接第一电源总线VDD的主体部分。例如，转接线TL位于第一栅金属层GM1或者第二栅金属层GM2中。
例如，如图14所示，本公开至少一个实施例提供的阵列基板的至少一个子像素包括多个像素开关PT(图14仅示出一个像素开关PT进行举例说明)，每个子像素中的多个像素开关PT与该子像素中的发光件电连接，每个像素开关PT包括有源层AL、栅极G、第一极E1和第二极E2，第一极E1和第二极E2之一为源极且另一为漏极。例如，有源层AL位于上述半导体层SM中，栅极G位于第一栅金属层GM1或第二栅金属层GM2中，第一极E1和第二极E2位于源漏金属层SD中。例如，有源层AL位于衬底基板BS上的缓冲层BF上并且被第一栅绝缘层GI1覆盖；栅极G位于第一栅绝缘层GI1上并且依次被第二栅绝缘层GI2和绝缘层ILD覆盖，像素开关PT的第一极E1和第二极E2位于绝缘层ILD上且依次被钝化绝缘层PVX和平坦化绝缘层PLN覆盖。
例如，如图14所示，发光件L包括正极AN、发光层EL和负极CA，并且发光件L的正极AN电连接像素开关PT的第一极E1。例如，发光件L的正极AN通过贯穿钝化绝缘层PVX和平坦化绝缘层PLN的过孔电连接像素开关PT的第一极E1。例如，相邻的发光件L通过像素定义层PDL隔开。在一些实施例中，像素定义层PDL上还设置有包括多个间隔部的有机层PS以更好地隔开相邻的发光件L。
例如，本公开至少一个实施例提供的阵列基板还包括用于封装发光件L的封装层，该封装层包括无机封装层IEP1和IEP2以及位于无机封装层IEP1和IEP2之间的有机封装层OEP。在其他实施例中，封装层可以包括多个有机封装层和多个无机封装层，并且该多个有机封装层与该多个无机封装层交替设置。
本公开实施例提供的防腐蚀电路及其制作方法、阵列基板和电子装置的实施例中相同部件的设置方式可以相同。
以上仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (32)

  1. 一种阵列基板，包括：
    衬底基板，包括显示区和至少位于所述显示区一侧的周边区；
    多个子像素，位于所述显示区；
    多个源极信号线，位于所述显示区且分别与所述多个子像素电连接，并且被配置为向所述多个子像素提供数据信号，其中，所述多个源极信号线沿第一方向延伸且沿不同于所述第一方向的第二方向依次排列；
    第一电源总线，位于所述周边区并且包括沿所述第二方向延伸的主体部分；
    多个子电源线，位于所述显示区且分别与所述多个子像素电连接，并且被配置为向所述多个子像素提供第一电源信号，其中，所述第一电源总线与所述多个子电源线电连接；
    静电释放保护电路，位于所述第一电源总线的所述主体部分远离所述显示区的一侧，与所述多个源极信号线电连接，并且包括多个第一子信号线和多个第二子信号线，其中，所述多个第一子信号线和所述多个第二子信号线沿所述第二方向延伸且沿所述第一方向交替排列，所述第一电源总线的所述主体部分与一个第一子信号线相邻，并且所述第一电源总线的电性与所述一个第一子信号线的电性相同。
  2. 根据权利要求1所述的阵列基板，其中，所述静电释放保护电路还包括第一母信号线和第二母信号线，所述多个第一子信号线电连接所述第一母信号线，所述多个第二子信号线电连接所述第二母信号线。
  3. 根据权利要求1或2所述的阵列基板，其中，所述静电释放保护电路包括多个开关组，每个开关组包括共用同一电极的第一开关和第二开关，所述第一开关和所述第二开关通过所述共用的同一电极电连接同一源极信号线，并且不同的开关组电连接不同的源极信号线。
  4. 根据权利要求3所述的阵列基板，其中，
    所述第一电源总线的所述主体部分为第一信号线，与所述主体部分相邻的所述一个第一子信号线为第二信号线，并且与所述第二信号线相邻的第二子信号线为第三信号线；
    所述第一开关包括第一输入端和第一输出端，所述第一输入端与所述同一源极信号线电连接，并且所述第一输出端与所述第二信号线电连接；
    所述第二开关包括第二输入端和第二输出端，所述第二输入端与所述第三信号线电连接，并且所述第二输出端与所述同一源极信号线电连接。
  5. 根据权利要求4所述的阵列基板，其中，
    所述第一开关为第一晶体管，所述第一晶体管包括第一栅极、第一极和第二极，所述第一极作为所述第一输入端，所述第二极电连接所述第一栅极且作为所述第一输出端；
    所述第二开关为第二晶体管，所述第二晶体管包括第二栅极、第三极和第四极，所述第三极作为所述第二输入端，所述第四极电连接所述第二栅极且作为所述第二输出端。
  6. 根据权利要求4或5所述的阵列基板，其中，所述第一信号线和所述第二信号线 都具有正电性，并且所述第三信号线具有负电性。
  7. 根据权利要求4或5所述的阵列基板，其中，所述第一信号线和所述第二信号线都具有负电性，并且所述第三信号线具有正电性。
  8. 根据权利要求4-7中任一项所述的阵列基板，其中，所述第一信号线的电压、所述第二信号线的电压和所述第三信号线的电压都为恒定电压。
  9. 根据权利要求4-8中任一项所述的阵列基板，其中，所述第一信号线、所述第二信号线和所述第三信号线并排位于同一表面上。
  10. 根据权利要求3-9中任一项所述的阵列基板，其中，所述多个源极信号线包括沿所述第二方向依次排列的信号线组，每个信号线组包括沿所述第二方向依次排列的第一源极信号线、第二源极信号线、第三源极信号线和第四源极信号线；
    所述静电释放保护电路包括的所述多个开关组包括沿所述第一方向依次排列的第一开关组、第二开关组、第三开关组和第四开关组，所述第一开关组电连接所述第一源极信号线，所述第二开关组电连接所述第二源极信号线，所述第三开关组电连接所述第三源极信号线，所述第四开关组电连接所述第四源极信号线。
  11. 根据权利要求1-10中任一项所述的阵列基板，其中，
    所述阵列基板包括依次位于所述衬底基板上的第一栅金属层、第二栅金属层和源漏金属层，
    所述第一栅金属层包括所述多个源极信号线中的一部分，
    所述第二栅金属层包括所述多个源极信号线中的另一部分，
    所述源漏金属层包括所述第一电源总线的所述主体部分、所述多个子电源线、所述多个第一子信号线和所述多个第二子信号线。
  12. 根据权利要求11所述的阵列基板，其中，所述多个子像素中的至少一个包括多个像素开关，其中，
    每个像素开关包括栅极、第一极和第二极；
    所述栅极位于所述第一栅金属层或所述第二栅金属层中，所述第一极和所述第二极位于源漏金属层中。
  13. 根据权利要求1-12中任一项所述的阵列基板，其中，所述第一电源总线的所述主体部分和所述一个第一子信号线中的至少一个的材料包括铝金属。
  14. 根据权利要求1-13中任一项所述的阵列基板，其中，所述第一电源总线的所述主体部分和所述一个第一子信号线中的至少一个为多层膜结构，所述多层膜结构包括依次层叠的第一金属层、第二金属层和第三金属层，所述第二金属层的金属活泼性大于所述第一金属层和所述第三金属层的金属活泼性。
  15. 根据权利要求1-3中任一项所述的阵列基板，其中，所述第一电源总线的所述主体部分和所述一个第一子信号线的电压都为恒定电压。
  16. 根据权利要求1-15中任一项所述的阵列基板，其中，所述第一电源总线的所述主体部分和所述一个第一子信号线之间的间隙在所述第一方向上的尺寸小于或等于300 微米。
  17. 根据权利要求1-16中任一项所述的阵列基板，还包括第二电源总线，其中，所述第二电源总线位于所述周边区并且被配置为向所述多个子像素提供第二电源信号。
  18. 一种防腐蚀电路，包括沿第一方向依次排列的第一信号线、第二信号线和第三信号线，其中，
    所述第一信号线、所述第二信号线和所述第三信号线都沿第二方向延伸，所述第二方向不同于所述第一方向；
    所述第一信号线和所述第三信号线都与所述第二信号线相邻；并且
    所述第二信号线与所述第一信号线具有相同的电性，并且所述第二信号线与所述第三信号线具有不同的电性。
  19. 根据权利要求18所述的防腐蚀电路，其中，所述第一信号线与所述第二信号线之间的电压差的绝对值小于所述第一信号线与所述第三信号线之间的电压差的绝对值。
  20. 根据权利要求18或19所述的防腐蚀电路，其中，所述第一信号线的电压、所述第二信号线的电压和所述第三信号线的电压都为恒定电压。
  21. 根据权利要求18-20中任一项所述的防腐蚀电路，其中，所述第一信号线、所述第二信号线和所述第三信号线并排位于同一表面上。
  22. 根据权利要求18-21中任一项所述的防腐蚀电路，其中，所述第一信号线和所述第二信号线中的至少一个为多层膜结构，所述多层膜结构包括依次层叠的第一金属层、第二金属层和第三金属层，所述第二金属层的金属活泼性大于所述第一金属层和所述第三金属层的金属活泼性。
  23. 根据权利要求18-22中任一项所述的防腐蚀电路，包括彼此间隔开的第一子电路和第二子电路，其中，
    所述第一信号线和所述第二信号线中的一者属于所述第一子电路，所述第一信号线和所述第二信号线中的另一者属于所述第二子电路。
  24. 根据权利要求23所述的防腐蚀电路，其中，所述第二子电路为静电释放保护电路，所述静电释放保护电路包括所述第一信号线和所述第二信号线中的所述另一者以及所述第三信号线。
  25. 根据权利要求24所述的防腐蚀电路，其中，
    所述静电释放保护电路包括依次排列的第一母信号线和第二母信号线；
    所述静电释放保护电路还包括依次排列的多个第一子信号线和多个第二子信号线，所述多个第一子信号线电连接所述第一母信号线，所述多个第二子信号线电连接所述第二母信号线；并且
    所述第一信号线和所述第二信号线中的所述另一者属于所述第一母信号线、所述第二母信号线、所述多个第一子信号线或者所述多个第二子信号线。
  26. 根据权利要求25所述的防腐蚀电路，其中，所述静电释放保护电路包括所述第二信号线以及所述第三信号线，所述第二信号线为所述多个第一子信号线之一，并且所述 第三信号线为所述多个第二子信号线之一。
  27. 根据权利要求26所述的防腐蚀电路，其中，所述第一信号线与所述第二信号线之间的间隙在所述第一方向上的尺寸小于或等于300微米。
  28. 根据权利要求25所述的防腐蚀电路，其中，所述静电释放保护电路包括所述第一信号线以及所述第三信号线，所述第一信号线为所述第一母信号线，并且所述第三信号线为所述第二母信号线。
  29. 根据权利要求28所述的防腐蚀电路，其中，所述第一信号线和所述第二信号线之间的间隙在所述第一方向上的尺寸小于或等于60微米。
  30. 一种电子装置，包括权利要求1-17中任一项所述的阵列基板或者权利要求18-29中任一项所述的防腐蚀电路。
  31. 根据权利要求30所述的电子装置，包括：
    像素基板，其包括多个子像素；
    电路板，其与所述像素基板的一侧连接，
    其中，在所述电子装置包括所述防腐蚀电路的情况下，所述电路板被配置为向所述第一信号线、所述第二信号线和所述第三信号线提供信号，所述防腐蚀电路的所述第二信号线和所述第三信号线位于所述电路板与所述像素基板之间，所述防腐蚀电路的所述第一信号线位于所述第二信号线的面向所述像素基板的一侧。
  32. 根据权利要求30所述的电子装置，包括：
    像素基板，其包括多个子像素；
    电路板，其与所述像素基板的一侧连接；以及
    检测电路，其位于所述电路板的远离所述像素基板的一侧，
    其中，所述检测电路为所述防腐蚀电路，所述防腐蚀电路的所述第一信号线和所述第三信号线位于所述电路板的远离所述像素基板的一侧，所述第二信号线被配置为向所述多个子像素提供重置信号。
PCT/CN2020/086443 2020-04-23 2020-04-23 防腐蚀电路、阵列基板和电子装置 WO2021212421A1 (zh)

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