WO2020094044A1 - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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Publication number
WO2020094044A1
WO2020094044A1 PCT/CN2019/115932 CN2019115932W WO2020094044A1 WO 2020094044 A1 WO2020094044 A1 WO 2020094044A1 CN 2019115932 W CN2019115932 W CN 2019115932W WO 2020094044 A1 WO2020094044 A1 WO 2020094044A1
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source
drain region
forming
manufacturing
semiconductor substrate
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English (en)
French (fr)
Inventor
肖魁
方冬
卞铮
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a semiconductor device structure and a method of manufacturing the same.
  • Trench VDMOS products are more widely used power devices.
  • the maturity of the trench process further reduces the size of the cell.
  • the trench area passes through the bottom of the P-type base region, the channel formed is located Between the source region and the drift region, the on-resistance is greatly reduced compared to the ordinary VDMOS eliminating the JFET region, so the trench VDMOS greatly improves the performance of the MOS power device.
  • the structure adopted today is that the polysilicon gate plane in the trench is lower than the silicon plane, the manufacturing process is etching trench, growing gate oxygen, polysilicon deposition, polysilicon etching, well region formation, NSD formation, hole Formation, metal electrode formation, back process.
  • the masks used based on the above manufacturing methods include at least trench masks, NSD masks, CT masks, and metal masks. Secondly, to improve performance, such as passivation layer masks will also be added.
  • one aspect of the present invention provides a semiconductor device, including: a semiconductor substrate; a trench formed in the semiconductor substrate; an interlayer dielectric layer formed in the trench and the semiconductor substrate Above; contact holes formed in the interlayer dielectric layer and the semiconductor substrate; first source / drain regions and second source / drain regions, the first source / drain regions and the second source / Drain regions are formed through the contact holes.
  • a further aspect of the present invention provides a manufacturing method, including: providing a semiconductor substrate; forming a trench in the semiconductor substrate; forming an interlayer dielectric layer above the trench and the semiconductor substrate; A contact hole is formed on the interlayer dielectric layer, and the contact hole extends from the top to the bottom of the interlayer dielectric layer; the first source / drain region is formed through the contact hole implantation; and the second source is formed through the contact hole implantation / Drain area.
  • the invention can omit the source / drain region mask plate, at the same time omit the manufacturing lithography link, and save the manufacturing cost.
  • FIG. 1A to 1J show schematic cross-sectional views of devices obtained by relevant steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention
  • FIGS. 2A to 2K show schematic cross-sectional views of a device obtained by relevant steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention
  • FIG. 3 shows a schematic diagram of relevant steps of a method for manufacturing a VDMOS device according to an embodiment of the present invention.
  • first element, component, region, layer, or section discussed below can be represented as a second element, component, region, layer, or section.
  • Spatial relationship terms such as “below”, “below”, “below”, “below”, “above”, “above”, etc. It can be used here for the convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then elements or features described as “below” or “beneath” or “below” will be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “below” can include both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. In this way, changes from the shown shape due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present invention should not be limited to the specific shapes of the regions shown here, but include shape deviations due to, for example, manufacturing. For example, an implanted area shown as a rectangle generally has round or curved features and / or implant concentration gradients at its edges, rather than a binary change from the implanted area to the non-implanted area. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is proceeding. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the present invention.
  • the present invention provides an aspect of the present invention to provide a semiconductor device and a manufacturing method thereof, including: a semiconductor substrate; a trench formed in the semiconductor substrate; an interlayer dielectric layer, Formed above the trench and the semiconductor substrate; contact holes formed in the interlayer dielectric layer and the semiconductor substrate; the first source / drain region and the second source / drain region, the Both the first source / drain region and the second source / drain region are formed through the contact hole.
  • the source / drain mask can be omitted, and the photolithography process can be omitted, which can save manufacturing costs.
  • VDMOS manufacturing process of the VDMOS will be described below with reference to the cross-sectional schematic diagram of the device obtained by the relevant steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention shown in FIGS. 1 to 1J.
  • step 1 a silicon wafer 100 is provided as a substrate, and a silicon epitaxial layer 101 is formed on the silicon substrate, as shown in FIG. 1A.
  • Step 2 forming a first oxide layer 102, forming a first oxide layer 102 on the silicon epitaxial layer 101, and forming a trench, forming the trench in the first oxide layer 102 and the silicon epitaxial layer 101, the first oxide layer It is a thermal oxide layer, as shown in Figure 1B.
  • the first oxide layer 102 above the silicon epitaxial layer 101 is removed.
  • Step 3 forming a second oxide layer 103 and filling polysilicon, forming a second oxide layer 103 on the surface of the silicon epitaxial layer 101 and the trench, the second oxide layer is a gate oxide layer GOX, and depositing polysilicon on the surface of the gate oxide layer GOX To fill the trench and above the trench.
  • the method further includes the step of etching the polysilicon layer 104, and the polysilicon layer 104 is etched.
  • the height of the etched polysilicon layer 104 is lower than the top surface of the groove, as shown in FIG.
  • Step 4 a well region 105 is formed, and a P well region is implanted in the silicon epitaxial layer 101, as shown in FIG. 1D;
  • step 5 an NSD, that is, an N-type first source / drain region 106 is formed, and an N-type first source / drain region 106 is implanted into the well region 105, as shown in FIG. 1E.
  • step 6 an interlayer dielectric layer (ILD) 107 is formed, and an interlayer dielectric layer 107 is formed over the trench and the first source / drain region 106, as shown in FIG. 1F.
  • ILD interlayer dielectric layer
  • Step 7 forming a hole 108, forming a contact hole (CT) 108 on the interlayer dielectric layer 107, the contact hole 108 extending from the top to the bottom of the interlayer dielectric layer 107, and the bottom of the contact hole 108 is located in the
  • CT contact hole
  • Step 8 Deepen the hole and further process the CT contact hole, such as photolithography, to deepen the depth of the contact hole 108, as shown in FIG. 1H.
  • step 9 the PSD, that is, the P-type second source / drain region 109 is implanted through the contact hole 108, as shown in FIG. 1I.
  • Step 10 forming a cell structure, forming contact layers 1101, 1102 above the interlayer dielectric layer 107 and below the silicon wafer 100, and forming leads through the contact layers 1101, 1102, respectively, connected to the source (S) and the drain Pole (D), thereby forming a cell structure, as shown in Figure 1J.
  • a lithography step is required.
  • a mask plate, a glue coating, a development exposure, and a glue removal step are used. Therefore, preparation The process is complicated and the cost is rising and the efficiency is low.
  • step 1 a silicon wafer 200 is provided as a substrate, and a silicon epitaxial layer 201 is formed on the silicon substrate, as shown in FIG. 2A.
  • the silicon wafer 200 and the silicon epitaxial layer 201 are used as a semiconductor substrate.
  • the semiconductor substrate material may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V Compound semiconductors also include multilayer structures composed of these semiconductors or silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) And germanium on insulator (GeOI), etc.
  • Devices such as NMOS and / or PMOS may be formed on the semiconductor substrate.
  • a conductive member may also be formed in the semiconductor substrate, and the conductive member may be the gate, source, or drain of the transistor.
  • Step 2 forming a first oxide layer 202, forming a first oxide layer 202 on the silicon epitaxial layer 201, and forming a trench, forming the trench in the first oxide layer 202 and the silicon epitaxial layer 201, the first oxide layer It is a thermal oxide layer TOX, as shown in FIG. 2B.
  • the first oxide layer 202 may use various oxides, such as silicon dioxide.
  • the first oxide layer can be produced by methods such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition) and the like.
  • the step of removing the first oxide layer 202 is also included.
  • Step 3 forming a second oxide layer 203 and filling polysilicon, forming a second oxide layer 203 on the surface of the silicon epitaxial layer and the trench, the second oxide layer is a gate oxide layer GOX, and depositing polysilicon on the surface of the gate oxide layer GOX, Fill the trench and above the trench.
  • the method further includes the step of etching the polysilicon layer 204 to etch the polysilicon layer 204.
  • the height of the etched polysilicon layer 204 is lower than the top surface of the groove, as shown in FIG. 2C.
  • the second oxide layer 203 can be made of various insulating materials, such as oxide, nitride, oxynitride, and the like.
  • the second oxide layer can be produced by methods such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition) and the like.
  • the second oxide layer uses TEOS (ethyl orthosilicate, Si (OC2H5) 4) oxide, that is, silicon dioxide formed by TEOS (ethyl orthosilicate, Si (OC 2 H 5 ) 4 ) Floor.
  • TEOS ethyl orthosilicate, Si (OC2H5)
  • the second oxide layer 203 is manufactured by a furnace tube process, the process temperature is 680 degrees exemplarily, and the thickness of the second oxide layer 203 is exemplarily
  • Step 4 a well region 205 is formed, and a well region of a second doping type, such as a P-type well region 205, is implanted into the silicon epitaxial layer 201, as shown in FIG. 2D.
  • a well region of a second doping type such as a P-type well region 205
  • the well region 205 may also be of the first doping type, such as an N-well region.
  • step 5 an interlayer dielectric layer (ILD) 207 is formed, and an interlayer dielectric layer 207 is formed over the trench and well region 205, as shown in FIG. 2E.
  • ILD interlayer dielectric layer
  • the interlayer dielectric layer is deposited between different layers to isolate the conductive layer to be deposited next.
  • the interlayer dielectric layer usually refers to the insulating layer between the semiconductor layer and the metal layer, which can be a single layer
  • the layer structure may be a multi-layer structure.
  • Step 6 forming a hole contact hole 208, forming a contact hole (CT) 208 on the interlayer dielectric layer 207, the contact hole 208 extends from the top to the bottom of the interlayer dielectric layer 207, and the contact hole 208 The bottom is located on the upper surface of the well region 205, as shown in FIG. 2F.
  • CT contact hole
  • a first source / drain region 206 is formed, and a first source / drain region 206 is formed in the well region 205.
  • the first source / drain region 206 is of a first doping type, for example, an N-type source / drain region, As shown in FIG. 2G; the first source / drain region 206 may also be of a second doping type, such as a P-type source / drain region.
  • the implantation of the first source / drain region 206 is completed through the contact hole 208.
  • the first source / drain region 206 is formed by implantation, and an ion implantation doping process may be used. This process is to implant an ion beam accelerated to a certain high energy into the surface layer of a solid material to change the surface layer physical and Chemical process. Implanting corresponding impurity atoms into the semiconductor (such as implanting boron, phosphorus or arsenic into silicon) can change the surface conductivity or form a PN junction to form N-type source / drain regions, and choose to implant phosphorus or arsenic into silicon However, when forming P-type source / drain regions, boron is implanted in silicon. Of course, the choice of dopant is not limited to the above.
  • the first doping type and the second doping type generally refer to P-type or N-type, where the first doping type and the second doping type are opposite, such as the first doping
  • the hetero type is one of P type, low doped P-type, and high doped P + type
  • the second doped type is one of N type, low doped N- type, and high doped N + type.
  • the first doping type is one of N-type, low-doping N-type, and high-doping N + type
  • the second doping type is P-type, low-doping P-type, and high-doping P + type one of them.
  • Step 9 Expand the size of the first source / drain region 206 to expand to the lateral region to make it larger and closer to the trench position, as shown in FIG. 2H; the way to expand the size of the first source / drain region Heat treatment can be used.
  • Step 10 Deepen the hole and further process the contact hole 208, such as photolithography, to deepen the depth of the contact hole 208 so that the bottom of the contact hole 208 is lower than the lower surface of the first source / drain region, As shown in Figure 2I.
  • Step 11 forming a second source / drain region 209, and forming the second source / drain region 209 through the deepened contact hole 208, such as a P-type source / drain region, as shown in FIG. 2J; the source / drain region 209 also It may be a first doping type N-type source / drain region.
  • step 10 further includes the step of filling the contact hole 208.
  • Step 12 forming a cell structure, forming contact layers 2101,2102 above the interlayer dielectric layer ILD207 and below the silicon wafer substrate, and forming leads through the contact layers 2101,2102, respectively, connected to the source Pole (S) and drain (D), thereby forming a cell structure, as shown in Figure 2K.
  • an etching method may be used, and the etching includes wet etching and / or dry etching.
  • the method of mask implantation is used.
  • the embodiment shown in FIG. 2 is:
  • the step of forming the first source / drain region is formed after the step of etching the interlayer dielectric layer to form the CT contact hole, and the mask plate is not used in the process of forming the N-type source / drain region, and the manufacturing process is omitted
  • the lithography link in the process saves manufacturing costs, reduces process complexity, and improves production efficiency.
  • the diffusion can be realized by a thermal process, and the manufacturing process can be fully compatible with the existing process.
  • the first source / drain region mask and the corresponding lithography link are not used in the process of forming the first source / drain region, therefore, in the embodiment shown in FIG. 2, during the formation of the cell device , It can reduce the use of mask plate and photolithography process, on the premise of fully compatible with the existing process, to achieve the reduction of process complexity, improve production efficiency, save production costs, etc.
  • a method of manufacturing a semiconductor device characterized in that it includes:
  • Step S101 providing a semiconductor substrate
  • Step S102 forming a trench in the semiconductor substrate
  • Step S103 forming an interlayer dielectric layer above the trench and the semiconductor substrate
  • Step S104 forming a contact hole on the interlayer dielectric layer, the contact hole extending from the top to the bottom of the interlayer dielectric layer;
  • Step S105 forming a first source / drain region through the contact hole implantation
  • Step S106 forming a second source / drain region through the contact hole implantation.
  • the present invention also provides a semiconductor device, including: a semiconductor substrate; a trench formed in the semiconductor substrate; an interlayer dielectric layer formed in the trench and the Above the semiconductor substrate; contact holes formed in the interlayer dielectric layer and the semiconductor substrate; first source / drain regions and second source / drain regions, the first source / drain regions and the The second source / drain regions are all formed through the contact holes.
  • the semiconductor device further includes a well region formed in the semiconductor substrate, and both the first source / drain region and the second source / drain region are formed in the well region.
  • the semiconductor device further includes contact layers formed above and below the semiconductor device, respectively, connected to the source electrode and the drain electrode, thereby forming a cell structure.
  • the present invention can omit the source / drain region mask, and at the same time omit the manufacturing lithography link, saving manufacturing costs.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种半导体器件及其制造方法，所述方法包括：提供半导体衬底；在所述半导体衬底内形成沟槽；在所述沟槽和所述半导体衬底上方形成层间介电层；在所述层间介电层上形成接触孔，该接触孔从层间介电层的顶端向底部延伸；通过所述接触孔注入形成第一源/漏区；通过所述接触孔注入形成第二源/漏区。

Description

一种半导体器件及其制造方法 技术领域
本发明涉及半导体技术领域，具体而言涉及一种半导体器件结构及其制造方法。
背景技术
沟槽型VDMOS产品是较为广泛应用的功率器件，一方面，沟槽工艺的成熟使单元胞尺寸进一步下降，另一方面，由于沟槽区域穿过P型基区最下端，形成的沟道位于源区与漂移区之间，相比普通VDMOS消除JFET区，导通电阻大大减小，所以沟槽型VDMOS极大提高了MOS功率器件的性能。对于沟槽型VDMOS，如今采用的结构是沟槽内多晶硅栅平面低于硅平面，制造过程是刻蚀沟槽、生长栅氧、多晶硅淀积、多晶硅刻蚀、阱区形成、NSD形成、孔形成、金属电极形成、背面工艺。基于以上制造方法使用到的掩模板至少有沟槽掩模板、NSD掩模板、CT掩模板、金属掩模板，其次为提高性能，还会增加如钝化层掩模板等。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
针对的不足，本发明一方面提供一种半导体器件，包括：半导体衬底；沟槽，形成于所述半导体衬底中；层间介电层，形成于所述沟槽和所述半导体衬底上方；接触孔，形成于所述层间介电层和所述半导体衬底中；第一源/漏区和第二源/漏区，所述第一源/漏区和所述第二源/漏区均通过所述接触孔形成。
本发明再一方面提供一种制造方法，包括：提供半导体衬底；在所述半导体衬底内形成沟槽；在所述沟槽和所述半导体衬底上方形成层间介电层； 在所述层间介电层上形成接触孔，该接触孔从层间介电层的顶端向底部延伸；通过所述接触孔注入形成第一源/漏区；通过所述接触孔注入形成第二源/漏区。
本发明可以省去源/漏区掩模板，同时省去制造光刻环节，节省制造成本。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1A至图1J示出了本发明一个实施方式的半导体器件的制造方法的相关步骤所获得的器件的剖面示意图；
图2A至图2K示出了本发明一个实施方式的半导体器件的制造方法的相关步骤所获得的器件的剖面示意图；
图3示出了本发明一个实施方式的VDMOS器件的制造方法的相关步骤示意图。
附图标记说明
100，200硅片
101，201硅外延层
102，202第一氧化层
103，203第二氧化层
104，204多晶硅层
105，205阱区
106，206第一源/漏区
107，207层间介电层
108，208接触孔
109，209第二源/漏区
1101，1102，2101，2102接触层
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆， 对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所 示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
为了彻底理解本发明，将在下列的描述中提出详细步骤以及结构，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
为了解决前述的技术问题，本发明提供一种本发明一方面提供一种半导体器件及其制造方法，包括：半导体衬底；沟槽，形成于所述半导体衬底中；层间介电层，形成于所述沟槽和所述半导体衬底上方；接触孔，形成于所述层间介电层和所述半导体衬底中；第一源/漏区和第二源/漏区，所述第一源/漏区和所述第二源/漏区均通过所述接触孔形成。
综上所述，本发明的可以省去源/漏区掩模板，同时省去制造光刻环节，节省制造成本。
下面参见图1至图1J所示出的本发明一个实施方式的半导体器件的制造方法的相关步骤所获得的器件的剖面示意图来说明VDMOS的制造过程。
步骤1，提供硅片100，作为基板，并在硅基板上形成硅外延层101，如图1A所示。
步骤2，形成第一氧化层102，在硅外延层101上形成第一氧化层102，并形成沟槽，在第一氧化层102和硅外延层101内形成所述沟槽，第一氧化层为热氧化层，如图1B所示。
在一实施例中，形成所述沟槽后，将硅外延层101上方的第一氧化层102去除。
步骤3，形成第二氧化层103并填充多晶硅，在硅外延层101的表面和沟槽内形成第二氧化层103，第二氧化层为栅氧化层GOX，在栅氧化层GOX的表面沉积多晶硅，对沟槽及沟槽上方进行填充。
在一实施例中，还包括刻蚀多晶硅层104的步骤，对多晶硅层104进行刻蚀，刻蚀后的多晶硅层104顶部高度的位置低于凹槽的顶面位置，如图1C所示。
步骤4，形成阱区105，在硅外延层101中注入形成P阱区，如图1D所示；
步骤5，形成NSD，即N型的第一源/漏区106，在阱区105中注入形成N型的第一源/漏区106，如图1E所示。
步骤6，形成层间介电层(ILD)107，在沟槽和第一源/漏区106上方形成层间介电层107，如图1F所示。
步骤7，形成孔108，在层间介电层107上形成接触孔(CT)108，该接触孔108从层间介电层107的顶端向底部延伸，且该接触孔108的底部位于所述第一源/漏区106的上表面，如图1G所示。
步骤8，深化孔，对CT接触孔进行进一步处理，比如光刻，以加深所述接触孔108的深度，如图1H所示。
步骤9，通过接触孔108进行注入形成PSD，即P型的第二源/漏区109，如图1I所示。
步骤10，形成元胞结构，在层间介电层107的上方和硅片100的下方形成接触层1101,1102，并且通过接触层1101,1102分别形成引线，连接于源极(S)和漏极(D)，从而形成元胞结构，如图1J所示。
前述实施方式的缺点如下：
制造过程中步骤2，7，8，10过程中，均需用到光刻步骤，每一次光刻步骤中均需用到掩膜板、涂胶显影曝光、去胶等步骤，因此，导致制备工艺的复杂以及成本的上升而且效率较低。
下面参见图2A至图2K所示出的本发明一个实施方式的VDMOS器件的制造方法的相关步骤所获得的器件的剖面示意图来说明VDMOS的又一制造过程。
步骤1，提供硅片200，作为基板，并在硅基板上形成硅外延层201，如图2A所示。
硅片200和硅外延层201作为半导体衬底半导体衬底材料可以是以下所提到的材料中的至少一种：Si、Ge、SiGe、SiC、SiGeC、InAs、GaAs、InP或者其它III/V化合物半导体，还包括这些半导体构成的多层结构等或者为绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。半导体衬底上可以形成有器件，例如NMOS和/或PMOS等。同样，半导体衬底中还可以形成有导电构件，导电构件可以是晶体管的栅极、源极或漏极等等。
步骤2，形成第一氧化层202，在硅外延层201上形成第一氧化层202，并形成沟槽，在第一氧化层202和硅外延层201内形成所述沟槽，第一氧化层为热氧化层TOX，如图2B所示。
第一氧化层202可以采用各种氧化物，例如二氧化硅。第一氧化层可以通过诸如热氧化法、PVD(物理气相沉积)、CVD(化学气相沉积)、ALD(原子层沉积)等方法制作。
形成所述沟槽后，还包括将第一氧化层202去除的步骤。
步骤3，形成第二氧化层203并填充多晶硅，在硅外延层的表面和沟槽内形成第二氧化层203，第二氧化层为栅氧化层GOX，在栅氧化层GOX的表面沉积多晶硅，对沟槽及沟槽上方进行填充。
在一实施例中，还包括刻蚀多晶硅层204的步骤，对多晶硅层204进行刻蚀，刻蚀后的多晶硅层204顶部高度的位置低于凹槽的顶面位置，如图2C所示。
第二氧化层203可以采用各种绝缘材料制作，例如氧化物、氮化物、氮氧化物等。第二氧化层可以通过诸如热氧化法、PVD(物理气相沉积)、CVD(化学气相沉积)、ALD(原子层沉积)等方法制作。
示例性地，第二氧化层采用TEOS(正硅酸乙酯，Si(OC2H5)4)氧化物，即利用TEOS(正硅酸乙酯，Si(OC 2H 5) 4)形成的二氧化硅层。示例性地，第二氧化层203采用炉管工艺制作，工艺温度示例地为680度，第二氧化层203厚度示例性地为
Figure PCTCN2019115932-appb-000001
步骤4，形成阱区205，在硅外延层201中注入形成第二掺杂类型的阱区，比如P型的阱区205，如图2D所示。
可选地，该阱区205也可以是第一掺杂类型，比如N阱区。
步骤5，形成层间介电层(ILD)207，在沟槽和阱区205上方形成层间介电层207，如图2E所示。
层间介电层是沉积在不同层之间，用来和下一步要沉积的导电层做一隔离，层间介电层通常指位于半导体层和金属层之间的绝缘层，其可以为单层结构，可以为多层结构，通过对介电层自身参数的选择，比如介电系数，导热系数等，可以获得需要的导热性及RC延迟时间常数。
步骤6，形成孔接触孔208，在所述层间介电层207上形成接触孔(CT)208，该接触孔208从层间介电层207的顶端向底部延伸，且该接触孔208的底部位于所述阱区205的上表面，如图2F所示。
步骤7，形成第一源/漏区206，在阱区205中形成第一源/漏区206，该第一源/漏区206为第一掺杂类型，比如，N型源/漏区，如图2G所示；该第一源/漏区206也可以第二掺杂类型，比如P型源/漏区。
第一源/漏区206的注入通过所述接触孔208完成。
其中所述第一源/漏区206是通过注入方式形成的，可以采用离子注入掺杂工艺，该工艺是将加速到一定高能量的离子束注入固体材料表面层内，以改变表面层物理和化学性质的工艺。在半导体中注入相应的杂质原子(如在硅中注入硼、磷或砷等)，可改变其表面电导率或形成PN结，形成N型源/漏区时，选用在硅中注入磷或砷，而形成P型源/漏区时，选用在硅中注入硼，当然，掺杂剂的选择并不限于以上几种。
需要说明的是，本说明书中第一掺杂类型和第二掺杂类型泛指P型或N型，其中，所述第一掺杂类型和所述第二掺杂类型相反，比如第一掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一，第二掺杂类型是N型，低掺杂N-型，高掺杂N+型其中之一。或者相反地，第一掺杂类型是N型，低掺杂N-型，高掺杂N+型其中之一，第二掺杂类型是P型，低掺杂P-型，高掺杂P+型其中之一。
步骤9，扩展第一源/漏区206的尺寸，使其向横向区域扩展，使其尺寸更大并且更靠近沟槽位置，如图2H所示；该扩展第一源/漏区尺寸的方式可以采用热处理。
步骤10，深化孔，对接触孔208进行进一步处理，比如光刻，以加深所述接触孔208的深度，以使得该接触孔208的底部低于所述第一源/漏区的下表面，如图2I所示。
步骤11，形成第二源/漏区209，通过所述深化接触孔208进行形成第二源/漏区209，比如P型源/漏区，如图2J所示；该源/漏区209也可以是第一掺杂类型N型源/漏区。
在另一实施例中，步骤10还包括接触孔208的填充步骤。
步骤12，形成元胞结构，在所述层间介电层ILD207的上方和所述硅片基板的下方形成接触层2101,2102，并且通过所述接触层2101,2102分别形成引线，连接于源极(S)和漏极(D)，从而形成元胞结构，如图2K所示。在步骤2，3，6，9中分别形成沟槽、多晶硅层的形成和/或接触孔的过程中，可以采用蚀刻的方法形成，所述蚀刻包括湿法蚀刻和/或干法蚀刻。在步骤4，7，10中分别执行注入操作时，采用掩膜注入的方式。
附图2所示的实施方式相较于附图1所示的实施方式而言：
形成第一源/漏区的步骤在层间介电层刻蚀形成CT接触孔的步骤后形成，且形成N型源/漏区的过程中并没有使用掩膜板，同时省去了制造工艺中的光刻环节，节省了制造成本，降低了工艺复杂度，提高了生产效率。
并且相较于附图1所示的实施方式，仅增加了一道第一源/漏区扩散，该扩散可以采用热工艺实现，其制造工艺能够与现有工艺完全兼容。
由于在形成第一源/漏区区的过程中没有用到第一源/漏区掩膜板以及相应的光刻环节，因此，附图2所示的实施例中，在形成元胞器件过程中，能够减少掩膜板及光刻工艺的使用，在与现有工艺完全兼容的前提下，实现了降低工艺复杂度，提高生产效率，节约生产成本等。
下面参见图3所示出的本发明一个实施方式的VDMOS器件的制造方法的相关步骤示意图。一种半导体器件的制造方法，其特征在于，包括：
步骤S101，提供半导体衬底；
步骤S102，在所述半导体衬底内形成沟槽；
步骤S103，在所述沟槽和所述半导体衬底上方形成层间介电层；
步骤S104，在所述层间介电层上形成接触孔，该接触孔从层间介电层的顶端向底部延伸；
步骤S105，通过所述接触孔注入形成第一源/漏区；
步骤S106，通过所述接触孔注入形成第二源/漏区。
在另一个实施例中，本发明还提供了一种半导体器件，包括：半导体衬底；沟槽，形成于所述半导体衬底中；层间介电层，形成于所述沟槽和所述半导体衬底上方；接触孔，形成于所述层间介电层和所述半导体衬底中；第一源/漏区和第二源/漏区，所述第一源/漏区和所述第二源/漏区均通过所述接触孔形成。
半导体器件还包括阱区，阱区形成于所述半导体衬底中，第一源/漏区和第二源/漏区均形成于阱区中。
半导体器件还包括接触层，分别形成于所述半导体器件的上方和下方，连接于源极和漏极，从而形成元胞结构。
根据以上分析，本发明可以省去源/漏区掩模板，同时省去制造光刻环节，节省制造成本。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围 内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (15)

  1. 一种半导体器件，包括：
    半导体衬底；
    沟槽，形成于所述半导体衬底中；
    层间介电层，形成于所述沟槽和所述半导体衬底上方；
    接触孔，形成于所述层间介电层和所述半导体衬底中；以及
    第一源/漏区和第二源/漏区，所述第一源/漏区和所述第二源/漏区均通过所述接触孔形成。
  2. 如权利要求1所述的半导体器件，其中，还包括
    阱区，所述阱区形成于所述半导体衬底中，所述第一源/漏区和所述第二源/漏区均形成于所述阱区中。
  3. 如权利要求1或2所述的半导体器件，其中，所述第一源/漏区的尺寸大于所述第二源/漏区的尺寸。
  4. 如权利要求1或2所述的半导体器件，其中，还包括：接触层，分别形成于所述半导体器件的上方和下方，连接于源极和漏极，从而形成元胞结构。
  5. 一种半导体器件的制造方法，包括：
    提供半导体衬底；
    在所述半导体衬底内形成沟槽；
    在所述沟槽和所述半导体衬底上方形成层间介电层；
    在所述层间介电层上形成接触孔，该接触孔从层间介电层的顶端向底部延伸；
    通过所述接触孔注入形成第一源/漏区；以及
    通过所述接触孔注入形成第二源/漏区。
  6. 如权利要求5所述的制造方法，其中，还包括：形成阱区，所述阱区形成于所述半导体衬底中，所述第一源/漏区和所述第二源/漏区均形成于所述阱区中。
  7. 如权利要求5所述的制造方法，其中，在形成所述第一源/漏区和所述第二源/漏区的步骤之间还包括步骤：扩展所述第一源/漏区，使其更靠近沟槽。
  8. 如权利要求7所述的制造方法，其中，采用热处理实现扩展所述第一源/漏区。
  9. 如权利要求5所述的制造方法，其中，还包括深化孔步骤，在形成第一源/漏区后对所述接触孔进行进一步处理从而加深所述接触孔的深度，以使得所述接触孔的底部低于所述第一源/漏区的下表面。
  10. 如权利要求9所述的制造方法，其中，利用深化后的接触孔形成第二源/漏区。
  11. 如权利要求5-10任一项所述的制造方法，其中，还包括所述接触孔的填充步骤。
  12. 如权利要求5-10任一项所述的制造方法，其中，在所述层间介电层的上方和所述半导体衬底的下方形成接触层，并且通过所述接触层分别形成引线，连接于源极和漏极，从而形成元胞结构。
  13. 如权利要求6所述的制造方法，其中，所述第一源/漏区为第一掺杂类型，所述第二源/漏区为第二掺杂类型，所述阱区为第二掺杂类型。
  14. 如权利要求13所述的制造方法，其中，所述第一掺杂类型为N型，所述第二掺杂类型为P型。
  15. 如权利要求5所述的制造方法，其中，所述半导体器件为VDMOS器件。
PCT/CN2019/115932 2018-11-06 2019-11-06 一种半导体器件及其制造方法 Ceased WO2020094044A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6534830B2 (en) * 1999-05-12 2003-03-18 Infineon Technologies Ag Low impedance VDMOS semiconductor component
CN102064132A (zh) * 2009-11-18 2011-05-18 无锡华润上华半导体有限公司 半导体结构的制造方法
CN103187287A (zh) * 2011-12-29 2013-07-03 立新半导体有限公司 一种沟槽半导体分立器件的制备方法
US20160329413A1 (en) * 2013-06-21 2016-11-10 Chip Integration Tech. Co., Ltd. Structure of Trench-Vertical Double Diffused MOS Transistor and Method of Forming the Same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076342A (ja) * 2000-09-05 2002-03-15 Fuji Electric Co Ltd トレンチゲート型半導体装置
CN103632964A (zh) * 2012-08-21 2014-03-12 深圳市力振半导体有限公司 一种制备沟槽半导体功率器件的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6534830B2 (en) * 1999-05-12 2003-03-18 Infineon Technologies Ag Low impedance VDMOS semiconductor component
CN102064132A (zh) * 2009-11-18 2011-05-18 无锡华润上华半导体有限公司 半导体结构的制造方法
CN103187287A (zh) * 2011-12-29 2013-07-03 立新半导体有限公司 一种沟槽半导体分立器件的制备方法
US20160329413A1 (en) * 2013-06-21 2016-11-10 Chip Integration Tech. Co., Ltd. Structure of Trench-Vertical Double Diffused MOS Transistor and Method of Forming the Same

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