WO2020087387A1 - 集成电路器件及其制备方法 - Google Patents

集成电路器件及其制备方法 Download PDF

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Publication number
WO2020087387A1
WO2020087387A1 PCT/CN2018/113167 CN2018113167W WO2020087387A1 WO 2020087387 A1 WO2020087387 A1 WO 2020087387A1 CN 2018113167 W CN2018113167 W CN 2018113167W WO 2020087387 A1 WO2020087387 A1 WO 2020087387A1
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Prior art keywords
dummy gate
fin
gate
semiconductor layer
exposed
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PCT/CN2018/113167
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English (en)
French (fr)
Inventor
朴善钦
马小龙
刘燕翔
汪大祥
陈赞锋
夏禹
陈华彬
周永杰
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2018/113167 priority Critical patent/WO2020087387A1/zh
Priority to CN201880092717.XA priority patent/CN112074930A/zh
Priority to EP18938517.2A priority patent/EP3863042A4/en
Publication of WO2020087387A1 publication Critical patent/WO2020087387A1/zh
Priority to US17/244,410 priority patent/US20210249311A1/en

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    • H—ELECTRICITY
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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Definitions

  • the present application relates to the field of semiconductor technology, in particular to an integrated circuit device and a method of manufacturing the same.
  • an isolation segment needs to be formed between adjacent transistors discharged together.
  • FIG. 1 taking two transistors as an example, when the two transistors are designed to be discharged together, the active regions 50 of the two transistors cannot be directly connected together, and it is usually necessary to form an isolation section between the two transistors 70, so that the two transistors can work independently, the electrical characteristics and logical operations do not affect each other. Therefore, how to achieve isolation between transistors is a very important technical point.
  • the present application provides an integrated circuit device and a method for manufacturing the same.
  • a simple process can form an isolation section for suppressing leakage current paths of two adjacent transistors.
  • a first aspect of the present application provides an integrated circuit device including: a substrate and a fin protruding from the substrate.
  • the integrated circuit device further includes two adjacent transistors, and the two adjacent transistors connect the fins
  • the two sections of the gap serve as their respective channels; where a portion of the fin between the two sections of the gap is processed to obtain an isolation section, which is used to suppress the separation between the two channels of two adjacent transistors Current transfer.
  • the current transfer between the two channels of the two transistors can be suppressed, which has a greater impact on the structure and stress of the transistors on both sides of the isolation section Small, introduced device characteristic parameter variability is minimum, the area resource occupied by the isolation section is small, and no special winding resources need to be designed.
  • the fin includes a first semiconductor layer, wherein the isolation is doped with inert atoms.
  • the fin includes a first semiconductor layer, and the thickness of the first semiconductor layer in the isolation section is less than the thickness of the channels of two adjacent transistors.
  • the fin includes alternately arranged first semiconductor layers and auxiliary layers
  • the auxiliary layer includes a gate material layer and a gate dielectric material layer wrapped around the gate material layer, and the isolation section and the channel are formed in the first semiconductor layer in.
  • the inert atom includes at least one of a hydrogen atom, an oxygen atom, a nitrogen atom, a carbon atom, and a silicon atom.
  • a method for manufacturing an integrated circuit device is provided.
  • a fin protruding from the substrate is formed on a substrate; at least two first dummy gates and at least one second dummy gate are formed; at least two first dummy The gate and at least one second dummy gate are arranged along the length of the gate, and each second dummy gate is located between two adjacent first dummy gates; the first dummy gate and the second dummy gate are opposite to the fins
  • the two side surfaces and the top surface are in contact; an interlayer insulating layer is formed, the upper surface of the interlayer insulating layer is flush with the upper surfaces of the first dummy gate and the second dummy gate; at least the second dummy gate is removed, and the fin
  • the exposed part is processed to form an isolation section to suppress the current from passing through the exposed part of the fin after the second dummy gate is removed.
  • the second dummy gate can be removed by a simple process, so that the second dummy gate can be removed and exposed
  • the semiconductor wafer is processed to form an isolation section that suppresses leakage current paths of two adjacent transistors.
  • the isolation section is formed based on this method, it has a small effect on the structure and stress of the transistors on both sides of the isolation section, the introduced device characteristic parameters have the least variability, the area resource occupied by the isolation section is small, and no special winding resources need to be designed. advantage.
  • the fin includes a first semiconductor layer; processing the exposed portion of the fin second dummy gate after removal to form an isolation section to suppress current transfer in the exposed portion of the fin second dummy gate removed, Including: adopting a process of plasma treatment, plasma implantation and ion implantation to dope the inert atoms of the exposed part of the first semiconductor layer after the second dummy gate is removed to insulate the exposed part of the first semiconductor layer Change.
  • the inert atom includes at least one of a hydrogen atom, an oxygen atom, a nitrogen atom, a carbon atom, and a silicon atom.
  • the fin includes a first semiconductor layer; processing the exposed portion of the fin second dummy gate after removal to form an isolation section to suppress current transfer in the exposed portion of the fin second dummy gate removed,
  • the method includes: using an etching process to process the exposed part of the first semiconductor layer after the second dummy gate is removed, so as to change the appearance of the exposed part of the first semiconductor layer.
  • an etching process is used to process the exposed part of the first semiconductor layer after the second dummy gate is removed to change the morphology of the exposed part of the first semiconductor layer, including: At least a portion of the first semiconductor layer exposed after the second dummy gate is removed is processed to reduce the thickness of the exposed portion of the first semiconductor layer in a direction perpendicular to the gate length direction or the thickness direction of the substrate.
  • an etching process is used to process the exposed part of the first semiconductor layer after the second dummy gate is removed to change the morphology of the exposed part of the first semiconductor layer, including: The fin exposed after the second dummy gate is removed is processed to change the shape of the exposed portion of the first semiconductor layer.
  • the fin is composed of a first semiconductor layer; at least the second dummy gate is removed, and the exposed part of the fin is removed after the second dummy gate is removed to form an isolation section to suppress current flow in the fin
  • the transfer of the exposed part of the second dummy gate after the removal includes: removing the second dummy gate, and processing the exposed part of the fin after the second dummy gate is removed to form an isolation section to suppress current flow in the fin
  • Two parts exposed after the removal of the dummy gate; after forming the isolation section, the manufacturing method of the integrated circuit device further includes: removing the first dummy gate, and forming a gate dielectric at the position where the first dummy gate and the second dummy gate are removed, respectively Layer and gate.
  • the fin includes multiple first semiconductor layers and multiple second semiconductor layers, the first semiconductor layers and the second semiconductor layers are alternately arranged along the thickness direction of the substrate; before forming the interlayer insulating layer, the integrated circuit device
  • the preparation method further includes: forming side walls on both sides of the first dummy gate and the second dummy gate along the length of the gate; removing side walls that are not the first dummy gate and both sides, the second dummy gate, and both sides thereof
  • the fin covered by the side wall of the fin; the second semiconductor layer of the remaining fin, the area covered by the side wall is processed to form an inner wall, and the remaining area not covered by the side wall is used as a sacrificial layer; at least the second dummy gate is removed , And process the exposed part of the second dummy gate of the fin, including: removing the first dummy gate, the second dummy gate, and the sacrificial layer, and perform the exposed part of the second dummy gate of the fin Process to form an isolation section to suppress the transfer of
  • FIG. 1 is a schematic diagram of forming an isolation section between adjacent transistors provided by the prior art
  • FIG. 2 is a schematic flow chart of a method for manufacturing an integrated circuit device provided by this application.
  • FIG. 3 is a schematic flowchart of another method for manufacturing an integrated circuit device provided by this application.
  • 4a is a schematic diagram of forming a fin on a substrate provided by this application.
  • 4b is another schematic diagram of forming a fin on a substrate provided by this application.
  • FIG. 5a is a schematic diagram of forming a first dummy gate and a second dummy gate on the basis of FIG. 4a;
  • FIG. 5b is a schematic cross-sectional view taken along the line A1A1 ′ in FIG. 5a;
  • FIG. 5c is a schematic cross-sectional view of B1B1 ′ in FIG. 5a;
  • FIG. 5d is a schematic cross-sectional view of C1C1 ′ in FIG. 5a;
  • FIG. 6a is a schematic diagram of forming a side wall on the basis of FIG. 5a;
  • FIG. 6b is a schematic cross-sectional view taken along the line A2A2 'in FIG. 6a;
  • FIG. 7a is a schematic diagram of forming a source and a drain on the basis of FIG. 6a;
  • FIG. 7b is a schematic cross-sectional view of A3A3 ′ in FIG. 7a;
  • FIG. 8a is a schematic diagram of forming an interlayer insulating layer on the basis of FIG. 7a;
  • FIG. 8b is a schematic cross-sectional view taken along the line A4A4 'in FIG. 8a;
  • FIG. 9a is a schematic diagram after removing the second dummy gate on the basis of FIG. 8a;
  • FIG. 9b is a schematic cross-sectional view taken along the line A5A5 'in FIG. 9a;
  • FIG. 9c is a schematic cross-sectional view of B5B5 'in FIG. 9a;
  • 9d is a schematic diagram of forming a first photosensitive layer exposing the second dummy gate on the interlayer insulating layer before removing the second dummy gate;
  • FIG. 10a is a schematic diagram of forming an isolation section based on FIG. 9a;
  • FIG. 10b is a schematic cross-sectional view taken along the line A6A6 'in FIG. 10a;
  • 10c is a schematic cross-sectional view taken along B6B6 'in FIG. 10a;
  • FIG. 11a is a schematic diagram of forming a gate dielectric layer and a gate on the basis of FIG. 10a;
  • FIG. 11b is a schematic cross-sectional view taken along the line A7A7 'in FIG. 11a;
  • FIG. 11c is a schematic cross-sectional view taken along B7B7 ′ in FIG. 11a;
  • 11d is a schematic cross-sectional view taken along line C7C7 'in FIG. 11a;
  • FIG. 12 is a schematic flowchart of another method for manufacturing an integrated circuit device provided by the present application.
  • FIG. 13a is a schematic diagram of forming a fin and a first dummy gate and a second dummy gate on a substrate provided by this application;
  • FIG. 13b is a schematic cross-sectional view taken along the line D1D1 'in FIG. 13a;
  • 13c is a schematic cross-sectional view taken along E1E1 'direction in FIG. 13a;
  • FIG. 13d is a schematic cross-sectional view of F1F1 ′ in FIG. 13a;
  • FIG. 14a is a schematic diagram of forming a side wall on the basis of FIG. 13a and removing fins not covered by the first dummy gate and the side walls on both sides, the second dummy gate and the side walls on both sides;
  • FIG. 14b is a schematic cross-sectional view taken along the line D2D2 'in FIG. 14a;
  • FIG. 14c is a schematic diagram of forming an inner wall and a sacrificial layer on the basis of FIG. 14b;
  • 15a is a schematic diagram of forming a source and a drain on the basis of FIG. 14a;
  • FIG. 15b is a schematic cross-sectional view taken along the line D3D3 'in FIG. 15a;
  • 16a is a schematic diagram of forming an interlayer insulating layer on the basis of FIG. 15a;
  • 16b is a schematic cross-sectional view taken along D4D4 'in FIG. 16a;
  • 17a is a schematic diagram after removing the first dummy gate, the second dummy gate, and the sacrificial layer based on FIG. 16a;
  • 17b is a schematic cross-sectional view taken along the line D5D5 'in FIG. 17a;
  • 17c is a schematic cross-sectional view taken along E5E5 'in FIG. 17a;
  • 17d is a schematic cross-sectional view of F5F5 ′ in FIG. 17a;
  • 17e is a schematic diagram of forming a second photosensitive layer that exposes and removes the second dummy gate region before processing the first semiconductor layer in the fin exposed after the second dummy gate is removed;
  • FIG. 18a is a schematic cross-sectional view taken along the line D5D5 'after the isolation section is formed on the basis of FIG. 17b;
  • 18b is a schematic cross-sectional view of the E5E5 ′ direction after the isolation section is formed on the basis of FIG. 17c;
  • 18c is a schematic cross-sectional view of the F5F5 ′ direction after the isolation section is formed on the basis of FIG. 17d;
  • 19a is a schematic diagram of forming a gate dielectric layer and a gate on the basis of FIG. 17a;
  • 19b is a schematic cross-sectional view taken along the line D7D7 'in FIG. 19a;
  • 19c is a schematic cross-sectional view taken along the line E7E7 'in FIG. 19a;
  • FIG. 19d is a schematic cross-sectional view taken along F7F7 'in FIG. 19a.
  • An embodiment of the present application provides a method for manufacturing an integrated circuit device, as shown in FIG. 2, including:
  • a fin 20 protruding from the substrate 10 is formed on the substrate 10.
  • the multiple fins 20 may be divided into multiple groups, each group including at least one fin 20, and each group including multiple In the case of one fin 20, a plurality of fins 20 are arranged in parallel.
  • the thickness t of the fin 20 may be on the order of nanometers, and the thickness direction of the fin 20 is perpendicular to the gate length direction and the thickness direction of the substrate 10.
  • the shape of the fin 20 may have a substantially rectangular shape, for example.
  • the fin 20 has four side surfaces extending vertically from the upper surface of the substrate 10 and top surfaces on the four side surfaces, and the top surface may be substantially parallel to the upper surface of the substrate 10.
  • FIG. 4a is illustrated by a group including three fins 20, but the present application is not limited thereto.
  • a group may also include only one fin 20.
  • 4a and 4b only illustrate the formation of a group of fins 20 on the substrate 10, but the present application is not limited thereto, and may be determined according to the design of a specific integrated circuit device.
  • the method for manufacturing the integrated circuit device provided by the embodiments of the present application uses three fins 20 formed on the substrate 10, and the three fins 20 are used as a group for illustrative description.
  • At least two first dummy gates 31 and at least one second dummy gate 32 are formed; at least two first dummy gates 31 and at least one second dummy gate 32 are along the gate length direction X Arranged, and each second dummy gate 32 is located between two adjacent first dummy gates 31; both the first dummy gate 31 and the second dummy gate 32 are in contact with the two side surfaces and the top surface of the fin 20 .
  • the first dummy gate 31 and the second dummy gate 32 span each fin in a group along the thickness t direction of the fin 20 20, and in contact with the two side surfaces of each fin 20 perpendicular to the thickness direction of the fin 20 and the top surface between the two side surfaces.
  • the first dummy gate 31 and the second dummy gate 32 across each set of fins 20 are not connected.
  • the thickness direction of the fin 20 is perpendicular to the gate length direction X. Since the top surface of the fin 20 is substantially parallel to the upper surface of the substrate 10, in the plane of the upper surface of the substrate 10, the thickness direction of the fin 20 is also perpendicular to the gate length direction X.
  • an interlayer insulating layer 60 is formed.
  • the upper surface of the interlayer insulating layer 60 is flush with the upper surfaces of the first dummy gate 31 and the second dummy gate 32.
  • the isolation section 70 has a function of suppressing the transmission of current inside.
  • the part exposed after the second dummy gate 32 of the fin 20 is removed may be processed in the following two ways.
  • Method 1 Using a process of plasma processing (Plasma trimming), plasma implantation (Plasma doping) and ion implantation, inert atoms are doped on the exposed part of the second dummy gate 32 of the fin 20 after removal, so that At least a part of the exposed part of the fin 20 is insulated to form the isolation section 70.
  • the inert atoms here are distinguished from ordinary impurity atoms.
  • the outermost electrons of ordinary impurity atoms are 3 or 5.
  • the ordinary impurity atoms can be ionized in the silicon lattice.
  • the impurity atoms that generate free electrons are called donors, and the impurity atoms that generate free holes are called acceptors.
  • Inert atoms are implanted into the silicon lattice, which has the effect of destroying the silicon lattice and semiconductor energy band structure and suppressing the generation of carriers.
  • the inert atom is at least one of a hydrogen atom (H), an oxygen atom (O), a nitrogen atom (N), a carbon atom (C), and a silicon atom (Si).
  • Manner 2 An etching process is used to process at least a part of the exposed part of the second dummy gate 32 of the fin 20 after the removal, so that the exposed fin 20 is changed in shape and the isolation section 70 is formed.
  • a hydrogen baking (H 2 baking) process may be used to process at least a portion of the exposed portion of the second dummy gate 32 of the fin 20 after the removal, so that the exposed fin 20 has a changed shape.
  • H 2 baking belongs to a vapor phase etching-surface treatment technology.
  • the change in shape includes thinning the thickness of the exposed fin 20 in a direction perpendicular to the gate length direction X or the thickness direction of the substrate 10, or the shape of the exposed fin 20 may be changed.
  • the spacer 40, the source 51, and the drain 52 need to be formed.
  • the manufacturing method of the integrated circuit device further includes:
  • sidewall spacers 40 are formed on both sides of the first dummy gate 31 and the second dummy gate 32.
  • a source 51 and a drain 52 are formed on each side of each first dummy gate 31 along the gate length direction X.
  • the integrated circuit device since the integrated circuit device includes multiple transistors, for each transistor, it includes a gate, a source 51 and a drain 52, and the source 51 and the drain 52 are covered by the gate
  • the channel region 53 is formed in the region, and it can be seen that one transistor can be formed on each side of the second dummy gate 32.
  • the isolation section 70 is formed, the purpose of forming the isolation section 70 is to suppress the leakage current path of the transistors on both sides, so the isolation section 70 is basically insulated, so that the true gate formed at the position of the second dummy gate 32 Does not have normal channel opening characteristics.
  • the terms “upper surface” and “top surface” mentioned in this application refer to the surface of the corresponding structure that is away from the substrate 10.
  • the upper surface of the interlayer insulating layer 60 means the upper surface of the interlayer insulating layer 60 away from the substrate 10.
  • the upper surface of the first dummy gate 31 refers to the upper surface of the interlayer insulating layer 60 away from the substrate 10.
  • the present application provides a method for manufacturing an integrated circuit device. Since the upper surfaces of the first dummy gate 31 and the second dummy gate 32 are exposed after the formation of the interlayer insulating layer 60, the first The second dummy gate 32 is removed, so that the exposed portion of the second dummy gate 32 of the fin 20 can be processed to form an isolation section 70 that suppresses leakage current paths of two adjacent transistors.
  • the isolation section 70 is formed based on this method, it has less influence on the structure and stress of the transistors on both sides of the isolation section 70, the introduced device characteristic parameter has the least variability, the isolation section 70 occupies less area resources, and does not require special design Line resources and other advantages.
  • the formation of grooves and filling of insulating materials to suppress leakage current path will cause large stress changes, resulting in The parameters of adjacent transistors vary greatly.
  • the formation of the isolation section 70 during the preparation of the integrated circuit device provided by the present application can maintain the structural integrity of the exposed part of the fin 20 after the second dummy gate 32 is removed or partially retain the structural integrity, resulting in relatively small stress changes .
  • SWAP N / P workfunction metal SWAP N / P workfunction metal
  • SWAP N / P work function metal
  • the essence of SWAPN / P is to set the threshold voltage of the isolation device to a relatively high level, and the leakage current of the isolation device is suppressed as much as possible. Essentially, it is an electrical shutdown.
  • SWAP N / P makes the integration process of metal gate work function more complicated, and the restricted design rules make the use of SWAP N / P limited.
  • the method for forming the isolation section 70 during the manufacturing process of the integrated circuit device provided by the present application does not make the metal gate work function integration process complicated.
  • the gate fixing is essentially to fix the gate potential of the isolation device to a high voltage (VDD) or a low voltage (VSS), so that the P-type or N-type isolation device is in a forced off state.
  • VDD high voltage
  • VSS low voltage
  • the fixed gate occupies more contact and winding resources in design.
  • the formation of the isolation section 70 in the manufacturing process of the integrated circuit device provided by the present application does not require the help of the gate potential.
  • the embodiments of the present application also provide another method for manufacturing an integrated circuit device, as shown in FIG. 3, including:
  • the substrate 10 and the fin 20 are formed by etching a semiconductor base. That is, trenches are formed in the semiconductor substrate by processes such as photolithography or etching, the protrusions between adjacent trenches form the fins 20, and the semiconductor substrate at the bottom of the fins 20 forms the substrate 10.
  • the materials of the substrate 10 and the fin 20 are the same.
  • the materials of the substrate 10 and the fins 20 may be bulk silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), silicon-on-insulator (SiGe-On-Insulator, SGOI) One of them.
  • the fin 20 is formed on the upper surface of the substrate 10 through an epitaxial process.
  • one way to form the fins 20 is to epitaxial the semiconductor film layer on the upper surface of the substrate 10, etch the semiconductor film layer until the upper surface of the substrate 10 is exposed, and form a groove in the semiconductor film layer.
  • the protrusions between adjacent trenches form fins 20.
  • Another way to form the fin 20 is to form an isolation layer on the upper surface of the substrate 10, etch the isolation layer until the upper surface of the substrate 10 is exposed, and form a trench in the isolation layer; on this basis, The fin 20 is epitaxially formed in the trench, and after the fin 20 is formed, the isolation layer is etched so that the surface of the isolation layer is lower than the top surface of the fin 20.
  • the material of the substrate 10 may be one of bulk silicon, silicon germanium, silicon carbide, SOI, and GOI; the material of the fin 20 may be one of silicon, silicon germanium, germanium, or silicon carbide.
  • the material of the fin 20 is the same as or different from that of the substrate 10.
  • At least two first dummy gates 31 and at least one second dummy gate 32 are formed; at least two first dummy gates 31 and at least one second dummy gate 32 are arranged along the gate length direction X, and each second dummy gate 32 is located between two adjacent first dummy gates 31; the first dummy gate 31 and the second dummy gate 32 are opposite to the fin 20 The two sides and the top are in contact.
  • the first dummy gate 31 is used to occupy space and position for the subsequently formed true gate and gate dielectric layer. Therefore, the first dummy gate 31 needs to be removed later.
  • the main purpose of the second dummy gate 32 is to form the isolation segment 70 in the subsequent process. Therefore, the size of the second dummy gate 32 can be determined according to the dimension of the isolation segment 70.
  • the materials of the first dummy gate 31 and the second dummy gate 32 may be the same, and the material of the first dummy gate 31 and the second dummy gate 32 may be at least one of polysilicon, amorphous silicon, and amorphous carbon. Since polysilicon, amorphous silicon, amorphous carbon and other materials are easily etched, have good shape retention, and are easily removed, at least one of polysilicon, amorphous silicon, and amorphous carbon is used to form the first dummy gate In the case of 31 and the second dummy gate 32, the first dummy gate 31 and the second dummy gate 32 can have good morphology, stable structure and be easily removed.
  • the first dummy gate 31 and the second dummy gate 32 can be simultaneously formed by photolithography and etching processes.
  • sidewall spacers 40 are formed on both sides of the first dummy gate 31 and the second dummy gate 32.
  • the sidewall spacer 40 plays a role in protecting the first dummy gate 31 and the second dummy gate 32, and at the same time, in the subsequent process of forming the source and drain, the first dummy gate 31 and the second dummy gate 32 In the manner of alignment, source and drain are formed on both sides of the first dummy gate 31 respectively.
  • the material of the side wall 40 may be silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or the like.
  • the sidewall spacer 40 can be formed by, for example, an isotropic deposition-anisotropic etching method.
  • a source 51 and a drain 52 are formed on each side of each first dummy gate 31 along the gate length direction X.
  • the source electrode 51 and the drain electrode 52 are formed in the region of the fin 20 that is not covered by the first dummy gate 31 and the sidewalls 40 on both sides thereof, the second dummy gate 32 and the sidewalls on both sides thereof .
  • the source 51 and the drain 52 are formed on both sides of the first dummy gate 31 along the gate length direction X
  • the source 51 and the drain 52 One of the electrodes is located between the first dummy gate 31 and the second dummy gate 32.
  • the source 51 and the drain One of the poles 52 is located between the first dummy gate 31 and the second dummy gate 32.
  • the region of the fin 20 covered by the first dummy gate 31 forms the channel region 53.
  • the projection of the channel region 53 on the substrate 10 overlaps with the projection of the first dummy gate 31 on the substrate 10.
  • the source 51, the drain 52, and the channel region 53 of the FinFET have been formed.
  • the source 51, the drain 52, and the channel region 53 constituting the FinFET have also been formed.
  • silicon germanium (SiGe) containing boron (B) can be epitaxially grown on both sides of the first dummy gate 31 along the gate length direction X through a selective epitaxial process, thereby forming the source 51 and Drain 52.
  • silicon (Si) containing phosphorus (P) is epitaxially grown on both sides of the first dummy gate 31 along the gate length direction X through a selective epitaxial process, thereby forming a source 51 and a drain 52.
  • a plurality of source electrodes 51 and a plurality of drain electrodes 52 are formed on both sides of the first dummy gate 31 along the gate length direction X (the “multiple” here may be the same as the The number is the same), but the application is not limited to this, multiple source electrodes 51 on one side of the first dummy gate 31 along the gate length direction X may also be combined into one source electrode 51, and the first dummy gate 31 A plurality of drains 52 on the other side of the gate length direction X may be combined into one drain 52.
  • an interlayer insulating layer 60 is formed.
  • the upper surface of the interlayer insulating layer 60 is flush with the upper surfaces of the first dummy gate 31 and the second dummy gate 32.
  • an insulating material for example, silicon oxide, silicon nitride, etc.
  • CMP Chemical Mechanical Polishing
  • a first photosensitive layer 81 is formed by a photolithography process.
  • the layer 81 exposes the second dummy gate 32 so that the first photosensitive layer 81 protects the first dummy gate 31.
  • the material of the first photosensitive layer 81 may be, for example, photoresist.
  • the first dummy gate 31 remains to protect the channel region 53.
  • the second dummy gate 32 may be removed by wet etching or dry etching. After the second dummy gate 32 is removed, the area of the fin 20 covered by the second dummy gate 32 is exposed. The portion of the second dummy gate 32 from which the fin 20 is removed is exposed, and the projection on the substrate 10 overlaps with the projection of the second dummy gate 32 on the substrate 10.
  • the exposed portion of the second dummy gate 32 of the fin 20 is removed to form an isolation section 70 to suppress current flow in the second dummy gate 32 of the fin 20.
  • the part exposed after removal is passed.
  • the conductivity of the exposed portion of the second dummy gate 32 of the fin 20 after the removal can be changed to reduce or even completely insulate the conductivity.
  • the isolation section 70 can suppress the leakage current path between the two adjacent transistors.
  • the semiconductor layer in the exposed portion is processed to form an isolation section to suppress current transfer in the exposed portion of the fin 20 after the second dummy gate 32 is removed.
  • Method 1 Using one of plasma processing, plasma implantation, and ion implantation, inert atomic doping is performed on the exposed part of the second dummy gate 32 of the first semiconductor layer 231 after removal to change the first semiconductor layer 231 After the second dummy gate 32 is removed, the conductivity of the exposed portion forms the isolation segment 70.
  • the first semiconductor exposed after the second dummy gate 32 is removed may be implanted into the first semiconductor layer 231 exposed after the second dummy gate 32 is removed and at least one of H, O, N, Si, and C is implanted.
  • the conductivity of the layer 231 changes, thereby forming the isolation section 70.
  • all the first semiconductor layer 231 exposed after the second dummy gate 32 is removed may be processed, or the second dummy gate 32 may be removed
  • the exposed part of the entire first semiconductor layer 231 may be processed as long as the leakage current path can be suppressed.
  • Method 2 Using an etching process, the exposed part of the first semiconductor layer 231 after the second dummy gate 32 is removed is processed to change the appearance of the exposed part of the first semiconductor layer 231 to change the second dummy gate 32 The conductivity of the first semiconductor layer 231 exposed after the removal is formed to form the isolation section 70.
  • the etching process includes at least one of dry etching, wet etching, and atomic layer etching.
  • the shape of the exposed portion of the first semiconductor layer 231 after the second dummy gate 32 is removed may be changed by reducing the thickness t of at least a portion of the exposed first semiconductor layer 231.
  • an etching process is used to process the exposed portion of the first semiconductor layer 231 after the second dummy gate 32 is removed, so that the exposed portion of the first semiconductor layer 231 is perpendicular to the gate length direction X or the thickness of the substrate 10
  • the thickness t in the direction is thinned.
  • the reduction in thickness is based on the current new process that can provide the required isolation effect. For example, it can be reduced by 30% -70% on the basis of the thickness of the semiconductor layer, or relative to the thickness of the channel, for example, by the original 5 to 7nm thinning is 2 to 3nm.
  • the threshold voltage of the first semiconductor layer 231 with the reduced thickness t is increased, so that the leakage current is greatly reduced Reduce, so as to achieve the suppression of leakage current path.
  • an etching process may be used to process the fin 20 exposed after the second dummy gate 32 is removed, so that the shape of the exposed portion of the first semiconductor layer 231 is changed.
  • the shape of the exposed portion of the first semiconductor layer 231 after the second dummy gate 32 is removed is changed, for example, the shape of the exposed first semiconductor layer 231 may be etched into a dumbbell shape, or, along the gate length In the direction X, the exposed first semiconductor layer 231 is broken to block the leakage current path, thereby suppressing the leakage current path.
  • the second dummy gate 32 can be removed by a simple process, and the first semiconductor layer 231 exposed after the second dummy gate 32 is removed can be processed to form a leakage current path for suppressing two adjacent FinFETs Of the isolation section 70.
  • a real gate can be formed through a replacement gate (Replacement Metal) (RMG) process.
  • RMG Replacement Metal
  • the manufacturing method of the integrated circuit device also includes:
  • the gate dielectric layer 91 and the gate 92 are made of a high-k dielectric layer + a metal gate (High-k metal gate (HKMG)).
  • HKMG High-k metal gate
  • the first photosensitive layer 81 since the first photosensitive layer 81 is formed after S24 and before S25, the first photosensitive layer 81 should be removed before the first dummy gate 31 is removed in S27.
  • the gate dielectric layer 91 and the gate 92 are also formed above the isolation section 70, the gate 92 does not have normal channel opening characteristics.
  • Each fin field effect transistor includes a source 51, a drain 52, a channel region 53, a gate dielectric layer 91, and a gate 92.
  • a contact structure can also be formed above the source 51, the drain 52, and the gate 92 of the transistor (ie, the side of the source 51, the drain 52, and the gate 92 of the transistor away from the substrate 10).
  • the interconnection between the transistors can also be achieved through the metal wiring layer and the metal via layer.
  • the embodiment of the present application provides another method for manufacturing an integrated circuit device, as shown in FIG. 12, including:
  • a fin 20 protruding from the substrate 10 is formed on the substrate 10.
  • the fin 20 includes a plurality of first semiconductor layers 231 and a plurality of second layers
  • the semiconductor layer 232, the first semiconductor layer 231 and the second semiconductor layer 232 are alternately stacked along the thickness direction of the substrate 10, and the thickness direction t of the fin 20 is perpendicular to the gate length direction X and the thickness direction of the substrate 10.
  • the “multilayer” in the multilayer first semiconductor layer 231 and the multilayer second semiconductor layer 232 refers to at least two layers, and the specific number of layers may be set reasonably according to needs.
  • the first layer formed is the first semiconductor layer 231 or the second semiconductor layer 232
  • the last layer formed is the first semiconductor layer 231 or the second semiconductor layer 232.
  • the material of the first semiconductor layer 231 and the material of the second semiconductor layer 232 are different.
  • the fin 20 is formed on the upper surface of the substrate 10 through an epitaxial process.
  • one way to form the fin 20 is to epitaxially multi-layer the first semiconductor layer 231 and the multi-layer second semiconductor layer 232 on the upper surface of the substrate 10, with the first semiconductor layer 231 and the second semiconductor layer 232 along The substrate 10 is formed alternately in the thickness direction; after that, the first semiconductor layer 231 and the second semiconductor layer 232 are etched until the upper surface of the substrate 10 is exposed, and trenches are formed in the first semiconductor layer 231 and the second semiconductor layer 232, The protruding portions between adjacent trenches form fins 20.
  • Another way to form the fin 20 is to form an isolation layer on the upper surface of the substrate 10, etch the isolation layer until the upper surface of the substrate 10 is exposed, and form a trench in the isolation layer; on this basis, Multiple first semiconductor layers 231 and multiple second semiconductor layers 232 are epitaxially formed in the trench, and the first semiconductor layers 231 and the second semiconductor layers 232 are alternately formed along the thickness direction of the substrate 10 to form fins in the trench 20. After that, the isolation layer is etched back so that the surface of the isolation layer is lower than the top surface of the fin 20.
  • the material of the substrate 10 may be one of bulk silicon, silicon germanium, silicon carbide, SOI, and GOI; the material of the fin 20 may be one of silicon, silicon germanium, germanium, or silicon carbide.
  • At least two first dummy gates 31 and at least one second dummy gate 32 are formed; at least two first dummy gates 31 and at least one second dummy gate 32 are arranged along the gate length direction X, and each second dummy gate 32 is located between two adjacent first dummy gates 31; the first dummy gate 31 and the second dummy gate 32 are opposite to the fin 20 The two sides and the top are in contact.
  • the first dummy gate 31 is used to occupy space and position for the true gate and gate dielectric layer to be formed later, and therefore, the first dummy gate 31 needs to be removed later.
  • the main purpose of the second dummy gate 32 is to form the isolation segment 70 in the subsequent process. Therefore, the size of the second dummy gate 32 can be determined according to the dimension of the isolation segment 70.
  • the materials of the first dummy gate 31 and the second dummy gate 32 are the same.
  • the material of the first dummy gate 31 and the second dummy gate 32 may be at least one of polysilicon, amorphous silicon, and amorphous carbon.
  • the first dummy gate 31 and the second dummy gate 32 can be simultaneously formed by photolithography and etching processes.
  • sidewall spacers 40 are formed on both sides of the first dummy gate 31 and the second dummy gate 32.
  • the sidewall spacer 40 plays a role in protecting the first dummy gate 31 and the second dummy gate 32, and at the same time, in the subsequent process of forming the source and drain, the first dummy gate 31 and the second dummy gate 32 In the manner of alignment, source and drain are formed on both sides of the first dummy gate 31 respectively.
  • the area covered by the sidewall spacers 40 in the second semiconductor layer 232 of the remaining fin 20 is processed so that the second semiconductor layer 232 of the remaining fin 20
  • the area covered by the side wall 40 is oxidized, so that the oxidized part of the area forms the inner wall 233.
  • the remaining second semiconductor layer 232 is covered by the sidewall spacer 40, that is, the remaining second semiconductor layer 232 is not covered by the first dummy gate 31 and the second dummy gate 32.
  • a source 51 and a drain 52 are formed on each side of each first dummy gate 31 along the gate length direction X.
  • the source electrode 51 and the drain electrode 52 are formed in an area not covered by the first dummy gate 31 and the sidewalls 40 on both sides thereof, the second dummy gate 32 and the sidewalls on both sides thereof.
  • the source 51 and the drain 52 are formed on both sides of the first dummy gate 31 along the gate length direction X
  • the source 51 and the drain 52 One of the electrodes is located between the first dummy gate 31 and the second dummy gate 32.
  • the source 51 and the drain One of the poles 52 is located between the first dummy gate 31 and the second dummy gate 32.
  • the region of the fin 20 covered by the first dummy gate 31 forms the channel region 53.
  • the projection of the channel region 53 on the substrate 10 overlaps with the projection of the first dummy gate 31 on the substrate 10.
  • the source 51, the drain 52, and the channel region 53 constituting the stacked ring-gate nanochip transistor have been formed.
  • a source 51, a drain 52, and a channel region 53 constituting a stacked ring-gate nanochip transistor have also been formed.
  • a Si-containing Ge When forming an N-type stacked ring gate nanochip transistor, a Si-containing Ge may be epitaxially grown on both sides of the first dummy gate 31 along the gate length direction X through a selective epitaxial process, thereby forming the source 51 and the drain 52.
  • P-containing Si When forming a P-type stacked ring gate nanochip transistor, through a selective epitaxial process, P-containing Si is epitaxially grown on both sides of the first dummy gate 31 along the gate length direction X, thereby forming the source 51 and the drain 52.
  • FIG. 15a illustrates that a plurality of source electrodes 51 and a plurality of drain electrodes 52 are formed on both sides of the first dummy gate 31 along the gate length direction X (the “multiple” here may be different from the fin 20 The same number of), but this application is not limited to this, multiple source electrodes 51 on one side of the first dummy gate 31 along the gate length direction X may also be merged into one source electrode 51, and the first dummy gate 31 A plurality of drains 52 on the other side of the gate length direction X may be combined into one drain 52.
  • an interlayer insulating layer 60 is formed.
  • the upper surface of the interlayer insulating layer 60 is flush with the upper surfaces of the first dummy gate 31 and the second dummy gate 32.
  • an insulating material for example, silicon oxide, silicon nitride, etc.
  • an insulating material for example, silicon oxide, silicon nitride, etc.
  • the upper surface of the interlayer insulating layer 60 is flush with the upper surfaces of the first dummy gate 31 and the second dummy gate 32, that is, the first dummy gate 31 and the side walls 40 on both sides, the second dummy gate 32 and the two The upper surface of the side wall 40 is exposed.
  • the sacrificial layer 234 can be removed by a wet etching process using a flowing etching liquid.
  • the exposed part of the second dummy gate 32 of the fin 20 is processed to form an isolation section to prevent the current from being removed at the second dummy gate 32 of the fin 20 After the exposed part passes.
  • the second dummy gate 32 of the fin 20 is removed and exposed The processing is performed on the part exposed in the first semiconductor layer 231 of the fin 20 after the second dummy gate 32 is removed.
  • a second photosensitive layer 82 is formed by a photolithography process, and the second photosensitive layer 82 exposes the area after the second dummy gate 32 is removed. In this way, the first photosensitive layer 81 can protect the area after removing the first dummy gate 31.
  • the isolation section 70 can suppress the leakage current path between the two adjacent transistors.
  • the part exposed in the first semiconductor layer 231 of the fin 20 after the second dummy gate 32 is removed may be processed in the following two ways.
  • Method 1 Using one of the processes of plasma treatment, plasma implantation, and ion implantation, the exposed portion of the first semiconductor layer 231 of the fin 20 after the second dummy gate 32 is removed is doped with inert atoms to make the first The exposed portion of the semiconductor layer 231 is insulated.
  • the first semiconductor layer 231 of the fin 20 may be implanted with H, O, N, Si, C, etc. to expose the second dummy gate 32 in the first semiconductor layer 231 of the fin 20 to make the first The conductivity of the exposed portion of the second dummy gate 32 is changed.
  • the entire portion of the first semiconductor layer 231 that is exposed after the second dummy gate 32 of the fin 20 is removed may also be processed. It is possible to process a part of the first semiconductor layer 231 of the fin 20 that is exposed after the second dummy gate 32 is removed, as long as the leakage current path can be suppressed.
  • Method 2 Use an etching process to process the exposed portion of the first semiconductor layer 231 of the fin 20 after the second dummy gate 32 is removed, so that the second dummy gate 32 of the first semiconductor layer 231 of the fin 20 is removed.
  • the topography of the exposed portion changes to change the conductivity of the exposed portion of the first semiconductor layer 231 of the fin 20 after the second dummy gate 32 is removed.
  • the etching process includes at least one of dry etching, wet etching, and atomic layer etching.
  • the morphology of the exposed part of the second dummy gate 32 in the first semiconductor layer 231 of the fin 20 after being removed may be changed in the direction perpendicular to the gate length direction X or the thickness direction of the substrate 10 In the first semiconductor layer 231 of 20, the thickness of at least a portion of the exposed portion of the second dummy gate 32 after the removal is reduced, or it may be exposed after the second dummy gate 32 of the first semiconductor layer 231 of the fin 20 is removed.
  • the shape of a part changes, or it may be a shape change in other manners, as long as the change in shape can achieve the suppression of the leakage current path, all belong to the protection scope of the present application.
  • the threshold voltage of the first semiconductor layer 231 in the thinned fin 20 will be increased.
  • the leakage current is greatly reduced, thereby realizing the suppression of the leakage current path.
  • the second dummy gate 32 in the first semiconductor layer 231 of the fin 20 may be removed
  • the shape of the exposed portion is etched into a dumbbell shape, or, along the gate length pattern X, the exposed portion of the second dummy gate 32 in the first semiconductor layer 231 of the fin 20 is broken to remove the leakage current path, Thus, the leakage current path can be suppressed.
  • the exposed portion of the first dummy layer 231 of the fin 20 after the second dummy gate 32 is removed can be processed by a simple process to suppress leakage current paths of two adjacent transistors.
  • the real gate can be formed through the RMG process.
  • the manufacturing method of the integrated circuit device also includes:
  • the gate dielectric layer 91 and the gate 92 are formed at the position where the first dummy gate 31 and the second dummy gate 32 are removed; and the gate is formed at the position of the sacrificial layer 234.
  • the material layer 2351 and the gate dielectric material layer 2352 wrapped around the gate material layer 2351 serve as the auxiliary layer 235.
  • the gate material layer 2351 and the gate dielectric material layer 2352 in the auxiliary layer 235 can be formed by, for example, an ALD (Atomic Layer Deposition, atomic layer deposition) process.
  • ALD Atomic Layer Deposition, atomic layer deposition
  • the gate dielectric layer 91 and the gate 92 are made of a high-k dielectric layer + a metal gate (High-k metal gate (HKMG)).
  • HKMG High-k metal gate
  • the second photosensitive layer 82 for protecting the region where the first dummy gate 31 is removed is formed, so before the gate dielectric layer 91 and the gate 92 are formed, The second photosensitive layer 82 should be removed.
  • the gate dielectric layer 91 and the gate 92 are also formed above the isolation section 70, the gate 92 does not have normal channel opening characteristics.
  • Each stacked ring gate nanochip transistor includes a source 51, a drain 52, a channel region 53, a gate dielectric layer 91, and a gate 92.
  • a contact structure can also be formed above the source 51, the drain 52, and the gate 92 of the transistor (ie, the side of the source 51, the drain 52, and the gate 92 of the transistor away from the substrate 10).
  • the interconnection between the transistors can also be achieved through the metal wiring layer and the metal via layer.
  • An embodiment of the present application further provides an integrated circuit device, as shown in FIGS. 11a to 11d or 19a to 19d, including a substrate 10 and fins 20 protruding from the substrate 10, and the integrated circuit device further includes two Two adjacent transistors 100, the two adjacent transistors 100 use two spaced sections of the fin 20 as their respective channels 53; wherein, a part of the fin 20 between the spaced sections is processed
  • the isolation section 70 is used to suppress current transfer between two channels 53 of two adjacent transistors 100.
  • the fin 20 must include a film structure made of a semiconductor material.
  • the fin 20 may be a semiconductor layer, or the fin 20 may include an alternately stacked structure, and some of the layers may be semiconductor layers.
  • FIGS. 11 a to 11 d and FIGS. 19 a to 19 d merely illustrate that the substrate 10 includes three fins 20, three fins 20 as a group, and two transistors 100 share one fin 20 as an example. Multiple sets of fins 20 can be provided as required, each set does not limit the number of fins 20 included in each set, and multiple transistors 100 can share one fin 20 and any adjacent transistors sharing the same fin 20 There are isolation sections 70 between the channels 53 of 100.
  • the isolation section 70 is used to suppress the current transfer between the two channels 53 of the two transistors 100, and the isolation section 70 may include a break region to block the current between the two channels 53 of the two transistors 100 It can also be a special structure of the isolation section 70 so that the current between the two channels 53 of the two transistors 100 cannot be transmitted through the isolation section 70.
  • the integrated circuit device may be a microprocessor, memory, logic element, and other devices made of integrated circuits.
  • the integrated circuit device provided by the embodiment of the present application can process a part of the fin 20 between the two sections of the gap through a simple process, so as to suppress the gap between the two channels 53 of the two transistors 100
  • the current transfer has less influence on the structure and stress of the transistor 100 on both sides of the isolation section 70, the introduced device characteristic parameter has the least variability, the area resource occupied by the isolation section 70 is smaller, and no special winding resources need to be designed.
  • the fin 20 includes a first semiconductor layer 231, and the isolation section 70 is doped with inert atoms.
  • the isolation section 70 is obtained by doping the first semiconductor layer 231 with inert atoms.
  • the doping here is only to dope the portion as the isolation section 70 as needed, and not dope the portion as the channel 53.
  • the inert atom may include, for example, at least one of a hydrogen atom, an oxygen atom, a nitrogen atom, a carbon atom, and a silicon atom.
  • the fin 20 includes a first semiconductor layer 231, and the thickness t of the first semiconductor layer 231 in the isolation section 70 is smaller than the thickness t of the channel 53 of two adjacent transistors 100.
  • the thickness t of the isolation section 70 in the first semiconductor layer 231 in the direction perpendicular to the interval between the source 51 and the drain 52 of the transistor 10 is smaller than the thickness t of the channel 53 of the two transistors 100.
  • the shape of the isolation section 70 may be, for example, rectangular, and the thickness t of each part of the isolation section 70 is smaller than the thickness t of the channel 53 of the two transistors 100.
  • the shape of the isolation section 70 may also be a dumbbell shape.
  • the thickness t of the isolation section 70 in the middle portion is smaller than the thickness t of the channel 53 of the two transistors 100.
  • the shape of the isolation section 70 may further include a broken portion.
  • the thickness t (thickness is 0) of the isolated section 70 at the broken portion is smaller than the thickness t of the channel 53 of the two transistors 100.
  • the shape of the isolation section 70 may also be other shapes, as long as the current transfer between the two channels 53 of the two transistors 100 can be suppressed.
  • the fin 20 includes alternately arranged first semiconductor layers 231 and an auxiliary layer 235.
  • the auxiliary layer 235 includes a gate material layer 2351 and is wrapped around the gate material layer 2351 The gate dielectric material layer 2352, the isolation segment 70 and the channel 53 are formed in the first semiconductor layer 231.
  • a portion of the first semiconductor layer 231 for isolating the segment 70 is doped with inert atoms
  • a portion of the first semiconductor layer 231 for the channel 53 is not doped with inert atoms
  • the first semiconductor layer 231 and the auxiliary layer 235 are alternately arranged
  • the auxiliary layer 235 only plays an auxiliary role, and does not actually play the role of the isolation section 70 or the channel 53. Therefore, when the fin 20 includes multiple first semiconductor layers 231 and multiple auxiliary layers 235, a portion of the multiple first semiconductor layers 231 serves as the isolation section 70 or the channel 53.
  • the number of the first semiconductor layer 231 and the auxiliary layer 235 is not limited, and can be set reasonably according to needs. In addition, whether the layer closest to the most substrate 10 and farthest from the substrate 10 is the first semiconductor layer 231 or the auxiliary layer 235 is not limited here.

Abstract

本申请提供一种集成电路器件及其制备方法，涉及半导体技术领域，通过简单的工艺便可形成对相邻两个晶体管漏电流通路抑制的隔离段。该集成电路器件，包括：衬底以及凸出于所述衬底上的鳍片，所述集成电路器件还包括两个相邻的晶体管，所述两个相邻的晶体管将所述鳍片上间隔的两段部分作为各自的沟道；其中，所述鳍片的位于所述间隔的两段部分之间的一部分被加工得到隔离段，所述隔离段用于抑制所述两个相邻的晶体管的两个沟道间的电流传递。

Description

集成电路器件及其制备方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种集成电路器件及其制备方法。
背景技术
在集成电路设计与制造时，为降低晶体管的漏电流，排放在一起的相邻晶体管之间需形成隔离段。如图1所示，以两个晶体管为例，当该两个晶体管被设计排放在一起的时候，两个晶体管的有源区50不能直接连接在一起，通常需要在两个晶体管间形成隔离段70，以使两个晶体管能分别独立工作，电学特性以及逻辑运算互不影响。因此，如何实现晶体管之间的隔离是非常重要的技术点。
发明内容
本申请提供一种集成电路器件及其制备方法，通过简单的工艺便可形成对相邻两个晶体管漏电流通路抑制的隔离段。
为达到上述目的，本申请采用如下技术方案：
本申请的第一方面，提供一种集成电路器件，包括：衬底以及凸出于衬底上的鳍片，集成电路器件还包括两个相邻的晶体管，两个相邻的晶体管将鳍片上间隔的两段部分作为各自的沟道；其中，鳍片的位于间隔的两段部分之间的一部分被加工得到隔离段，隔离段用于抑制两个相邻的晶体管的两个沟道间的电流传递。通过简单的工艺对鳍片的位于间隔的两段部分之间的一部分进行加工处理，即可抑制两个晶体管的两个沟道间的电流传递，对隔离段两侧晶体管的结构和应力影响较小、引入的器件特性参数变异性最小、隔离段占用的面积资源较小、不需要设计特殊的绕线资源。
可选的，鳍片包括第一半导体层，其中，隔离掺杂有惰性原子。
可选的，鳍片包括第一半导体层，隔离段中的第一半导体层的厚度小于两个相邻的晶体管的沟道的厚度。
可选的，鳍片包括交替设置的第一半导体层和辅助层，辅助层包括栅极材料层和包裹于栅极材料层外的栅介质材料层，隔离段和沟道形成于第一半导体层中。
可选的，惰性原子包括：氢原子、氧原子、氮原子、碳原子、硅原子中的至少一种。
第二方面，提供一种集成电路器件的制备方法，在衬底上形成凸出于衬底的鳍片；形成至少两个第一假栅和至少一个第二假栅；至少两个第一假栅和至少一个第二假栅沿栅长方向排布，且每个第二假栅位于相邻的两个第一假栅之间；第一假栅和第二假栅均与鳍片的相对的两个侧面以及顶面接触；形成层间绝缘层，层间绝缘层的上表面与第一假栅和第二假栅的上表面齐平；至少将第二假栅去除，并对鳍片的第二假栅去除后露出的部分进行处理，形成隔离段，以抑制电流在鳍片的第二假栅去除后露出的部分传递。由于在形成层间绝缘层之后，第一假栅和第二假栅的上表面被暴露出，因而，通过简单的工艺便可将第二假栅去除，从而可对第二假栅去除后露出的半导体薄 片进行处理而形成对相邻两个晶体管漏电流通路抑制的隔离段。基于此方式形成隔离段时，具有对隔离段两侧晶体管的结构和应力影响较小、引入的器件特性参数变异性最小、隔离段占用的面积资源较小、不需要设计特殊的绕线资源等优点。
可选的，鳍片包括第一半导体层；对鳍片的第二假栅去除后露出的部分进行处理，形成隔离段，以抑制电流在鳍片的第二假栅去除后露出的部分传递，包括：采用等离子体处理、等离子体注入、离子注入中的一种工艺，对第一半导体层中第二假栅去除后露出的部分进行惰性原子掺杂，使第一半导体层中露出的部分绝缘化。
可选的，惰性原子包括：氢原子、氧原子、氮原子、碳原子、硅原子中的至少一种。
可选的，鳍片包括第一半导体层；对鳍片的第二假栅去除后露出的部分进行处理，形成隔离段，以抑制电流在鳍片的第二假栅去除后露出的部分传递，包括：采用刻蚀工艺，对第一半导体层中第二假栅去除后露出的部分进行处理，使第一半导体层中露出的部分的形貌发生改变。
可选的，采用刻蚀工艺，对第一半导体层中第二假栅去除后露出的部分进行处理，使第一半导体层中露出的部分的形貌发生改变，包括：采用刻蚀工艺，对第一半导体层中第二假栅去除后露出的至少一部分进行处理，使第一半导体层中露出的部分沿垂直于栅长方向或衬底的厚度方向上的厚度减薄。
可选的，采用刻蚀工艺，对第一半导体层中第二假栅去除后露出的部分进行处理，使第一半导体层中露出的部分的形貌发生改变，包括：采用刻蚀工艺，对第二假栅去除后露出的鳍片进行处理，使第一半导体层中露出的部分的形状改变。
可选的，鳍片由一层第一半导体层构成；至少将第二假栅去除，并对鳍片的第二假栅去除后露出的部分进行处理，形成隔离段，以抑制电流在鳍片的第二假栅去除后露出的部分传递，包括：将第二假栅去除，并对鳍片的第二假栅去除后露出的部分进行处理，形成隔离段，以抑制电流在鳍片的第二假栅去除后露出的部分传递；在形成隔离段后，集成电路器件的制备方法还包括：去除第一假栅，并分别在去除第一假栅和第二假栅的位置，形成栅介质层和栅极。
可选的，鳍片包括多层第一半导体层和多层第二半导体层，第一半导体层与第二半导体层沿衬底的厚度方向交替设置；形成层间绝缘层之前，集成电路器件的制备方法还包括：沿栅长方向，在第一假栅和第二假栅两侧均形成侧墙；去除未被第一假栅以及其两侧的侧墙、第二假栅以及其两侧的侧墙覆盖的鳍片；对保留的鳍片的第二半导体层，被侧墙覆盖的区域进行处理形成内侧墙，未被侧墙覆盖的其余区域作为牺牲层；至少将第二假栅去除，并对鳍片的第二假栅去除后露出的部分进行处理，包括：将第一假栅、第二假栅以及牺牲层去除，并对鳍片的第二假栅去除后露出的部分进行处理，形成隔离段，以抑制电流在鳍片的第二假栅去除后露出的部分传递；在去除第一假栅和第二假栅的位置形成栅介质层和栅极；在牺牲层的位置形成栅极材料层和包裹于栅极材料外的栅介质材料层，作为辅助层。
附图说明
图1为现有技术提供的一种在相邻晶体管之间形成隔离段的示意图；
图2为本申请提供的一种集成电路器件的制备方法的流程示意图；
图3为本申请提供的另一种集成电路器件的制备方法的流程示意图；
图4a为本申请提供的一种在衬底上形成鳍片的示意图；
图4b为本申请提供的另一种在衬底上形成鳍片的示意图；
图5a为在图4a基础上形成第一假栅和第二假栅的示意图；
图5b为图5a中A1A1′向剖视示意图；
图5c为图5a中B1B1′向剖视示意图；
图5d为图5a中C1C1′向剖视示意图；
图6a为在图5a基础上形成侧墙的示意图；
图6b为图6a中A2A2′向剖视示意图；
图7a为在图6a基础上形成源极和漏极的示意图；
图7b为图7a中A3A3′向剖视示意图；
图8a为在图7a基础上形成层间绝缘层的示意图；
图8b为图8a中A4A4′向剖视示意图；
图9a为在图8a基础上去除第二假栅后的示意图；
图9b为图9a中A5A5′向剖视示意图；
图9c为图9a中B5B5′向剖视示意图；
图9d为在去除第二假栅之前，在层间绝缘层上形成露出第二假栅的第一感光层的示意图；
图10a为在图9a基础上形成隔离段的示意图；
图10b为图10a中A6A6′向剖视示意图；
图10c为图10a中B6B6′向剖视示意图；
图11a为在图10a基础上形成栅介质层和栅极的示意图；
图11b为图11a中A7A7′向剖视示意图；
图11c为图11a中B7B7′向剖视示意图；
图11d为图11a中C7C7′向剖视示意图；
图12为本申请提供的另一种集成电路器件的制备方法的流程示意图；
图13a为本申请提供的一种在衬底上形成鳍片以及第一假栅和第二假栅的示意图；
图13b为图13a中D1D1′向剖视示意图；
图13c为图13a中E1E1′向剖视示意图；
图13d为图13a中F1F1′向剖视示意图；
图14a为在图13a基础上形成侧墙以及去除未被第一假栅以及其两侧的侧墙、第二假栅以及其两侧的侧墙覆盖的鳍片后的示意图；
图14b为图14a中D2D2′向剖视示意图；
图14c为在图14b基础上形成内侧墙和牺牲层的示意图；
图15a为在图14a基础上形成源极和漏极的示意图；
图15b为图15a中D3D3′向剖视示意图；
图16a为在图15a基础上形成层间绝缘层的示意图；
图16b为图16a中D4D4′向剖视示意图；
图17a为在图16a基础上将第一假栅、第二假栅以及牺牲层去除后的示意图；
图17b为图17a中D5D5′向剖视示意图；
图17c为图17a中E5E5′向剖视示意图；
图17d为图17a中F5F5′向剖视示意图；
图17e为在对第二假栅去除后露出的鳍片中第一半导体层进行处理之前，形成露出去除第二假栅区域的第二感光层的示意图；
图18a为在图17b基础上形成隔离段后D5D5′向剖视示意图；
图18b为在图17c基础上形成隔离段后E5E5′向剖视示意图；
图18c为在图17d基础上形成隔离段后F5F5′向剖视示意图；
图19a为在图17a基础上形成栅介质层和栅极的示意图；
图19b为图19a中D7D7′向剖视示意图；
图19c为图19a中E7E7′向剖视示意图；
图19d为图19a中F7F7′向剖视示意图。
附图标记：
10-衬底；20-鳍片；31-第一假栅；32-第二假栅；40-侧墙；50-有源区；51-源极；52-漏极；53-沟道区；60-层间绝缘层；70-隔离段；81-第一感光层；82-第二感光层；91-栅介质层；92-栅极；231-第一半导体层；232-第二半导体层；233-内侧墙；234-牺牲层；235-辅助层；2351-栅极材料层；2352-栅介质材料层；100-晶体管。
具体实施方式
本申请的实施例提供一种集成电路器件的制备方法，如图2所示，包括：
S10、如图4a所示，在衬底10上形成凸出于衬底10的鳍片20。
其中，鳍片20可以是一个也可以是多个，在鳍片20为多个的情况下，多个鳍片20可以划分为多组，每组包括至少一个鳍片20，在每组包括多个鳍片20的情况下，多个鳍片20平行设置。鳍片20的厚度t可以为纳米级，鳍片20的厚度方向垂直于栅长方向和衬底10的厚度方向。
对于鳍片20的形状，例如可以具有基本为矩形的形状。在此情况下，鳍片20具有从衬底10的上表面垂直延伸的四个侧面以及位于四个侧面上的顶面，该顶面基本可以与衬底10的上表面平行。
图4a以一组包括三个鳍片20进行示意，但本申请并不限于此，例如如图4b所示，一个组还可以仅包括一个鳍片20。图4a和图4b中仅示意出在衬底10上形成一组鳍片20，但本申请并不限于此，可根据具体的集成电路器件的设计而定。
本申请的实施例提供的集成电路器件的制备方法以衬底10上形成三个鳍片20，三个鳍片20为一组进行示例性说明。
S11、如图5a或者图13a所示，形成至少两个第一假栅31和至少一个第二假栅32；至少两个第一假栅31和至少一个第二假栅32沿栅长方向X排布，且每个第二假栅32位于相邻的两个第一假栅31之间；第一假栅31和第二假栅32均与鳍片20相对的两个侧面以及顶面接触。
示例性的，不管是第一假栅31还是第二假栅32，沿鳍片20的厚度t方向，第一假栅31和第二假栅32均横跨在一组中的每个鳍片20上，并与每个鳍片20的垂直于鳍片20的厚度方向的两个侧面以及两个侧面之间的顶面接触。
其中，当在衬底10上形成多组鳍片20时，横跨在每组鳍片20上的第一假栅31和第二假栅32不连接。
在平行于鳍片20顶面的平面内，鳍片20的厚度方向与栅长方向X垂直。由于鳍片20顶面与衬底10的上表面基本平行，因而，在衬底10的上表面平面内，鳍片20的厚度方向与栅长方向X也垂直。
对于上述的“第一假栅”、“第二假栅”，之所以成为“假栅”，是因为对于最终制备形成的集成电路器件而言，“第一假栅”、“第二假栅”都会被去除，并形成真正的栅极。
S14、如图8a或者图16a所示，形成层间绝缘层60，层间绝缘层60的上表面与第一假栅31和第二假栅32的上表面齐平。
S15、如图9a～9c或者图10a～图10c或者图17a以及图18a～图18c所示，至少将第二假栅32去除，并对鳍片20的第二假栅32去除后暴露出的部分进行处理，形成隔离段70，以抑制电流在鳍片20的第二假栅32去除后露出的部分中传递。
即，隔离段70具有抑制电流在其内部传递的作用。
可选的，对鳍片20的第二假栅32去除后露出的部分进行处理，可采用如下两种方式。
方式一：采用等离子体处理(Plasma trimming)、等离子体注入(Plasma doping)、离子注入中的一种工艺，对鳍片20的第二假栅32去除后露出的部分进行惰性原子掺杂，使鳍片20中露出的部分的中的至少一部分绝缘化，形成隔离段70。
此处的惰性原子区别于普通的杂质原子。普通的杂质原子最外层电子数为3或者5，普通杂质原子在硅晶格中能够发生电离，产生自由电子的杂质原子称为施主，产生自由空穴的杂质原子称为受主。而惰性原子注入到硅晶格中，具有破坏硅的晶格以及半导体能带结构，抑制载流子产生的作用。示例性的，惰性原子为氢原子(H)、氧原子(O)、氮原子(N)、碳原子(C)、硅原子(Si)中的至少一种。
方式二：采用刻蚀工艺，对鳍片20的第二假栅32去除后露出的部分中的至少一部分进行处理，使露出的鳍片20的形貌发生改变，形成隔离段70。
示例的，可采用氢气烘焙(H 2baking)工艺，对鳍片20的第二假栅32去除后露出的部分中的至少一部分进行处理，使露出的鳍片20的形貌发生改变。其中H 2baking属于一种气相刻蚀-表面处理技术。
形貌的变化包括使露出的鳍片20的沿垂直于栅长方向X或衬底10的厚度方向上的厚度减薄，也可以是使露出的鳍片20的形状发生变化。
在一些实施例中，在形成层间绝缘层60之前，需形成侧墙40、源极51和漏极52，集成电路器件的制备方法还包括：
S12、如图6a或者图14a所示，沿栅长方向X，在第一假栅31和第二假栅32两侧均形成侧墙40。
S13、如图7a～图7b或者图15a～图15b所示，在每个第一假栅31沿栅长方向X的两侧分别形成源极51和漏极52。
基于以上步骤，如图10b所示，当在每个第一假栅31沿栅长方向X的两侧分别形成源极51和漏极52时，被第一假栅31所覆盖的鳍片20的区域形成沟道区53。
在此基础上，由于集成电路器件中包括多个晶体管，对于每个晶体管而言，其包括栅极、源极51和漏极52，且源极51和漏极52之间被栅极覆盖的区域形成沟道区53，由此可知，在第二假栅32两侧可分别形成一个晶体管。
上述，虽然在第二假栅32去除后，也会在第二假栅32的位置处形成真正的栅极，但是由于对鳍片20的第二假栅32去除后露出的部分进行处理后形成了隔离段70，而形成该隔离段70的目的在于对其两侧晶体管的漏电流通路进行抑制，因而该隔离段70基本绝缘，从而可知，在第二假栅32位置处形成的真正栅极不具有正常的沟道开启特性。
需要说明的是，本申请中提到的“上表面”、“顶面”等词，均是指相应结构的远离衬底10的一侧表面。例如，层间绝缘层60的上表面是指层间绝缘层60远离衬底10的上表面。第一假栅31的上表面是指层间绝缘层60远离衬底10的上表面。
本申请提供一种集成电路器件的制备方法，由于在形成层间绝缘层60之后，第一假栅31和第二假栅32的上表面被暴露出，因而，通过简单的工艺便可将第二假栅32去除，从而可对鳍片20的第二假栅32去除后露出的部分进行处理而形成对相邻两个晶体管漏电流通路抑制的隔离段70。基于此方式形成隔离段70时，具有对隔离段70两侧晶体管的结构和应力影响较小、引入的器件特性参数变异性最小、隔离段70占用的面积资源较小、不需要设计特殊的绕线资源等优点。
相对于单扩散区隔断(Single Diffusion Break，SDB)和双扩散区隔断(Double Diffusion Break，DDB)技术中通过形成凹槽并填充绝缘材料来对漏电流通路进行抑制，会造成应力变化大，导致临近晶体管的参数变化大。本申请提供的集成电路器件制备过程中隔离段70的形成方式，可保持鳍片20的第二假栅32去除后露出的部分的结构完整性或者部分保留结构完整性，造成的应力变化比较小。
相对于交换N/P功函数金属(SWAP N/P workfunction metal，SWAP N/P)，SWAPN/P的本质是将隔离器件的阈值电压设置到比较高，隔离器件的漏电流被尽量抑制，其本质上是一种电学的关断。但是SWAP N/P使得金属栅功函数的集成流程变的更加复杂，而且受限的设计规则使得SWAP N/P的使用受限。本申请提供的集成电路器件制备过程中隔离段70的形成方式，不会使金属栅功函数集成流程变的复杂。
栅极固定的本质上是将隔离器件的栅极电位固定的高电压(VDD)或者低电压(VSS)上，使P型或者N型隔离器件处于强制关断状态。但是栅极固定在设计上占用更多的接触(contact)和绕线资源。相对于栅极固定(Gate Tie)，本申请提供的集成电路器件制备过程中隔离段70的形成方式，不需要借助栅极的电势。
以集成电路器件包括鳍式场效应晶体管(Fin Field-Effect Transistor，FinFET)为例，本申请的实施例还提供另一种集成电路器件的制备方法，如图3所示，包括：
S20、如图4a所示，在衬底10上形成凸出于衬底10的鳍片20。
在一些实施例中，衬底10和鳍片20由半导体基底刻蚀形成。即，通过光刻或者刻蚀等工艺在半导体基底内形成沟槽，相邻沟槽之间的凸出部分形成鳍片20，而位于鳍片20底部的半导体基底形成衬底10。
在此情况下，衬底10和鳍片20的材料相同。其中，衬底10和鳍片20的材料可以为体硅、硅锗、碳化硅、绝缘体上的硅(Silicon-On-Insulator，SOI)、绝缘体上的锗 硅(SiGe-On-Insulator，SGOI)中的一种。
在另一些实施例中，鳍片20通过外延工艺形成于衬底10的上表面。
基于此，形成鳍片20的一种方式为：在衬底10的上表面外延半导体膜层，刻蚀半导体膜层直至暴露出衬底10的上表面，在半导体膜层内形成沟槽，相邻沟槽之间的凸出部分形成鳍片20。
形成鳍片20的另一种方式为：在衬底10的上表面形成隔离层，刻蚀隔离层直至暴露出衬底10的上表面为止，在隔离层内形成沟槽；在此基础上，在沟槽内外延形成鳍片20，并在形成鳍片20之后，会刻蚀隔离层，使隔离层的表面低于鳍片20的顶部表面。
其中，衬底10的材料可以为体硅、硅锗、碳化硅、SOI、GOI中的一种；鳍片20的材料可以为硅、硅锗、锗或碳化硅中的一种。鳍片20的材料与衬底10的材料相同或不同。
S21、如图5a、图5b、图5c和图5d所示，形成至少两个第一假栅31和至少一个第二假栅32；至少两个第一假栅31和至少一个第二假栅32沿栅长方向X排布，且每个第二假栅32位于相邻的两个第一假栅31之间；第一假栅31和第二假栅32均与鳍片20的相对的两个侧面以及顶面接触。
在本申请的实施例中，第一假栅31用于为后续形成的真正的栅极和栅介质层占据空间和位置，因而，第一假栅31后续需要去除。对于第二假栅32而言，其主要目的是用来在后续工艺中形成隔离段70，因而，第二假栅32的尺寸可根据隔离段70的尺寸而定。
第一假栅31和第二假栅32的材料可以相同，第一假栅31和第二假栅32的材料可采用多晶硅、非晶硅、非晶碳中的至少一种。由于多晶硅、非晶硅、非晶碳等材料易于被刻蚀、保型性良好、且易于被去除，因此，以多晶硅、非晶硅、非晶碳中的至少一种材料形成第一假栅31和第二假栅32时，能够使第一假栅31和第二假栅32的形貌良好、结构稳定、易于被去除。
第一假栅31和第二假栅32可通过光刻、刻蚀工艺同时制备形成。
S22、如图6a和图6b所示，沿栅长方向X，在第一假栅31和第二假栅32两侧均形成侧墙40。
侧墙40起到保护第一假栅31、第二假栅32的作用，同时，使得后续在形成源极和漏极的工艺中，相对于第一假栅31、第二假栅32以自对准的方式，分别在第一假栅31两侧形成源极和漏极。
侧墙40的材料可采用氮化硅(Si 3N 4)、氮氧化硅(SiON)等。侧墙40例如可通过各向同性淀积-各向异性刻蚀方法形成。
S23、如图7a和图7b所示，在每个第一假栅31沿栅长方向X的两侧分别形成源极51和漏极52。
本领域技术人员明白，源极51和漏极52形成在未被第一假栅31及其两侧的侧墙40、第二假栅32及其两侧的侧墙覆盖的鳍片20的区域。
对于第二假栅32其中一侧的第一假栅31，当该第一假栅31沿栅长方向X的两侧分别形成源极51和漏极52时，源极51和漏极52中的其中一极位于该第一假栅31 与第二假栅32之间。同理，对于第二假栅32另一侧的第一假栅31，当该第一假栅31沿栅长方向X的两侧分别形成源极51和漏极52时，源极51和漏极52中的其中一极位于该第一假栅31与第二假栅32之间。
由此可知，如图7b所示，第一假栅31所覆盖的鳍片20的区域形成沟道区53。沟道区53在衬底10上的投影与第一假栅31在衬底10上的投影重叠。
在S23之后，在第二假栅32沿栅长方向X的其中一侧，已经形成了FinFET的源极51、漏极52和沟道区53。同样，在第二假栅32沿栅长方向X的另一侧，也已经形成了构成FinFET的源极51、漏极52和沟道区53。
其中，当形成N型FinFET时，可通过选择性外延工艺，在第一假栅31沿栅长方向X的两侧外延生长含硼(B)的锗硅(SiGe)，从而形成源极51和漏极52。当形成P型FinFET时，通过选择性外延工艺，在第一假栅31沿栅长方向X的两侧外延生长含磷(P)的硅(Si)，从而形成源极51和漏极52。
需要说明的是，图7a以在第一假栅31沿栅长方向X的两侧分别形成多个源极51和多个漏极52(此处的“多个”可以与鳍片20的个数一致)进行示意，但本申请并不限于此，也可将第一假栅31沿栅长方向X其中一侧的多个源极51可合并为一个源极51，将第一假栅31沿栅长方向X另一侧的多个漏极52可合并为一个漏极52。
S24、如图8a和图8b所示，形成层间绝缘层60，层间绝缘层60的上表面与第一假栅31和第二假栅32的上表面齐平。
可选的，通过沉积绝缘材料，绝缘材料例如可以为氧化硅、氮化硅等，并通过化学机械抛光(Chemical Mechanical Polishing，CMP)工艺，使层间绝缘层60的上表面与第一假栅31和第二假栅32的上表面齐平，从而露出第一假栅31和第二假栅32。
S25、如图9a、图9b和图9c所示，将第二假栅32去除。
为避免第二假栅32在去除时，将第一假栅31也去除，因而，在S24之后，在S25之前，如图9d所示，通过光刻工艺形成第一感光层81，第一感光层81露出第二假栅32，以使第一感光层81对第一假栅31形成保护。第一感光层81的材料例如可以是光刻胶。
在去除第二假栅32时，保留第一假栅31，目的在于保护沟道区53。
在此基础上，可采用湿法刻蚀或干法刻蚀工艺来去除第二假栅32，去除第二假栅32后，第二假栅32所覆盖的鳍片20的区域便裸露在外。而去除鳍片20的第二假栅32去除后露出的部分，在衬底10上的投影与第二假栅32在衬底10上的投影重叠。
S26、如图10a、图10b和图10c所示，对鳍片20的第二假栅32去除后露出的部分进行处理，形成隔离段70，以抑制电流在鳍片20的第二假栅32去除后露出的部分传递。
通过对鳍片20的第二假栅32去除后露出的部分进行处理，可改变鳍片20的第二假栅32去除后露出的部分的导电性，使其导电性降低甚至完全绝缘。当隔离段70形成后，隔离段70可实现与其相邻的两个晶体管之间漏电流通路的抑制。
对鳍片20的第二假栅32去除后，对露出的部分中的半导体层进行处理，形成隔离段，以抑制电流在鳍片20的第二假栅32去除后露出的部分传递，可采用如下两种方式。
方式一：采用等离子体处理、等离子体注入、离子注入中的一种工艺，对第一半导体层231的第二假栅32去除后露出的部分进行惰性原子掺杂，以改变第一半导体层231的第二假栅32去除后露出的部分的导电性，形成隔离段70。
示例的，可通过向第二假栅32去除后露出的第一半导体层231注入H、O、N、Si、C中的至少一种等，使第二假栅32去除后露出的第一半导体层231的导电性改变，从而形成隔离段70。
对于第一半导体层231的第二假栅32去除后露出的部分，可以是对第二假栅32去除后露出的全部第一半导体层231进行处理，也可以是对第二假栅32去除后露出的全部第一半导体层231中的部分区域进行处理，只要能达到对漏电流通路抑制的目的即可。
方式二：采用刻蚀工艺，对第一半导体层231中第二假栅32去除后露出的部分进行处理，使第一半导体层231中露出的部分的形貌发生改变，以改变第二假栅32去除后露出的第一半导体层231的导电性，形成隔离段70。
刻蚀工艺包括干法刻蚀、湿法刻蚀、原子层刻蚀中的至少一种。
其中，使第一半导体层231中第二假栅32去除后露出的部分的形貌发生改变，可以是使露出的第一半导体层231的至少一部分的厚度t减薄。例如，采用刻蚀工艺，对第一半导体层231中第二假栅32去除后露出的部分进行处理，使第一半导体层231中露出的部分沿垂直于栅长方向X或衬底10的厚度方向上的厚度t减薄。减薄的幅度以基于当前新工艺能够提供需要的隔离效果为准，比如，可以在半导体层厚度的基础上，或者说相对于沟道的厚度，减薄30％-70％，例如由原来的5～7nm减薄为2～3nm。
当采用使第一半导体层231中第二假栅32去除后露出的部分的厚度t减薄的方式时，厚度t减薄的第一半导体层231的阈值电压会被提高，使得漏电流被大大降低，从而实现对漏电流路径的抑制。
也可以是采用刻蚀工艺，对第二假栅32去除后露出的鳍片20进行处理，使第一半导体层231中露出的部分的形状改变。
当采用使第一半导体层231中第二假栅32去除后露出的部分的形状发生变化的方式时，例如可将露出的第一半导体层231的形状刻蚀呈哑铃形状，或者，沿栅长方向X，使露出的第一半导体层231断裂，以阻断漏电流通路，从而实现对漏电流路径的抑制。
或者还可以是其它方式的形貌变化，只要这种形貌的变化能实现对漏电流路径的抑制都属于本申请的保护范围。
基于上述的S20～S26，通过简单的工艺便可将第二假栅32去除，并对第二假栅32去除后露出的第一半导体层231进行处理而形成抑制相邻两个FinFET漏电流通路的隔离段70。
在S26之后，便可通过替代栅(Replacement Metal Gate，RMG)工艺，形成真正的栅极。
基于此，集成电路器件的制备方法，还包括：
S27、如图11a、图11b、图11c和图11d所示，去除第一假栅31，并分别在去除第一假栅31和第二假栅32的位置，形成栅介质层91和栅极92。
可选的，利用高k介电层+金属栅(High-k metal gate，HKMG)制作栅介质层91和栅极92。
需要说明的是，由于在S24之后，在S25之前，形成了第一感光层81，因此，在S27的去除第一假栅31之前，应将第一感光层81去除。
此外，虽然在隔离段70上方也形成了栅介质层91和栅极92，但是，该栅极92不具有正常的沟道开启特性。
由此，在S27之后，在隔离段70所在区域两侧，分别形成了一个FinFET。每个鳍式场效应晶体管均包括源极51、漏极52、沟道区53、栅介质层91和栅极92。
基于此，后续还可在晶体管的源极51、漏极52、栅极92上方(即，晶体管的源极51、漏极52、栅极92远离衬底10一侧)形成接触结构。此外，还可通过金属连线层和金属通孔层实现晶体管之间的互连。
以集成电路器件包括堆叠环栅纳米片晶体管(Stacked Gate-All-Around Nanosheet Transistor)为例，本申请的实施例提供另一种集成电路器件的制备方法，如图12所示，包括：
S30、如图13a、图13b、图13c和图13d所示，在衬底10上形成凸出于衬底10的鳍片20，鳍片20包括多层第一半导体层231和多层第二半导体层232，第一半导体层231与第二半导体层232沿衬底10的厚度方向交替层叠设置，鳍片20的厚度方向t垂直于栅长方向X和衬底10的厚度方向。
此处，多层第一半导体层231和多层第二半导体层232中的“多层”，均指至少两层，具体的层数根据需要合理设置即可。最先形成的一层是第一半导体层231还是第二半导体层232，以及最后形成的一层是第一半导体层231还是第二半导体层232。本申请实施例中均不做限定。其中，第一半导体层231的材料和第二半导体层232的材料不同。
可选的，鳍片20通过外延工艺形成于衬底10的上表面。
基于此，形成鳍片20的一种方式为：在衬底10的上表面外延多层第一半导体层231和多层第二半导体层232，且第一半导体层231和第二半导体层232沿衬底10厚度方向交替形成；之后，刻蚀第一半导体层231和第二半导体层232直至暴露出衬底10的上表面，在第一半导体层231和第二半导体层232内形成沟槽，相邻沟槽之间的凸出部分形成鳍片20。
形成鳍片20的另一种方式为：在衬底10的上表面形成隔离层，刻蚀隔离层直至暴露出衬底10的上表面为止，在隔离层内形成沟槽；在此基础上，在沟槽内外延多层第一半导体层231和多层第二半导体层232，且第一半导体层231和第二半导体层232沿衬底10厚度方向交替形成，从而在沟槽内形成鳍片20。之后，回刻蚀隔离层，使隔离层的表面低于鳍片20的顶部表面。
其中，衬底10的材料可以为体硅、硅锗、碳化硅、SOI、GOI中的一种；鳍片20的材料可以为硅、硅锗、锗或碳化硅中的一种。
S31、如图13a、图13b、图13c和图13d所示，形成至少两个第一假栅31和至少一个第二假栅32；至少两个第一假栅31和至少一个第二假栅32沿栅长方向X排布，且每个第二假栅32位于相邻的两个第一假栅31之间；第一假栅31和第二假栅32均 与鳍片20的相对的两个侧面以及顶面接触。
第一假栅31用于为后续形成的真正的栅极和栅介质层占据空间和位置，因而，第一假栅31后续需要去除。对于第二假栅32而言，其主要目的是用来在后续工艺中形成隔离段70，因而，第二假栅32的尺寸可根据隔离段70的尺寸而定。
第一假栅31和第二假栅32的材料相同，第一假栅31和第二假栅32的材料可采用多晶硅、非晶硅、非晶碳中的至少一种。
第一假栅31和第二假栅32可通过光刻、刻蚀工艺同时制备形成。
S32、如图14a和图14b所示，沿栅长方向X，在第一假栅31和第二假栅32两侧均形成侧墙40。
侧墙40起到保护第一假栅31、第二假栅32的作用，同时，使得后续在形成源极和漏极的工艺中，相对于第一假栅31、第二假栅32以自对准的方式，分别在第一假栅31两侧形成源极和漏极。
S33、如图14a和图14b所示，去除未被第一假栅31以及其两侧的侧墙40、第二假栅32以及其两侧的侧墙40覆盖的鳍片20；并且，如图14c所示，对保留的鳍片20的第二半导体层232中被侧墙40覆盖的区域进行处理，形成内侧墙233，第二半导体层232中未被侧墙40覆盖的其余区域，作为牺牲层234。
可选的，通过选择性氧化(selectively oxidization)工艺，对保留的鳍片20的第二半导体层232中被侧墙40覆盖的区域进行处理，使保留的鳍片20的第二半导体层232中被侧墙40覆盖的区域氧化，从而使得被氧化的这一部分区域形成内侧墙233。保留的第二半导体层232中被侧墙40覆盖的区域，也即是，保留的第二半导体层232中未被第一假栅31和第二假栅32覆盖的区域。
S34、如图15a和图15b所示，在每个第一假栅31沿栅长方向X的两侧分别形成源极51和漏极52。
本领域技术人员明白，源极51和漏极52形成在未被第一假栅31及其两侧的侧墙40、第二假栅32及其两侧的侧墙覆盖的区域。
对于第二假栅32其中一侧的第一假栅31，当该第一假栅31沿栅长方向X的两侧分别形成源极51和漏极52时，源极51和漏极52中的其中一极位于该第一假栅31与第二假栅32之间。同理，对于第二假栅32另一侧的第一假栅31，当该第一假栅31沿栅长方向X的两侧分别形成源极51和漏极52时，源极51和漏极52中的其中一极位于该第一假栅31与第二假栅32之间。
由此可知，如图15b所示，第一假栅31所覆盖的鳍片20的区域形成沟道区53。沟道区53在衬底10上的投影与第一假栅31在衬底10上的投影重叠。
在S34之后，在第二假栅32沿栅长方向X的其中一侧，已经形成了构成堆叠环栅纳米片晶体管的源极51、漏极52和沟道区53。同样，在第二假栅32沿栅长方向X的另一侧，也已经形成了构成堆叠环栅纳米片晶体管的源极51、漏极52和沟道区53。
当形成N型堆叠环栅纳米片晶体管时，可通过选择性外延工艺，在第一假栅31沿栅长方向X的两侧外延生长含B的SiGe，从而形成源极51和漏极52。当形成P型堆叠环栅纳米片晶体管时，通过选择性外延工艺，在第一假栅31沿栅长方向X的两侧外延生长含P的Si，从而形成源极51和漏极52。
需要说明的是，图15a以在第一假栅31沿栅长方向X的两侧分别形成多个源极51和多个漏极52进行示意(此处的“多个”可以与鳍片20的个数一致)，但本申请并不限于此，也可将第一假栅31沿栅长方向X其中一侧的多个源极51可合并为一个源极51，将第一假栅31沿栅长方向X另一侧的多个漏极52可合并为一个漏极52。
S35、如图16a和图16b所示，形成层间绝缘层60，层间绝缘层60的上表面与第一假栅31和第二假栅32的上表面齐平。
可选的，通过沉积绝缘材料，绝缘材料例如可以为氧化硅、氮化硅等，并通过CMP工艺使层间绝缘层60的上表面与第一假栅31和第二假栅32的上表面齐平，从而露出第一假栅31和第二假栅32。
层间绝缘层60的上表面与第一假栅31和第二假栅32的上表面齐平，即，第一假栅31及其两侧的侧墙40、第二假栅32及其两侧的侧墙40的上表面裸露出。
S36、如图17a、图17b、图17c和图17d所示，将第一假栅31、第二假栅32以及牺牲层234去除。
由于第一半导体层231的材料和第二半导体层232的材料不同，此处，可以通过湿法去除工艺，利用流动的刻蚀液体，对牺牲层234进行去除。
S37、如图18a、图18b和图18c所示，对鳍片20的第二假栅32去除后露出的部分进行处理，形成隔离段，以抑制电流在鳍片20的第二假栅32去除后露出的部分传递。
由于在S36中牺牲层234已被去除，鳍片20的第二假栅32去除后露出的部分中实际只有第一半导体层231存在，因此，对鳍片20的第二假栅32去除后露出的部分进行处理，实际上是对鳍片20的第一半导体层231中第二假栅32去除后露出的部分进行处理。
为避免在对鳍片20中第一半导体层231的第二假栅32去除后露出的部分进行处理时，对第一假栅31去除后露出的沟道区53造成影响，因而，在S36之后，S37之前，如图17e所示，通过光刻工艺形成第二感光层82，第二感光层82露出去除第二假栅32后的区域。这样，第一感光层81可对去除第一假栅31后的区域形成保护。
本领域技术人员明白，通过对鳍片20的第一半导体层231中第二假栅32去除后露出的部分进行处理，可改变第一半导体层231的导电性，使其导电性降低甚至完全绝缘。当隔离段70形成后，隔离段70可实现与其相邻的两个晶体管之间漏电流通路的抑制。
可选的，对鳍片20的第一半导体层231中第二假栅32去除后露出的部分进行处理，可采用如下两种方式。
方式一：采用等离子体处理、等离子体注入、离子注入中的一种工艺，对鳍片20的第一半导体层231中第二假栅32去除后露出的部分进行惰性原子掺杂，使第一半导体层231中露出的部分绝缘化。
示例的，可通过向鳍片20的第一半导体层231中第二假栅32去除后露出的部分注入H、O、N、Si、C等，使鳍片20的第一半导体层231中第二假栅32去除后露出的部分的导电性改变。
对于鳍片20的第一半导体层231中第二假栅32去除后露出的部分，可以是对鳍 片20的第二假栅32去除后露出的第一半导体层231的全部部分进行处理，也可以是对鳍片20的第一半导体层231中第二假栅32去除后露出的部分中的部分区域进行处理，只要能达到对漏电流通路抑制的目的即可。
方式二：采用刻蚀工艺，对鳍片20的第一半导体层231中第二假栅32去除后露出的部分进行处理，使鳍片20的第一半导体层231中第二假栅32去除后露出的部分的形貌发生改变，以改变鳍片20的第一半导体层231中第二假栅32去除后露出的部分的导电性。
刻蚀工艺包括干法刻蚀、湿法刻蚀、原子层刻蚀中的至少一种。
其中，使鳍片20的第一半导体层231中第二假栅32去除后露出的部分的形貌发生改变，可以是沿垂直于栅长方向X或衬底10的厚度方向上，使鳍片20的第一半导体层231中第二假栅32去除后露出的部分中的至少一部分的厚度减薄，也可以是使鳍片20的第一半导体层231中第二假栅32去除后露出的部分的形状发生变化，或者还可以是其它方式的形貌变化，只要这种形貌的变化能实现对漏电流路径的抑制都属于本申请的保护范围。
当采用使鳍片20的第一半导体层231中第二假栅32去除后露出的部分的厚度减薄的方式时，减薄的鳍片20中第一半导体层231的阈值电压会被提高，使得漏电流被大大降低，从而实现对漏电流路径的抑制。
当采用使鳍片20的第一半导体层231中第二假栅32去除后露出的部分的形状发生变化的方式时，例如可将鳍片20的第一半导体层231中第二假栅32去除后露出的部分的形状刻蚀呈哑铃形状，或者，沿栅长方式X，使鳍片20的第一半导体层231中第二假栅32去除后露出的部分断裂，以阻断漏电流通路，从而实现对漏电流路径的抑制。
基于上述的S30～S37，通过简单的工艺便可对鳍片20的第一半导体层231中第二假栅32去除后露出的部分进行处理而抑制相邻两个晶体管漏电流通路。
在S37之后，便可通过RMG工艺，形成真正的栅极。
基于此，集成电路器件的制备方法，还包括：
S38、如图19a、图19b、图19c和图19d所示，去除第一假栅31和第二假栅32的位置形成栅介质层91和栅极92；在牺牲层234的位置形成栅极材料层2351和包裹于栅极材料层2351外的栅介质材料层2352，作为辅助层235。
辅助层235中的栅极材料层2351和栅介质材料层2352，例如可以通过ALD(Atomic Layer Deposition，原子层沉积)工艺来形成。
可选的，利用高k介电层+金属栅(High-k metal gate，HKMG)制作栅介质层91和栅极92。
需要说明的是，由于在对第一半导体层231进行处理之前，形成了用于保护第一假栅31去除区域的第二感光层82，因而，在形成栅介质层91和栅极92之前，应将第二感光层82去除。
此外，虽然在隔离段70上方也形成了栅介质层91和栅极92，但是，该栅极92不具有正常的沟道开启特性。
由此，在S38之后，在隔离段70所在区域两侧，分别形成了一个堆叠环栅纳米片 晶体管。每个堆叠环栅纳米片晶体管均包括源极51、漏极52、沟道区53、栅介质层91和栅极92。
基于此，后续还可在晶体管的源极51、漏极52、栅极92上方(即，晶体管的源极51、漏极52、栅极92远离衬底10一侧)形成接触结构。此外，还可通过金属连线层和金属通孔层实现晶体管之间的互连。
本申请的实施例还提供一种集成电路器件，如图11a～11d或图19a～图19d所示，包括衬底10以及凸出于衬底10上的鳍片20，集成电路器件还包括两个相邻的晶体管100，两个相邻的晶体管100将鳍片20上间隔的两段部分作为各自的沟道53；其中，鳍片20的位于间隔的两段部分之间的一部分被加工得到隔离段70，隔离段70用于抑制两个相邻的晶体管100的两个沟道53间的电流传递。
本领域技术人员应该明白，鳍片20上的部分被用作晶体管100的沟道53，因此，鳍片20必然包括由半导体材料制成的膜层结构。可以是鳍片20为一层半导体层，也可以是鳍片20包括交替设置的层叠结构，其中的某几层为半导体层。
图11a～11d和图19a～图19d仅是以衬底10上包括三个鳍片20，三个鳍片20为一组，两个晶体管100共用一鳍片20为例进行示意。可根据需要设置多组鳍片20，每组对每组中包括的鳍片20的个数不做限定，可以是多个晶体管100共用一个鳍片20，共用同一鳍片20的任意相邻晶体管100的沟道53之间均设置有隔离段70。
此处，隔离段70用于抑制两个晶体管100的两个沟道53间的电流传递，可以是隔离段70中包括断裂区，以阻断两个晶体管100的两个沟道53间的电流传递；也可以是隔离段70的特殊结构使得两个晶体管100的两个沟道53间的电流无法通过隔离段70传递。
该集成电路器件可以是微处理器、存储器、逻辑元件、以及其他由集成电路制成的器件。
本申请的实施例提供的集成电路器件，通过简单的工艺便对鳍片20的位于间隔的两段部分之间的一部分进行加工处理，即可抑制两个晶体管100的两个沟道53间的电流传递，对隔离段70两侧晶体管100的结构和应力影响较小、引入的器件特性参数变异性最小、隔离段70占用的面积资源较小、不需要设计特殊的绕线资源。
在一些实施例中，如图11a～11d所示，鳍片20包括第一半导体层231，隔离段70掺杂有惰性原子。
即，隔离段70为通过对第一半导体层231掺杂惰性原子得到。
当然，此处的掺杂仅是根据需要对作为隔离段70的部分进行掺杂，不会对作为沟道53的部分掺杂。
惰性原子例如可以包括：氢原子、氧原子、氮原子、碳原子、硅原子中的至少一种。
在一些实施例中，鳍片20包括第一半导体层231，隔离段70中的第一半导体层231的厚度t小于相邻两个晶体管100的沟道53的厚度t。
即，沿与晶体管10的源极51和漏极52之间的间距垂直的方向第一半导体层231中隔离段70的厚度t小于两个晶体管100的沟道53的厚度t。
隔离段70的形状例如可以是矩形，隔离段70的每一部分的厚度t均小于两个晶 体管100的沟道53的厚度t。
隔离段70的形状还可以是哑铃型，隔离段70的位于中间部分的厚度t小于两个晶体管100的沟道53的厚度t。
隔离段70的形状还可以是包括断裂部分，隔离段70的位于断裂部分的厚度t(厚度为0)小于两个晶体管100的沟道53的厚度t。
当然，隔离段70的形状还可以是其他形状，能够抑制两个晶体管100的两个沟道53间的电流传递即可。
在一些实施例中，如图19a～图19d所示，鳍片20包括交替设置的第一半导体层231和辅助层235，辅助层235包括栅极材料层2351和包裹于栅极材料层2351外的栅介质材料层2352，隔离段70和沟道53形成于第一半导体层231中。
此处，第一半导体层231用于隔离段70的部分掺杂惰性原子，第一半导体层231中用于沟道53的部分未掺杂惰性原子，第一半导体层231和辅助层235交替设置，辅助层235仅起到辅助作用，并不实际发挥隔离段70或沟道53的作用。因此，鳍片20包括多层第一半导体层231和多层辅助层235时，多层第一半导体层231中的部分段用作隔离段70或沟道53。
不对第一半导体层231和辅助层235的数量进行限定，根据需要合理设置即可。此外，靠近最衬底10和最远离衬底10的一层是第一半导体层231还是辅助层235，此处不做限定。
以上，仅为本申请的具体实施方式，但申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (11)

  1. 一种集成电路器件，其特征在于，包括：衬底以及凸出于所述衬底上的鳍片，所述集成电路器件还包括两个相邻的晶体管，所述两个相邻的晶体管将所述鳍片上间隔的两段部分作为各自的沟道；
    其中，所述鳍片的位于所述间隔的两段部分之间的一部分被加工得到隔离段，所述隔离段用于抑制所述两个相邻的晶体管的两个沟道间的电流传递。
  2. 如权利要求1所述的集成电路器件，其特征在于，所述鳍片包括第一半导体层，其中，所述隔离掺杂有惰性原子，或者，所述隔离段中的第一半导体层的厚度小于所述两个相邻的晶体管的沟道的厚度。
  3. 如权利要求1或2所述的集成电路器件，其特征在于，所述鳍片包括交替设置的第一半导体层和辅助层，所述辅助层包括栅极材料层和包裹于所述栅极材料层外的栅介质材料层，所述隔离段和所述沟道形成于所述第一半导体层中。
  4. 如权利要求2或3所述的集成电路器件，其特征在于，惰性原子包括：氢原子、氧原子、氮原子、碳原子、硅原子中的至少一种。
  5. 一种集成电路器件的制备方法，其特征在于，包括：
    在衬底上形成凸出于所述衬底的鳍片；
    形成至少两个第一假栅和至少一个第二假栅；至少两个所述第一假栅和至少一个所述第二假栅沿栅长方向排布，且每个所述第二假栅位于相邻的两个所述第一假栅之间；所述第一假栅和所述第二假栅均与所述鳍片的相对的两个侧面以及顶面接触；
    形成层间绝缘层，所述层间绝缘层的上表面与所述第一假栅和所述第二假栅的上表面齐平；
    至少将所述第二假栅去除，并对所述鳍片的所述第二假栅去除后露出的部分进行处理以形成隔离段，以抑制电流在所述鳍片的所述第二假栅去除后露出的部分传递。
  6. 如权利要求5所述的集成电路器件的制备方法，其特征在于，所述鳍片包括第一半导体层；
    对所述鳍片的所述第二假栅去除后露出的部分进行处理，以抑制电流在所述鳍片的所述第二假栅去除后露出的部分传递，形成隔离段，包括：
    采用等离子体处理、等离子体注入、离子注入中的一种工艺，对所述第一半导体层中所述第二假栅去除后露出的部分进行惰性原子掺杂，使所述第一半导体层中露出的部分绝缘化。
  7. 如权利要求6所述的集成电路器件的制备方法，其特征在于，所述惰性原子包括：氢原子、氧原子、氮原子、碳原子、硅原子中的至少一种。
  8. 如权利要求5所述的集成电路器件的制备方法，其特征在于，所述鳍片包括第一半导体层；
    对所述鳍片的所述第二假栅去除后露出的部分进行处理，以抑制电流在所述鳍片的所述第二假栅去除后露出的部分传递，形成隔离段，包括：
    采用刻蚀工艺，对所述第一半导体层中所述第二假栅去除后露出的部分进行处理，使所述第一半导体层中露出的部分的形貌发生改变。
  9. 如权利要求8所述的集成电路器件的制备方法，其特征在于，采用刻蚀工艺， 对所述第一半导体层中所述第二假栅去除后露出的部分进行处理，使所述第一半导体层中露出的部分的形貌发生改变，包括：
    采用刻蚀工艺，对所述第一半导体层中所述第二假栅去除后露出的部分进行处理，使所述第一半导体层中露出的至少一部分沿垂直于所述栅长方向或所述衬底的厚度方向上的厚度减薄；
    或者，
    采用刻蚀工艺，对所述第二假栅去除后露出的所述鳍片进行处理，使所述第一半导体层中露出的部分的形状改变。
  10. 如权利要求6-9任一项所述的集成电路器件的制备方法，其特征在于，所述鳍片由一层所述第一半导体层构成；
    至少将所述第二假栅去除，并对所述鳍片的所述第二假栅去除后露出的部分进行处理，以抑制电流在所述鳍片的所述第二假栅去除后露出的部分传递，形成隔离段，包括：
    将所述第二假栅去除，并对所述鳍片的所述第二假栅去除后露出的部分进行处理，以抑制电流在所述鳍片的所述第二假栅去除后露出的部分传递，形成所述隔离段；
    在形成所述隔离段后，所述集成电路器件的制备方法还包括：去除所述第一假栅，并分别在去除所述第一假栅和所述第二假栅的位置，形成栅介质层和栅极。
  11. 如权利要求6-9任一项所述的集成电路器件的制备方法，其特征在于，所述鳍片包括多层所述第一半导体层和多层第二半导体层，所述第一半导体层与所述第二半导体层沿所述衬底的厚度方向交替设置；
    形成所述层间绝缘层之前，所述集成电路器件的制备方法还包括：沿所述栅长方向，在所述第一假栅和所述第二假栅两侧均形成侧墙；
    去除未被所述第一假栅以及其两侧的所述侧墙、所述第二假栅以及其两侧的所述侧墙覆盖的所述鳍片；
    对保留的所述鳍片的所述第二半导体层，被所述侧墙覆盖的区域进行处理形成内侧墙，未被所述侧墙覆盖的其余区域作为牺牲层；
    至少将所述第二假栅去除，并对所述鳍片的所述第二假栅去除后露出的部分进行处理，以抑制电流在所述鳍片的所述第二假栅去除后露出的部分传递，形成隔离段，包括：
    将所述第一假栅、所述第二假栅以及所述牺牲层去除，并对所述鳍片的所述第二假栅去除后露出的部分进行处理，以抑制电流在所述鳍片的所述第二假栅去除后露出的部分传递，形成所述隔离段；
    在形成所述隔离段后，所述集成电路器件的制备方法还包括：在去除所述第一假栅和所述第二假栅的位置形成栅介质层和栅极；在所述牺牲层的位置形成栅极材料层和包裹于所述栅极材料外的栅介质材料层，作为辅助层。
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