WO2020082472A1 - 一种阵列基板及其制造方法 - Google Patents

一种阵列基板及其制造方法 Download PDF

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Publication number
WO2020082472A1
WO2020082472A1 PCT/CN2018/116217 CN2018116217W WO2020082472A1 WO 2020082472 A1 WO2020082472 A1 WO 2020082472A1 CN 2018116217 W CN2018116217 W CN 2018116217W WO 2020082472 A1 WO2020082472 A1 WO 2020082472A1
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Prior art keywords
layer
drain
source
organic filling
via hole
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PCT/CN2018/116217
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English (en)
French (fr)
Inventor
谢炎
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/484,509 priority Critical patent/US10916609B2/en
Publication of WO2020082472A1 publication Critical patent/WO2020082472A1/zh
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
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    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
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Definitions

  • the invention relates to the field of display technology, in particular to an array substrate and a method for manufacturing the same.
  • Organic Light Emitting Display (Organic Light Emitting Display, OLED) has wide color gamut, high contrast, energy saving, and foldability, so it has strong competitiveness in the new generation of displays. Foldability is one of the key development directions of flexible displays.
  • the lifetime of electroluminescent devices is an important index parameter of OLED products.
  • By increasing the pixel definition layer (Pixel Define Layer (PDL) openings can increase the lifespan of OLEDs, slow down the attenuation of OLED brightness, and improve product quality.
  • PDL Pixel Definition Layer
  • the anode is connected to the exposed source and drain (SD) through the via, which makes the electrical connection between the SD and the anode need to open a hole in the flat layer (PLN), and this opening The hole will cause the aperture ratio of the pixel definition layer to become smaller.
  • One aspect of the present invention is to provide an array substrate whose structure can increase the aperture ratio of the pixel definition layer, thereby achieving the effect of prolonging the lifespan of the OLED where it is located.
  • An array substrate includes a pixel area and a bending area connected thereto.
  • the pixel area includes a flexible substrate and a buffer layer, an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, and a second gate formed on the flexible substrate in sequence Metal layer, inter-insulation layer (ILD), first organic fill layer (ODH), source-drain trace layer, flat layer (PLN), anode layer, pixel definition layer (PDL), support layer (PS).
  • ILD inter-insulation layer
  • ODH organic fill layer
  • PNL flat layer
  • PDL pixel definition layer
  • PS support layer
  • the active layer includes a source region and a drain region
  • the source-drain routing layer includes a source and a drain
  • the source is electrically connected to the source region through a first via
  • the A drain covering the first organic filling layer is electrically connected to the drain region through a second via
  • the anode layer is electrically connected to the drain region through the drain.
  • the first organic filling layer is convexly arranged on the inter-insulating layer, so that the source-drain wiring layer covered thereon is convexly arranged.
  • the drain is raised upward by the first organic filling layer, so that the drain portion on the first organic filling layer is correspondingly raised, so that it can be directly connected to the anode layer Without opening a via in the flat layer, so that the anode layer is electrically connected to the drain region through the drain.
  • the aperture ratio of the pixel definition layer can be increased to a certain extent, thereby achieving the effect of prolonging the life of the OLED where it is located .
  • the surface of the convex portion of the drain of the source-drain wiring layer is parallel to the surface of the organic flat layer. That is to say, the protruding arrangement of the first organic filling layer makes the source-drain wiring layer also partially protruding, and at the same time, the protruding portion of the source-drain wiring layer protrudes upward and the organic flat layer It is arranged in parallel instead of being covered by the organic flat layer.
  • the first organic filling layer protrudes upward to form an island-like structure.
  • first organic filling layer is disposed on a side of the second via far away from the first via.
  • the bending region further includes a second organic filling layer on the inter-insulating layer, a source-drain wiring layer on the second organic filling layer, an opening provided in the inter-insulating layer and a hole
  • the bottom reaches the third via of the flexible substrate, wherein the second organic filling layer fills the third via and partially protrudes from the inter-insulating layer.
  • the function of the organic filling layer composed of the first organic filling layer and the second organic filling layer is to reduce the bending stress, and the purpose of the bending is to realize a narrow frame design.
  • the organic filling layer includes a first organic filling layer and a second organic filling layer;
  • S8 Manufacture a source-drain (SD) wiring layer on the organic filling layer, including a source electrode and a drain electrode located in the pixel area and a source-drain wiring layer located on the second organic filling layer in the bending area;
  • SD source-drain
  • An anode layer is formed on the flat layer, the anode layer is electrically connected to the first organic filling layer and is provided corresponding to the active layer;
  • step S3 includes:
  • a layer of amorphous silicon (a-si) is deposited on the buffer layer;
  • the polysilicon layer is patterned and ion doped to form an active layer including a source region and a drain region.
  • step S3 includes:
  • the amorphous silicon layer is converted into a poly-silicon (Poly-Si) layer through an excimer laser annealing process.
  • step S6 includes:
  • a first etching process is used on the second gate insulating layer to make a first via hole, a second via hole in the pixel area, and a third via hole in the bending area, the first etching The process makes the bottom of the first via hole and the second via hole reach the active layer; wherein, the first via hole exposes the source region in the active layer, and the second via hole makes the The drain region in the source layer is exposed;
  • the second etching process is used to continue etching the third via hole, so that the bottom of the third via hole reaches the flexible substrate.
  • step S8 includes:
  • the advantage of the present invention is that the present invention provides an array substrate and a manufacturing method, wherein the array substrate is provided with a raised first organic filling layer on the insulating layer therebetween to raise the drain thereon, thereby making it
  • the anode layer can be directly connected without opening a via in the flat layer, so that the anode layer is electrically connected to the drain region through the drain.
  • the aperture ratio of the pixel definition layer can be increased to a certain extent, thereby achieving the effect of prolonging the life of the OLED where it is located .
  • the drain is no longer exposed through the via hole to connect to the drain region, but the drain is raised through the upwardly projected first organic filling layer, so that the drain portion of the height can be directly connected to the anode layer, thereby achieving the anode
  • the layer is electrically connected to the drain region through the drain without opening a via in the flat layer. Therefore, the effect of the via on the aperture ratio of the pixel definition layer can be eliminated, and the aperture ratio of the pixel definition layer can be increased to achieve The effect of prolonging the life of OLED.
  • FIG. 1 is a schematic structural diagram of an embodiment of an array substrate provided by the present invention.
  • FIG. 2 is a schematic flowchart of an embodiment of a method for manufacturing an array substrate provided by the present invention
  • step S7 is a schematic structural diagram of step S7;
  • step S8 is a schematic structural diagram of step S8;
  • Second gate metal layer 9 insulating layers, 10 organic filling layer,
  • Source-drain trace layer 12 flat layer, 13 anode layer,
  • an embodiment of the present invention provides an array substrate including a pixel area 100 and a bending area 200 connected thereto.
  • the pixel area 100 includes a flexible substrate 1 and a buffer layer 3, an active layer 4, a first gate insulating layer 5, a first gate metal layer 6, a second gate formed on the flexible substrate 1 in sequence
  • the active layer 4 includes a source region 401 and a drain region 402, the source-drain trace layer 11 includes a source 111 and a drain 112, and the source 111 passes through the first via 16 and the The source region 401 is electrically connected, the drain 112 covers the first organic filling layer 101 and is electrically connected to the drain region 402 through the second via hole 17, and the anode layer 13 is connected to the drain through the drain 112 The drain region 402 is electrically connected.
  • the first organic filling layer 101 protrudes upward on the inter-insulating layer 9 so that the source-drain wiring layer 11 covered thereon protrudes.
  • the drain 112 is raised upward through the first organic filling layer 101 so that the height of the drain 112 can be directly connected to the anode layer 13 so that the anode layer 13 passes through the drain 112 and the drain region 402 Electrical connection without opening vias in the flat layer 12.
  • the surface of the protrusion of the drain 112 of the source-drain wiring layer 11 is parallel to the surface of the organic flat layer 12. That is to say, the protruding arrangement of the first organic filling layer 101 makes the source-drain wiring layer 11 also partially protruding, and at the same time, the protruding portion of the source-drain wiring layer 11 extends upwardly with the The organic flat layer 12 is disposed in parallel, rather than being covered by the organic flat layer 12.
  • first organic filling layer 101 protrudes upward to form an island-like structure.
  • first organic filling layer 101 is disposed on the side of the second via 17 away from the first via 16.
  • the bending region further includes a second organic filling layer 102 on the inter-insulating layer 9, a source-drain wiring layer 11 on the second organic filling layer 102, and an opening provided in the The inter-insulating layer 9 and the bottom of the hole reach the third via 18 of the flexible substrate 1, wherein the second organic filling layer 102 fills the third via 18 and partially protrudes from the inter-insulating layer 9.
  • the function of the organic filling layer 10 composed of the first organic filling layer 101 and the second organic filling layer 102 is to reduce the bending stress, and the purpose of the bending is to realize a narrow frame design.
  • an embodiment of the present invention provides a method for manufacturing an array substrate.
  • the array substrate includes a pixel area 100 and a bending area 200 connected thereto.
  • the method includes the following steps:
  • the flexible base 1 includes a flexible polyimide substrate.
  • a buffer layer 3 is formed on the flexible substrate 1.
  • the buffer layer 3 includes a multi-layer structure, which is generally SiOx, SiNx or a mixture thereof.
  • An active layer 4 is formed on the buffer layer 3, and the active layer 4 is doped to form the source region 401 and the drain region 402 on the active layer 4.
  • the active layer 4 is generally doped polysilicon.
  • step S3 may specifically include:
  • An amorphous silicon layer is first deposited on the buffer layer 3, and then the amorphous silicon layer is converted into a polysilicon layer by an excimer laser annealing process, and then the polysilicon layer is patterned and ion doped to form a source
  • the amorphous silicon layer may be patterned first, and then the patterned amorphous silicon may be subjected to an excimer annealing process.
  • a first gate insulating layer 5 is formed on the active layer 4, and a first gate metal layer 6 is formed on the first gate insulating layer 5.
  • the first gate insulating layer 5 generally uses SiOx, SiNx or a mixture thereof.
  • the first gate insulating layer 5 covers the active layer 4 and the buffer layer 3.
  • a first metal layer (not shown) is formed on the first gate insulating layer 5, and the first metal layer is patterned to form the first gate metal layer 6 in the pixel area 100. Specifically, the first gate metal layer 6 is provided corresponding to the active layer 4.
  • a second gate insulating layer 7 is formed on the first gate metal layer 6, and a second gate metal layer 8 is formed on the second gate insulating layer 7.
  • the second gate metal layer 8 is formed in the pixel area 100. Specifically, the second gate metal layer 8 is provided corresponding to the active layer 4.
  • the second metal gate layer 8 has the same metal material as the first gate metal layer 6 and is patterned to form capacitors and some traces in the pixel driving circuit.
  • steps S4-S6 can be specifically referred to FIG. 4.
  • the bottom of the first via 16 is located in the source region 401 of the active layer 4, the bottom of the second via 17 is located in the drain region 402 of the active layer 4, and the bottom of the third via 18 is located in the flexible Base 1;
  • the inter-insulation layer 9 covers the second gate metal layer 8 and the second gate insulation layer 7.
  • the array substrate can be etched by dry etching.
  • the steps include:
  • the first etching The process makes the bottoms of the first via hole 16 and the second via hole 17 reach the active layer 4; wherein, the first via hole 16 exposes the source region 401 in the active layer 4 and the second via hole 17 makes the active The drain region 402 in layer 4 is exposed;
  • the second etching process is used to continue etching the third via hole 18 so that the bottom of the third via hole 18 reaches the flexible substrate 1.
  • An organic filling layer 10 is formed on the interlayer insulating layer 9, the organic filling layer includes a first organic filling layer 101 and a second organic filling layer 102.
  • an organic material is coated on the inter-insulation layer 9, and the organic material is disposed on the side of the second via 17 away from the first via 16 to form an island relative to the drain region 402 of the active layer 4
  • an organic material is filled in the third via hole 18 to form a second organic filled layer 102.
  • the coated organic material is preferably an oxidative dehydrogenated organic substance.
  • the organic material may be a series of flexible organic materials such as polyimide resin or siloxane.
  • a third metal layer (not shown) is formed on the organic filling layer 10, and the third metal layer is patterned to form the source 111 and the drain 112; wherein, The source electrode 111 is connected to the source region 401 through the first via hole 16, and the drain electrode 112 is connected to the drain region 402 through the second via hole 17 and covers the first organic filling layer 101.
  • a flat layer 12 is formed on the source-drain trace layer 11.
  • the formation of 12 flat layers is used to flatten the surface of the array substrate, which is beneficial to subsequent operations.
  • the organic flat layer 12 covers the source-drain wiring layer 11, and at the same time, the convex portion of the drain 112 of the source-drain wiring layer 11 extends upward and is arranged parallel to the organic flat layer 12, instead of being affected by The organic flat layer 12 is covered.
  • the height of the first organic filling layer 101 of the pixel region 100 on the inter-insulating layer 9 is greater than the height of the second organic filling layer 102 filled in the third via hole 18 by the bending region 200. This is advantageous for the anode layer 13 to be electrically connected to the drain region 402 through the drain 112 and to cover the via cover layer 113 through the flat layer 12.
  • the second organic filling layer 102 is filled in the third via hole 18, so that the flexibility of the array substrate can be improved to improve the bending performance of the panel.
  • An anode layer 13 is formed on the flat layer 12.
  • the anode layer 13 is electrically connected to the first organic filling layer 101 and is provided corresponding to the active layer 4.
  • the pixel definition layer 14 is electrically connected to the drain electrode 112 through the anode layer 13 through the via hole in the flat layer.

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Abstract

一种阵列基板，从下至上依次包括柔性基底(1)、缓冲层(3)、有源层(4)、第一栅极绝缘层(5)、第一栅极金属层(6)、第二栅极绝缘层(7)、第二栅极金属层(8)、间绝缘层(9)、第一有机填充层(101)、源漏走线层(11)、平坦层(12)、阳极层(13)、像素定义层(14)、支撑层(15)；所述第一有机填充层(101)向上凸起于所述间绝缘层(9)上进而使得其上覆盖的所述源漏走线层(11)凸起设置。漏极(112)直接连接阳极层(13)，无需在平坦层(12)开设过孔，在一定程度上增大像素定义层(14)的开口率，从而达到延长其所在OLED的寿命的效果。还提供了一种阵列基板的制造方法。

Description

一种阵列基板及其制造方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制造方法。
 背景技术
有机发光二极管显示器件(Organic Light Emitting Display，OLED)色域广、对比度高、节能、可折叠性，因而在新世代显示器中具有强有力的竞争力。可折叠性是柔性显示重点发展方向之一。
其中电致发光器件的寿命是OLED产品的重要指标参数，通过增大像素定义层（Pixel Define Layer，PDL）的开口，可以增加OLED寿命，使OLED亮度衰减减缓，提升产品品质。
在传统OLED显示面板中，其阳极是通过过孔连接至裸露出的源漏极（SD），这就使得SD与阳极之间电连接需要在平坦层（PLN）上开孔，而这一开孔将导致像素定义层开口率变小。
因此，确有必要来开发一种新型的阵列基板，来克服现有技术中的缺陷。
 技术问题
本发明的一个方面在于提供一种阵列基板，其结构能够增大像素定义层的开口率，从而达到延长其所在OLED的寿命的效果。
 技术解决方案
为了实现上述目的，本发明采用以下技术方案：
一种阵列基板，包括像素区以及与其相接的弯折区。其中所述像素区包括柔性基底和在所述柔性基底上依次形成的缓冲层、有源层、第一栅极绝缘层、第一栅极金属层、第二栅极绝缘层、第二栅极金属层、间绝缘层(ILD)、第一有机填充层（ODH）、源漏走线层、平坦层（PLN）、阳极层、像素定义层（PDL）、支撑层（PS）。其中，所述有源层包括源极区域和漏极区域，所述源漏走线层包括源极和漏极，所述源极通过第一过孔与所述源极区域电连接，所述漏极覆盖所述第一有机填充层通过第二过孔与所述漏极区域电连接，所述阳极层通过所述漏极与所述漏极区域电连接。其中所述第一有机填充层向上凸起设置于所述间绝缘层上进而使得其上覆盖的所述源漏走线层凸起设置。
其中所述漏极通过所述第一有机填充层的向上凸起设置，使得所述第一有机填充层上的所述漏极部分相应的被垫高，进而使其可直接连接所述阳极层，而无需在平坦层开设过孔，从而实现阳极层通过漏极与漏极区域的电连接。相应的，因不需开孔也就不存在对所述像素定义层开口率的影响，反而能在一定程度上增大所述像素定义层的开口率，从而达到延长其所在OLED的寿命的效果。
进一步的，其中所述源漏走线层的漏极的凸起部表面平行于所述有机平坦层的表面。也就是说，所述第一有机填充层的凸起设置使得所述源漏走线层也是局部凸起设置，同时所述源漏走线层的凸起部向上伸出与所述有机平坦层平行设置，而非被所述有机平坦层所覆盖。
进一步的，其中所述第一有机填充层向上凸起呈岛状结构。
进一步的，其中所述第一有机填充层设于所述第二过孔旁远离所述第一过孔的一侧。
进一步的，其中所述弯折区还包括的位于所述间绝缘层上的第二有机填充层、位于第二有机填充层上的源漏走线层、开口设于所述间绝缘层且孔底达到所述柔性基底的第三过孔，其中所述第二有机填充层填充所述第三过孔并部分凸出于所述间绝缘层。
第一有机填充层和第二有机填充层构成的有机填充层的作用就是为了实现弯折应力的减小，弯折的目的是实现窄边框设计。
一种阵列基板的制作方法，其中所述阵列基板包括像素区以及与其相接的弯折区，包括步骤：
S1、提供一柔性基底；
S2、在所述柔性基底上制作缓冲层;
S3、在所述缓冲层上制作有源层，并对有源层进行掺杂，以在有源层上形成源极区域和漏极区域；
S4、在有源层上制作第一栅极绝缘层，在第一栅极绝缘层上制作第一栅极金属层；
S5、在第一栅极金属层上制作第二栅极绝缘层，在第二栅极绝缘层上制作第二栅极金属层；
S6、在第二栅极金属层上制作间绝缘层，并在所述间绝缘层上在像素区制作第一过孔、第二过孔以及在弯折区制作第三过孔；
S7、在间绝缘层上形成有机填充层，有机填充层包括第一有机填充层和第二有机填充层；
S8、在有机填充层上制作源漏（SD）走线层，包括位于像素区的源极、漏极和位于弯折区的位于所述第二有机填充层上的源漏走线层；
S9、在源漏走线层上制作平坦层；
S10、在平坦层上制作阳极层，所述阳极层与所述第一有机填充层电连接且与所述有源层相应设置；
S11、在阳极层上制作像素定义层，裸露所述阳极层形成第四过孔；
S12、在像素定义层上制作支撑层。
进一步的，其中所述步骤S3包括：
在缓冲层上沉积一层非晶硅(a-si)层；
通过准分子激光退火(ELA)工艺将所述非晶硅层转化结晶为多晶硅(Poly-Si)层；
将所述多晶硅层进行图案化处理，并进行离子掺杂，形成包括源极区域和漏极区域的有源层。
进一步的，其中另一实施例中所述步骤S3包括：
在缓冲层上沉积一层非晶硅层；
对非晶硅层进行图案化处理；
通过准分子激光退火工艺将所述非晶硅层转化结晶为多晶硅(Poly-Si)层。
进一步的，其中所述步骤S6包括：
在所述第二栅极绝缘层上采用第一次刻蚀工艺在所述像素区制作第一过孔、第二过孔以及在所述弯折区制作第三过孔，第一次刻蚀工艺使第一过孔、第二过孔的孔底达到有源层；其中，所述第一过孔使所述有源层中的源极区域裸露，所述第二过孔使所述有源层中的漏极区域裸露；
采用第二次刻蚀工艺对所述第三过孔继续刻蚀，以使所述第三过孔的孔底达到所述柔性基底。
进一步的，其中所述步骤S8包括：
在所述有机填充层上形成第三金属层，并对所述第三金属层进行图案化处理，以形成源极和漏极；其中，所述源极通过所述第一过孔连接所述源极区域，所述漏极通过所述第二过孔连接所述漏极区域。
 有益效果
本发明的优点在于，本发明提出一种阵列基板及制造方法，其中所述阵列基板在其间绝缘层上设置一个凸起的第一有机填充层用以垫高其上的漏极，进而使其可直接连接所述阳极层，而无需在平坦层开设过孔，从而实现阳极层通过漏极与漏极区域的电连接。相应的，因不需开孔也就不存在对所述像素定义层开口率的影响，反而能在一定程度上增大所述像素定义层的开口率，从而达到延长其所在OLED的寿命的效果。
使漏极不再通过过孔露出来连接至漏极区域，而是将漏极通过向上凸起的第一有机填充层垫高、使得垫高的漏极部分可直接连接阳极层，从而实现阳极层通过漏极与漏极区域的电连接，而无需在平坦层开设过孔，因此，可以消除所述过孔对像素定义层开口率的影响，能够增大像素定义层的开口率，从而达到延长其所在OLED的寿命的效果。
 附图说明
图1是本发明提供的阵列基板的一实施例的结构示意图；
图2是本发明提供的阵列基板的制作方法一实施例的流程示意图；
图3是步骤S1-S3的结构示意图；
图4是步骤S4-S6的结构示意图；
图5是步骤S7的结构示意图；
图6是步骤S8的结构示意图；
图7是步骤S9-S11的结构示意图。
图中部件标识如下：
1柔性基底、      3缓冲层、        4有源层、
5第一栅极绝缘层、6第一栅极金属层、7第二栅极绝缘层、
8第二栅极金属层、9间绝缘层、      10有机填充层、
11源漏走线层、   12平坦层、       13阳极层、
14像素定义层、   15支撑层、       16第一过孔、
17第二过孔、     18第三过孔、     19第四过孔，
100像素区、      200弯折区，
101第一有机填充层、102第二有机填充层、111源极、
112漏极、       401源极区域、     402漏极区域。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
请参阅图1所示，本发明一实施例中提供一种阵列基板，包括像素区100以及与其相接的弯折区200。其中所述像素区100包括柔性基底1和在所述柔性基底1上依次形成的缓冲层3、有源层4、第一栅极绝缘层5、第一栅极金属层6、第二栅极绝缘层7、第二栅极金属层8、间绝缘层9、第一有机填充层101、源漏走线层11、平坦层12、阳极层13、像素定义层14、支撑层15。其中，所述有源层4包括源极区域401和漏极区域402，所述源漏走线层11包括源极111和漏极112，所述源极111通过第一过孔16与所述源极区域401电连接，所述漏极112覆盖所述第一有机填充层101通过第二过孔17与所述漏极区域402电连接，所述阳极层13通过所述漏极112与所述漏极区域402电连接。其中所述第一有机填充层101向上凸起于所述间绝缘层9上进而使得其上覆盖的所述源漏走线层11凸起设置。
其中所述漏极112通过第一有机填充层101向上凸起垫高、使得垫高的漏极112部分可直接连接所述阳极层13，从而实现阳极层13通过漏极112与漏极区域402的电连接，而无需在平坦层12开设过孔。
进一步的，其中所述源漏走线层11的漏极112的凸起部表面平行于所述有机平坦层12的表面。也就是说，所述第一有机填充层101的凸起设置使得所述源漏走线层11也是局部凸起设置，同时所述源漏走线层11的凸起部向上伸出与所述有机平坦层12平行设置，而非被所述有机平坦层12所覆盖。
进一步的，其中所述第一有机填充层101向上凸起呈岛状结构。
进一步的，其中所述第一有机填充层101设于所述第二过孔17旁远离所述第一过孔16的一侧。
进一步的，其中所述弯折区还包括的位于所述间绝缘层9上的第二有机填充层102、位于所述第二有机填充层102上的源漏走线层11、开口设于所述间绝缘层9且孔底达到所述柔性基底1的第三过孔18，其中所述第二有机填充层102填充所述第三过孔18并部分凸出于所述间绝缘层9。
第一有机填充层101和第二有机填102充层构成的有机填充层10的作用就是为了实现弯折应力的减小，弯折的目的是实现窄边框设计。
请参阅图2所示，本发明一实施例中提供一种阵列基板的制作方法，阵列基板包括像素区100以及与其相接的弯折区200，其中，包括步骤：
S1、提供一柔性基底1。
其中，柔性基底1包括柔性聚酰亚胺衬底。
S2、在柔性基底1上制作缓冲层3。
其中，缓冲层3包括多层结构，一般为SiOx、SiNx或其混合物。
S3、在缓冲层3上制作有源层4，并对有源层4进行掺杂，以在有源层4上形成源极区域401和漏极区域402。
有源层4一般为经过掺杂的多晶硅。
上述步骤S1-S3可以具体参阅图3。
具体地，在一实施例中，步骤S3可以具体包括：
在缓冲层3上先沉积一层非晶硅层，再通过准分子激光退火工艺将非晶硅层转化结晶为多晶硅层，再将多晶硅层进行图案化处理，并进行离子掺杂，形成包括源极区域401和漏极区域402的有源层4。另外，也可以先将非晶硅层进行图案化，再对图案化后的非晶硅进行准分子退火工艺制程。
S4、在有源层4上制作第一栅极绝缘层5，在第一栅极绝缘层5上制作第一栅极金属层6。
其中，第一栅极绝缘层5一般也采用SiOx、SiNx或其混合物。第一栅极绝缘层5覆盖有源层4以及缓冲层3。
在第一栅极绝缘层5上制作第一金属层（图未示），并对第一金属层进行图案化处理，以在像素区100形成第一栅极金属层6。具体地，该第一栅极金属层6对应有源层4设置。
S5、在第一栅极金属层6上制作第二栅极绝缘层7，在第二栅极绝缘层7上制作第二栅极金属层8。
在第一栅极金属层6上制作第二栅极绝缘层7，在第二栅极绝缘层7上制作第二金属层（图未示），并对第二金属层进行图案化处理，以在像素区100形成第二栅极金属层8。具体地，该第二栅极金属层8对应有源层4设置。第二金属栅极层8，只是与第一栅极金属层6金属材质相同，图案化形成像素驱动电路中的电容和一些走线。
S6、在第二栅极金属层8上制作间绝缘层9，并在间绝缘层9上在像素区100制作第一过孔16、第二过孔17以及在弯折区200制作第三过孔18。
上述步骤S4-S6可以具体参阅图4。
其中，第一过孔16的孔底位于有源层4的源极区域401，第二过孔17的孔底位于有源层4的漏极区域402，第三过孔18的孔底位于柔性基底1；
其中，间绝缘层9覆盖第二栅极金属层8以及第二栅极绝缘层7。
具体地，这里可以采用干法刻蚀的方法对阵列基板进行刻蚀，步骤包括：
在第二栅极绝缘层7上采用第一次刻蚀工艺在像素区100制作第一过孔16、第二过孔17以及在弯折区200制作第三过孔18，第一次刻蚀工艺使第一过孔16、第二过孔17的孔底达到有源层4；其中，第一过孔16使有源层4中的源极区域401裸露，第二过孔17使有源层4中的漏极区域402裸露；
采用第二次刻蚀工艺对第三过孔18继续刻蚀，以使第三过孔18的孔底达到柔性基底1。
S7、在间绝缘层9上形成有机填充层10，有机填充层包括第一有机填充层101和第二有机填充层102。
如图5所示，在间绝缘层9上涂覆有机材料，且有机材料在第二过孔17旁远离第一过孔16的一侧相对有源层4的漏极区域402相对设置呈岛状结构，有机材料填充于第三过孔18中，形成第二有机填充层102。其中，涂覆的有机材料优选氧化脱氢有机物。在其他实施例中，有机材料可以是聚酰亚胺树脂或硅氧烷等系列的柔性有机材料。
S8、在有机填充层10上制作源漏走线层11，包括位于像素区100的源极111、漏极112和位于弯折区200的位于所述第二有机填充层102上的源漏走线层11。
如图6所示，更具体的，在有机填充层10上形成第三金属层（图未示），并对第三金属层进行图案化处理，以形成源极111和漏极112；其中，源极111通过第一过孔16连接源极区域401，漏极112通过第二过孔17连接漏极区域402并覆盖第一有机填充层101。
S9、在源漏走线层11上制作平坦层12。
制作平坦层12层用于使阵列基板的表面平整，有利于后续的作业。
所述有机平坦层12覆盖所述源漏走线层11，同时所述源漏走线层11的漏极112的凸起部向上伸出与所述有机平坦层12平行设置，而非被所述有机平坦层12所覆盖。
在间绝缘层9上像素区100的第一有机填充层101的高度大于弯折区200填充于第三过孔18中第二有机填充层102的高度。这样有利于阳极层13通过漏极112与漏极区域402电连接，并能通过平坦层12将过孔覆盖层113覆盖。
第二有机填充层102填充于第三过孔18中，这样可以提升阵列基板的柔性度，以提高面板的弯折性能。
S10、在平坦层12上制作阳极层13，阳极层13与第一有机填充层101电连接且与有源层4相应设置。
S11、在阳极层13上制作像素定义层14，裸露阳极层13形成第四过孔19；
其中，像素定义层14通过平坦层上的过孔通过阳极层13电连接到漏极112。
上述步骤S9-S11可以具体参阅图7。
S12、在像素定义层14上制作支撑层15。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种阵列基板，包括像素区以及与其相接的弯折区；
    其中所述像素区包括柔性基底和在所述柔性基底上依次形成的缓冲层、有源层、第一栅极绝缘层、第一栅极金属层、第二栅极绝缘层、第二栅极金属层、间绝缘层、第一有机填充层、源漏走线层、平坦层、阳极层、像素定义层、支撑层；其中，所述有源层包括源极区域和漏极区域，所述源漏走线层包括源极和漏极，所述源极通过第一过孔与所述源极区域电连接，所述漏极通过第二过孔与所述漏极区域电连接，所述阳极层通过所述漏极与所述漏极区域电连接，其中：
    所述漏极覆盖所述第一有机填充层，其中所述第一有机填充层向上凸起于所述间绝缘层上进而使得其上覆盖的所述源漏走线层凸起设置。
  2. 根据权利要求1所述的阵列基板，其中，所述源漏走线层的漏极的凸起部表面平行于所述有机平坦层的表面。
  3. 根据权利要求1所述的阵列基板，其中，所述第一有机填充层向上凸起呈岛状结构
  4. 根据权利要求1所述的阵列基板，其中，所述第一有机填充层设于所述第二过孔旁远离所述第一过孔的一侧。
  5. 根据权利要求1所述的阵列基板，其中，所述弯折区还包括的位于所述间绝缘层上的第二有机填充层、位于所述第二有机填充层上的源漏走线层、开口设于所述间绝缘层且孔底达到所述柔性基底的第三过孔，其中所述第二有机填充层填充所述第三过孔并部分凸出于所述间绝缘层。
  6. 一种阵列基板的制作方法，所述阵列基板包括像素区以及与其相接的弯折区，其中，包括步骤：
    S1、提供一柔性基底；
    S2、在所述柔性基底上制作制作缓冲层；
    S3、在所述缓冲层上制作有源层，并对有源层进行掺杂，以在有源层上形成源极区域和漏极区域；
    S4、在有源层上制作第一栅极绝缘层，在第一栅极绝缘层上制作第一栅极金属层；
    S5、在第一栅极金属层上制作第二栅极绝缘层，在第二栅极绝缘层上制作第二栅极金属层8；
    S6、在第二栅极金属层上制作间绝缘层，并在所述间绝缘层上在像素区制作第一过孔、第二过孔以及在弯折区制作第三过孔；
    S7、在间绝缘层上形成有机填充层，有机填充层包括第一有机填充层和第二有机填充层；
    S8、在有机填充层上制作源漏走线层，包括位于像素区的源极、漏极和位于弯折区的位于所述第二有机填充层上的源漏走线层；
    S9、在源漏走线层上制作平坦层；
    S10、在平坦层上制作阳极层，所述阳极层与所述第一有机填充层电连接且与所述有源层相应设置；
    S11、在阳极层上制作像素定义层，裸露所述阳极层形成第四过孔；
    S12、在像素定义层上制作支撑层。
  7. 根据权利要求6所述的制作方法，其中，所述步骤S3包括：
    在缓冲层上沉积一层非晶硅层；
    通过准分子激光退火工艺将所述非晶硅层转化结晶为多晶硅层；
    将所述多晶硅层进行图案化处理，并进行离子掺杂，形成包括源极区域和漏极区域的有源层。
  8. 根据权利要求6所述的制作方法，其中，所述步骤S3包括：
    在缓冲层上沉积一层非晶硅层；
    对非晶硅层进行图案化处理；
    通过准分子激光退火工艺将所述非晶硅层转化结晶为多晶硅层。
  9. 根据权利要求6所述的制作方法，其中，所述步骤S6包括：
    在所述第二栅极绝缘层上采用第一次刻蚀工艺在所述像素区制作第一过孔、第二过孔以及在所述弯折区制作第三过孔，第一次刻蚀工艺使第一过孔、第二过孔的孔底达到有源层；其中，所述第一过孔使所述有源层中的源极区域裸露，所述第二过孔使所述有源层中的漏极区域裸露；
    采用第二次刻蚀工艺对所述第三过孔继续刻蚀，以使所述第三过孔的孔底达到所述柔性基底。
  10. 根据权利要求6所述的制作方法，其中，所述步骤S8包括：
    在所述有机填充层上形成第二金属层，并对所述第二金属层进行图案化处理，以形成源极和漏极；其中，所述源极通过所述第一过孔连接所述源极区域，所述漏极通过所述第二过孔连接所述漏极区域。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10950677B2 (en) * 2018-12-05 2021-03-16 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Array substrate, manufacturing method thereof, and display panel
CN110112186A (zh) * 2019-04-19 2019-08-09 武汉华星光电半导体显示技术有限公司 一种阵列基板、显示面板以及显示装置
CN110349974A (zh) * 2019-06-25 2019-10-18 武汉华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示装置
CN110429107B (zh) * 2019-07-05 2021-04-27 武汉华星光电半导体显示技术有限公司 一种柔性显示面板及其制备方法
KR102932778B1 (ko) 2019-07-26 2026-03-03 삼성디스플레이 주식회사 표시 장치
CN110544710A (zh) * 2019-08-08 2019-12-06 武汉华星光电半导体显示技术有限公司 柔性阵列基板及显示装置
CN110718572B (zh) * 2019-10-17 2022-10-11 京东方科技集团股份有限公司 一种有机电致发光显示基板及其制备方法和显示装置
CN111610659A (zh) * 2020-05-19 2020-09-01 深圳市华星光电半导体显示技术有限公司 阵列基板及其制备方法
CN111768706A (zh) * 2020-06-24 2020-10-13 武汉华星光电半导体显示技术有限公司 一种显示面板、其制备方法及显示装置
CN118368934A (zh) 2020-06-30 2024-07-19 京东方科技集团股份有限公司 显示基板和显示装置
CN111883483B (zh) * 2020-08-26 2024-05-14 维信诺科技股份有限公司 阵列基板的制备方法
CN112259555A (zh) 2020-10-13 2021-01-22 武汉华星光电半导体显示技术有限公司 一种阵列基板及其制备方法、显示面板
CN112309988B (zh) * 2020-10-22 2022-09-27 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法
CN113192983B (zh) * 2021-04-19 2022-12-06 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法
CN113871403A (zh) * 2021-09-26 2021-12-31 深圳市华星光电半导体显示技术有限公司 薄膜晶体管、显示面板及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080018850A1 (en) * 2006-07-20 2008-01-24 Au Optronics Corp. Array substrate and method for fabricating thereof
CN104867939A (zh) * 2015-04-13 2015-08-26 合肥京东方光电科技有限公司 像素单元及其制备方法、阵列基板和显示装置
CN105319792A (zh) * 2015-11-16 2016-02-10 深圳市华星光电技术有限公司 阵列基板及液晶显示面板
CN107146809A (zh) * 2017-05-16 2017-09-08 京东方科技集团股份有限公司 阵列基板及其制造方法
CN107994055A (zh) * 2017-11-10 2018-05-04 武汉华星光电半导体显示技术有限公司 可弯折显示面板及其制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101338108B1 (ko) * 2006-12-14 2013-12-06 엘지디스플레이 주식회사 액정표시장치의 제조방법
KR100941298B1 (ko) * 2008-04-11 2010-02-11 엘지이노텍 주식회사 표시장치 및 이의 제조방법
CN103995381A (zh) * 2014-04-17 2014-08-20 上海天马微电子有限公司 一种像素结构、液晶面板及其工艺方法
CN105954953A (zh) * 2016-07-13 2016-09-21 深圳市华星光电技术有限公司 液晶显示面板和显示装置
CN107611145A (zh) * 2017-09-21 2018-01-19 京东方科技集团股份有限公司 阵列基板、显示装置及制作方法
US10847596B2 (en) 2017-11-10 2020-11-24 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Bendable display panel and fabricating method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080018850A1 (en) * 2006-07-20 2008-01-24 Au Optronics Corp. Array substrate and method for fabricating thereof
CN104867939A (zh) * 2015-04-13 2015-08-26 合肥京东方光电科技有限公司 像素单元及其制备方法、阵列基板和显示装置
CN105319792A (zh) * 2015-11-16 2016-02-10 深圳市华星光电技术有限公司 阵列基板及液晶显示面板
CN107146809A (zh) * 2017-05-16 2017-09-08 京东方科技集团股份有限公司 阵列基板及其制造方法
CN107994055A (zh) * 2017-11-10 2018-05-04 武汉华星光电半导体显示技术有限公司 可弯折显示面板及其制作方法

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