WO2020082459A1 - 一种显示面板的制作方法和显示面板 - Google Patents

一种显示面板的制作方法和显示面板 Download PDF

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Publication number
WO2020082459A1
WO2020082459A1 PCT/CN2018/115609 CN2018115609W WO2020082459A1 WO 2020082459 A1 WO2020082459 A1 WO 2020082459A1 CN 2018115609 W CN2018115609 W CN 2018115609W WO 2020082459 A1 WO2020082459 A1 WO 2020082459A1
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Prior art keywords
layer
gate
oxide film
metal
gate insulating
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Ceased
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PCT/CN2018/115609
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English (en)
French (fr)
Inventor
杨凤云
卓恩宗
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
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Priority to US16/349,988 priority Critical patent/US20200185431A1/en
Publication of WO2020082459A1 publication Critical patent/WO2020082459A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0215—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned selective metal deposition simultaneously on gate electrodes and the source regions or drain regions
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10D99/00—Subject matter not provided for in other groups of this subclass
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
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    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates

Definitions

  • the present application relates to the field of display technology, and in particular, to a method for manufacturing a display panel and a display panel.
  • the liquid crystal display known by the inventor is mostly a backlight type liquid crystal display, which includes a liquid crystal panel and a backlight module.
  • the working principle of the liquid crystal panel is to place liquid crystal molecules in two parallel glass substrates, and apply a driving voltage on the two glass substrates to control the rotation direction of the liquid crystal molecules, so as to refract the light of the backlight module to generate a picture.
  • IGZO indium gallium zinc oxide
  • BCE back channel etching
  • ESL etch stopper layer, etching barrier layer
  • Self-aligned Top Gate self-aligned top gate
  • the ESL structure can protect the back channel
  • it is not suitable for short channel structure and has a large parasitic capacitance.
  • the top gate type can be used for short channel structure and has a small parasitic capacitance, but the photomask will have one more.
  • the purpose of this application is to provide a manufacturing method of a display panel and a display panel, so as to reduce the photomask manufacturing process of the display panel.
  • the present application provides a method for manufacturing a display panel, including:
  • the first metal layer, the buffer layer and the oxide film layer are formed by etching the same mask
  • a passivation layer and a transparent electrode layer are sequentially formed on the gate layer, the source layer, and the drain layer.
  • This application discloses a method for manufacturing a display panel, including:
  • a gate insulating layer including a middle part, a first side part, a second side part and a hollow part on the oxide film layer through a half-tone mask;
  • the thickness of the middle portion of the gate insulating layer is thicker than the thickness of the first side portion, and the thickness of the middle portion of the gate insulating layer is thicker than the thickness of the second side portion;
  • the hollow part is formed between the middle part and the first side part, and between the middle part and the second side part;
  • Metal is sputtered on the gate insulating layer to form a second layer of metal, and the second layer of metal is etched through the same photomask process to obtain a gate layer, a source layer and a drain layer, and the source layer is formed Connected with the drain layer through the oxide film layer;
  • the gate layer is located on the middle of the insulating layer with the gate
  • the width of the gate layer is smaller than the width of the middle of the gate insulating layer, and the source layer and the drain layer are located on both sides of the gate insulating layer;
  • the source layer, the drain layer and the gate layer are insulated;
  • a passivation layer and a transparent electrode layer are sequentially formed on the gate layer, the source layer, and the drain layer.
  • the application also discloses a display panel, including:
  • the gate insulating layer, the gate layer, the source layer and the drain layer are formed on the oxide film layer;
  • a passivation layer and a transparent electrode layer are sequentially formed on the second metal layer;
  • the first metal layer, the buffer layer and the oxide film layer are formed by the same photomask process.
  • the gate insulating layer is located on the oxide film layer
  • the gate insulating layer includes a middle portion, a first side portion, and a second side portion, and the thickness of the middle portion is greater than the thickness of the first side portion and the second side portion;
  • the gate insulating layer further includes a first hollow portion formed between the middle portion and the first side portion, and a second hollow portion formed between the middle portion and the second side portion;
  • the gate layer is formed on the middle
  • the source layer is formed on the first side portion, and is connected to the oxide film layer through the first hollow portion;
  • the drain layer is formed on the second side portion, and is connected to the oxide film layer through the second hollow portion;
  • the gate layer, the source layer and the drain layer are formed of the same metal layer through the same mask process.
  • the top gate structure is improved, and a layer of metal, buffer material and oxide are deposited on the substrate in sequence, and then the first metal layer, buffer layer and oxide are formed by etching the same mask Film layer; relative to the process of forming the first metal layer, the buffer layer and the oxide film layer separately with different photomasks, at least one photomask is reduced, one exposure and development time is saved, and the purpose of saving costs and increasing productivity is achieved .
  • 1a to 1g are schematic diagrams of a manufacturing process of seven masks for a display panel according to an embodiment of the present application;
  • FIGS. 2a to 2e are schematic diagrams of a five-mask manufacturing process of a display panel according to an embodiment of the present application
  • 3a to 3f are schematic diagrams of a manufacturing process of six masks for a display panel according to an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a method of manufacturing a display panel according to an embodiment of the present application (1);
  • FIG. 5 is a schematic flowchart (2) of a method for manufacturing a display panel according to an embodiment of the present application.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more.
  • the term “including” and any variations thereof are intended to cover non-exclusive inclusions.
  • connection should be understood in a broad sense, for example, it can be fixed or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • installation should be understood in a broad sense, for example, it can be fixed or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • a first metal layer 120 is formed on the glass substrate 110 through a mask process
  • a buffer deposition layer is deposited on the first metal layer 120, and an oxide film deposition layer is deposited on the buffer deposition layer, and the buffer deposition layer and the oxide film deposition layer are etched through the same photomask process to obtain a covering A buffer layer 130 and an oxide film layer 140 around a metal layer 120;
  • a gate insulating deposit layer is deposited on the oxide film layer 140, and a gate metal layer is deposited on the gate insulating deposit layer, and the gate insulating deposit layer and the gate metal layer are formed through a photomask process Etching to form the gate insulating layer 150 and the gate layer 161;
  • an interconnect layer 160 including a middle portion 151, a first side portion 152, a second side portion 153, and a hollow portion is formed on the oxide film layer 140 by a mask, the hollow portion is formed on the middle portion 151 and the first Side 152, and between the middle 151 and the second side 153;
  • a second layer of metal is formed on the interconnect layer 160, and the second layer of metal is etched through the same photomask process to obtain the drain layer 163 and the source layer 162;
  • a passivation layer 170 is obtained by etching through a photomask process
  • a transparent electrode layer 180 is obtained by etching with a photomask.
  • an embodiment of the present application discloses a manufacturing method of a display panel 100, including:
  • S41 deposit a layer of metal, buffer material and oxide on the substrate 110 in sequence, and form the first metal layer 120, the buffer layer 130 and the oxide film layer 140 by etching with the same mask;
  • Passivation layer 170 and transparent electrode layer 180 are sequentially formed on gate layer 161, source layer 162, and drain layer 163.
  • the substrate 110 is a glass substrate 110.
  • the self-aligned top gate structure is improved to deposit a layer of metal, buffer material and oxide on the substrate 110 in sequence, and then the first metal layer 120, the buffer layer 130 and the oxide film are formed by the same mask etching Layer 140; compared to the process of forming the first metal layer 120, the buffer layer 130, and the oxide film layer 140 with different photomasks, one mask is reduced, from seven masks to six masks, saving one Exposure and development time, to achieve cost savings and increase productivity.
  • the step of forming the gate insulating layer 150, the gate layer 161, the source layer 162, and the drain layer 163 on the oxide film layer 140 includes :
  • a gate insulating layer 150 including a middle portion 151, a first side portion 152, a second side portion 153, and a hollow portion on the oxide film layer 140 through a half-tone mask;
  • the thickness of the middle portion 151 of the gate insulating layer 150 is thicker than the thickness of the first side portion 152, and the thickness of the middle portion 151 of the gate insulating layer 150 is higher than the thickness of the second side portion 153;
  • the hollow portion is formed between the middle portion 151 and the first side portion 152, and between the middle portion 151 and the second side portion 153;
  • the formed source layer 162 and drain layer 163 are connected through the oxide film layer 140.
  • metal is sputtered on the gate insulating layer 150 to form a second layer of metal, and the second layer of metal is etched through the same photomask process to obtain the gate layer 161, the source layer 162, and the drain layer 163 ;
  • the present application reduces the photomask process by forming the first metal layer 120, the buffer layer 130 and the oxide film layer 140 through the same photomask, and then passes the same photomask process In the mask process, the second layer of metal is etched to obtain the gate layer 161, the source layer 162, and the drain layer 163, which further reduces the photomask process, further improves production efficiency, and achieves the purpose of better cost saving and productivity improvement. .
  • the step of forming the gate insulating layer 150, the gate layer 161, the source layer 162, and the drain layer 163 on the oxide film layer 140 includes :
  • the gate insulating layer and the gate metal layer are etched through a photomask process to form the gate insulating layer 150 and the gate layer 161;
  • An interconnect layer 160 including a middle portion 151, a first side portion 152, a second side portion 153, and a hollow portion is formed on the oxide film layer 140 through a photomask;
  • the hollow portion is formed between the middle portion 151 and the first side portion 152 and between the middle portion 151 and the second side portion 153.
  • the gate layer 161 is formed first, and then the source layer 162 and the drain layer 163 are formed.
  • the source layer 162 and the drain layer 163 are formed on the same layer, and are not the same layer as the gate layer 161.
  • the source layer 162, the drain layer 163, and the gate layer 161 can be insulated.
  • the interconnect layer 160 includes a middle portion 151, a first side portion 152, a second side portion 153, and a hollow portion. Due to the provision of the hollow portion, a short circuit condition can be avoided, insulation is ensured, and the switching performance of the TFT is ensured.
  • the steps of sequentially forming the first metal layer 120, the buffer layer 130, and the oxide film layer 140 on the substrate 110 by the same photomask etching include:
  • the photoresist layer on the oxide film layer 140 is stripped and removed.
  • the buffer layer 130 will be slightly larger than the oxide film layer 140, and the first metal layer 120 will be slightly larger than the buffer layer 130, which is normal; even, the design itself makes the buffer layer 130 is larger than the oxide film layer 140, and the first metal layer 120 may be larger than the buffer layer 130.
  • the first metal layer 120, the buffer layer 130 and the oxide film layer 140 pass through the same photomask to form a barrier layer on the first metal layer 120, the buffer layer 130 and the oxide film layer 140, and then can pass through different etching liquids
  • the first metal layer 120, the buffer layer 130 and the oxide film layer 140 are respectively etched, so that the barrier layer is clear after the etching is completed, which can further reduce the use of the photomask, achieve cost savings and increase productivity purpose.
  • the second metal layer is formed on the gate insulating layer 150, and the gate layer 161, the source layer 162, and the drain layer 163 are etched through the same photomask process.
  • the gate layer 161 is located on the middle 151 of the gate insulating layer 150;
  • the width of the gate layer 161 is smaller than the width of the middle portion 151 of the gate insulating layer 150, and the source layer 162 and the drain layer 163 are located on both sides of the gate insulating layer 150;
  • the source layer 162, the drain layer 163 and the gate layer 161 are insulated.
  • the gate layer 161 is overlapped with the middle portion 151 of the gate insulating layer 150, the width of the gate layer 161 is smaller than the width of the middle portion 151 of the gate insulating layer 150, and the source layer 162 and the drain layer 163 are respectively located On both sides of the insulating layer 150, the parasitic capacitance generated between the gate layer 161 and the drain layer 163 and the parasitic capacitance generated between the gate layer 161 and the source layer 162 can be reduced.
  • a manufacturing method of the display panel 100 including:
  • S51 deposit a layer of metal, buffer material and oxide on the substrate 110 in sequence;
  • S52 forming a gate insulating layer 150 including a middle portion 151, a first side portion 152, a second side portion 153, and a hollow portion on the oxide film layer 140 through a halftone mask;
  • the thickness of the middle portion 151 of the gate insulating layer 150 is thicker than the thickness of the first side portion 152, and the thickness of the middle portion 151 of the gate insulating layer 150 is thicker than the thickness of the second side portion 153; Between the middle portion 151 and the first side portion 152, and between the middle portion 151 and the second side portion 153;
  • S53 Sputtering metal on the gate insulating layer 150 to form a second layer of metal, and etching the second layer of metal through the same photomask process to obtain the gate layer 161, the source layer 162, and the drain layer 163 to form The source layer 162 and the drain layer 163 are connected through the oxide film layer 140;
  • the gate layer 161 is located on the middle 151 of the gate insulating layer 150;
  • the width of the gate layer 161 is smaller than the width of the middle portion 151 of the gate insulating layer 150, and the source layer 162 and the drain layer 163 are located on both sides of the gate insulating layer 150;
  • the source layer 162, the drain layer 163 and the gate layer 161 are insulated;
  • a passivation layer 170 and a transparent electrode layer 180 are sequentially formed on the gate layer 161, the source layer 162, and the drain layer 163.
  • the solution of the present application can be obtained through five masks, which greatly improves production efficiency, achieves the purpose of saving costs and increasing production capacity.
  • the source layer 162 and the drain layer 163, before the gate layer 161 can avoid the short circuit due to the arrangement of the break structure and the hollow part, ensure insulation, and ensure the switching performance of the TFT.
  • the present application reduces the photomask process by forming the first metal layer 120, the buffer layer 130 and the oxide film layer 140 through the same photomask, and then passes the same photomask process In the mask process, the second layer of metal is etched to obtain the gate layer 161, the source layer 162, and the drain layer 163, which further reduces the photomask process, further improves production efficiency, and achieves the purpose of better cost saving and productivity improvement. .
  • a display panel 100 including:
  • the gate insulating layer 150, the gate layer 161, the source layer 162, and the drain layer 163 are formed on the oxide film layer 140;
  • the passivation layer 170 and the transparent electrode layer 180 are sequentially formed on the second metal layer;
  • the first metal layer 120, the buffer layer 130 and the oxide film layer 140 are formed by the same photomask process.
  • the first metal layer 120, the buffer layer 130, and the oxide film layer 140 are formed by the same photomask process; compared to using the first metal layer 120, the buffer layer 130, and the oxide film layer 140 with different light
  • one mask is reduced, and seven masks are changed to six masks, which saves one exposure and development time, and achieves the purpose of saving costs and increasing productivity.
  • the gate insulating layer 150 is located on the oxide film layer 140;
  • the gate insulating layer 150 includes a middle portion 151, a first side portion 152, and a second side portion 153, and the thickness of the middle portion 151 is greater than the thickness of the first side portion 152 and the second side portion 153;
  • the gate insulating layer 150 further includes a first hollow portion 154 formed between the middle portion 151 and the first side portion 152, and a second hollow portion formed between the middle portion 151 and the second side portion 153 155;
  • the gate layer 161 is formed on the middle portion 151;
  • the source layer 162 is formed on the first side portion 152 and connected to the oxide film layer 140 through the first hollow portion 154;
  • the drain layer 163 is formed on the second side portion 153, and is connected to the oxide film layer 140 through the second hollow portion 155;
  • the gate layer 161, the source layer 162, and the drain layer 163 are formed of the same metal layer through the same mask process.
  • the solution of the present application can be obtained through five masks, which greatly improves production efficiency, achieves the purpose of saving costs and increasing production capacity.
  • the gate insulating layer 150 is located on the middle portion 151 of the oxide film layer 140;
  • the gate layer 161 is located on the gate insulating layer 150;
  • the interconnection layer 160 is located on the oxide film layer 140;
  • the interconnect layer 160 includes a middle portion 151, a first side portion 152 and a second side portion 153, a first hollow portion 154 is formed between the middle portion 151 and the first side portion 152, and the middle portion 151 and the second side portion 153 The second hollow 155 is formed between;
  • the source layer 162 is located on the first side portion 152 and the middle portion 151, and is connected to the oxide film layer 140 through the first hollow portion 154;
  • the drain layer 163 is located on the second side portion 153 and the middle portion 151, and is connected to the oxide film layer 140 through the second hollow portion 155;
  • the source layer 162 and the drain layer 163 are made of the same metal layer through the same mask process.
  • the gate layer 161 is formed first, and then the source layer 162 and the drain layer 163 are formed.
  • the source layer 162 and the drain layer 163 are formed on the same layer, and are not the same layer as the gate layer 161.
  • the source layer 162, the drain layer 163, and the gate layer 161 can be insulated.
  • the interconnect layer 160 includes a middle portion 151, a first side portion 152, a second side portion 153, and a hollow portion. Due to the provision of the hollow portion, a short circuit condition can be avoided, insulation is ensured, and the switching performance of the TFT is guaranteed.
  • the width of the gate layer 161 is smaller than the width of the middle portion 151 of the gate insulating layer 150, the source layer 162, the drain layer 163 are insulated from the gate layer 161, and the source layer 162 and The drain layer 163 is connected through the oxide film layer 140.
  • the width of the gate layer 161 is smaller than the width of the middle portion 151 of the gate insulating layer 150, and the source layer 162 and the drain layer 163 are located on both sides of the gate insulating layer 150, which can reduce the gate layer 161 and the drain The parasitic capacitance generated between the electrode layer 163 and the parasitic capacitance generated between the gate layer 161 and the source layer 162.
  • the panel of this application can be a TN panel (full name Twisted Nematic, ie twisted nematic panel), IPS panel (In-Plane Switching, plane switching), VA panel (Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology), Of course, other types of panels can also be used.
  • TN panel full name Twisted Nematic, ie twisted nematic panel
  • IPS panel In-Plane Switching, plane switching
  • VA panel Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology

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Abstract

一种显示面板（100）的制作方法和显示面板（100），制作方法包括：在基板（110）上依次沉积一层金属、缓冲材料和氧化物；通过同一道光罩蚀刻形成第一金属层（120）、缓冲层（130）和氧化物膜层（140）（S51）。

Description

一种显示面板的制作方法和显示面板
本申请要求于2018年10月22日提交中国专利局、申请号为CN2018112304716、发明名称为“一种显示面板的制作方法和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板的制作方法和显示面板。
背景技术
这里的陈述仅提供与本申请相关的背景信息，而不必然的构成现有技术，
随着科技的发展和进步，液晶显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。发明人已知的一种液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(backlight module)。液晶面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。
目前IGZO(铟镓锌氧化物)技术已得到广泛的研究及应用，常见的IGZO结构有三种，BCE(back channel etch，背沟道刻蚀)结构，ESL(etch stopper layer，刻蚀阻挡层)结构，Self-aligned Top Gate(自对准的顶栅)结构，其中，BCE结构因是背沟道蚀刻，会产生背沟道损坏,影响TFT器件稳定性，ESL结构可以对背沟道进行保护，但不适合做短沟道结构，并且有较大的寄生电容,顶栅型可以做短沟道结构并且有极小的寄生电容，但光罩会多一道。
技术解决方案
本申请的目的在于提供一种显示面板的制作方法和显示面板，以减少显示面板的光罩制程。
为实现上述目的，本申请提供了一种显示面板的制作方法，包括：
在基板上依次沉积一层金属、缓冲材料和氧化物；
通过同一道光罩蚀刻形成第一金属层、缓冲层和氧化物膜层；
在所述氧化物膜层上形成栅极绝缘层、栅极层、源极层和漏极层；
在栅极层、源极层和漏极层上依次形成钝化层和透明电极层。
本申请公开了一种显示面板的制作方法，包括：
在基板上依次沉积一层金属、缓冲材料和氧化物；
通过同一道光罩蚀刻依次形成第一金属层、缓冲层和氧化物膜层；
在所述氧化物膜层上通过半色调掩膜形成包括中部、第一侧部、第二侧部以及镂空部的栅极绝缘层；
所述栅极绝缘层的中部的厚度厚于第一侧部的厚度，所述栅极绝缘层的中部的厚度厚于第二侧部的厚度；
所述镂空部形成在中部和第一侧部，以及中部和第二侧部之间；
在所述栅极绝缘层上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层、源极层和漏极层，形成的所述源极层和漏极层通过所述氧化物膜层连接；
所述栅极层位于与栅极绝缘层中部上；
所述栅极层的宽度小于栅极绝缘层中部的宽度，源极层和漏极层分别位于栅极绝缘层两侧部上；
所述源极层、漏极层与栅极层绝缘；
在栅极层、源极层和漏极层上依次形成钝化层和透明电极层。
本申请还公开了一种显示面板，包括：
第一基板，所述第一基板上依次设置有第一金属层、缓冲层和氧化物膜层；
栅极绝缘层、栅极层、源极层和漏极层，形成在氧化物膜层上；
钝化层和透明电极层，依次形成在所述第二金属层上；
所述第一金属层、缓冲层和氧化物膜层通过同一道光罩制程形成。
可选的，所述栅极绝缘层，位于所述氧化物膜层上；
所述栅极绝缘层包括中部、第一侧部和第二侧部，所述中部的厚度大于所述第一侧部和第二侧部的厚度；
所述栅极绝缘层还包括形成在所述中部和第一侧部之间的第一镂空部，以及形成在所述中部和第二侧部之间的第二镂空部；
所述栅极层形成在所述中部上；
所述源极层形成在所述第一侧部上，并通过所述第一镂空部连接于所述氧化物膜层；
所述漏极层形成在所述第二侧部上，并通过所述第二镂空部连接于所述氧化物膜层；
所述栅极层、源极层和漏极层由同一金属层，通过同一道光罩制程形成。
本方案中，区别于一般性的设计，对顶栅结构进行改进，在基板上依次沉积一层金属、缓冲材料和氧化物,然后通过同一道光罩蚀刻形成第一金属层、缓冲层和氧化物膜层；相对于将第一金属层、缓冲层和氧化物膜层用不同的光罩分开形成的制程来说，至少减少一道光罩,节省一道曝光显影时间，达到节约成本及提升产能的目的。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1a到图1g是本申请一实施例一种显示面板七道光罩制程的示意图；
图2a到图2e是本申请一实施例一种显示面板五道光罩制程的示意图；
图3a到图3f是本申请一实施例一种显示面板六道光罩制程的示意图；
图4是本申请一实施例一种显示面板的制作方法流程示意图(1)；
图5是本申请一实施例一种显示面板的制作方法流程示意图(2)。
本申请的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
参考图1a，在玻璃基板110上通过一道光罩的制程形成第一金属层120；
参考图1b，在第一金属层120上沉积形成缓冲沉积层，并在缓冲沉积层上沉积形成氧化物膜沉积层，通过同一道光罩制程蚀刻缓冲沉积层和氧化物膜沉积层，得到覆盖第一金属层120四周的缓冲层130和氧化物膜层140；
参考图1c，在氧化物膜层140上沉积形成栅极绝缘沉积层，并在栅极绝缘沉积层上沉积形成栅极金属层，通过一道光罩制程对栅极绝缘沉积层和栅极金属层进行蚀刻，形成栅极绝缘层150和栅极层161；
参考图1d，在氧化物膜层140上通过一道光罩形成包括中部151、第一侧部152、第二侧部153以及镂空部的互联层160，所述镂空部形成在中部151和第一侧部152，以及中部151和第二侧部153之间；
参考图1e，在互联层160上形成第二层金属，并对第二层金属通过同一道光罩制程进行蚀刻得到漏极层163和源极层162；
参考图1f，在漏极层163和源极层162上，通过一道光罩制程蚀刻得到钝化层170；
参考图1g，在钝化层170上，通过一道光罩蚀刻得到透明电极层180。
总共使用了七道光罩。
下面结合附图和可选的实施例对本申请作进一步说明。
参考图2a至4所示，本申请实施例公开了一种显示面板100的制作方法，包括：
S41：在基板110上依次沉积一层金属、缓冲材料和氧化物，通过同一道光罩蚀刻形成第一金属层120、缓冲层130和氧化物膜层140；
S42：在所述氧化物膜层140上形成栅极绝缘层150、栅极层161、源极层162和漏极层163；
S43：在栅极层161、源极层162和漏极层163上依次形成钝化层170和透明电极层180。
其中，基板110为玻璃基板110。
本方案中，对自对准的顶栅结构进行改善在基板110上依次沉积一层金属、缓冲材料和氧化物,然后通过同一道光罩蚀刻形成第一金属层120、缓冲层130和氧化物膜层140；相对于将第一金属层120、缓冲层130和氧化物膜层140用不同的光罩分开形成的制程来说，减少一道光罩,由七道光罩变为六道光罩,节省一道曝光显影时间，达到节约成本及提升产能的目的。
其中，一般性的示例方案中，采用了七道光罩制程，而本申请由于通过同一道光罩蚀刻形成第一金属层120、缓冲层130和氧化物膜层140，因而，相对减少了一道光罩制程。
在一实施例中，参考图2b至图2c所示，所述在所述氧化物膜层140上形成栅极绝 缘层150、栅极层161、源极层162和漏极层163的步骤包括：
在所述氧化物膜层140上通过半色调掩膜形成包括中部151、第一侧部152、第二侧部153以及镂空部的栅极绝缘层150；
所述栅极绝缘层150的中部151的厚度厚于第一侧部152的厚度，所述栅极绝缘层150的中部151的厚度高于第二侧部153的厚度；
所述镂空部形成在中部151和第一侧部152，以及中部151和第二侧部153之间；
在所述栅极绝缘层150上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163；
形成的所述源极层162和漏极层163通过所述氧化物膜层140连接。
本方案中，在所述栅极绝缘层150上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163；再次减少光罩的使用，进一步减少制程，使得极大提高生产效率,达到节约成本及提升产能的目的。
其中，相对于一般性示例的七道光罩制程，本申请在通过同一道光罩蚀刻形成第一金属层120、缓冲层130和氧化物膜层140减少一道光罩制程的基础上，又通过同一道光罩制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163，进一步减少了光罩制程，进一步提高了生产效率，达到了更好的节约成本及提升产能的目的。
在一实施例中，参考图3b至图3d所示，所述在所述氧化物膜层140上形成栅极绝缘层150、栅极层161、源极层162和漏极层163的步骤包括：
在氧化物膜层140上沉积形成栅极绝缘沉积层，并在栅极绝缘沉积层上沉积形成栅极金属层；
通过一道光罩制程对栅极绝缘沉积层和栅极金属层进行蚀刻，形成栅极绝缘层150和栅极层161；
在氧化物膜层140上通过一道光罩形成包括中部151、第一侧部152、第二侧部153以及镂空部的互联层160；
在互联层160的上形成第二层金属，并对第二层金属进行蚀刻得到漏极层163和源极层162；
所述镂空部形成在中部151和第一侧部152，以及中部151和第二侧部153之间。
本方案中，先形成栅极层161，再形成源极层162和漏极层163，源极层162和漏极层163是在同一层上形成的，与栅极层161不是再同一层，可以使得源极层162、漏极层163与栅极层161绝缘。在互联层160包括中部151、第一侧部152、第二侧部153以及镂空部，由于镂空部的设置，可以避免短路的情况，保证绝缘，保证了TFT的开关性能。
在一实施例中，参考图2a所示，所述在基板110上通过同一道光罩蚀刻依次形成第一金属层120、缓冲层130和氧化物膜层140的步骤包括：
在氧化物膜沉积层上通过一道光罩形成预设图案的光阻层；
对所述氧化物膜沉积层的两侧部不重叠于光阻层的部分进行蚀刻得到氧化物膜层140；
对所述缓冲层130的两侧部且不重叠于氧化物膜层140的部分进行蚀刻得到缓冲层130；
对所述第一金属层120的两侧部且不重叠于缓冲层130的部分进行蚀刻，得到第一金属层120；
剥离清除氧化物膜层140上的光阻层。
实际上，由于蚀刻的原因，该缓冲层130会略大于氧化物膜层140，该第一金属层120会略大于该缓冲层130，这都是正常情况；甚至，本身就设计使得该缓冲层130大于氧化物膜层140，该第一金属层120大于该缓冲层130也是可以的。
第一金属层120、缓冲层130和氧化物膜层140通过同一光罩，在第一金属层120、缓冲层130和氧化物膜层140上形成一阻挡层，然后便可以通过不同的蚀刻液分别蚀刻得到该第一金属层120、缓冲层130和氧化物膜层140，如此，完成蚀刻之后再清楚该阻挡层，这样做可以进一步的减少了光罩的使用，达到节约成本及提升产能的目的。
在一实施例中，参考图2c所示，所述在栅极绝缘层150上形成第二层金属，并通过同一道光罩制程蚀刻得到栅极层161、源极层162和漏极层163的步骤中；
所述栅极层161位于与栅极绝缘层150中部151上；
所述栅极层161的宽度小于栅极绝缘层150中部151的宽度，源极层162和漏极层163分别位于栅极绝缘层150两侧部上；
所述源极层162、漏极层163与栅极层161绝缘。
本方案中，栅极层161位于与栅极绝缘层150中部151重叠上，栅极层161的宽度小于栅极绝缘层150中部151的宽度，源极层162和漏极层163分别位于栅极绝缘层150两侧部上，可以减少栅极层161和漏极层163之间产生的寄生电容，以及栅极层161和源极层162之间产生的寄生电容。
作为本申请的另一实施例，参考图2a至图2e以及参考图4所示，公开了一种显示面板100的制作方法，包括：
S51：在基板110上依次沉积一层金属、缓冲材料和氧化物；
通过同一道光罩蚀刻依次形成第一金属层120、缓冲层130和氧化物膜层140；
S52：在所述氧化物膜层140上通过半色调掩膜形成包括中部151、第一侧部152、第二侧部153以及镂空部的栅极绝缘层150；
所述栅极绝缘层150的中部151的厚度厚于第一侧部152的厚度，所述栅极绝缘层150的中部151的厚度厚于第二侧部153的厚度；所述镂空部形成在中部151和第一侧部152，以及中部151和第二侧部153之间；
S53：在所述栅极绝缘层150上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163，形成的所述源极层162和漏极层163通过所述氧化物膜层140连接；
所述栅极层161位于与栅极绝缘层150中部151上；
所述栅极层161的宽度小于栅极绝缘层150中部151的宽度，源极层162和漏极层163分别位于栅极绝缘层150两侧部上；
所述源极层162、漏极层163与栅极层161绝缘；
S54：在栅极层161、源极层162和漏极层163上依次形成钝化层170和透明电极层180。
本方案中，在所述栅极绝缘层150上金属溅渡形成第二层金属，并通过同一道光罩 制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163，再次减少光罩的使用，进一步减少制程，使得本申请的方案可以通过五道光罩得到，极大提高生产效率,达到节约成本及提升产能的目的。并且源极层162和漏极层163，同栅极层161之前，由于断差结构和镂空部的设置，可以避免短路的情况，保证绝缘，保证了TFT的开关性能。
其中，相对于一般性示例的七道光罩制程，本申请在通过同一道光罩蚀刻形成第一金属层120、缓冲层130和氧化物膜层140减少一道光罩制程的基础上，又通过同一道光罩制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163，进一步减少了光罩制程，进一步提高了生产效率，达到了更好的节约成本及提升产能的目的。
作为本申请的另一实施例，参考图3a所示，公开了一种显示面板100，包括：
第一基板110，所述第一基板110上依次设置有第一金属层120、缓冲层130和氧化物膜层140；
栅极绝缘层150、栅极层161、源极层162和漏极层163，形成在氧化物膜层140上；
钝化层170和透明电极层180，依次形成在所述第二金属层上；
所述第一金属层120、缓冲层130和氧化物膜层140通过同一道光罩制程形成。
本方案中，所述第一金属层120、缓冲层130和氧化物膜层140通过同一道光罩制程形成；相对于将第一金属层120、缓冲层130和氧化物膜层140用不同的光罩分开形成的制程来说，减少一道光罩,由七道光罩变为六道光罩,节省一道曝光显影时间，达到节约成本及提升产能的目的。
在一实施例中，参考图2c所示，所述栅极绝缘层150，位于所述氧化物膜层140的上；
所述栅极绝缘层150包括中部151、第一侧部152和第二侧部153，所述中部151的厚度大于所述第一侧部152和第二侧部153的厚度；
所述栅极绝缘层150还包括形成在所述中部151和第一侧部152之间的第一镂空部154，以及形成在所述中部151和第二侧部153之间的第二镂空部155；
所述栅极层161形成在所述中部151上；
所述源极层162形成在所述第一侧部152上，并通过所述第一镂空部154连接于所述氧化物膜层140；
所述漏极层163形成在所述第二侧部153上，并通过所述第二镂空部155连接于所述氧化物膜层140；
所述栅极层161、源极层162和漏极层163由同一金属层，通过同一道光罩制程形成。
本方案中，在所述栅极绝缘层150上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层161、源极层162和漏极层163，再次减少光罩的使用，进一步减少制程，使得本申请的方案可以通过五道光罩得到，极大提高生产效率,达到节约成本及提升产能的目的。
在一实施例中，参考图3b至3d所示，所述栅极绝缘层150，位于所述氧化物膜层140的中部151上；
栅极层161，位于所述栅极绝缘层150上；
互联层160，位于所述氧化物膜层140上；
所述互联层160包括中部151、第一侧部152和第二侧部153，所述中部151和第一侧部152之间形成第一镂空部154，所述中部151和第二侧部153之间形成第二镂空部155；
所述源极层162位于第一侧部152和中部151上，并通过所述第一镂空部154连接于所述氧化物膜层140；
所述漏极层163位于第二侧部153和中部151上，并通过所述第二镂空部155连接于所述氧化物膜层140；
所述源极层162和漏极层163由同一金属层，通过同一道光罩制程形成。
本方案中，先形成栅极层161，再形成源极层162和漏极层163，源极层162和漏极层163是在同一层上形成的，与栅极层161不是再同一层，可以使得源极层162、漏极层163与栅极层161绝缘。在互联层160包括中部151、第一侧部152、第二侧部153 以及镂空部，由于镂空部的设置，可以避免短路的情况，保证绝缘，保证了TFT的开关性能。
在一实施例中，所述栅极层161的宽度小于栅极绝缘层150中部151的宽度，所述源极层162、漏极层163与栅极层161绝缘，所述源极层162和漏极层163通过氧化物膜层140连接。
本方案中，栅极层161的宽度小于栅极绝缘层150中部151的宽度，源极层162和漏极层163分别位于栅极绝缘层150两侧部上，可以减少栅极层161和漏极层163之间产生的寄生电容，以及栅极层161和源极层162之间产生的寄生电容。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的面板可以是TN面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS面板(In-Plane Switching，平面转换)、VA面板(Multi-domain Vertical Alignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，适用即可。
以上内容是结合具体的可选的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (17)

  1. 一种显示面板的制作方法，包括：
    在基板上依次沉积一层金属、缓冲材料和氧化物，通过同一道光罩蚀刻形成第一金属层、缓冲层和氧化物膜层；
    在所述氧化物膜层上形成栅极绝缘层、栅极层、源极层和漏极层；以及
    在栅极层、源极层和漏极层上依次形成钝化层和透明电极层。
  2. 如权利要求1所述的一种显示面板的制作方法，其中，所述在所述氧化物膜层上形成栅极绝缘层、栅极层、源极层和漏极层的步骤包括：
    在所述氧化物膜层上通过半色调掩膜形成包括中部、第一侧部、第二侧部以及镂空部的栅极绝缘层；
    所述栅极绝缘层的中部的厚度厚于第一侧部的厚度，所述栅极绝缘层的中部的厚度高于第二侧部的厚度；
    所述镂空部形成在中部和第一侧部，以及中部和第二侧部之间；
    在所述栅极绝缘层上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层、源极层和漏极层；以及
    形成的所述源极层和漏极层通过所述氧化物膜层连接。
  3. 如权利要求1所述的一种显示面板的制作方法，其中，所述在所述氧化物膜层上形成栅极绝缘层、栅极层、源极层和漏极层的步骤包括：
    在氧化物膜层上沉积形成栅极绝缘沉积层，并在栅极绝缘沉积层上沉积形成栅极金属层；
    通过一道光罩制程对栅极绝缘沉积层和栅极金属层进行蚀刻，形成栅极绝缘层和栅极层；
    在氧化物膜层上通过一道光罩形成包括中部、第一侧部、第二侧部以及镂空部的互联层；
    在互联层上形成第二层金属，并对第二层金属进行蚀刻得到漏极层和源极层；以及
    所述镂空部形成在中部和第一侧部，以及中部和第二侧部之间。
  4. 如权利要求1所述的一种显示面板的制作方法，其中，所述在基板上通过同一道光罩蚀刻依次形成第一金属层、缓冲层和氧化物膜层的步骤包括：
    在氧化物膜沉积层上通过一道光罩形成预设图案的光阻层；
    对所述氧化物膜沉积层的两侧部不重叠于光阻层的部分进行蚀刻得到氧化物膜层；
    对所述缓冲层的两侧部且不重叠于氧化物膜层的部分进行蚀刻得到缓冲层；
    对所述第一金属层的两侧部且不重叠于缓冲层的部分进行蚀刻，得到第一金属层；以及
    剥离清除氧化物膜层上的光阻层。
  5. 如权利要求4所述的一种显示面板的制作方法，其中，所述缓冲层宽度大于所述氧化物膜层宽度。
  6. 如权利要求4所述的一种显示面板的制作方法，其中，所述第一金属层宽度大于所述缓冲层宽度。
  7. 如权利要求2所述的一种显示面板的制作方法，其中，所述在栅极绝缘层上形成第二层金属，并通过同一道光罩制程蚀刻得到栅极层、源极层和漏极层的步骤中；
    所述栅极层位于与栅极绝缘层中部上；
    所述栅极层的宽度小于栅极绝缘层中部的宽度，源极层和漏极层分别位于栅极绝缘层两侧部上；以及
    所述源极层、漏极层与栅极层绝缘。
  8. 如权利要求1所述的一种显示面板的制作方法，其中，所述基板为玻璃基板。
  9. 一种显示面板的制作方法，包括：
    在基板上依次沉积一层金属、缓冲材料和氧化物；
    通过同一道光罩蚀刻依次形成第一金属层、缓冲层和氧化物膜层；
    在所述氧化物膜层上通过半色调掩膜形成包括中部、第一侧部、第二侧部以及镂空部的栅极绝缘层；
    所述栅极绝缘层的中部的厚度厚于第一侧部的厚度，所述栅极绝缘层的中部的厚度 厚于第二侧部的厚度；
    所述镂空部形成在中部和第一侧部，以及中部和第二侧部之间；
    在所述栅极绝缘层上金属溅渡形成第二层金属，并通过同一道光罩制程对第二层金属进行蚀刻得到栅极层、源极层和漏极层，形成的所述源极层和漏极层通过所述氧化物膜层连接；
    所述栅极层位于与栅极绝缘层中部上；
    所述栅极层的宽度小于栅极绝缘层中部的宽度，源极层和漏极层分别位于栅极绝缘层两侧部上；
    所述源极层、漏极层与栅极层绝缘；以及
    在栅极层、源极层和漏极层上依次形成钝化层和透明电极层。
  10. 一种显示面板，包括：
    第一基板，所述第一基板上依次设置有第一金属层、缓冲层和氧化物膜层；
    栅极绝缘层、栅极层、源极层和漏极层，形成在氧化物膜层上；以及
    钝化层和透明电极层，依次形成在所述第二金属层上；
    所述第一金属层、缓冲层和氧化物膜层通过同一道光罩制程形成。
  11. 如权利要求10所述的一种显示面板，其中，所述第一基板为玻璃基板。
  12. 如权利要求10所述的一种显示面板，其中，所述缓冲层宽度大于所述氧化物膜层宽度。
  13. 如权利要求10所述的一种显示面板，其中，所述第一金属层宽度大于所述缓冲层宽度。
  14. 如权利要求10所述的一种显示面板，其中，所述栅极绝缘层，位于所述氧化物膜层上；
    所述栅极绝缘层包括中部、第一侧部和第二侧部，所述中部的厚度大于所述第一侧部和第二侧部的厚度；
    所述栅极绝缘层还包括形成在所述中部和第一侧部之间的第一镂空部，以及形成在所述中部和第二侧部之间的第二镂空部；
    所述栅极层形成在所述中部上；
    所述源极层形成在所述第一侧部上，并通过所述第一镂空部连接于所述氧化物膜层；
    所述漏极层形成在所述第二侧部上，并通过所述第二镂空部连接于所述氧化物膜层；
    所述栅极层、源极层和漏极层由同一金属层，通过同一道光罩制程形成。
  15. 如权利要求10所述的一种显示面板，其中，所述栅极绝缘层，位于所述氧化物膜层的中部上；
    栅极层，位于所述栅极绝缘层上；以及
    互联层，位于所述氧化物膜层上；
    所述互联层包括中部、第一侧部和第二侧部，所述中部和第一侧部之间形成第一镂空部，所述中部和第二侧部之间形成第二镂空部；
    所述源极层位于第一侧部和中部上，并通过所述第一镂空部连接于所述氧化物膜层；
    所述漏极层位于第二侧部和中部上，并通过所述第二镂空部连接于所述氧化物膜层；
    所述源极层和漏极层由同一金属层，通过同一道光罩制程形成。
  16. 如权利要求14所述的一种显示面板，其中，所述栅极层的宽度小于栅极绝缘层中部的宽度，所述源极层、漏极层与栅极层绝缘，所述源极层和漏极层通过氧化物膜层连接。
  17. 如权利要求10所述的一种显示面板，其中，所述显示面板为扭曲向列型显示面板、平面转换显示面板和多象限垂直配向显示面板中的一种。
PCT/CN2018/115609 2018-10-22 2018-11-15 一种显示面板的制作方法和显示面板 Ceased WO2020082459A1 (zh)

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CN111129083A (zh) * 2019-12-11 2020-05-08 深圳市华星光电半导体显示技术有限公司 显示面板的制造方法及显示面板
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