WO2020079810A1 - Dispositif d'aide à la conception, procédé d'aide à la conception et programme - Google Patents

Dispositif d'aide à la conception, procédé d'aide à la conception et programme Download PDF

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Publication number
WO2020079810A1
WO2020079810A1 PCT/JP2018/038851 JP2018038851W WO2020079810A1 WO 2020079810 A1 WO2020079810 A1 WO 2020079810A1 JP 2018038851 W JP2018038851 W JP 2018038851W WO 2020079810 A1 WO2020079810 A1 WO 2020079810A1
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WO
WIPO (PCT)
Prior art keywords
design
unit
error
drc
image data
Prior art date
Application number
PCT/JP2018/038851
Other languages
English (en)
Japanese (ja)
Inventor
浩彦 松沢
勝義 生田
清久 長谷川
榮一 古田
佐藤　光浩
Original Assignee
株式会社図研
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社図研 filed Critical 株式会社図研
Priority to JP2020551677A priority Critical patent/JP7112506B2/ja
Priority to PCT/JP2018/038851 priority patent/WO2020079810A1/fr
Publication of WO2020079810A1 publication Critical patent/WO2020079810A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]

Definitions

  • the present invention relates to a design support device, a design support method, and a program.
  • Patent Document 1 describes a pseudo error registration method having a function of registering pseudo error data in a library server.
  • the number of errors provided by the DRC function can be enormous, for example, hundreds or thousands. It is very troublesome for the designer to individually determine whether or not each of such a huge number of errors is a pseudo error. Further, in this troublesome work, there is a risk of overlooking the true error by erroneously determining the true error to be corrected as a pseudo error.
  • the purpose of the present invention is to provide an advantageous technique for improving the efficiency of the work of confirming whether the error determined by the design rule check is a true error.
  • an advantageous technique is provided to streamline the work of confirming whether the error determined by the design rule check is a true error.
  • the second DRC unit 113 can perform a design rule check on the image data generated by the generation unit 112 by the artificial intelligence that has undergone deep learning, and can output the first information indicating the result of the design rule check.
  • the display control unit 114 can display the first information indicating the result of the design rule check by the second DRC unit 113 on (the display screen of) the display unit 103.
  • the error editing unit 115 can exclude the error information selected by the designer (user) from the list including a plurality of error information.
  • the teaching unit 116 can generate processed image data by processing the image data generated by the generation unit 112. Then, the teaching unit 116 uses, as learning data, teacher information indicating whether the configuration indicated by the processed image data should be determined to be an error by the design rule check by the second DRC unit 113 and the processed image data. , And can be provided to the second DRC unit 113.
  • the board editing unit 117 can edit the board design data in accordance with an instruction from a user (designer) who operates the input unit 104.
  • the display control unit 114 causes the display unit 103 to display the error data 120.
  • the display control unit 114 can scroll the error data 120 on the display unit 103.
  • the display control unit 114 can display the error data 120 on the display unit 103, for example, in the form of a list including a plurality of error information.
  • Each error information may include identification information that identifies a portion determined to be in error by the first DRC unit 111.
  • each error information may include identification information that identifies a portion determined to be an error by the first DRC unit 111, and first information that indicates a result of the design rule check by the second DRC unit 113.
  • the generation unit 112 can binarize the image data 305 and generate the image data 203.
  • the image data 203 may typically be bitmap data (raster data).
  • the generation unit 112 can generate the image data 203 so as not to include objects other than the object that is the target of the error.
  • a plurality of learning data is generated from the original data by the teaching unit 116 and provided to the second DRC unit 113, so that the preparation work of the learning data required for causing the second DRC unit 113 to perform the learning by the deep learning is made efficient. be able to.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Image Analysis (AREA)

Abstract

L'invention concerne un dispositif d'aide à la conception qui réalise des vérifications de règles de conception sur des données de conception pour un substrat sur lequel sont disposés des éléments de circuit. Le dispositif d'aide à la conception comporte : une première unité DRC qui réalise des vérifications de règles de conception sur les données de conception par calcul géométrique ; une unité de génération qui génère, à partir des données de conception, des données d'image dans lesquelles une partie déterminée comme étant une erreur par la première unité DRC est centrée ; une seconde unité DRC qui réalise des vérifications de règle de conception sur les données d'image à l'aide d'une intelligence artificielle obtenue par apprentissage profond ; et une unité de commande d'affichage qui amène une unité d'affichage à afficher des premières informations indiquant le résultat de vérifications de règle de conception par la seconde unité DRC.
PCT/JP2018/038851 2018-10-18 2018-10-18 Dispositif d'aide à la conception, procédé d'aide à la conception et programme WO2020079810A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2020551677A JP7112506B2 (ja) 2018-10-18 2018-10-18 設計支援装置、設計支援方法およびプログラム
PCT/JP2018/038851 WO2020079810A1 (fr) 2018-10-18 2018-10-18 Dispositif d'aide à la conception, procédé d'aide à la conception et programme

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2018/038851 WO2020079810A1 (fr) 2018-10-18 2018-10-18 Dispositif d'aide à la conception, procédé d'aide à la conception et programme

Publications (1)

Publication Number Publication Date
WO2020079810A1 true WO2020079810A1 (fr) 2020-04-23

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2018/038851 WO2020079810A1 (fr) 2018-10-18 2018-10-18 Dispositif d'aide à la conception, procédé d'aide à la conception et programme

Country Status (2)

Country Link
JP (1) JP7112506B2 (fr)
WO (1) WO2020079810A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1139365A (ja) * 1997-07-22 1999-02-12 Nec Corp 半導体集積回路のレイアウトデータにおけるデザインルールチェック方法および該方法を実施するための装置
JP2013175016A (ja) * 2012-02-24 2013-09-05 Fujitsu Ltd 欠陥箇所予測装置，欠陥箇所予測プログラムおよび欠陥箇所予測方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1139365A (ja) * 1997-07-22 1999-02-12 Nec Corp 半導体集積回路のレイアウトデータにおけるデザインルールチェック方法および該方法を実施するための装置
JP2013175016A (ja) * 2012-02-24 2013-09-05 Fujitsu Ltd 欠陥箇所予測装置，欠陥箇所予測プログラムおよび欠陥箇所予測方法

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Publication number Publication date
JPWO2020079810A1 (ja) 2021-09-09
JP7112506B2 (ja) 2022-08-03

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