WO2020073995A1 - 磁性随机存储器 - Google Patents

磁性随机存储器 Download PDF

Info

Publication number
WO2020073995A1
WO2020073995A1 PCT/CN2019/110672 CN2019110672W WO2020073995A1 WO 2020073995 A1 WO2020073995 A1 WO 2020073995A1 CN 2019110672 W CN2019110672 W CN 2019110672W WO 2020073995 A1 WO2020073995 A1 WO 2020073995A1
Authority
WO
WIPO (PCT)
Prior art keywords
driver
substrate
group
random access
access memory
Prior art date
Application number
PCT/CN2019/110672
Other languages
English (en)
French (fr)
Inventor
李辉辉
戴强
Original Assignee
浙江驰拓科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 浙江驰拓科技有限公司 filed Critical 浙江驰拓科技有限公司
Publication of WO2020073995A1 publication Critical patent/WO2020073995A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

Definitions

  • the present disclosure relates to the field of storage, and in particular, to a magnetic random access memory.
  • the width of the MOS tube as the driver must be made large enough to ensure the write power supply capacity.
  • the area of the transistor in the IT1R structure is significantly larger than the MTJ The area limits the MRAM storage density.
  • the above 1T1R indicates that one transistor corresponds to one storage bit.
  • the structure and material of the MTJ bit in the MRAM memory are relatively complex, the MTJ film is expensive to prepare, and the substrate surface roughness is extremely high, and the MTJ magnetic and electrical properties are sensitive to temperature, so the MRAM is not suitable for 3D stacking to improve storage density.
  • the main purpose of the present disclosure is to provide a magnetic random access memory to solve the problem that the storage density of the magnetic random access memory in the prior art is small.
  • a magnetic random access memory including: a substrate; a plurality of driver groups, each of the above driver groups is located on a surface of the above substrate, and a plurality of the above drivers The groups are sequentially arranged in a direction away from the substrate.
  • Each of the driver groups includes one or more drivers spaced along the first direction.
  • the center of each driver in the driver group is the same distance from the substrate.
  • the projection of at least one of the drivers in the driver group on the substrate overlaps with the projection of at least one of the drivers in the adjacent driver group on the surface of the substrate.
  • the driver group with the largest distance is the top driver group, and the first direction is perpendicular to the thickness direction of the substrate; a plurality of MTJ bits spaced along the first direction are located on the top driver group away from the substrate On one side, one or more of the above MTJ bits and one or more of the above drivers It should be electrically connected.
  • each of the driver groups includes a plurality of the same drivers, and the projection of the driver in each driver group on the substrate is the same as the projection of the driver in the adjacent driver group on the substrate Corresponding to the overlap, the drivers are electrically connected to the MTJ bits in a one-to-one correspondence, and the projections on the substrate correspond one-to-one to the two MTJ bits that are electrically connected to the two drivers that overlap and are adjacent to each other.
  • the projection of the driver on the substrate in each of the driver groups coincides with the projection of the driver on the substrate in the adjacent driver group on a one-to-one correspondence.
  • the magnetic random access memory further includes a plurality of isolation dielectric layers, each of the isolation dielectric layers is disposed on the surface of the substrate, and the plurality of isolation dielectric layers are sequentially stacked in a direction away from the substrate, each The driver group is located in at least one of the isolation media layers, and the multiple MTJ bits are located in at least one of the isolation media layers.
  • the magnetic random access memory further includes a plurality of through hole groups, each of the through hole groups includes at least one through hole, the height of the through holes in at least two of the through hole groups is different, and each of the through holes is located in the isolation medium
  • at least part of the plurality of via groups correspond to the driver group in one-to-one correspondence, and the vias in one via group corresponding to the driver group are used to electrically connect one MTJ bit and one driver One of the above drives in the group.
  • the magnetic random access memory includes at least one driving interconnection group, the driving interconnection group is located in the isolation dielectric layer, and the driving interconnection group includes a plurality of driving interconnection metal portions spaced apart along the first direction, at least There is one of the above-mentioned driving interconnection metal parts in the above-mentioned driving interconnection group for electrically connecting the above-mentioned via holes and the above-mentioned driver in a one-to-one correspondence.
  • driver groups there are two driver groups, namely a first driver group and a second driver group, the first driver group is located on the surface of the substrate, and the second driver group is located away from the liner of the first driver group On the bottom side, the first driver group includes a plurality of first drivers, and the second driver group includes a plurality of second drivers.
  • the driver is a MOSFET.
  • the MOSFET includes a source, a gate, and a drain.
  • the magnetic random access memory further includes a plurality of spaced source lines, a plurality of spaced word lines, and a plurality of spaced bit lines.
  • the source line is electrically connected to the source in one-to-one correspondence
  • the word line corresponds to the driver group in one-to-one correspondence
  • one word line is electrically connected to the gate of each driver in the driver group
  • the bit line is in The above MTJ bits are electrically connected in one-to-one correspondence.
  • each MTJ bit on the surface of the substrate is located inside the projection of the electrically connected driver on the surface of the substrate, and each MTJ bit is located Magnetic layer, insulating layer, fixed magnetic layer and top electrode.
  • the resistance values of all the through holes for electrically connecting the MTJ bit and the driver are equal.
  • a plurality of stacked driver groups are provided in the magnetic random access memory, and the projections of the drivers in the adjacent driver groups on the substrate surface have overlapping parts, which is relative to the prior art
  • the areal density of the drive in the vertical direction is improved, so that the areal density of the corresponding MTJ storage bit is also increased accordingly, and finally the storage density of the magnetic random access memory is Existing technology has improved.
  • it does not increase the processing difficulty of the most challenging MTJ storage bit, making the manufacturing process of the high-density magnetic random access memory simple and the manufacturing cost low.
  • FIG. 1 shows a schematic circuit diagram of an embodiment of a magnetic random access memory according to the present disclosure
  • FIG. 2 shows a schematic structural diagram of a magnetic random access memory in Embodiment 1 of the present disclosure
  • FIG. 3 shows a schematic structural diagram of a magnetic random access memory in Embodiment 2 of the present disclosure.
  • the width of the MOS tube must be made large enough to ensure the power supply capacity, resulting in
  • the area of the transistor in the IT1R structure is significantly larger than the area of the MTJ, which limits the MRAM storage density and makes the storage density of the magnetic random access memory smaller.
  • the present disclosure proposes a magnetic random access memory.
  • a magnetic random access memory is provided, as shown in FIGS. 1 to 3, the magnetic random access memory includes a substrate 10, a plurality of driver groups 20, and a plurality of along the first direction MTJ bit 60 set at intervals.
  • Each of the driver groups 20 is located on the surface of the substrate 10, a plurality of the driver groups 20 are sequentially arranged in a direction away from the substrate 10, and each of the driver groups 20 includes one or more spaced apart along the first direction
  • the driver 200 that is, each of the above-mentioned driver groups includes at least one driver.
  • the driver group includes a plurality of drivers, the plurality of drivers are sequentially arranged and spaced apart along the first direction.
  • the center of each of the above-mentioned drivers 200 in one driver group 20 is The distance between the substrates 10 is the same, that is, the distance from the same surface of the substrate is the same. At least one of the driver 200 in each driver group 20 is projected on the substrate 10 and the adjacent driver group 20 At least one of the drivers 200 has an overlapping projection on the surface of the substrate 10.
  • the driver group 20 having the largest distance from the substrate 10 is a top layer driver group.
  • the thickness direction of the bottom is perpendicular. As shown in Figure 2 and Figure 3, and the first direction in these two figures is also perpendicular to the paper or computer screen.
  • a plurality of MTJ bits 60 spaced apart along the first direction are a plurality of MTJ bits arranged sequentially and spaced along the first direction, and the MTJ bits 60 are located on the side of the top layer driver group away from the substrate 10,
  • One or more of the above-mentioned MTJ bits 60 are electrically connected to one or more of the above-mentioned drivers 200, that is, one driver can be electrically connected to one MTJ bit, namely 1T1R; one driver can also be corresponding to multiple MTJ bits It is electrically connected separately, namely 1TNR; it can also be that multiple drivers are respectively electrically connected to one MTJ bit, namely NT1R.
  • the magnetic random access memory a plurality of stacked driver groups are provided, and the projections of the drivers in adjacent driver groups on the substrate surface have overlapping parts.
  • the areal density of the driver in the vertical direction so that the areal density of the corresponding MTJ storage bit is also correspondingly improved, and finally the storage density of the magnetic random access memory is improved relative to the prior art.
  • it does not increase the processing difficulty of the most challenging MTJ storage bit, making the manufacturing process of the high-density magnetic random access memory simple and the manufacturing cost low.
  • the magnetic random access memory of the present invention may be RRAM, PCRAM or MRAM.
  • each of the above-mentioned driver groups 20 includes a plurality of the same above-mentioned drivers 200, and each of the above-mentioned driver groups 20
  • the projection of the driver 200 on the substrate 10 overlaps with the projection of the driver 200 on the substrate 10 in the adjacent driver group 20, and the projection on the substrate 10 corresponds to
  • the two overlapping drivers 200 are adjacent to the two electrically connected MTJ bits 60.
  • overlap refers to a part with overlap, specifically, it may be only partially overlapped, or may overlap all, that is, overlap.
  • the projection of the driver 200 in each of the driver groups 20 on the substrate 10 and the driver 200 in the adjacent driver group 20 in the background coincide with each other. This can minimize the width of multiple drives, thereby further increasing the storage density of the magnetic random access memory.
  • the magnetic random access memory of the present disclosure further includes a plurality of isolation dielectric layers 30, each of the isolation dielectric layers 30 is disposed on the surface of the substrate 10, and a plurality of the isolation dielectric layers Each of the driver groups 20 is located in at least one of the isolation dielectric layers 30, and a plurality of MTJ bits 60 are located in at least one of the isolation dielectric layers 30.
  • the number of isolation media layers provided is different, and those skilled in the art can set an appropriate number of isolation media layers according to the actual situation, as long as it is greater than the number of driver groups.
  • the magnetic random access memory further includes a plurality of through-hole groups 40, and each of the through-hole groups 40 includes at least one through-hole and at least two of the above-mentioned through-holes
  • the heights of the above-mentioned through-holes in the group 40 are different, as shown in the first through-hole 41 and the second through-hole 42 shown in FIG. 2 and FIG.
  • the vias with smaller heights are located in one isolation dielectric layer; they may also be located in multiple isolation dielectric layers, as shown in FIGS. 2 and 3, the vias with larger heights are located in multiple isolation media Floor.
  • At least part of the plurality of through-hole groups 40 corresponds to the driver group 20 in one-to-one correspondence, and the through-holes in one of the through-hole groups 40 corresponding to the driver group 20 are used to electrically connect one MTJ bit and one One of the aforementioned drivers 200 in the driver group 20.
  • the through-holes in the present disclosure are commonly referred to as through-holes in semiconductors.
  • the through-holes are actually conductive through-holes, that is, the empty through-holes are filled with conductors, and the conductors may be copper or tungsten. metal.
  • the magnetic random access memory includes at least one driving interconnection group 50, the driving interconnection group 50 is located in the isolation dielectric layer 30, and the driving interconnection group 50 includes A plurality of drive interconnect metal portions 500 spaced apart along the first direction, at least one of the drive interconnect metal portions 500 in the drive interconnect group 50 is used to electrically connect the through holes and the driver 200 in a one-to-one correspondence .
  • the first driver group 21 is located on the surface of the substrate 10
  • the second driver group 22 is located on the side of the first driver group 21 away from the substrate 10
  • the first driver group 21 includes a plurality of With the first drivers 210 spaced along the first direction
  • the second driver group 22 includes a plurality of second drivers 220 spaced along the first direction.
  • the driver in the present disclosure may be any available driver in the prior art, and may be a diode or a triode. Those skilled in the art may select a suitable device as the driver according to actual conditions.
  • the driver 200 is a MOSFET.
  • the MOSFET includes a source, a gate, and a drain.
  • the magnetic random access memory further includes multiple Source lines 70 arranged at intervals, word lines 80 arranged at intervals and bit lines 90 arranged at intervals, the source lines 70 are electrically connected to the sources in one-to-one correspondence, the word lines 80 are connected to the drivers The groups 20 correspond to each other, one word line 80 is electrically connected to the gate of each driver 200 of the driver group 20, and the bit line 90 is electrically connected to the MTJ bit 60 in one-to-one correspondence.
  • the source line 70 and the word line 80 are indicated by dotted lines because they are not in the current cross-section, but in a direction perpendicular to the paper or screen or On the outward section.
  • each of the above-mentioned MTJ bits 60 includes a bottom electrode 61, a free magnetic layer, an insulating layer, a fixed magnetic layer, and a top electrode 63 which are sequentially stacked, wherein the free magnetic layer, the insulating layer, and the The fixed magnetic layer is shown as a whole, and is called an MTJ portion 62.
  • the resistance values of all the through holes for electrically connecting the MTJ bit and the driver are equal.
  • the resistance values of all the first through holes for electrically connecting the first driver and the MTJ bit are equal to those of the second through holes for electrically connecting the second driver and the MTJ bit.
  • the resistance values of the through holes are equal. Specifically, since the first through holes are longer, the diameters of the through holes may be slightly larger in order to have the same resistance value as the second through holes.
  • the magnetic random access memory includes a substrate 10, two driver groups 20, multiple identical MTJ bits 60, multiple isolation dielectric layers 30, six via groups 40, multiple identical source lines 70.
  • Two word lines 80, multiple identical bit lines 90, and multiple other interconnect metal parts 100 For the positional relationship of each structure, refer to the above description and shown in FIG. 2.
  • the two driver groups are a first driver group 21 and a second driver group 22, respectively.
  • the first driver group 21 is located on the surface of the substrate 10, and the second driver group 22 is located away from the liner of the first driver group 21
  • the first driver group 21 includes a plurality of first drivers 210
  • the second driver group 22 includes a plurality of second drivers 220.
  • the first driver 210 and the second driver 220 are the same, and the projection of the first driver 210 on the substrate 10 overlaps with the corresponding projection of the second driver 220 on the substrate 10 in a one-to-one correspondence.
  • Each MTJ bit includes a bottom electrode, a free magnetic layer, an insulating layer, a fixed magnetic layer, and a top electrode stacked in this order.
  • the free magnetic layer, the insulating layer, and the fixed magnetic layer are shown as a whole, which is called MTJ. ⁇ 62.
  • the six via groups are the first via group, the second via group, the third via group, the fourth via group, the fifth via group, the sixth via group and the seventh via group, of which ,
  • the first through-hole group includes multiple identical first through-holes 41
  • the second through-hole group includes multiple identical second through-holes 42
  • the first through-hole 41 in the first through-hole group and the first driver group The first driver 210 in the one-to-one correspondence and electrically connects one MTJ bit 60 and one first driver 210, the second through hole 42 in the second through hole group and the second driver 220 in the second driver group one to one Correspondingly, and one MTJ bit 60 and one second driver 220 are electrically connected.
  • the third through-hole group, the fourth through-hole group and the fifth through-hole group all include one through-hole, which are the third through-hole 43, the fourth through-hole 44 and the fifth through-hole 45 respectively, and the sixth through-hole group includes two The same sixth through hole 46, third through hole 43, fourth through hole 44, one sixth through hole 46 and the metal interconnection between the through holes lead the first word line 81 out of the first word line to the electrode 810 lead out, the fifth via hole 45 and one sixth via hole 46 and other interconnection metal parts 100 between the via holes lead the second word line 82 out of the second word line lead electrode 820, the seventh via group includes multiple The same seventh through holes 47 are provided at intervals.
  • Each of the through hole groups 40 includes at least one through hole.
  • the height of the through holes in at least two of the through hole groups 40 is different.
  • Each of the through holes is located in the isolation dielectric layer 30. At least partly corresponds one-to-one to the driver group 20, and the through-hole in one of the through-hole groups 40 corresponding to the drive group 20 is used to electrically connect one of the MTJ bit and one of the drivers 200 in the one of the driver groups 20 .
  • the driver 200 is a MOSFET.
  • the MOSFET includes a source, a gate, and a drain.
  • the source line 70 is electrically connected to the source in a one-to-one correspondence.
  • the two word lines are a first word line 81 and a second word line, respectively. 82, wherein the first word line 81 is electrically connected to the gate of each first driver 210 in the first driver group 21, and the second word line 82 is connected to the gate of each second driver 220 in the second driver group 22 Electrically connected, the bit line 90 is electrically connected to the MTJ bit 60 in a one-to-one correspondence, and is electrically connected to the top electrode 63 through the seventh through hole 47.
  • Embodiment 3 it is different from Embodiment 1 in that the projection of the first driver 210 on the substrate 10 and the corresponding projection of the second driver 220 on the substrate 10 coincide with each other, that is, all coincide .
  • the magnetic random access memory further includes an eighth through-hole group and a driving interconnection group 50.
  • the eighth through-hole group includes a plurality of spaced and identical eighth through-holes 48, each eighth through-hole 48 is located in each first driver
  • the driving interconnection group 50 is located in the isolation dielectric layer 30, and the driving interconnection group 50 includes a plurality of identical driving interconnection metal portions spaced apart along the first direction 500, the driving interconnect metal portion 500 in the driving interconnect group 50 is used to electrically connect the first through hole 41 and the eighth through hole 48 in one-to-one correspondence, thereby electrically connecting the MTJ bit 60 and the first driver 210.
  • a plurality of stacked driver groups are provided, and the projections of the drivers in adjacent driver groups on the substrate surface have overlapping parts, so that relative to the prior art, by passing in a vertical space
  • the driver is arranged in an upper layer to increase the areal density of the driver in the vertical direction, so that the areal density of the corresponding MTJ storage bit is also correspondingly improved, and finally the storage density of the magnetic random access memory is improved relative to the prior art .
  • it does not increase the processing difficulty of the most challenging MTJ storage bit, making the manufacturing process of the high-density magnetic random access memory simple and the manufacturing cost low.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

一种磁性随机存储器，包括：衬底（10），位于衬底（10）的表面沿远离衬底（10）的方向依次设置的多个驱动器组，其包括一个或多个沿第一方向间隔设置的驱动器（200），一个驱动器组中的各驱动器（200）的中心与衬底（10）的距离相同，各驱动器组中的至少一个驱动器（200）在衬底（10）上的投影与相邻驱动器组中的至少一个驱动器（200）在衬底（10）表面的投影有重叠，第一方向与衬底（10）的厚度方向垂直；位于顶层驱动器组远离衬底（10）一侧的多个沿第一方向间隔设置的MTJ位元（60），一个或者多个MTJ位元（60）与一个或多个驱动器（200）对应电连接。该磁性随机存储器的存储密度较大。

Description

磁性随机存储器
本公开以2018年10月12日递交的、申请号为201811191866.X且名称为“磁性随机存储器”的专利文件为优先权文件，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及存储领域，具体而言，涉及一种磁性随机存储器。
背景技术
由于目前MTJ位元的写入电流较大，在传统1T1R-MRAM存储器中，作为驱动器的MOS管的宽度必须做得足够大来保证写入供电能力，结果导致IT1R结构中晶体管的面积明显大于MTJ的面积，限制了MRAM存储密度。上述1T1R表示一个晶体管对应一个存储位元。
MRAM存储器中MTJ位元的结构和材料都较复杂，MTJ薄膜制备成本高昂，对衬底表面粗糙度要求极高，且MTJ磁电性能对温度敏感，因此MRAM不适合通过3D堆垛方式提升存储密度。
在背景技术部分中公开的以上信息只是用来加强对本文所描述技术的背景技术的理解，因此，背景技术中可能包含某些信息，这些信息对于本领域技术人员来说并未形成在本国已知的现有技术。
发明内容
本公开的主要目的在于提供一种磁性随机存储器，以解决现有技术中的磁性随机存储器的存储密度较小的问题。
为了实现上述目的，根据本公开的一个方面，提供了一种磁性随机存储器，该磁性随机存储器包括：衬底；多个驱动器组，各上述驱动器组位于上述衬底的表面上，多个上述驱动器组沿远离上述衬底的方向依次设置，各上述驱动器组包括一个或者多个沿第一方向间隔设置的驱动器，一个上述驱动器组中的各上述驱动器的中心与上述衬底的距离相同，各上述驱动器组中的至少一个上述驱动器在上述衬底上的投影与相邻的上述驱动器组中的至少一个上述驱动器在上述衬底表面的投影有重叠，多个上述驱动器组中，与上述衬底之间距离最大的上述驱动器组为顶层驱动器组，上述第一方向与上述衬底的厚度方向垂直；多个沿上述第一方向间隔设置的MTJ位元，位于上述顶层驱动器组的远离上述衬底的一侧，一个或者多个上述MTJ位元与一个或者多个上述驱动器对应电连接。
进一步地，各上述驱动器组包括多个相同的上述驱动器，各上述驱动器组中的上述驱动器在上述衬底上的投影与相邻的上述驱动器组中的上述驱动器在上述衬底上的投影一一对应 有重叠，上述驱动器与上述MTJ位元一一对应地电连接，且在上述衬底上的投影一一对应有重叠的两个上述驱动器对应电连接的两个上述MTJ位元相邻。
进一步地，上述各上述驱动器组中的上述驱动器在上述衬底上的投影与相邻的上述驱动器组中的上述驱动器在上述衬底上的投影一一对应重合。
进一步地，上述磁性随机存储器还包括多个隔离介质层，各上述隔离介质层设置在上述衬底的表面上，且多个上述隔离介质层沿着远离上述衬底的方向依次叠置设置，各上述驱动器组位于至少一个上述隔离介质层中，多个MTJ位元至少位于一个上述隔离介质层中。
进一步地，上述磁性随机存储器还包括多个通孔组，各上述通孔组包括至少一个通孔，至少两个上述通孔组中的上述通孔的高度不同，各上述通孔位于上述隔离介质层中，多个上述通孔组中的至少部分与上述驱动器组一一对应，与上述驱动器组对应的一个上述通孔组中的上述通孔用于电连接一个上述MTJ位元和一个上述驱动器组中的一个上述驱动器。
进一步地，上述磁性随机存储器包括至少一个驱动互连组，上述驱动互连组位于上述隔离介质层中，上述驱动互连组包括多个沿上述第一方向间隔设置的驱动互连金属部，至少有一个上述驱动互连组中的上述驱动互连金属部用于一一对应地电连接上述通孔和上述驱动器。
进一步地，上述驱动器组有两个，分别为第一驱动器组和第二驱动器组，上述第一驱动器组位于上述衬底的表面上，上述第二驱动器组位于上述第一驱动器组的远离上述衬底的一侧，上述第一驱动器组包括多个第一驱动器，上述第二驱动器组包括多个第二驱动器。
进一步地，上述驱动器为MOSFET，上述MOSFET包括源极、栅极和漏极，上述磁性随机存储器还包括多个间隔设置的源极线、多个间隔设置的字线和多个间隔设置的位线，上述源极线与上述源极一一对应地电连接，上述字线与上述驱动器组一一对应，一个上述字线与上述驱动器组的各上述驱动器的上述栅极电连接，上述位线与上述MTJ位元一一对应地电连接。
进一步地，各上述MTJ位元在上述衬底表面上的投影位于对应电连接的上述驱动器在上述衬底表面上的投影的内部，各上述MTJ位元位于包括依次叠置设置的底电极、自由磁性层、绝缘层、固定磁性层以及顶电极。
进一步地，所有用于电连接上述MTJ位元和上述驱动器的上述通孔的电阻值相等。
应用本公开的技术方案，该磁性随机存储器中通过设置多个堆叠的驱动器组，且相邻的驱动器组中的驱动器在衬底表面上的投影具有重合的部分，这样相对于现有技术来说，通过在垂直空间上分层排布驱动器，使驱动器在垂直方向上的面密度获得提升，从而相对应的MTJ存储位元的面密度也获得相应提升，最终使得磁性随机存储器的存储密度相对于现有技术有提升。并且，在提升存储密度的同时，并没有增加最具挑战性的MTJ存储位元的加工难度，使该高密度磁性随机存储器的制作工艺简单且制造成本低。
附图说明
构成本公开的一部分的说明书附图用来提供对本公开的进一步理解，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1示出了根据本公开的磁性随机存储器的实施例的电路结构示意图；
图2示出了本公开的实施例1中的磁性随机存储器的结构示意图；
图3示出了本公开的实施例2中的磁性随机存储器的结构示意图。
其中，上述附图包括以下附图标记：
10、衬底；20、驱动器组；21、第一驱动器组；22、第二驱动器组；200、驱动器；210、第一驱动器；220、第二驱动器；30、隔离介质层；40、通孔组；50、驱动互连组；500、驱动互连金属部；60、MTJ位元；70、源极线；80、字线；90、位线；81、第一字线；82、第二字线；41、第一通孔；42、第二通孔；43、第三通孔；44、第四通孔；45、第五通孔；46、第六通孔；47、第七通孔；48、第八通孔；810、第一字线引出电极；820、第二字线引出电极；61、底电极；62、MTJ部；63、顶电极；100、其他互连金属部。
具体实施方式
应该指出，以下详细说明都是例示性的，旨在对本公开提供进一步的说明。除非另有指明，本文使用的所有技术和科学术语具有与本公开所属技术领域的普通技术人员通常理解的相同含义。
需要注意的是，这里所使用的术语仅是为了描述具体实施方式，而非意图限制根据本公开的示例性实施方式。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式，此外，还应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在特征、步骤、操作、器件、组件和/或它们的组合。
应该理解的是，当元件(诸如层、膜、区域、或衬底)描述为在另一元件“上”时，该元件可直接在该另一元件上，或者也可存在中间元件。而且，在说明书以及权利要求书中，当描述有元件“连接”至另一元件时，该元件可“直接连接”至该另一元件，或者通过第三元件“连接”至该另一元件。
正如背景技术所介绍的，现有技术中，由于MTJ位元的写入电流较大，在传统1T1R-MRAM磁性随机存储器件中，MOS管的宽度必须做得足够大来保证供电能力，结果导致IT1R结构中晶体管的面积明显大于MTJ的面积，限制了MRAM存储密度，使得磁性随机存储器的存储密度较小，为了解决如上的技术问题，本公开提出了一种磁性随机存储器。
本公开的一种典型的实施方式中，提供了一种磁性随机存储器，如图1至图3所示，该磁性随机存储器包括衬底10、多个驱动器组20以及多个沿上述第一方向间隔设置的MTJ位元60。其中，各上述驱动器组20位于上述衬底10的表面上，多个上述驱动器组20沿远离上述 衬底10的方向依次设置，各上述驱动器组20包括一个或者多个沿第一方向间隔设置的驱动器200，即各上述驱动器组包括至少一个驱动器，当驱动器组包括多个驱动器时，多个驱动器依次沿着第一方向排列且间隔设置，一个上述驱动器组20中的各上述驱动器200的中心与上述衬底10的距离相同，即与衬底的同一个表面的距离相同，各上述驱动器组20中的至少一个上述驱动器200在上述衬底10上的投影与相邻的上述驱动器组20中的至少一个上述驱动器200在上述衬底10表面的投影有重叠，多个上述驱动器组20中，与上述衬底10之间距离最大的上述驱动器组20为顶层驱动器组，上述第一方向与上述衬底的厚度方向垂直。如图2和图3所示，且这两个图中的第一方向还垂直纸面或电脑屏幕。多个沿第一方向间隔设置的MTJ位元60即多个沿着第一方向依次排列且间隔设置的MTJ位元，MTJ位元60位于上述顶层驱动器组的远离上述衬底10的一侧，一个或者多个上述MTJ位元60与一个或者多个上述驱动器200对应电连接，即可以为一个驱动器对应与一个MTJ位元电连接，即1T1R；也可以为一个驱动器对应与多个MTJ位元分别电连接，即1TNR；还可以是多个驱动器对应分别与一个MTJ位元电连接，即NT1R。
该磁性随机存储器中通过设置多个堆叠的驱动器组，且相邻的驱动器组中的驱动器在衬底表面上的投影具有重合的部分，这样相对于现有技术来说，通过在垂直空间上分层排布驱动器，使驱动器在垂直方向上的面密度获得提升，从而相对应的MTJ存储位元的面密度也获得相应提升，最终使得磁性随机存储器的存储密度相对于现有技术有提升。并且，在提升存储密度的同时，并没有增加最具挑战性的MTJ存储位元的加工难度，使该高密度磁性随机存储器的制作工艺简单且制造成本低。
本发明的磁性随机存储器可以为RRAM、PCRAM或MRAM等。
为了进一步提高磁性随机存储器的存储密度，本公开的一种实施例中，如图2和图3所示，各上述驱动器组20包括多个相同的上述驱动器200，各上述驱动器组20中的上述驱动器200在上述衬底10上的投影与相邻的上述驱动器组20中的上述驱动器200在上述衬底10上的投影一一对应有重叠，且在上述衬底10上的投影一一对应有重叠的两个上述驱动器200对应电连接的两个上述MTJ位元60相邻。
需要说明的是，本公开中的“有重叠”就是指具有重叠的部分，具体可以只有部分重叠，也可以全部重叠，即重合。
如图3所示，本公开的一种实施例中，上述各上述驱动器组20中的上述驱动器200在上述衬底10上的投影与相邻的上述驱动器组20中的上述驱动器200在上述衬底10上的投影一一对应重合。这样可以最大限度地减小多个驱动器的宽度，从而进一步提高磁性随机存储器的存储密度。
具体地，如图2和图3所示，本公开的磁性随机存储器还包括多个隔离介质层30，各上述隔离介质层30设置在上述衬底10的表面上，且多个上述隔离介质层30沿着远离上述衬底10的方向依次叠置设置，各上述驱动器组20位于至少一个上述隔离介质层30中，多个MTJ位元60至少位于一个上述隔离介质层30中。针对不同的工艺，设置的隔离介质层的数量不 同，本领域技术人员可以根据实际情况设置合适数量的隔离介质层，只要大于驱动器组的个数即可。
本公开的另一种实施例中，如图2和图3所示，上述磁性随机存储器还包括多个通孔组40，各上述通孔组40包括至少一个通孔，至少两个上述通孔组40中的上述通孔的高度不同，如图2和图3示出的第一通孔41和第二通孔42，各上述通孔位于上述隔离介质层30中，可能位于一个隔离介质层中，如图2和图3的高度较小的通孔位于一个隔离介质层中；也可能位于多个隔离介质层中，如图2和图3中高度较大的通孔位于多个隔离介质层。多个上述通孔组40中的至少部分与上述驱动器组20一一对应，与上述驱动器组20对应的一个上述通孔组40中的上述通孔用于电连接一个上述MTJ位元和一个上述驱动器组20中的一个上述驱动器200。
需要说明的是，本公开中的通孔就是半导体中的常说的通孔，该通孔实际上为导电通孔，即在空通孔中填充了导体形成的，导体可以为铜或者钨等金属。
本公开的再一种实施例中，如图3所示，上述磁性随机存储器包括至少一个驱动互连组50，上述驱动互连组50位于上述隔离介质层30中，上述驱动互连组50包括多个沿上述第一方向间隔设置的驱动互连金属部500，至少有一个上述驱动互连组50中的上述驱动互连金属部500用于一一对应地电连接上述通孔和上述驱动器200。
为了简化磁性随机存储器的结果，简化其制作工艺，本公开的一种实施例中，如图2和图3所示，上述驱动器组20有两个，分别为第一驱动器组21和第二驱动器组22，上述第一驱动器组21位于上述衬底10的表面上，上述第二驱动器组22位于上述第一驱动器组21的远离上述衬底10的一侧，上述第一驱动器组21包括多个沿着第一方向间隔设置的第一驱动器210，上述第二驱动器组22包括沿着第一方向间隔设置的多个第二驱动器220。
本公开中的驱动器可以是现有技术中任何一种可用的驱动器，可以为二极管，也可以为三级管，本领域技术人员可以根据实际情况选择合适的器件作为驱动器。
本公开的再一种实施例中，如图1所示，上述驱动器200为MOSFET，上述MOSFET包括源极、栅极和漏极，如图2和图3所示，上述磁性随机存储器还包括多个间隔设置的源极线70、多个间隔设置的字线80和多个间隔设置的位线90，上述源极线70与上述源极一一对应地电连接，上述字线80与上述驱动器组20一一对应，一个上述字线80与上述驱动器组20的各上述驱动器200的上述栅极电连接，上述位线90与上述MTJ位元60一一对应地电连接。
需要说明的是，图2和图3中，源极线70和字线80之所以用虚线表示，是因为其并在不在当前的截面中，而是在垂直于纸面或者屏幕的方向内或者向外的截面上。
具体的实施例中，如图2和图3所示，各上述MTJ位元在上述衬底10表面上的投影位于对应电连接的上述驱动器200在上述衬底10表面上的投影的内部，本公开的一种实施例中，各上述MTJ位元60位于包括依次叠置设置的底电极61、自由磁性层、绝缘层、固定磁性层 以及顶电极63，其中，将自由磁性层、绝缘层以及固定磁性层作为一个整体示出，称为MTJ部62。
上述为了保持各存储单元电性的均一性，本公开的一种实施例中，所有用于电连接上述MTJ位元和上述驱动器的上述通孔的电阻值相等。如图2和图3所示的实施例中，所有用于电连接第一驱动器和MTJ位元的第一通孔的电阻值相等和所有用于电连接第二驱动器和MTJ位元的第二通孔的电阻值相等，具体地，由于第一通孔较长，所以为了与第二通孔的电阻值相同，其的直径可以稍大些。
为了使得本领域技术人员能够更加清楚地了解本公开的技术方案以及技术效果，以下将结合具体的实施例来说明。
实施例1
如图2所示，该磁性随机存储器包括衬底10、两个驱动器组20、多个相同MTJ位元60、多个隔离介质层30、六个通孔组40、多个相同的源极线70、两个字线80、多个相同的位线90与多个其他互连金属部100。各个结构的位置关系参考上述描述以及图2所示。
两个驱动器组分别为第一驱动器组21和第二驱动器组22，上述第一驱动器组21位于上述衬底10的表面上，上述第二驱动器组22位于上述第一驱动器组21的远离上述衬底10的一侧，上述第一驱动器组21包括多个第一驱动器210，上述第二驱动器组22包括多个第二驱动器220。第一驱动器210和第二驱动器220相同，且第一驱动器210在上述衬底10上的投影与对应的第二驱动器220在上述衬底10上的投影一一对应部分重叠。
各MTJ位元包括依次叠置设置底电极、自由磁性层、绝缘层、固定磁性层以及顶电极，图2中，将自由磁性层、绝缘层以及固定磁性层作为一个整体示出，称为MTJ部62。
六个通孔组分别为第一通孔组、第二通孔组、第三通孔组、第四通孔组、第五通孔组、第六通孔组和第七通孔组，其中，第一通孔组包括多个相同的第一通孔41，第二通孔组包括多个相同的第二通孔42，第一通孔组中的第一通孔41与第一驱动器组中的第一驱动器210一一对应，且电连接一个MTJ位元60和一个第一驱动器210，第二通孔组中的第二通孔42与第二驱动器组中的第二驱动器220一一对应，且电连接一个MTJ位元60和一个第二驱动器220。第三通孔组、第四通孔组和第五通孔组均包括一个通孔，分别为第三通孔43、第四通孔44和第五通孔45，第六通孔组包括两个相同的第六通孔46，第三通孔43、第四通孔44、一个第六通孔46以及通孔之间的金属互连部将第一字线81从第一字线引出电极810引出，第五通孔45和一个第六通孔46以及通孔之间的其他互连金属部100将第二字线82从第二字线引出电极820引出，第七通孔组包括多个间隔设置的相同的第七通孔47。
各上述通孔组40包括至少一个通孔，至少两个上述通孔组40中的上述通孔的高度不同，各上述通孔位于上述隔离介质层30中，多个上述通孔组40中的至少部分与上述驱动器组20一一对应，与上述驱动器组20对应的一个上述通孔组40中的上述通孔用于电连接一个上述MTJ位元和一个上述驱动器组20中的一个上述驱动器200。
上述驱动器200为MOSFET，上述MOSFET包括源极、栅极和漏极，上述源极线70与上述源极一一对应地电连接，两个字线分别为第一字线81和第二字线82，其中第一字线81与第一驱动器组21中的各第一驱动器210的上述栅极电连接，第二字线82与第二驱动器组22中的各第二驱动器220的上述栅极电连接，上述位线90与上述MTJ位元60一一对应地电连接，且通过第七通孔47与顶电极63电连接。
实施例2
如图3所示，与实施例1不同之处在于：第一驱动器210在上述衬底10上的投影与对应的第二驱动器220在上述衬底10上的投影一一对应重合，即全部重合。
该磁性随机存储器还包括第八通孔组和一个驱动互连组50，第八通孔组包括多个间隔设置的且相同的第八通孔48，各第八通孔48位于各第一驱动器210的远离上述衬底10的表面上，上述驱动互连组50位于上述隔离介质层30中，上述驱动互连组50包括多个沿上述第一方向间隔设置的且相同的驱动互连金属部500，上述驱动互连组50中的上述驱动互连金属部500用于一一对应地电连接上述第一通孔41和上述第八通孔48，从而电连接MTJ位元60与第一驱动器210。
从以上的描述中，可以看出，本公开上述的实施例实现了如下技术效果：
本公开的磁性随机存储器中通过设置多个堆叠的驱动器组，且相邻的驱动器组中的驱动器在衬底表面上的投影具有重合的部分，这样相对于现有技术来说，通过在垂直空间上分层排布驱动器，使驱动器在垂直方向上的面密度获得提升，从而相对应的MTJ存储位元的面密度也获得相应提升，最终使得磁性随机存储器的存储密度相对于现有技术有提升。并且，在提升存储密度的同时，并没有增加最具挑战性的MTJ存储位元的加工难度，使该高密度磁性随机存储器的制作工艺简单且制造成本低。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (10)

  1. 一种磁性随机存储器，其特征在于，所述磁性随机存储器包括：
    衬底(10)；
    多个驱动器组(20)，各所述驱动器组(20)位于所述衬底(10)的表面上，多个所述驱动器组(20)沿远离所述衬底(10)的方向依次设置，各所述驱动器组(20)包括一个或者多个沿第一方向间隔设置的驱动器(200)，一个所述驱动器组(20)中的各所述驱动器(200)的中心与所述衬底(10)的距离相同，各所述驱动器组(20)中的至少一个所述驱动器(200)在所述衬底(10)上的投影与相邻的所述驱动器组(20)中的至少一个所述驱动器(200)在所述衬底(10)表面的投影有重叠，多个所述驱动器组(20)中，与所述衬底(10)之间距离最大的所述驱动器组(20)为顶层驱动器组，所述第一方向与所述衬底(10)的厚度方向垂直；
    多个沿所述第一方向间隔设置的MTJ位元(60)，位于所述顶层驱动器组的远离所述衬底(10)的一侧，一个或者多个所述MTJ位元(60)与一个或者多个所述驱动器(200)对应电连接。
  2. 根据权利要求1所述的磁性随机存储器，其特征在于，各所述驱动器组(20)包括多个相同的所述驱动器(200)，各所述驱动器组(20)中的所述驱动器(200)在所述衬底(10)上的投影与相邻的所述驱动器组(20)中的所述驱动器(200)在所述衬底(10)上的投影一一对应有重叠，所述驱动器(200)与所述MTJ位元(60)一一对应地电连接，且在所述衬底(10)上的投影一一对应有重叠的两个所述驱动器(200)对应电连接的两个所述MTJ位元(60)相邻。
  3. 根据权利要求2所述的磁性随机存储器，其特征在于，所述各所述驱动器组(20)中的所述驱动器(200)在所述衬底(10)上的投影与相邻的所述驱动器组(20)中的所述驱动器(200)在所述衬底(10)上的投影一一对应重合。
  4. 根据权利要求1所述的磁性随机存储器，其特征在于，所述磁性随机存储器还包括多个隔离介质层(30)，各所述隔离介质层(30)设置在所述衬底(10)的表面上，且多个所述隔离介质层(30)沿着远离所述衬底(10)的方向依次叠置设置，各所述驱动器组(20)位于至少一个所述隔离介质层(30)中，多个MTJ位元(60)至少位于一个所述隔离介质层(30)中。
  5. 根据权利要求4所述的磁性随机存储器，其特征在于，所述磁性随机存储器还包括多个通孔组(40)，各所述通孔组(40)包括至少一个通孔，至少两个所述通孔组(40)中的所述通孔的高度不同，各所述通孔位于所述隔离介质层(30)中，多个所述通孔组(40)中的至少部分与所述驱动器组(20)一一对应，与所述驱动器组(20)对应的一个所述通孔组(40)中的所述通孔用于电连接一个所述MTJ位元(60)和一个所述驱动器组(20)中的一个所述驱动器(200)。
  6. 根据权利要求5所述的磁性随机存储器，其特征在于，所述磁性随机存储器包括至少一个驱动互连组(50)，所述驱动互连组(50)位于所述隔离介质层(30)中，所述驱动互连组(50)包括多个沿所述第一方向间隔设置的驱动互连金属部(500)，至少有一个所述驱动互连组(50)中的所述驱动互连金属部(500)用于一一对应地电连接所述通孔和所述驱动器(200)。
  7. 根据权利要求1至6中任一项所述的磁性随机存储器，其特征在于，所述驱动器组(20)有两个，分别为第一驱动器组(21)和第二驱动器组(22)，所述第一驱动器组(21)位于所述衬底(10)的表面上，所述第二驱动器组(22)位于所述第一驱动器组(21)的远离所述衬底(10)的一侧，所述第一驱动器组(21)包括多个第一驱动器(210)，所述第二驱动器组(22)包括多个第二驱动器(220)。
  8. 根据权利要求1至6中任一项所述的磁性随机存储器，其特征在于，所述驱动器(200)为MOSFET，所述MOSFET包括源极、栅极和漏极，所述磁性随机存储器还包括多个间隔设置的源极线(70)、多个间隔设置的字线(80)和多个间隔设置的位线(90)，所述源极线(70)与所述源极一一对应地电连接，所述字线(80)与所述驱动器组(20)一一对应，一个所述字线(80)与所述驱动器组(20)的各所述驱动器(200)的所述栅极电连接，所述位线(90)与所述MTJ位元(60)一一对应地电连接。
  9. 根据权利要求1至6中任一项所述的磁性随机存储器，其特征在于，各所述MTJ位元(60)在所述衬底(10)表面上的投影位于对应电连接的所述驱动器(200)在所述衬底(10)表面上的投影的内部，各所述MTJ位元(60)位于包括依次叠置设置的底电极、自由磁性层、绝缘层、固定磁性层以及顶电极。
  10. 根据权利要求5所述的磁性随机存储器，其特征在于，所有用于电连接所述MTJ位元(60)和所述驱动器(200)的所述通孔的电阻值相等。
PCT/CN2019/110672 2018-10-12 2019-10-11 磁性随机存储器 WO2020073995A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811191866.XA CN111048130B (zh) 2018-10-12 2018-10-12 磁性随机存储器
CN201811191866.X 2018-10-12

Publications (1)

Publication Number Publication Date
WO2020073995A1 true WO2020073995A1 (zh) 2020-04-16

Family

ID=70164460

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/110672 WO2020073995A1 (zh) 2018-10-12 2019-10-11 磁性随机存储器

Country Status (2)

Country Link
CN (1) CN111048130B (zh)
WO (1) WO2020073995A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112259574B (zh) * 2020-10-21 2024-04-16 浙江驰拓科技有限公司 一种存储器件及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1469386A (zh) * 2002-02-22 2004-01-21 ��ʽ���綫֥ 磁随机存取存储器
CN1543651A (zh) * 2001-08-17 2004-11-03 �ʼҷ����ֵ��ӹɷ����޹�˾ 存储器电路
CN104081463A (zh) * 2011-12-22 2014-10-01 英特尔公司 带有具有两个堆叠的磁性隧道结(mtj)部件的元件的存储器
US20180102365A1 (en) * 2016-10-11 2018-04-12 Imec Vzw Memory device for a dynamic random access memory

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6940748B2 (en) * 2002-05-16 2005-09-06 Micron Technology, Inc. Stacked 1T-nMTJ MRAM structure
JP2011023476A (ja) * 2009-07-14 2011-02-03 Toshiba Corp 磁気記憶装置
KR20130068144A (ko) * 2011-12-15 2013-06-25 에스케이하이닉스 주식회사 적층형 메모리 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1543651A (zh) * 2001-08-17 2004-11-03 �ʼҷ����ֵ��ӹɷ����޹�˾ 存储器电路
CN1469386A (zh) * 2002-02-22 2004-01-21 ��ʽ���綫֥ 磁随机存取存储器
CN104081463A (zh) * 2011-12-22 2014-10-01 英特尔公司 带有具有两个堆叠的磁性隧道结(mtj)部件的元件的存储器
US20180102365A1 (en) * 2016-10-11 2018-04-12 Imec Vzw Memory device for a dynamic random access memory

Also Published As

Publication number Publication date
CN111048130B (zh) 2022-03-04
CN111048130A (zh) 2020-04-21

Similar Documents

Publication Publication Date Title
TWI731796B (zh) 半導體記憶體
US12119336B2 (en) Fusion memory device and method of fabricating the same
WO2022007571A1 (zh) 显示装置及其制作方法
JP2019057660A (ja) メモリデバイス
JP7341810B2 (ja) 半導体記憶装置
US8953361B2 (en) Stack memory apparatus
JP5606479B2 (ja) 半導体記憶装置
CN105762135A (zh) 具有不同厚度的堆叠金属层
CN107533859B (zh) 源极线布局与磁隧道结（mtj）存储器位单元中的存取晶体管接触布置的解耦以促进减小的接触电阻
JP2003209222A (ja) 大記憶容量のための３−ｄメモリ素子
CN112119458B (zh) 存储器装置的通道路由
CN107863122A (zh) 三维存储器控制电路
JP2003007977A (ja) 交点ダイオードメモリアレイをアドレス指定するための回路製造技術
JP2015082564A (ja) メモリセル構造、メモリ製造方法、メモリ装置
TWI409812B (zh) 對稱旋轉轉移力矩磁阻隨機存取記憶體位元單元設計
TWI285410B (en) Interlayer interconnect of three-dimensional memory and method for manufacturing the same
CN106104790A (zh) 磁阻存储器件
TW201715647A (zh) 以互補金氧半導體驅動電路實施磁性記憶體整合
WO2020073995A1 (zh) 磁性随机存储器
US9312241B2 (en) Semiconductor device
WO2024103744A1 (zh) Oled显示面板和oled显示装置
TWI381385B (zh) 具有嵌入式多類型記憶體的記憶體結構
TW202339167A (zh) 半導體記憶裝置
TWI788736B (zh) 積體電路和電子設備
WO2021036676A1 (zh) 阵列基板、显示面板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19870419

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19870419

Country of ref document: EP

Kind code of ref document: A1