WO2020073474A1 - Tft阵列基板的制作方法 - Google Patents

Tft阵列基板的制作方法 Download PDF

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Publication number
WO2020073474A1
WO2020073474A1 PCT/CN2018/120399 CN2018120399W WO2020073474A1 WO 2020073474 A1 WO2020073474 A1 WO 2020073474A1 CN 2018120399 W CN2018120399 W CN 2018120399W WO 2020073474 A1 WO2020073474 A1 WO 2020073474A1
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Prior art keywords
layer
photoresist
edge
pattern
array substrate
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Ceased
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PCT/CN2018/120399
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English (en)
French (fr)
Inventor
刘晓娣
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US16/319,349 priority Critical patent/US11087985B2/en
Publication of WO2020073474A1 publication Critical patent/WO2020073474A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
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    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
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    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
    • H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
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    • H10P50/00—Etching of wafers, substrates or parts of devices
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    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
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    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
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Definitions

  • the invention relates to the field of display technology, in particular to a TFT Array substrate manufacturing method.
  • LCD liquid crystal displays
  • AMOLED active matrix driven organic electroluminescence
  • LCD liquid crystal displays
  • AMOLED active matrix driven organic electroluminescence
  • the substrate is currently LCD Device and AMOLED
  • the main components in the device are directly related to the development direction of the high-performance flat panel display device, which is used to provide a driving circuit to the display.
  • a plurality of pixel units are defined by the data lines.
  • Each pixel unit is provided with a thin film transistor and a pixel electrode.
  • the gate of the thin film transistor is connected to the corresponding scan line.
  • the electrode and the drain are turned on, thereby inputting the data voltage on the data line to the pixel electrode, thereby controlling the display of the corresponding pixel area.
  • the active layer may include a channel layer 14 , Contact layer 15 ;
  • the second mask in this example is a grayscale mask, as shown in the figure 1
  • the gray scale photomask has light-shielding source and drain patterns twenty two And semi-transparent channel pattern twenty three , Using the gray scale photomask to resist the photoresist layer 17 Exposure development; first wet etching, patterning the source and drain layers 16 , Corresponding to the source-drain pattern twenty two And channel pattern twenty three , Forming the metal wire structure of the source and drain regions and the active region; the first dry etching corresponds to the source and drain patterns twenty two And channel pattern twenty three , Forming an active layer island structure, that is, a patterned channel layer 14 , Contact layer 15 ; Oxygen ashing reduces the photoresist layer 17 Thickness to expose the source-drain layer of the channel region 16 ; The second wet etching, patterning the source and drain; the second dry etching, etching the active layer, that is, etching the open channel layer 14 ,
  • a transparent electrode layer is prepared, and the transparent electrode layer is patterned.
  • the second layer of metal present in the process has amorphous silicon (channel layer) 14 ) And heavily doped silicon (contact layer 15 ) Residual problems, an urgent need for an optimization 4M Processed TFT Array preparation method.
  • the object of the present invention is to provide a TFT
  • the manufacturing method of the array substrate makes the semiconductor layer on the edge of the metal wire structure easy to be etched by thinning the edge of the photoresist layer, thereby reducing the problem of tailing of the active layer at the source and drain edges.
  • the present invention provides a TFT
  • the manufacturing method of the array substrate includes the following steps:
  • step S1 Providing a base substrate, forming a gate, a gate insulating layer, a semiconductor layer, and a source-drain metal layer on the base substrate;
  • step S2 Provide a semi-transparent photomask, coat a photoresist material on the source-drain metal layer, and expose and develop the photoresist material using the translucent photomask, to obtain a photoresist layer It includes a first photoresist pattern, a second photoresist pattern and a third photoresist pattern that are spaced apart from each other; the first photoresist pattern, the second photoresist pattern and the third photoresist pattern all include a middle part and two parts located in the middle part Side edge portion; the middle portion of the first photoresist pattern is further provided with a groove; the thickness of the edge portion is less than the thickness of the middle portion; the middle portion corresponds to a source and drain formed subsequently; the edge portion corresponds A semiconductor layer on the edge of the metal wire structure formed subsequently; the groove corresponds to the channel formed subsequently;
  • step S3 Perform the first wet etching to form a metal wire structure from the source-drain metal layer;
  • step S4 Perform the first dry etching to form the active layer structure from the semiconductor layer
  • step S5 Ashing the photoresist layer to reduce the thickness of the photoresist layer until the groove exposes the metal wire structure
  • step S6 Perform a second wet etching to form a source and drain from the metal wire structure
  • step S7 Perform the second dry etching to form a channel on the active layer structure to obtain the active layer and form TFT structure.
  • the semi-transparent photomask has a first figure, a second figure and an edge figure, wherein the second figure is continuous with the first figure, and the edge figure is continuously arranged along the edge of the first figure;
  • the steps S2 The photoresist material provided in is a positive photoresist material, the first pattern of the semi-transparent photomask is an opaque area, and the second pattern and the edge pattern are semi-transparent areas.
  • the semi-transparent mask is a half-tone mask.
  • the translucent mask is a gray-scale mask, and the light transmittance of the edge pattern of the translucent mask is 30% -50% .
  • the middle part of the photoresist layer formed in the embodiment has two or more connected photoresist strips, and the portion of the semi-transparent photomask corresponding to the connection between two adjacent photoresist strips is a first pattern or an edge pattern.
  • the steps S3 It also includes, after the first wet etching and before the first dry etching, performing an ashing process on the photoresist layer to reduce the width of the photoresist layer so that the semiconductor layer on the edge of the metal wire structure Easy to be etched;
  • the steps S6 It also includes, after the second wet etching and before the second dry etching, performing an ashing process on the photoresist layer to reduce the width of the photoresist layer so that the semiconductor layer on the edge of the metal wire structure Easy to be etched.
  • the semiconductor layer includes a channel layer and a contact layer provided on the channel layer.
  • the channel layer and the contact layer are formed by plasma enhanced chemical vapor deposition, sol-gel, sputtering, or atomic layer deposition.
  • the material of the channel layer and the contact layer is amorphous silicon or metal oxide semiconductor.
  • the steps S5 Obtained in TFT The structure is the display area or GOA Regional TFT structure.
  • TFT The manufacturing method of the array substrate is relative to the existing 4M
  • a reduced thickness edge portion is formed at the edge of the photoresist layer used to pattern the source and drain metal layers and the semiconductor layer, so that the edge of the photoresist layer is thinned, thereby making
  • the width of the photoresist layer is easy to be reduced in the subsequent manufacturing process, so that the semiconductor layer at the edge of the metal wire structure is easily etched during dry etching, reducing the problem of tailing of the active layer at the source and drain edges, and obtaining a finer metal wire structure
  • Optical stability and electrical performance, aperture ratio, reliability and the purpose of reducing power consumption improve TFT
  • the overall performance of the array substrate can solve or reduce the residual problem of amorphous silicon and heavily doped silicon at the source and drain edges based on the original manufacturing process.
  • Fig 1 For existing 4M Schematic diagram of the planar structure of the semi-transmissive mask used to form the source-drain and active layers in the manufacturing process;
  • Fig 3 For the present invention TFT Schematic diagram of the first planar structure of the semi-transparent photomask used in the manufacturing method of the array substrate;
  • Fig 4 For the present invention TFT Schematic diagram of the second planar structure of the semi-transparent mask used in the manufacturing method of the array substrate;
  • TFT A schematic diagram of a process for forming a source-drain and an active layer in a preferred embodiment of a method for manufacturing an array substrate
  • Fig 6 For the present invention TFT Schematic diagram of the manufacturing method of the array substrate.
  • the manufacturing method of the array substrate includes the following steps:
  • step S1 Provide substrate 10 , In the base substrate 10 Forming gate 20 ⁇ Gate insulation 30 Semiconductor layer 40 Source-drain metal layer 50 .
  • step S2 ⁇ Provide semi-transparent mask 90 , In the source-drain metal layer 50 Coat a photoresist material on it and use the semi-transmissive mask 90 Expose and develop the photoresist material to obtain a photoresist layer 80 , The photoresist layer 80 Including the first photoresist pattern 81 2. Second photoresist pattern 82 And the third photoresist pattern 83 ; The first photoresist pattern 81 2.
  • Second photoresist pattern 82 And the third photoresist pattern 83 Both include the middle 811 And in the middle 811 Edges on both sides 812 ;
  • the first photoresist pattern 81 Middle of 811 There are also grooves 813 ;
  • the edge 812 The thickness is less than the middle 811 The thickness of the middle part 811 Corresponding to the subsequently formed source and drain 55 ;
  • the groove 813 Corresponding to the subsequently formed channel; that is, through the semi-transparent mask 90 So that the photoresist layer 80 Thinning of the edges, making the photoresist layer 80
  • the width of is easy to be reduced in the subsequent process, which makes the metal wire structure 54 Edge semiconductor layer 40 It is easy to be etched by plasma during dry etching.
  • step S3 Perform the first wet etching by the source-drain metal layer 50 Form a metal wire structure 54 .
  • step S4 ⁇ For the first dry etching, the semiconductor layer 40 Formation of active layer structure 44 .
  • step S5 The photoresist layer 80 Perform ashing treatment to thin the photoresist layer 80 Thickness up to the groove 813 Exposed metal wire structure 54 .
  • step S6 Perform the second wet etching by the metal wire structure 54 Form source and drain 55 .
  • step S7 Second dry etching, in the active layer structure 44 Forming a channel on the active layer 45 ,form TFT structure.
  • the invention specifically relates to an optimized 4M Process technology backplane development, can be used to include the display area and GOA Circuit area TFT Array development and circuit performance optimization.
  • the steps S1 The first mask process is used to pattern the gate 20 .
  • the steps S2 Translucent mask used in 90
  • the steps S2 To step S7 Belongs to the second photomask process patterned semiconductor layer 40
  • Source-drain metal layer 50 To form an active layer 45
  • Source and drain 55 The invention TFT Array substrate manufacturing method, further including steps S8 , Forming a cover TFT
  • the passivation layer of the structure is formed by exposing the source and drain through patterning the passivation layer through the third photomask process 55 Contact vias; steps S9 , A transparent electrode layer is formed on the passivation layer, and a pixel electrode is formed by patterning the transparent electrode layer through the fourth photomask process 55 contact.
  • the gate 20 It can be prepared by sputtering, sol-gel, atomic layer deposition, evaporation, printing, etc.
  • the material can be Cu , Cu / Mo , Mo / Cu / Mo , MoNb / Cu / MoNb , Ti / Cu / Ti , Al , Al / Mo , Mo / Al / Mo Equal electrode materials.
  • the gate insulating layer 30 It can be formed by dielectric materials such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, and hafnium oxide prepared by plasma chemical vapor deposition, atmospheric pressure chemical vapor deposition, and sputtering.
  • the semiconductor layer 40 May include a channel layer 41 And provided in the channel layer 41 Contact layer 42 ,
  • the channel layer 41 And contact layer 42 It is made by plasma enhanced chemical vapor deposition, sol-gel, sputtering or atomic layer deposition.
  • the channel layer 41 And contact layer 42 The material is amorphous silicon or metal oxide semiconductor, such as IGZO , IZO , ITZO Channel layer 41 And contact layer 42 .
  • passivation layer deposition contact via etching and transparent electrode layers such as ITO For lead-out, etc.
  • transparent electrode layers such as ITO For lead-out, etc.
  • the edges are set continuously; the steps S2 In the first graphic 91 , Second graphics 92 And edge graphics 93 Used to form the middle part 811 , Groove 813 And the edge 812 .
  • the photoresist material provided in is a positive photoresist material
  • the translucent photomask 90 The first graphic 91 Is an opaque area, the second pattern 92 And edge graphics 93 It is a semi-transparent area.
  • the part of the present invention that optimizes the existing process mainly lies in that 80 Structural design, used to pattern the source and drain metal layers 50 And semiconductor layer 40 Photoresist layer 80 Of the edges form a reduced thickness edge 812 So that the photoresist layer 80 Thinning of edges to reduce source and drain 55 Edge active layer 45 The problem of tailing.
  • 80 Shown is the semi-transparent mask of the present invention 80 Schematic diagram of the first planar structure of the first type 90 The corresponding photoresist layer is formed 80 Middle of 811 The part where the two adjacent light-resisting strips are connected is still the opaque first pattern 91 .
  • the translucent reticle of the second structure 90 The corresponding photoresist layer is formed 80 Middle of 811
  • the part where the two adjacent photoresist strips are connected can also be a semi-transparent edge pattern 93 , Then by forming the first photoresist pattern 81 Adjust process conditions so that the first photoresist pattern 81 At this connection is still a connection structure.
  • the translucent light mask 90 It specifically relates to the above two structures but is not limited to the above two structures.
  • the translucent reticle 90 A gray scale mask can be used, and the semi-transparent mask 90 Upper edge graphics 93 The transmittance of 30% -50% .
  • the semi-transparent mask 90 Half-tone masks can also be used.
  • a schematic diagram of a process for forming a source-drain and an active layer in a preferred embodiment of a method for manufacturing an array substrate shows a second photomask process, which is the part of the present invention optimized for the existing process.
  • the first mask process is the step before the second mask process S1 In the base substrate 10 Deposited and patterned on top 20 , And then prepare the gate insulating layer 30 Semiconductor layer 40 Source-drain metal layer 50 . Then, perform the steps in applying the optimized grayscale mask S2 To step S7
  • the second mask process is the step before the second mask process S1 In the base substrate 10 Deposited and patterned on top 20 .
  • the gate insulating layer 30 Semiconductor layer 40 Source-drain metal layer 50 .
  • step S2 Translucent reticle with gray scale reticle 90 , Using the translucent mask 90 Expose and develop the photoresist material to obtain a photoresist layer 80 ,
  • the photoresist layer 80 Includes continuous first photoresist pattern 81 2.
  • Second photoresist pattern 82 And the third photoresist pattern 83 Both include the middle 811 And in the middle 811 Edges on both sides 812 ;
  • the first photoresist pattern 81 Middle of 811 There are also grooves 813 ;
  • the edge 812 The thickness is less than the middle 811 The thickness of the middle part 811 Corresponding to the subsequently formed source and drain 55 ;
  • the groove 813 Corresponding to the subsequently formed channel; that is, by changing the semi-transparent mask 90
  • the structure design makes the photoresist layer 80 Thinning of the edges, so that the photoresist layer 80 The width of is easy to be reduced in the subsequent process, which makes the metal wire structure 54 Edge semiconductor layer 40 Easily etched by plasma during dry etching, reducing source and drain 55
  • Edge active layer 45 The problem of tailing, to obtain a finer metal wire structure, to achieve improvement TFT Optical stability and electrical
  • step S3 Perform the first wet etching by the source-drain metal layer 50 Form a metal wire structure 54 ; Then on the photoresist layer 80 Perform ashing treatment.
  • step S4 ⁇ For the first dry etching, the semiconductor layer 40 Formation of active layer structure 44 .
  • the photoresist layer 80 Performing ashing treatment to further reduce the photoresist layer 80 The width of the metal wire structure 54 Edge semiconductor layer 40 Easy to be etched.
  • step S5 The photoresist layer 80 Perform ashing treatment to thin the photoresist layer 80 Thickness up to the groove 813 Exposed metal wire structure 54 .
  • step S6 Perform the second wet etching by the metal wire structure 54 Form source and drain 55 ; Then on the photoresist layer 80 Perform ashing treatment.
  • step S7 Second dry etching, in the active layer structure 44 Forming a channel on the active layer 45 ,form TFT structure. Therefore, after the second wet etching and before the second dry etching, the photoresist layer 80 Performing ashing treatment to further reduce the photoresist layer 80 The width of the metal wire structure 54 Edge semiconductor layer 40 Easy to be etched.
  • the present invention TFT Array substrate manufacturing method is available 4M
  • a reduced thickness edge portion is formed at the edge of the photoresist layer used to pattern the source and drain metal layers and the semiconductor layer, so that the edge of the photoresist layer is thinned, thereby making
  • the width of the photoresist layer is easy to be reduced in the subsequent manufacturing process, so that the semiconductor layer at the edge of the metal wire structure is easily etched during dry etching, reducing the problem of tailing of the active layer at the source and drain edges, and obtaining a finer metal wire structure
  • TFT Optical stability and electrical performance, aperture ratio, reliability and the purpose of reducing power consumption, improve TFT
  • the overall performance of the array substrate can solve or reduce the residual problem of amorphous silicon and heavily doped silicon at the source and drain edges based on the original manufacturing process.

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  • Thin Film Transistor (AREA)
  • Chemical & Material Sciences (AREA)
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Abstract

一种TFT阵列基板的制作方法。相对于现有4M制程，通过改变半透光光罩（90）的结构设计，在用于图形化源漏极金属层（50）和半导体层（40）的光阻层（80）的边缘形成厚度减小的边缘部（812），使得光阻层（80）边缘薄化，从而使得光阻层（80）的宽度在后续制程中易于缩减，进而使得金属导线结构（54）边缘的半导体层（40）易于在干刻时被蚀刻，减轻源漏极（55）边缘有源层（45）拖尾的问题，获得更为精细的金属导线结构（54），达到提高TFT光学稳定性和电学性能、开口率、可靠性以及减低功耗的目的，提高TFT阵列基板的整体性能，可以在现有4M制程基础上，解决或减少源漏极（55）边缘存在不定形硅和重掺杂硅的残留问题。

Description

TFT阵列基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种 TFT 阵列基板的制作方法。
背景技术
在显示技术领域，液晶显示器（ LCD ）和有源矩阵驱动式有机电致发光（ AMOLED ）显示器等平板显示装置因具有机身薄、高画质、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理（ PDA ）、数字相机、计算机屏幕或笔记本屏幕等。
薄膜晶体管（ TFT ）阵列（ Array ）基板是目前 LCD 装置和 AMOLED 装置中的主要组成部件，直接关系到高性能平板显示装置的发展方向，用于向显示器提供驱动电路，薄膜晶体管阵列基板通常设置有数条扫描线和数条数据线，该数条扫描线和数条数据线限定出多个像素单元，每个像素单元内设置有薄膜晶体管和像素电极，薄膜晶体管的栅极与相应的扫描线相连，当扫描线上的电压达到开启电压时，薄膜晶体管的源极和漏极导通，从而将数据线上的数据电压输入至像素电极，进而控制相应像素区域的显示。
在半导体生产的量产线中，曝光（ Photo ）设备是最核心、最昂贵的设备，因此量产产线的生产产能都是依据曝光设备而定，并且过多使用光罩（ Mask ）进行曝光会增加制程成本，同时也会增大单件工时（ Tact Time ），使生产效率大大降低，所以在半导体行业发展的过程中，节省使用光罩进行的曝光次数，提升产能，降低成本成为主要推进技术发展的需求。在 TFT 阵列基板的制作工艺中，四道光罩（ 4M ）工艺代替五道光罩（ 5M ）工艺为业内研发和制程趋势。在 4M 制程中存在第二层金属边缘有不定形硅和重掺杂硅残留问题，第二层金属即源漏极层金属。该问题影响 TFT 光学稳定性和电学性能，开口率，功耗和可靠性，这是由于其采用如图 1 所示的半色调光罩（ HTM ）或灰阶光罩（ GTM ）曝光图形化过程引起。
参见图 2 ，其为现有 4M 制程示意图，显示了现有 4M 制程中的第二道光罩制程。现有 4M 制程一般包括：
在第一道光罩制程中，在玻璃基板 11 上制备栅极层 12 ，并图形化栅极层 12 ；然后制备栅极绝缘层 13 、有源层、源漏极层 16 、光刻胶层 17 ，有源层可以包括沟道层 14 、接触层 15 ；
在第二道光罩制程中，此示例中第二道光罩为灰阶光罩，如图 1 所示，该灰阶光罩具有遮光的源漏极图形 22 和半透光的沟道区图形 23 ，利用该灰阶光罩对光刻胶层 17 进行曝光显影；第一次湿刻，图形化源漏极层 16 ，对应源漏极图形 22 和沟道区图形 23 ，形成源漏极区域和有源区域的金属导线结构；第一次干刻，对应源漏极图形 22 和沟道区图形 23 ，形成有源层岛状结构，也就是图形化沟道层 14 、接触层 15 ；氧气灰化，降低光刻胶层 17 厚度以露出沟道区域的源漏极层 16 ；第二次湿刻，图形化源漏极；第二次干刻，刻蚀有源层，也就是刻蚀开沟道层 14 、接触层 15 ，形成薄膜晶体管结构；
在第三道光罩制程中，制备钝化层，并图案化钝化层；
在第四道光罩制程中，制备透明电极层，并图案化透明电极层。
针对现有 4M 制程中存在的第二层金属边缘有不定形硅（沟道层 14 ）和重掺杂硅（接触层 15 ）残留的问题，亟需一种优化 4M 制程的 TFT 阵列制备方法。
技术问题
本发明的目的在于提供一种 TFT 阵列基板的制作方法，通过减薄光阻层的边缘，使得金属导线结构边缘的半导体层易于被蚀刻，从而减轻源漏极边缘有源层拖尾的问题。
技术解决方案
为实现上述目的，本发明提供一种 TFT 阵列基板的制作方法，包括如下步骤：
步骤 S1 、提供衬底基板，在所述衬底基板上形成栅极、栅极绝缘层、半导体层及源漏极金属层；
步骤 S2 、提供一半透光光罩，在所述源漏极金属层上涂布光阻材料，利用所述半透光光罩对光阻材料进行曝光，显影，得到光阻层，所述光阻层包括相互间隔的第一光阻图形、第二光阻图形及第三光阻图形；所述第一光阻图形、第二光阻图形及第三光阻图形均包括中间部以及位于中间部两侧的边缘部；所述第一光阻图形的中间部还设有凹槽；所述边缘部的厚度小于中间部的厚度；所述中间部对应后续形成的源漏极；所述边缘部对应后续形成的金属导线结构边缘的半导体层；所述凹槽对应后续形成的沟道；
步骤 S3 、进行第一次湿刻，由所述源漏极金属层形成金属导线结构；
步骤 S4 、进行第一次干刻，由半导体层形成有源层结构；
步骤 S5 、对所述光阻层进行灰化处理，减薄光阻层的厚度直至凹槽暴露出金属导线结构；
步骤 S6 、进行第二次湿刻，由所述金属导线结构形成源漏极；
步骤 S7 、进行第二次干刻，在有源层结构上形成沟道，得到有源层，形成 TFT 结构。
所述半透光光罩具有第一图形、第二图形及边缘图形，其中，所述第二图形与第一图形相连续，所述边缘图形沿着第一图形的边缘连续设置；
所述步骤 S2 中，所述第一图形、第二图形和边缘图形分别用于对应形成中间部、凹槽和边缘部；
所述步骤 S2 中提供的光阻材料为正型光阻材料，所述半透光光罩的第一图形为不透光区域，所述第二图形和边缘图形为半透光区域。
所述半透光光罩为半色调光罩。
所述半透光光罩为灰阶光罩，所述半透光光罩的边缘图形的透光率为 30%-50% 。
所述步骤 S2 中形成的光阻层的中间部具有两条或以上的相连接的光阻条，所述半透光光罩在对应形成相邻两光阻条连接处的部分为第一图形或边缘图形。
所述步骤 S3 还包括，在第一次湿刻之后和在第一次干刻之前，对所述光阻层进行灰化处理，以缩减所述光阻层的宽度，使得所述金属导线结构边缘的半导体层易于被蚀刻；
所述步骤 S6 还包括，在第二次湿刻之后并在第二次干刻之前，对所述光阻层进行灰化处理，以缩减所述光阻层的宽度，使得所述金属导线结构边缘的半导体层易于被蚀刻。
所述半导体层包括沟道层和设于所述沟道层上的接触层。
所述沟道层和接触层通过等离子体增强型化学气相沉积、溶胶凝胶、溅射或原子层沉积的方法制作形成。
所述沟道层和接触层的材料为非晶硅或金属氧化物半导体。
所述步骤 S5 中得到的 TFT 结构为显示区域或 GOA 区域的 TFT 结构。
有益效果
本发明的有益效果：本发明的 TFT 阵列基板的制作方法相对于现有 4M 制程，通过改变半透光光罩的结构设计，在用于图形化源漏极金属层和半导体层的光阻层的边缘形成厚度减小的边缘部，使得光阻层边缘薄化，从而使得光阻层的宽度在后续制程中易于缩减，进而使得金属导线结构边缘的半导体层易于在干刻时被蚀刻，减轻源漏极边缘有源层拖尾的问题，获得更为精细的金属导线结构，达到提高 TFT 光学稳定性和电学性能、开口率、可靠性以及减低功耗的目的，提高 TFT 阵列基板的整体性能，可以在原制程基础上，解决或减少源漏极边缘存在不定形硅和重掺杂硅的残留问题。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图 1 为现有 4M 制程中用于形成源漏极和有源层的半透光光罩的平面结构示意图；
图 2 为现有 4M 制程中形成源漏极和有源层的制程示意图；
图 3 为本发明 TFT 阵列基板的制作方法中所使用的半透光光罩的第一种平面结构示意图；
图 4 为本发明 TFT 阵列基板的制作方法中所使用的半透光光罩的第二种平面结构示意图；
图 5 为本发明 TFT 阵列基板的制作方法的一优选实施例中形成源漏极和有源层的制程示意图；
图 6 为本发明 TFT 阵列基板的制作方法的流程示意图。
本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图 6 ，本发明提供一种 TFT 阵列基板的制作方法，包括如下步骤：
步骤 S1 、提供衬底基板 10 ，在所述衬底基板 10 上形成栅极 20 、栅极绝缘层 30 、半导体层 40 及源漏极金属层 50 。
步骤 S2 、提供一半透光光罩 90 ，在所述源漏极金属层 50 上涂布光阻材料，利用所述半透光光罩 90 对光阻材料进行曝光，显影，得到光阻层 80 ，所述光阻层 80 包括第一光阻图形 81 、第二光阻图形 82 及第三光阻图形 83 ；所述第一光阻图形 81 、第二光阻图形 82 及第三光阻图形 83 均包括中间部 811 以及位于中间部 811 两侧的边缘部 812 ；所述第一光阻图形 81 的中间部 811 还设有凹槽 813 ；所述边缘部 812 的厚度小于中间部 811 的厚度；所述中间部 811 对应后续形成的源漏极 55 ；所述边缘部 812 对应后续形成的金属导线结构 54 边缘的半导体层 40 ；所述凹槽 813 对应后续形成的沟道；即通过半透光光罩 90 使得所述光阻层 80 的边缘薄化，从而使得光阻层 80 的宽度在后续制程中易于缩减，进而使得金属导线结构 54 边缘的半导体层 40 易于在干刻时被等离子体蚀刻。
步骤 S3 、进行第一次湿刻，由所述源漏极金属层 50 形成金属导线结构 54 。
步骤 S4 、进行第一次干刻，由半导体层 40 形成有源层结构 44 。
步骤 S5 、对所述光阻层 80 进行灰化处理，减薄光阻层 80 的厚度直至凹槽 813 暴露出金属导线结构 54 。
步骤 S6 、进行第二次湿刻，由所述金属导线结构 54 形成源漏极 55 。
步骤 S7 、进行第二次干刻，在有源层结构 44 上形成沟道，得到有源层 45 ，形成 TFT 结构。
本发明具体涉及一种优化的 4M 制程工艺背板开发，可用于包括显示区和 GOA 电路区 TFT 阵列开发以及电路性能优化。
具体地，所述步骤 S1 中采用第一道光罩制程图案化形成所述栅极 20 。所述步骤 S2 中所使用的半透光光罩 90 为第二道光罩，所述步骤 S2 至步骤 S7 属于第二道光罩制程图案化半导体层 40 及源漏极金属层 50 以形成有源层 45 和源漏极 55 。本发明的 TFT 阵列基板的制作方法，还包括步骤 S8 ，形成覆盖 TFT 结构的钝化层，通过第三道光罩制程图案化钝化层形成暴露出源漏极 55 的接触过孔；步骤 S9 ，在所述钝化层上形成透明电极层，通过第四道光罩制程图案化透明电极层形成像素电极，该像素电极通过接触过孔与源漏极 55 接触。
具体地，所述栅极 20 可通过溅射、溶胶凝胶、原子层沉积、蒸发、打印等方式制备，其材料可以为 Cu 、 Cu/Mo 、 Mo/Cu/Mo 、 MoNb/Cu/MoNb 、 Ti/Cu/Ti 、 Al 、 Al/Mo 、 Mo/Al/Mo 等电极材料。
具体地，所述栅极绝缘层 30 可通过采用等离子体化学气相沉积、常压化学气相沉积、溅射等方法制备的氮化硅、氧化硅、氮氧化硅、氧化铝、氧化铪等介质材料形成。
具体地，所述半导体层 40 可包括沟道层 41 和设于所述沟道层 41 上的接触层 42 ，所述沟道层 41 和接触层 42 通过等离子体增强型化学气相沉积、溶胶凝胶、溅射或原子层沉积等方法制作形成。所述沟道层 41 和接触层 42 的材料为非晶硅或金属氧化物半导体，如 IGZO ， IZO ， ITZO 等作为沟道层 41 和接触层 42 。
具体地，关于钝化层沉积、接触过孔刻蚀和透明电极层如 ITO 引出等，可采用现有技术，在此不再赘述。
具体地，所述半透光光罩 90 具有第一图形 91 、第二图形 92 及边缘图形 93 ，其中，所述第二图形 92 与第一图形 91 连续设置，所述边缘图形 93 沿着第一图形 91 的边缘连续设置；所述步骤 S2 中，所述第一图形 91 、第二图形 92 和边缘图形 93 分别用于对应形成中间部 811 、凹槽 813 和边缘部 812 。
具体地，所述步骤 S2 中提供的光阻材料为正型光阻材料，所述半透光光罩 90 的第一图形 91 为不透光区域，所述第二图形 92 和边缘图形 93 为半透光区域。
本发明对现有制程优化的部分主要在于，通过改变半透光光罩 80 的结构设计，在用于图形化源漏极金属层 50 和半导体层 40 的光阻层 80 的边缘形成厚度减小的边缘部 812 ，使得光阻层 80 边缘薄化，减轻源漏极 55 边缘有源层 45 拖尾的问题。如图 3 所示，为本发明半透光光罩 80 的第一种平面结构示意图，该第一种结构的半透光光罩 90 在对应形成的光阻层 80 的中间部 811 的相邻两光阻条连接处的部分仍为不透光的第一图形 91 。如图 4 所示，该第二种结构的半透光光罩 90 在对应形成的光阻层 80 的中间部 811 的相邻两光阻条连接处的部分也可以为半透光的边缘图形 93 ，则通过在形成第一光阻图形 81 时调节制程条件，使得第一光阻图形 81 在该连接处仍为连接结构。所述半透光光罩 90 具体涉及上述两种结构但不限于上述两种结构。
具体地，所述半透光光罩 90 可采用灰阶光罩，所述半透光光罩 90 上边缘图形 93 的透光率为 30%-50% 。或者，所述半透光光罩 90 也可采用半色调光罩。
参见图 5 ，其为本发明 TFT 阵列基板的制作方法的一优选实施例中形成源漏极和有源层的制程示意图，显示了第二道光罩制程，也就是本发明对现有制程所优化的部分。在第二道光罩制程前的第一道光罩制程即步骤 S1 中，在衬底基板 10 上沉积并图形化形成栅极 20 ，然后制备栅极绝缘层 30 、半导体层 40 及源漏极金属层 50 。然后，在应用优化的灰阶光罩进行步骤 S2 至步骤 S7 的第二道光罩制程：
步骤 S2 、应用灰阶光罩的半透光光罩 90 ，利用所述半透光光罩 90 对光阻材料进行曝光，显影，得到光阻层 80 ，所述光阻层 80 包括连续的第一光阻图形 81 、第二光阻图形 82 及第三光阻图形 83 ；所述第一光阻图形 81 、第二光阻图形 82 及第三光阻图形 83 均包括中间部 811 以及位于中间部 811 两侧的边缘部 812 ；所述第一光阻图形 81 的中间部 811 还设有凹槽 813 ；所述边缘部 812 的厚度小于中间部 811 的厚度；所述中间部 811 对应后续形成的源漏极 55 ；所述边缘部 812 对应后续形成的金属导线结构 54 边缘的半导体层 40 ；所述凹槽 813 对应后续形成的沟道；即通过改变半透光光罩 90 的结构设计，使得光阻层 80 边缘薄化，从而使得光阻层 80 的宽度在后续制程中易于缩减，进而使得金属导线结构 54 边缘的半导体层 40 易于在干刻时被等离子体蚀刻，减轻源漏极 55 边缘有源层 45 拖尾的问题，获得更为精细的金属导线结构，达到提高 TFT 光学稳定性和电学性能、开口率、可靠性以及减低功耗的目的，提高 TFT 阵列基板的整体性能，可以在原制程基础上，解决或减少源漏极边缘存在不定形硅和重掺杂硅的残留问题。
步骤 S3 、进行第一次湿刻，由所述源漏极金属层 50 形成金属导线结构 54 ；然后对所述光阻层 80 进行灰化处理。
步骤 S4 、进行第一次干刻，由半导体层 40 形成有源层结构 44 。从而通过在第一次湿刻之后和在第一次干刻之前，对所述光阻层 80 进行灰化处理，以进一步缩减所述光阻层 80 的宽度，使得所述金属导线结构 54 边缘的半导体层 40 易于被蚀刻。
步骤 S5 、对所述光阻层 80 进行灰化处理，减薄光阻层 80 的厚度直至凹槽 813 暴露出金属导线结构 54 。
步骤 S6 、进行第二次湿刻，由所述金属导线结构 54 形成源漏极 55 ；然后对所述光阻层 80 进行灰化处理。
步骤 S7 、进行第二次干刻，在有源层结构 44 上形成沟道，得到有源层 45 ，形成 TFT 结构。从而通过在第二次湿刻之后并在第二次干刻之前，对所述光阻层 80 进行灰化处理，以进一步缩减所述光阻层 80 的宽度，使得所述金属导线结构 54 边缘的半导体层 40 易于被蚀刻。
综上所述，本发明的 TFT 阵列基板的制作方法现有 4M 制程，通过改变半透光光罩的结构设计，在用于图形化源漏极金属层和半导体层的光阻层的边缘形成厚度减小的边缘部，使得光阻层边缘薄化，从而使得光阻层的宽度在后续制程中易于缩减，进而使得金属导线结构边缘的半导体层易于在干刻时被蚀刻，减轻源漏极边缘有源层拖尾的问题，获得更为精细的金属导线结构，达到提高 TFT 光学稳定性和电学性能、开口率、可靠性以及减低功耗的目的，提高 TFT 阵列基板的整体性能，可以在原制程基础上，解决或减少源漏极边缘存在不定形硅和重掺杂硅的残留问题。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (10)

  1. 一种TFT阵列基板的制作方法，包括如下步骤：
    步骤S1、提供衬底基板，在所述衬底基板上形成栅极、栅极绝缘层、半导体层及源漏极金属层；
    步骤S2、提供一半透光光罩，在所述源漏极金属层上涂布光阻材料，利用所述半透光光罩对光阻材料进行曝光、显影，得到光阻层，所述光阻层包括相互间隔的第一光阻图形、第二光阻图形及第三光阻图形；所述第一光阻图形、第二光阻图形及第三光阻图形均包括中间部以及位于中间部两侧的边缘部；所述第一光阻图形的中间部还设有凹槽；所述边缘部的厚度小于中间部的厚度；所述中间部对应后续形成的源漏极；所述边缘部对应后续形成的金属导线结构边缘的半导体层；所述凹槽对应后续形成的沟道；
    步骤S3、进行第一次湿刻，由所述源漏极金属层形成金属导线结构；
    步骤S4、进行第一次干刻，由半导体层形成有源层结构；
    步骤S5、对所述光阻层进行灰化处理，减薄光阻层的厚度直至凹槽暴露出金属导线结构；
    步骤S6、进行第二次湿刻，由所述金属导线结构形成源漏极；
    步骤S7、进行第二次干刻，在有源层结构上形成沟道，得到有源层，形成TFT结构。
  2. 如权利要求1所述的TFT阵列基板的制作方法，其中，所述半透光光罩具有第一图形、第二图形及边缘图形，其中，所述第二图形与第一图形相连续，所述边缘图形沿着第一图形的边缘连续设置；
    所述步骤S2中，所述第一图形、第二图形和边缘图形分别用于对应形成中间部、凹槽和边缘部；
    所述步骤S2中提供的光阻材料为正型光阻材料，所述半透光光罩的第一图形为不透光区域，所述第二图形和边缘图形为半透光区域。
  3. 如权利要求2所述的TFT阵列基板的制作方法，其中，所述半透光光罩为半色调光罩。
  4. 如权利要求2所述的TFT阵列基板的制作方法，其中，所述半透光光罩为灰阶光罩，所述半透光光罩的边缘图形的透光率为30%-50%。
  5. 如权利要求2所述的TFT阵列基板的制作方法，其中，所述步骤S2中形成的光阻层的中间部具有两条或以上的相连接的光阻条，所述半透光光罩在对应形成相邻两光阻条连接处的部分为第一图形或边缘图形。
  6. 如权利要求1所述的TFT阵列基板的制作方法，其中，所述步骤S3还包括，在第一次湿刻之后和在第一次干刻之前，对所述光阻层进行灰化处理，以缩减所述光阻层的宽度，使得所述金属导线结构边缘的半导体层易于被蚀刻；
    所述步骤S6还包括，在第二次湿刻之后和在第二次干刻之前，对所述光阻层进行灰化处理，以缩减所述光阻层的宽度，使得所述金属导线结构边缘的半导体层易于被蚀刻。
  7. 如权利要求1所述的TFT阵列基板的制作方法，其中，所述半导体层包括沟道层和设于沟道层上的接触层。
  8. 如权利要求7所述的TFT阵列基板的制作方法，其中，所述沟道层和接触层通过等离子体增强型化学气相沉积、溶胶凝胶、溅射或原子层沉积的方法制作形成。
  9. 如权利要求7所述的TFT阵列基板的制作方法，其中，所述沟道层和接触层的材料为非晶硅或金属氧化物半导体。
  10. 如权利要求1所述的TFT阵列基板的制作方法，其中，所述步骤S5中得到的TFT结构为显示区域或GOA区域的TFT结构。
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