WO2020073434A1 - 显示面板及显示器 - Google Patents

显示面板及显示器 Download PDF

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Publication number
WO2020073434A1
WO2020073434A1 PCT/CN2018/116397 CN2018116397W WO2020073434A1 WO 2020073434 A1 WO2020073434 A1 WO 2020073434A1 CN 2018116397 W CN2018116397 W CN 2018116397W WO 2020073434 A1 WO2020073434 A1 WO 2020073434A1
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WIPO (PCT)
Prior art keywords
fan
display panel
display area
line
insulating layer
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PCT/CN2018/116397
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English (en)
French (fr)
Inventor
李雪
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/321,912 priority Critical patent/US11508758B2/en
Publication of WO2020073434A1 publication Critical patent/WO2020073434A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the invention relates to the field of display technology, in particular to a display panel and a display.
  • the display panel generally includes a substrate 4, a multi-layer insulating layer 5 provided on the substrate 4 and multiple A metal trace 6 forms a display area 40 and a non-display area outside the display area 40.
  • the exemplary wiring manner of the first non-display area 50 on the left and right sides of the display area 40 can be known, and the multiple metal traces 6 of the first non-display area 50 It is often provided on the same insulating layer 5, and a certain gap between adjacent metal traces 6 needs to be maintained to prevent short circuits, and the gap between the metal traces 6 in the first non-display area 50 occupies a certain space, which The trace-like structure is obviously not conducive to reducing the occupied space of the non-display area to increase the screen ratio of the display panel.
  • the object of the present invention is to provide a display panel and a display to solve the above problems.
  • a display panel includes a substrate, a multi-layer insulating layer disposed on the substrate, and a plurality of metal traces.
  • the display panel includes a display area and first non-display areas located on the left and right sides of the display area.
  • the plurality of metal traces are located in the first non-display area, the plurality of metal traces are insulated from each other, and at least two adjacent metal traces are located on the insulation layers of different layers.
  • the multilayer insulating layer includes an interlayer buffer layer, a first inorganic insulating layer, and a second inorganic insulating layer that are sequentially disposed on the substrate.
  • the multiple metal traces include multiple GOA signal lines.
  • the plurality of GOA signal lines include: a gate-on voltage line provided on the interlayer buffer layer; a gate-off voltage line provided on the first inorganic insulating layer; The first clock signal line and the second clock signal line on the second inorganic insulating layer.
  • the first non-display area further includes a GOA driving circuit, and the plurality of GOA signal lines are connected to the GOA driving circuit.
  • the multiple metal traces include multiple test lines.
  • the plurality of test lines include: a first data signal test line and a first GOA signal test line provided on the interlayer buffer layer; and a second data signal provided on the first inorganic insulating layer A test line, a second GOA signal test line, and a third GOA signal test line; an enable signal test line provided on the second inorganic insulating layer.
  • the display panel further includes a second non-display area located under the display area, the second non-display area includes a first trace, a fan-out trace, a fan-out insulating layer, and a power line,
  • the first trace is provided on the substrate, and the fan-out insulating layer is provided on the first trace and the substrate.
  • the first trace is connected to the second trace of the display area.
  • the power line is provided on the fan-out insulating layer, wherein the first trace runs through the fan-out insulating layer to connect to the fan-out trace on the fan-out insulating layer, the fan-out The line is set on the same layer as the power line.
  • the second non-display area further includes a source driving circuit
  • the power supply line is disposed between the source driving circuit and the display area
  • the fan-out trace is disposed on the source driving circuit Between the power supply line and the power supply line, the power supply line and the fan-out wiring are respectively connected to the source driving circuit.
  • the multilayer insulation layer includes an interlayer buffer layer, a first inorganic insulation layer, and a second inorganic insulation layer that are sequentially disposed on the substrate.
  • the multiple metal traces include multiple GOA signal lines.
  • the plurality of GOA signal lines include: a gate-on voltage line provided on the interlayer buffer layer; a gate-off voltage line provided on the first inorganic insulating layer; and a The first clock signal line and the second clock signal line on the two inorganic insulating layers.
  • the first non-display area further includes a GOA driving circuit, and the plurality of GOA signal lines are connected to the GOA driving circuit.
  • the multiple metal traces include multiple test lines.
  • the plurality of test lines include: a first data signal test line and a first GOA signal test line provided on the interlayer buffer layer; and a second data signal test provided on the first inorganic insulating layer A second GOA signal test line and a third GOA signal test line; an enable signal test line provided on the second inorganic insulating layer.
  • the display panel further includes a second non-display area located under the display area, the second non-display area includes a first trace, a fan-out trace, a fan-out insulating layer, and a power line, the first A trace is provided on the substrate, the fan-out insulating layer is provided on the first trace and the substrate, the first trace is connected to the second trace of the display area, the The power line is disposed on the fan-out insulating layer, wherein the first trace runs through the fan-out insulating layer to connect to the fan-out trace on the fan-out insulating layer, the fan-out trace Set on the same layer as the power cord.
  • the second non-display area further includes a source drive circuit
  • the power line is disposed between the source drive circuit and the display area
  • the fan-out trace is disposed between the source drive circuit and Between the power lines, the power lines and the fan-out traces are respectively connected to the source driving circuit.
  • the present invention also provides a display including the display panel as described above.
  • the display panel and the display provided by the present invention on the one hand, by arranging a plurality of metal traces in the first non-display area on different layers of insulation, the metal traces not on the same insulation layer do not need to consider each other in the horizontal direction Can reduce the space occupied by the first non-display area; on the other hand, the display panel can be directly bent with the substrate with fan-out traces to achieve COP packaging, reducing the size of the lower side of the display area Space occupied by the second non-display area. Therefore, in the above manner, the display panel can reduce the space occupied by the non-display area and effectively increase the screen ratio.
  • FIG. 1 is a schematic structural diagram of a display panel in the prior art
  • FIG. 2 is a wiring diagram of a first non-display area of a display panel in the prior art
  • FIG. 3 is a schematic structural diagram of a display panel provided by Embodiment 1 of the present invention.
  • Example 4 is a schematic structural diagram corresponding to an implementation manner of a first non-display area in Example 1 of the present invention
  • Example 5 is a schematic structural diagram corresponding to another implementation manner of the first non-display area in Example 1 of the present invention.
  • FIG. 6 is a schematic structural diagram of a display area in Embodiment 1 of the present invention.
  • FIG. 7 is a wiring diagram of the GOA signal line of the first non-display area in Embodiment 1 of the present invention.
  • FIG. 8 is a schematic diagram of the connection between the GOA signal line and the GOA driving circuit in Embodiment 1 of the present invention.
  • FIG. 9 is a wiring diagram of the test line of the first non-display area in Embodiment 1 of the present invention.
  • FIG. 10 is a schematic structural diagram of a display panel provided by Embodiment 2 of the present invention.
  • FIG. 11 is a schematic structural diagram of a second non-display area in Embodiment 2 of the present invention.
  • the present invention provides a display panel including a substrate 1, a multi-layer insulating layer 2 stacked on the substrate 1, and a plurality of metal traces 3.
  • the display panel includes a display area 10 And first non-display areas 20 located on the left and right sides of the display area 10.
  • the pitch represents the line width of the metal trace 3
  • the plurality of metal traces 3 are located in the first non-display area 20
  • the plurality of metal traces 3 are insulated from each other, and at least two adjacent The metal trace 3 is located on the insulating layer 2 in different layers.
  • the first non-display area 20 of the display panel at least two adjacent metal traces 3 are respectively disposed on the insulating layers 2 of different layers, so that the metal traces 3 not on the same layer of the insulating layer 2 There is no need to consider the short circuit problem when the same layer is installed, the gap between these metal traces 3 in the horizontal direction parallel to the insulating layers 2 of each layer can be reduced, thereby reducing the first non-display area 20 in the horizontal direction
  • the space occupied by the display panel allows the frame of the display panel to be narrower, which is beneficial to increase the screen ratio of the display panel. As shown in FIG.
  • the two metal traces 3 when two adjacent metal traces 3 are located on the insulating layer 2 of different layers, the two metal traces 3 can be set closer to each other than other adjacent metal traces 3, so that the first non-display area 20 can be reduced in the horizontal direction corresponding to the gap change value of the two metal traces 3 length.
  • the width of general metal traces is about 2.8 ⁇ m, and the gap between two adjacent metal traces on the same insulating layer is about 3 ⁇ m or more.
  • the arrangement can reduce the gap between two adjacent metal traces 3 on the insulating layer 2 of different layers to 0.6 ⁇ m or less, which can effectively reduce the frame width of the display panel.
  • the distance between the two is zero, and the orthographic projections of two adjacent metal traces 3 on the substrate 1 can even overlap each other, so that the length of the first non-display area 20 in the horizontal direction can be further reduced .
  • any two adjacent metal traces 3 can be arranged closer than adjacent metal traces 3 in the same layer.
  • the orthographic projection of the plurality of metal traces 3 on the substrate 1 may be set to form a complete projection surface, that is, in the first non-display area 20, all adjacent metal traces 3 There is no gap in the horizontal direction.
  • the display area 10 includes a buffer layer 10a, an active layer 10b, a first insulating layer 10c, a gate metal layer 10d, and a Two insulating layers 10e, a capacitor electrode metal layer 10f, a third insulating layer 10g, a source / drain metal layer 10h, and an organic light-emitting layer 10i, the source / drain metal layer 10h penetrates the third insulating layer 10g, The second insulating layer 10e and the first insulating layer 10c are in contact with the active layer 10b.
  • the capacitance electrode of the storage capacitor of the display panel can be shared with the gate of the transistor, the above-mentioned gate metal layer 10d can be used as both the gate of the transistor and the capacitance electrode. Therefore, the gate metal layer 10d and the capacitor electrode metal layer 10f are made of the same material.
  • the multilayer insulating layer 2 includes an interlayer buffer layer 2a, a first inorganic insulating layer 2b, and a second inorganic insulating layer 2c that are sequentially disposed on the substrate And the organic layer 2d.
  • the interlayer buffer layer 2a and the buffer layer 10a of the display area 10 have the same layer structure, and the first inorganic insulating layer 2b
  • the first insulating layer 10e of the display area 10 has the same layer structure
  • the second inorganic insulating layer 2c and the second insulating layer 10f of the display area 10 have the same layer structure
  • the organic layer 2d and the The organic light-emitting layer 10i has the same layer structure.
  • the plurality of metal traces 3 can be selectively configured as gate layer traces formed simultaneously with the gate metal layer 10d or as capacitor electrode layer traces formed simultaneously with the capacitor electrode metal layer 10f Or, a source / drain layer trace formed simultaneously by the source / drain metal layer 10h is provided.
  • the traces of the gate layer and the traces of the capacitor electrode layer are made of the same material, for example, made of metal molybdenum together.
  • the multiple metal traces 3 include multiple GOA (Gate Driver On Array) signal lines.
  • GOA Gate Driver On Array
  • the plurality of GOA signal lines include: a gate-on voltage line (VGH) 3a provided on the interlayer buffer layer 2a; a gate-off voltage provided on the first inorganic insulating layer 2b A line (VGL) 3b; and a first clock signal line (CK) 3c and a second clock signal line (XCK) 3d provided on the second inorganic insulating layer 2c.
  • the gate-on voltage line 3a is formed simultaneously with the gate metal layer 10d on the display area 10
  • the gate-off voltage line 3b is formed simultaneously with the capacitor electrode metal layer 10f on the display area 10.
  • the first clock signal line 3c and the second clock signal line 3d are formed simultaneously with the source / drain metal layer 10h on the display area 10.
  • the first non-display area 20 further includes a GOA driving circuit 21, and the plurality of GOA signal lines are connected to the GOA driving circuit 21.
  • the multiple metal traces 3 include multiple test lines.
  • the plurality of test lines include: a first data signal test line (Data1) 3e and a first GOA signal test line (Test1) 3f provided on the interlayer buffer layer 2a; A second data signal test line (Data2) 3g, a second GOA signal test line (Test2) 3h and a third GOA signal test line (Test3) 3i provided on the first inorganic insulating layer 2b; An enable signal test line (EN) 3j on the two inorganic insulating layers 2c.
  • Data1 data signal test line
  • Test1 first GOA signal test line
  • Test1 first GOA signal test line
  • the first data signal test line 3e and the first GOA signal test line 3f are formed simultaneously with the gate metal layer 10d on the display area 10, the second data signal test line 3g, the second GOA signal test The line 3h and the third GOA signal test line 3i are formed simultaneously with the capacitor electrode metal layer 10f on the display area 10, and the enable signal test line 3j is formed simultaneously with the source / drain metal layer 10h on the display area 10 . Since the gate metal layer 10d and the capacitor electrode metal layer 10f are made of the same material, the materials of the corresponding test lines are the same, which avoids the influence of signal transmission due to different resistivity. Wherein, the first GOA signal test line 3f, the second GOA signal test line 3h and the third GOA signal test line 3i can be set as the test line for the output signal of the last stage of the GOA driving circuit.
  • this embodiment is based on the display panel provided in Embodiment 1. Further, the display panel further includes a second non-display area 30 located under the display area 10, and the first The second non-display area 30 includes a first trace 31, a fan-out trace 32, a fan-out insulating layer 33, and a power line 34.
  • the first trace 31 is provided on the substrate 1; the fan-out insulating layer 33 is provided on the first trace 31 and the substrate 1; the first trace 31 and the display area 10 is connected to the second trace, and the power line 34 is disposed on the fan-out insulating layer 33.
  • the first trace 31 penetrates the fan-out insulation layer 33 to be connected to the fan-out trace 32 on the fan-out insulation layer 33, the fan-out trace 32 is the same as the power line 34 Layer settings.
  • the first trace 31 may be a gate trace metal trace formed simultaneously with the gate metal layer 10d, and the second trace, the fan-out trace 32, and the power trace 34 of the display area are the same Source / drain layer metal traces formed simultaneously with the source / drain metal layer 10h.
  • the display panel in the prior art generally further includes a second non-display area 60.
  • the second non-display area 60 two fan-out wiring areas need to be provided to connect the display area 10
  • the second trace and the source driving unit 63 are bent through the connection area 610 between the first fan-out region 61 and the second fan-out region 62, so that the second fan-out region 62 follows the source driving unit 63 Turn over below the display area 40.
  • the second non-display area 60 needs to provide two fan-out wiring areas and the space occupied by the connection area 610, which limits the length of the display panel.
  • the display panel of this embodiment is equivalent to replacing the first fan-out area 61 with the first trace 31 to make the second trace on the source / drain metal layer 10h in the display area 10
  • the wire is changed through a via, and passes through the fan-out insulating layer 33 to connect to one end of the first trace 31 under the power line 34 and the fan-out insulating layer 33, and the other end of the first trace 31
  • the fan-out insulating layer 33 is connected to the fan-out trace 32 which is the same as the source / drain layer metal trace of the power line 34, that is, connected to the power line 34 Fan-out traces 32 on the same layer.
  • the fan-out trace 32 and the power line 34 are both source / drain layer metal traces, the two are at the neutral plane of the second non-display area 30, so that the fan-out trace 32 It can be bent with the substrate 1 with less stress to realize COP (Chip On Plastic, chip is mounted on a flexible substrate) package. Therefore, compared with the prior art, the display panel can be bent directly with the fan-out trace 32, saving the space of the second non-display area 30, and enabling the length of the display panel to be reduced accordingly, further The proportion of space occupied by the display area 10 is increased, and the screen proportion is increased.
  • a wire with good bending performance needs to be selected as the fan-out wire 32, and by removing the inorganic material in the area where the fan-out wire 32 is located, an organic material is filled into the fan-out wire 32.
  • Organic material is overlaid to form an organic insulating layer 35 so that the fan-out trace 32 approaches the neutral plane of the second non-display area 30.
  • the second non-display area 30 is provided with the source drive circuit 36, the power supply line 34 is provided between the source drive circuit 36 and the display area 10, the fan The output trace 32 is disposed between the source drive circuit 36 and the power supply line 34, and the power supply line 34 and the fan-out trace 32 are respectively connected to the source drive circuit 36.
  • the present invention also provides a display including the display panel as described above.
  • the display panel and the display provided by the present invention, by arranging a plurality of metal traces 3 in the first non-display area 20 on different layers of the insulating layer 2 respectively, the metal that is not on the same insulating layer 2 can The lines 3 do not need to consider the space between each other in the horizontal direction, which can reduce the space occupied by the first non-display area 20; and the display panel can be directly bent with the substrate 1 by fan-out traces 32 to realize COP packaging In view of the space occupied by the second non-display area 30, in this way, the display panel and the display can reduce the space occupied by the non-display area and effectively increase the screen ratio.

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Abstract

一种显示面板及显示器，显示面板包括基板（1）、设置于基板（1）上的多层绝缘层（2）以及多条金属走线（3），显示面板包括显示区（10）和位于显示区（10）左右两侧的第一非显示区（20），多条金属走线（3）位于第一非显示区（20），多条金属走线（3）彼此绝缘，至少两条相邻的金属走线（3）位于不同层的绝缘层（2）上。通过该布线方式，能缩减位于不同绝缘层（2）上的相邻的金属走线（3）在水平方向上的间隙，进而缩减了第一非显示区（20）占用的空间。而且，显示面板还能直接以扇出走线（32）随基板（1）进行弯折以实现COP封装，缩减位于显示区（10）下侧的第二非显示区（30）占用的空间，由此，显示面板和显示器能缩减非显示区所占空间，有效地提高屏占比。

Description

显示面板及显示器 技术领域
本发明涉及显示技术领域，尤其涉及显示面板及显示器。
背景技术
随着相关技术的发展，为提高用户的观感体验，缩减非显示区域的占用空间以提高显示面板的屏占比是业界生产显示面板的一个重要课题。参阅图1所示的现有技术中显示面板的结构图，现有的显示面板中，常采用以下设计：显示面板一般包括基板4、设置在所述基板4上的多层绝缘层5以及多条金属走线6，形成显示区40以及位于所述显示区40以外的非显示区。
结合图2所示出的现有显示面板中，位于所述显示区40左右两侧的第一非显示区50的示例性布线方式可以获知，第一非显示区50的多条金属走线6常设置于同一绝缘层5上，相邻的金属走线6之间需要保持一定的间隙以防止短路，而第一非显示区50的金属走线6之间的间隙占用了一定的空间，这类走线结构显然不利于缩减非显示区域的占用空间以提高显示面板的屏占比。
发明内容
有鉴于此，本发明的目的在于提供显示面板及显示器，来解决上述问题。
为了实现上述的目的，本发明采用了如下的技术方案：
一种显示面板，包括基板、设置于所述基板上的多层绝缘层以及多条金属走线，所述显示面板包括显示区和位于所述显示区左右两侧的第一非显示区，所述多条金属走线位于所述第一非显示区，所述多条金属走线彼此绝缘，至少两条相邻的所述金属走线位于不同层的所述绝缘层上。
优选地，至少两条相邻的所述金属走线在所述基板上的正投影之间无间隙。
优选地，所述多层绝缘层包括依次设置在所述基板上的层间缓冲层、第一无机绝缘层以及第二无机绝缘层。
优选地，所述多条金属走线包括多条GOA信号线。
优选地，所述多条GOA信号线包括：设置于所述层间缓冲层上的栅极导通电压线；设置于所述第一无机绝缘层上的栅极截止电压线；设置于所述第二无机绝缘层上的第一时钟信号线和第二时钟信号线。
优选地，所述第一非显示区还包括GOA驱动电路，所述多条GOA信号线连接到所述GOA驱动电路。
优选地，所述多条金属走线包括多条测试线。
优选地，所述多条测试线包括：设置于所述层间缓冲层上的第一数据信号测试线和第一GOA信号测试线；设置于所述第一无机绝缘层上的第二数据信号测试线、第二GOA信号测试线和第三GOA信号测试线；设置于所述第二无机绝缘层上的使能信号测试线。
优选地，所述显示面板还包括位于所述显示区下侧的第二非显示区，所述第二非显示区包括第一走线、扇出走线、扇出绝缘层以及电源线，所述第一走线设置于所述基板上，所述扇出绝缘层设置于所述第一走线和所述基板上，所述第一走线与所述显示区的第二走线连接，所述电源线设置于所述扇出绝缘层上，其中，所述第一走线贯穿所述扇出绝缘层以连接至位于所述扇出绝缘层上的所述扇出走线，所述扇出走线与所述电源线同层设置。
优选地，所述第二非显示区还包括源极驱动电路，所述电源线设置于所述源极驱动电路和所述显示区之间，所述扇出走线设置于所述源极驱动电路和所述电源线之间，所述电源线和所述扇出走线分别连接到所述源极驱动电路。
或者，所述多层绝缘层包括依次设置在所述基板上的层间缓冲层、第一无机绝缘层以及第二无机绝缘层。
或者，所述多条金属走线包括多条GOA信号线。
或者，所述多条GOA信号线包括：设置于所述层间缓冲层上的栅极导通电压线；设置于所述第一无机绝缘层上的栅极截止电压线；设置于所述第二无机绝缘层上的第一时钟信号线和第二时钟信号线。
或者，所述第一非显示区还包括GOA驱动电路，所述多条GOA信号线连接到所述GOA驱动电路。
或者，所述多条金属走线包括多条测试线。
或者，所述多条测试线包括：设置于所述层间缓冲层上的第一数据信号测 试线和第一GOA信号测试线；设置于所述第一无机绝缘层上的第二数据信号测试线、第二GOA信号测试线和第三GOA信号测试线；设置于所述第二无机绝缘层上的使能信号测试线。
或者，所述显示面板还包括位于所述显示区下侧的第二非显示区，所述第二非显示区包括第一走线、扇出走线、扇出绝缘层以及电源线，所述第一走线设置于所述基板上，所述扇出绝缘层设置于所述第一走线和所述基板上，所述第一走线与所述显示区的第二走线连接，所述电源线设置于所述扇出绝缘层上，其中，所述第一走线贯穿所述扇出绝缘层以连接至位于所述扇出绝缘层上的所述扇出走线，所述扇出走线与所述电源线同层设置。
或者，所述第二非显示区还包括源极驱动电路，所述电源线设置于所述源极驱动电路和所述显示区之间，所述扇出走线设置于所述源极驱动电路和所述电源线之间，所述电源线和所述扇出走线分别连接到所述源极驱动电路。
本发明还提供了一种显示器，包括如上所述的显示面板。
本发明提供的显示面板及显示器，一方面通过将第一非显示区的多条金属走线分别设置于不同层的绝缘上，使不在同一绝缘层上的金属走线无需考虑彼此在水平方向上的间隔，能缩减所述第一非显示区占用的空间；另一方面，所述显示面板能直接以扇出走线随基板进行弯折以实现COP封装，缩减了位于所述显示区下侧的第二非显示区占用的空间。由此，通过上述方式，所述显示面板能缩减非显示区所占空间，有效地提高屏占比。
附图说明
图1是现有技术中显示面板的结构示意图；
图2是现有技术中显示面板的第一非显示区的布线图；
图3是本发明实施例1提供的显示面板的结构示意图；
图4是本发明实施例1中的第一非显示区的一种实施方式对应的结构示意图；
图5是本发明实施例1中的第一非显示区的另一种实施方式对应的结构示意图；
图6是本发明实施例1中的显示区的结构示意图；
图7是本发明实施例1中的第一非显示区的GOA信号线的布线图；
图8是本发明实施例1中的GOA信号线与GOA驱动电路的连接示意图；
图9是本发明实施例1中的第一非显示区的测试线的布线图；
图10是本发明实施例2提供的显示面板的结构示意图；
图11是本发明实施例2中的第二非显示区的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式进行详细说明。这些优选实施方式的示例在附图中进行了例示。附图中所示和根据附图描述的本发明的实施方式仅仅是示例性的，并且本发明并不限于这些实施方式。
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了关系不大的其他细节。
实施例1
如图3所示，本发明提供了一种显示面板，包括基板1、叠层设置于所述基板1上的多层绝缘层2以及多条金属走线3，所述显示面板包括显示区10和位于所述显示区10左右两侧的第一非显示区20。
其中，结合图4和图5所示(图中的虚线代表两条所述金属走线3在所述基板1上的正投影方向，由同一条金属走线3上延伸出的虚线之间的间距代表所述金属走线3的线宽)，所述多条金属走线3位于所述第一非显示区20，所述多条金属走线3彼此绝缘，至少两条相邻的所述金属走线3位于不同层的所述绝缘层2上。
所述显示面板的第一非显示区20中通过将至少两条相邻的所述金属走线3分别设置于不同层的绝缘层2上，使得不在同层绝缘层2上的金属走线3无需考虑在同一层设置时的短路问题，可以缩减这些金属走线3彼此之间在平行于各层绝缘层2的水平方向上的间隙大小，进而减少所述第一非显示区20于水平方向上占用的空间，使所述显示面板的边框可以设计得更窄，有利于提高所述显示面板的屏占比。如图4所示，作为所述第一非显示区20的一种实施方式，当两条相邻的所述金属走线3位于不同层的所述绝缘层2上时，两条金属走线3 相互之间可以设置得比其他相邻的金属走线3之间更近，从而使所述第一非显示区20于水平方向上可以缩减对应这两条金属走线3的间隙变化值的长度。现有技术中，一般的金属走线的线宽约为2.8μm，设置于同层绝缘层上的相邻两条金属走线之间的间隙约为3μm以上，而采用本发明实施例的上述设置，可将位于不同层的所述绝缘层2上的相邻两条所述金属走线3之间的间隙缩减至0.6μm及以下，能有效地缩减所述显示面板的边框宽度。
本实施例可以进一步地设置为：至少两条相邻的所述金属走线3在所述基板1上的正投影之间无间隙，即两条相邻的所述金属走线3在水平方向上的间距为零，两条相邻的所述金属走线3在所述基板1上的正投影甚至可以相互交叠，使得所述第一非显示区20于水平方向上的长度可以进一步缩减。
当然，所述第一非显示区20也可以将更多条所述金属走线3设置为相邻的两条金属走线3之间位于不同层的绝缘层2上，例如图5对应的所述第一非显示区20的另一种实施方式，该实施方式中任意两条相邻的金属走线3之间都可以设置为比同层的相邻金属走线3之间更近。
另外，现有技术为了避免同层的金属走线发生短路，需要采用过孔换线的形式来连接到驱动电路，该布线方式不仅造成了空间占用问题，还增大了驱动信号传输到驱动电路的阻抗。而根据本发明提供的显示面板的布线方式，可以使一部分金属走线3进行接线时，无需进行过孔换线的设置，直接与驱动电路导通，并减少了传输阻抗。
进一步地，所述多条金属走线3在所述基板1上的正投影可设置为构成一完整的投影面，即所述第一非显示区20中，所有相邻的金属走线3之间于水平方向上均无间隙。
如图6所示，在本实施例中，所述显示区10包括依序设置于所述基板1上的缓冲层10a、有源层10b、第一绝缘层10c、栅极金属层10d、第二绝缘层10e、电容电极金属层10f、第三绝缘层10g、源极/漏极金属层10h以及有机发光层10i，所述源极/漏极金属层10h贯穿所述第三绝缘层10g、第二绝缘层10e以及第一绝缘层10c与所述有源层10b接触。由于所述显示面板的存储电容器的电容电极可以与晶体管的栅极共用，上述栅极金属层10d既可作为晶体管的栅极，又可作为电容电极。因此，所述栅极金属层10d和所述电容电极金属层10f由相同的材质制成。
结合图6-图8所示，在本实施例中，所述多层绝缘层2包括依次设置在所 述基板上的层间缓冲层2a、第一无机绝缘层2b、第二无机绝缘层2c以及有机层2d。所述第一非显示区20与所述显示区10相对应的结构中，所述层间缓冲层2a与所述显示区10的缓冲层10a为同一层结构，所述第一无机绝缘层2b与所述显示区10的第一绝缘层10e为同一层结构，所述第二无机绝缘层2c与所述显示区10的第二绝缘层10f为同一层结构，所述有机层2d与所述有机发光层10i为同一层结构。所述多条金属走线3分别可选择地设置为与所述栅极金属层10d同时形成的栅极层走线、或者设置为与所述电容电极金属层10f同时形成的电容电极层走线、或者设置为源极/漏极金属层10h同时形成的源极/漏极层走线。同理地，所述栅极层走线和所述电容电极层走线由相同的材质制成，例如一并采用金属钼制成。
示例性地，所述多条金属走线3包括多条GOA(Gate driver On Array)信号线。
具体地，所述多条GOA信号线包括：设置于所述层间缓冲层2a上的栅极导通电压线(VGH)3a；设置于所述第一无机绝缘层2b上的栅极截止电压线(VGL)3b；以及设置于所述第二无机绝缘层2c上的第一时钟信号线(CK)3c和第二时钟信号线(XCK)3d。所述栅极导通电压线3a与所述显示区10上的栅极金属层10d同时形成，所述栅极截止电压线3b与所述显示区10上的电容电极金属层10f同时形成，所述第一时钟信号线3c和第二时钟信号线3d与显示区10上的源极/漏极金属层10h同时形成。
进一步地，所述第一非显示区20还包括GOA驱动电路21，所述多条GOA信号线连接到所述GOA驱动电路21。
示例性地，所述多条金属走线3包括多条测试线。
具体地，结合图9所示，所述多条测试线包括：设置于所述层间缓冲层2a上的第一数据信号测试线(Data1)3e和第一GOA信号测试线(Test1)3f；设置于所述第一无机绝缘层2b上的第二数据信号测试线(Data2)3g、第二GOA信号测试线(Test2)3h和第三GOA信号测试线(Test3)3i；设置于所述第二无机绝缘层2c上的使能信号测试线(EN)3j。所述第一数据信号测试线3e和所述第一GOA信号测试线3f与显示区10上的栅极金属层10d同时形成，所述第二数据信号测试线3g、所述第二GOA信号测试线3h以及所述第三GOA信号测试线3i与显示区10上的电容电极金属层10f同时形成，所述使能信号测试线3j与显示区10上的源极/漏极金属层10h同时形成。由于所述栅极金属层10d 和所述电容电极金属层10f由相同的材质制成，因此对应的测试线的材质相同，避免了因电阻率不同而影响信号传递。其中，上述第一GOA信号测试线3f、第二GOA信号测试线3h以及第三GOA信号测试线3i可设置为GOA驱动电路最后一级输出信号的测试线。
实施例2
参阅图10和图11所示，本实施例基于实施例1所提供的显示面板，进一步地，所述显示面板还包括位于所述显示区10下侧的第二非显示区30，所述第二非显示区30包括第一走线31、扇出走线32、扇出绝缘层33以及电源线34。所述第一走线31设置于所述基板1上；所述扇出绝缘层33设置于所述第一走线31和所述基板1上；所述第一走线31与所述显示区10的第二走线连接，所述电源线34设置于所述扇出绝缘层33上。
其中，所述第一走线31贯穿所述扇出绝缘层33以连接至位于所述扇出绝缘层33上的所述扇出走线32，所述扇出走线32与所述电源线34同层设置。
本实施例的所述第一走线31可以设置为与栅极金属层10d同时形成的栅极层金属走线，而上述显示区的第二走线、扇出走线32以及电源线34同为与源极/漏极金属层10h同时形成的源极/漏极层金属走线。
结合图1和图11所示，现有技术中的显示面板一般还包括第二非显示区60，所述第二非显示区60中，需要设置两个扇出走线区连接显示区10的第二走线和源极驱动单元63，以通过第一扇出区61和第二扇出区62之间的连接区域610进行弯折，使所述第二扇出区62随源极驱动单元63翻转至显示区40的下方。该第二非显示区60需要提供两个扇出走线区以及连接区域610所占的空间，使显示面板的长度受到限制。而本实施例的显示面板相当于通过将所述第一扇出区61替换为所述第一走线31，使所述显示区10中位于源极/漏极金属层10h上的第二走线通过过孔换线，贯穿所述扇出绝缘层33连接至位于所述电源线34以及扇出绝缘层33之下的第一走线31的一端，所述第一走线31的另一端再通过过孔换线，贯穿所述扇出绝缘层33连接至与所述电源线34同为源极/漏极层金属走线的扇出走线32，即连接至与所述电源线34位于同一层上的扇出走线32。而由于所述扇出走线32与所述电源线34同为源极/漏极层金属走线，两者同处所述第二非显示区30的中性面，使所述扇出走线32能以受到较小的应力随所述基板1进行弯折，以实现COP(Chip On Plastic，芯片被贴装在柔性基板上)封装。因此，相比于现有技术，所述显示面板能直接以扇出走线32进行弯 折，节省了所述第二非显示区30的空间，使所述显示面板的长度能随之缩减，进一步提高所述显示区10所占空间比例，提高屏占比。
本实施例需要选用弯折性能良好的走线作为所述扇出走线32，并且通过去除所述扇出走线32所在区域的无机材料，向其中填入有机材料，在所述扇出走线32的上方覆设有机材料，形成有机绝缘层35，使所述扇出走线32趋近于所述第二非显示区30的中性面。
在本实施例中，所述第二非显示区30设置有所述源极驱动电路36，所述电源线34设置于所述源极驱动电路36和所述显示区10之间，所述扇出走线32设置于所述源极驱动电路36和所述电源线34之间，所述电源线34和所述扇出走线32分别连接到所述源极驱动电路36。
本发明还提供了一种显示器，包括如上所述的显示面板。
综上所述，本发明提供的显示面板及显示器，通过将第一非显示区20的多条金属走线3分别设置于不同层的绝缘层2上，使不在同一绝缘层2上的金属走线3无需考虑彼此在水平方向上的间隔，能缩减所述第一非显示区20占用的空间；而且所述显示面板能直接以扇出走线32随基板1进行弯折以实现COP封装，缩减了所述第二非显示区30占用的空间，由此，通过上述方式，所述显示面板和所述显示器能缩减非显示区所占空间，有效地提高屏占比。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (19)

  1. 一种显示面板，包括基板、设置于所述基板上的多层绝缘层以及多条金属走线，所述显示面板包括显示区和位于所述显示区左右两侧的第一非显示区，其中，所述多条金属走线位于所述第一非显示区，所述多条金属走线彼此绝缘，至少两条相邻的所述金属走线位于不同层的所述绝缘层上。
  2. 根据权利要求1所述的显示面板，其中，至少两条相邻的所述金属走线在所述基板上的正投影之间无间隙。
  3. 根据权利要求1所述的显示面板，其中，所述多层绝缘层包括依次设置在所述基板上的层间缓冲层、第一无机绝缘层以及第二无机绝缘层。
  4. 根据权利要求3所述的显示面板，其中，所述多条金属走线包括多条GOA信号线。
  5. 根据权利要求4所述的显示面板，其中，所述多条GOA信号线包括：
    设置于所述层间缓冲层上的栅极导通电压线；
    设置于所述第一无机绝缘层上的栅极截止电压线；
    设置于所述第二无机绝缘层上的第一时钟信号线和第二时钟信号线。
  6. 根据权利要求4所述的显示面板，其中，所述第一非显示区还包括GOA驱动电路，所述多条GOA信号线连接到所述GOA驱动电路。
  7. 根据权利要求3所述的显示面板，其中，所述多条金属走线包括多条测试线。
  8. 根据权利要求7所述的显示面板，其中，所述多条测试线包括：
    设置于所述层间缓冲层上的第一数据信号测试线和第一GOA信号测试线；
    设置于所述第一无机绝缘层上的第二数据信号测试线、第二GOA信号测试线和第三GOA信号测试线；
    设置于所述第二无机绝缘层上的使能信号测试线。
  9. 根据权利要求1所述的显示面板，其中，所述显示面板还包括位于所述显示区下侧的第二非显示区，所述第二非显示区包括第一走线、扇出走线、扇 出绝缘层以及电源线，所述第一走线设置于所述基板上，所述扇出绝缘层设置于所述第一走线和所述基板上，所述第一走线与所述显示区的第二走线连接，所述电源线设置于所述扇出绝缘层上，其中，所述第一走线贯穿所述扇出绝缘层以连接至位于所述扇出绝缘层上的所述扇出走线，所述扇出走线与所述电源线同层设置。
  10. 根据权利要求9所述的显示面板，其中，所述第二非显示区还包括源极驱动电路，所述电源线设置于所述源极驱动电路和所述显示区之间，所述扇出走线设置于所述源极驱动电路和所述电源线之间，所述电源线和所述扇出走线分别连接到所述源极驱动电路。
  11. 根据权利要求2所述的显示面板，其中，所述多层绝缘层包括依次设置在所述基板上的层间缓冲层、第一无机绝缘层以及第二无机绝缘层。
  12. 根据权利要求11所述的显示面板，其中，所述多条金属走线包括多条GOA信号线。
  13. 根据权利要求12所述的显示面板，其中，所述多条GOA信号线包括：
    设置于所述层间缓冲层上的栅极导通电压线；
    设置于所述第一无机绝缘层上的栅极截止电压线；
    设置于所述第二无机绝缘层上的第一时钟信号线和第二时钟信号线。
  14. 根据权利要求13所述的显示面板，其中，所述第一非显示区还包括GOA驱动电路，所述多条GOA信号线连接到所述GOA驱动电路。
  15. 根据权利要求11所述的显示面板，其中，所述多条金属走线包括多条测试线。
  16. 根据权利要求15所述的显示面板，其中，所述多条测试线包括：
    设置于所述层间缓冲层上的第一数据信号测试线和第一GOA信号测试线；
    设置于所述第一无机绝缘层上的第二数据信号测试线、第二GOA信号测试线和第三GOA信号测试线；
    设置于所述第二无机绝缘层上的使能信号测试线。
  17. 根据权利要求2所述的显示面板，其中，所述显示面板还包括位于所述显示区下侧的第二非显示区，所述第二非显示区包括第一走线、扇出走线、 扇出绝缘层以及电源线，所述第一走线设置于所述基板上，所述扇出绝缘层设置于所述第一走线和所述基板上，所述第一走线与所述显示区的第二走线连接，所述电源线设置于所述扇出绝缘层上，其中，所述第一走线贯穿所述扇出绝缘层以连接至位于所述扇出绝缘层上的所述扇出走线，所述扇出走线与所述电源线同层设置。
  18. 根据权利要求17所述的显示面板，其中，所述第二非显示区还包括源极驱动电路，所述电源线设置于所述源极驱动电路和所述显示区之间，所述扇出走线设置于所述源极驱动电路和所述电源线之间，所述电源线和所述扇出走线分别连接到所述源极驱动电路。
  19. 一种显示器，其中，包括如权利要求1所述的显示面板。
PCT/CN2018/116397 2018-10-10 2018-11-20 显示面板及显示器 WO2020073434A1 (zh)

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