WO2020073396A1 - 一种显示面板的像素驱动电路和显示装置 - Google Patents

一种显示面板的像素驱动电路和显示装置 Download PDF

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Publication number
WO2020073396A1
WO2020073396A1 PCT/CN2018/114064 CN2018114064W WO2020073396A1 WO 2020073396 A1 WO2020073396 A1 WO 2020073396A1 CN 2018114064 W CN2018114064 W CN 2018114064W WO 2020073396 A1 WO2020073396 A1 WO 2020073396A1
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Prior art keywords
circuit
scan signal
display panel
terminal
thin film
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PCT/CN2018/114064
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English (en)
French (fr)
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吴川
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惠科股份有限公司
重庆惠科金渝光电科技有限公司
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Priority to US16/320,481 priority Critical patent/US10803822B2/en
Publication of WO2020073396A1 publication Critical patent/WO2020073396A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit

Definitions

  • the present application relates to the field of display technology, and in particular to a pixel driving circuit and a display device of a display panel.
  • Flat panel displays include thin film transistor liquid crystal displays (Thin Film Transistor-Liquid Crystal (TFT-LCD) and organic light-emitting diode (Organic Light-Emitting Diode, OLED) displays, etc.
  • TFT-LCD Thi Film Transistor-Liquid Crystal
  • OLED Organic Light-Emitting Diode
  • the thin film transistor liquid crystal display controls the rotation direction of the liquid crystal molecules to refract the light of the backlight module to generate a picture, which has many advantages such as thin body, power saving, no radiation and so on.
  • the organic light-emitting diode display is made of organic electroluminescent diodes, and has many advantages such as self-luminescence, short response time, high definition and contrast, flexible display and large-area full-color display.
  • the display panel is a voltage-driven device, but in the technology we have mastered before, it can achieve the improvement of the penetration rate of the display panel, and the drive display architecture that reduces power consumption is rare, and the best display effect cannot be achieved.
  • the power consumption of the driving architecture is relatively large, and the panel penetration rate is low.
  • the present application is to provide a driving structure and a driving device for a display panel that enables the voltage loaded on the pixel electrode to be greater than the voltage of the data line, improve the transmittance of the display panel, and reduce power consumption.
  • a pixel driving circuit for a display panel including:
  • the first scan line provides the first scan signal corresponding to the current pixel
  • the data line cooperates with the first scan signal to provide the data voltage of the current pixel
  • Power supply circuit providing power supply voltage
  • An amplifier circuit is electrically connected to the data line and the power supply circuit, an output terminal of the amplifier circuit is electrically connected to the pixel electrode, and the amplifier circuit amplifies and outputs the data voltage provided by the data line to the pixel electrode.
  • the application also discloses a pixel driving circuit of a display panel, including:
  • the first scan line provides the first scan signal corresponding to the current pixel
  • the second scan line provides the second scan signal corresponding to the current pixel
  • the supply voltage line provides a supply voltage
  • the data line cooperates with the first scan signal to provide the data voltage of the current pixel
  • the first switch circuit, the second transistor and the third switch circuit are The first switch circuit, the second transistor and the third switch circuit;
  • the gate terminal of the first switch circuit is controlled to be connected to the first scan signal; the source terminal of the first switch circuit is electrically connected to the data line, and the drain terminal of the first switch circuit is connected to the second transistor Gate terminal
  • the source terminal of the second transistor is electrically connected to the power supply voltage line, and the drain terminal of the second transistor is electrically connected to the source terminal of the third switching circuit;
  • the gate terminal of the third switch circuit is control connected to the second scan signal, and the drain terminal of the third switch circuit is electrically connected to the input terminal of the pixel electrode;
  • a first capacitor is formed between the drain terminal of the first switching circuit and the drain terminal of the second transistor.
  • This application also discloses a display device, including:
  • the display panel includes the pixel driving circuit as described above;
  • a driving module to drive the display panel
  • the driving module outputs a first scan signal, power supply voltage and data voltage to the display panel
  • the first scan signal output by the driving module is at a high level, cooperates with the data voltage of the data line, and provides the current pixel data voltage to the amplification circuit;
  • the power supply voltage of the power supply circuit is at a high level to supply power to the amplifier circuit, and the amplifier circuit amplifies and outputs the data voltage to the pixel electrode.
  • the first scan line of this application outputs the first scan signal corresponding to the current pixel
  • the data line cooperates with the first scan signal, input the signal of the data voltage, provides the data voltage of the current pixel, and the power supply circuit
  • the high level is turned on to supply power to the amplifier circuit.
  • the data voltage input by the data line is output to the pixel electrode through the amplifier circuit to provide a higher pixel driving voltage to drive the pixel electrode.
  • the technology is improved. Through such improvements, the driving voltage of the pixel is greater than the data voltage of the data line itself, improving the penetration rate of the panel and reducing the power consumption.
  • the driving voltage loaded on the pixel electrode is greater than the driving voltage of the data line itself Possibly, guarantee the display effect.
  • FIG. 1 is a schematic diagram of a display panel driving architecture according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of a pixel driving circuit module according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a pixel driving circuit module according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a pixel driving circuit structure according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a corresponding driving timing according to an embodiment of the present application.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more.
  • the term “including” and any variations thereof are intended to cover non-exclusive inclusions.
  • connection should be understood in a broad sense, for example, it can be fixed or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • installation should be understood in a broad sense, for example, it can be fixed or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • the present application discloses a display device 100 including a display panel 101 and a driving module to drive the display panel 101.
  • a pixel driving circuit 110 of the display panel 101 includes: a pixel electrode 120; a first scan line to provide the first scan signal Gate1 corresponding to the current pixel; a data line 140 to cooperate with the first scan signal Gate1 to provide the current pixel
  • the data voltage VData the power supply circuit 150, which supplies the power supply voltage VDD
  • the amplifier circuit 160 which is electrically connected to the data line 140 and the power supply circuit 150, the output end of the amplifier circuit 160 is electrically connected to the pixel electrode 120, and the amplifier circuit 160 connects the data line 140
  • the supplied data voltage is amplified and output to the pixel electrode 120.
  • the thin film transistor (Thin Film Transistor, TFT) switch is controlled by the scanning line Gate signal, and the TFT switch and the common line on the array substrate (Array_COM) Form a storage capacitor (Cst) and a common line (CF_COM) on the color filter substrate to form a pixel capacitor (Clc).
  • TFT Thin Film Transistor
  • the voltage of the node m at the steady state of the display panel of the pixel driving circuit 110 can be equal to the maximum input data line 140 of the data line 140 The voltage VData; and the first scan line of this solution outputs the first scan signal Gate1 corresponding to the current pixel, the data line 140 cooperates with the first scan signal Gate1, inputs the signal of the data voltage, provides the data voltage of the current pixel, and the power supply circuit 150
  • the high level is turned on to supply power to the amplifier circuit 160.
  • the data voltage input from the data line 140 is output to the pixel electrode 120 through the amplifier circuit 160, which can provide a pixel with a higher data voltage relative to the data line 140 input.
  • the driving voltage drives the pixel electrode 120; in turn, this solution can greatly reduce the voltage value of the data on the data line 140, thereby further reducing
  • the amplitude of the voltage fluctuation on the data line 140 allows the display panel 101 to pass a smaller data voltage.
  • the power requirements of the display panel 101 can be met, and the display panel 101 is driven to improve the display panel 101.
  • the transmissivity reduces the power consumption of the display panel 101, realizing the possibility that the driving voltage loaded on the pixel electrode is greater than the driving voltage of the data line 140 itself, ensuring the display effect.
  • the driving module outputs the first scanning signal Gate1 at a high level, which cooperates with the data voltage of the data line 140 to provide
  • the data voltage of the current pixel is supplied to the amplifying circuit 160;
  • the power supply voltage of the power supply circuit 150 is at a high level to supply power to the amplifying circuit 160, and the amplifying circuit 160 amplifies and outputs the data voltage to the pixel electrode 120.
  • the driving module When the driving module outputs the first scan signal Gate1 at a high level, the data line 140 cooperates with the output data voltage, and the power supply circuit 150 provides a high-level power supply voltage to supply power to the amplifier circuit 160, and the amplifier circuit 160 amplifies and outputs the data voltage at this time
  • the possibility that the driving voltage loaded on the pixel electrode is greater than the driving voltage of the data line 140 itself is improved, improving the transmittance of the display panel 101 and reducing power consumption.
  • the power supply circuit 150 includes a power supply voltage line 151
  • the amplifier circuit 160 includes a second transistor 161.
  • the gate terminal of the second transistor 161 is controlled to be connected to the data line 140
  • the source terminal of the second transistor 161 is electrically connected to the power supply voltage line 151
  • the drain terminal of the second transistor 161 is controlled to be connected to the pixel electrode 120.
  • the second transistor 161 may be a thin film transistor (Thin Film Transistor, TFT) ), May also be other structures or circuits having the same function.
  • TFT Thin Film Transistor
  • the amplifying circuit 160 is an amplifying transistor, that is, the second transistor T2.
  • the main function here is to amplify, not just a switching function.
  • the signal from the data line 140 is small, it is amplified by T2 to make it Have enough energy to drive the actuator to complete specific tasks.
  • the pixel driving circuit 110 further includes a first switch circuit 170, and the data line 140 is electrically connected to the amplifier circuit 160 through the first switch circuit 170; the data line 140 is electrically connected to the source terminal of the first switch circuit 170, The drain terminal of the first switch circuit 170 is controlled to be connected to the amplifier circuit 160; the gate terminal of the first switch circuit 170 is controlled to be connected to the first scan signal Gate1 of the display panel 101.
  • the first switch circuit 170 may be a thin film transistor (Thin Film Transistor, TFT) may also be other structures or circuits having the same function.
  • the first switch circuit T1 when the first scan signal Gate1 is at a high level, the first switch circuit T1 is turned on, and at this time, the data line 140 supplies the data voltage corresponding to the current pixel to the amplifier circuit 160, so that the data line 140 converts the current pixel
  • the first switching circuit 170 here is directly controlled by the first scan signal Gate1, and controls the input and disconnection of the data voltage driving circuit.
  • a first capacitor C is formed between the drain terminal of the first switch circuit 170 and the output terminal of the amplifier circuit 160.
  • the first capacitor 180 is formed between the drain terminal of the first switching circuit 170 and the output terminal of the amplifying circuit 160.
  • This pixel driving circuit 110 makes the data voltage when the first scan signal Gate1 is input to a high level The first capacitor 180 is charged.
  • the first capacitor 180 maintains the voltage difference across the capacitor, and the first switch can be synchronized when the voltage at the output terminal (n point) of the amplifier circuit 160 is amplified.
  • the voltage of the drain terminal (point m) of the circuit 170 is pulled up, maintaining and enhancing the voltage of the drain terminal of the first switching circuit 170.
  • the pixel driving circuit 110 further includes: a second scan line, which provides a second scan signal Gate2 corresponding to the current pixel; a third The switching circuit 190 and the third switching circuit 190 are connected between the output terminal of the amplifier circuit 160 and the pixel electrode 120: the gate terminal of the third switching circuit 190 is electrically connected to the second scan line, and the source terminal of the third switching circuit 190 is connected to the amplifier The output terminal of the circuit 160 is electrically connected, and the drain terminal of the third switching circuit 190 is electrically connected to the pixel electrode 120.
  • the third switching circuit 190 may be a thin film transistor (Thin Film Transistor, TFT), or may be another structure having the same function or Circuit.
  • a switch circuit that is, a third switch circuit T3, is also provided between the amplifier circuit 160 and the pixel electrode 120, which disconnects the data line 140 and the amplifier circuit after the current line scan period is completed, preventing the amplifier circuit 160 and the data line 140 continue to affect the voltage of the pixel electrode 120, so that the pixel electrode 120 can maintain a higher pixel driving voltage related to the data voltage of the data line 140 within a frame period.
  • the driving module Based on the architecture of the pixel driving circuit 110 described above, the driving module also outputs a second scanning signal Gate2; the scanning cycle of a row of pixels of the display panel 101 includes a first cycle time and a second cycle time;
  • the first scan signal Gate1 is high level
  • the second scan signal Gate2 is high level
  • the power supply voltage is low level
  • the data line 140 outputs the data voltage corresponding to the current pixel
  • the first scan signal Gate1 is low level
  • the second scan signal Gate2 is high level
  • the power supply voltage is high level.
  • the work in each period of the period is endless Similarly, in the first period T2, the first scan signal Gate1 and the second scan signal Gate2 are both high level, the power supply voltage is low level, the first switch circuit 170 and the third switch circuit 190 are turned on, and the second triode The tube 161 is pulled up to VGH, and at the same time, the Data signal is input.
  • the voltage Vm of the node m VData
  • the voltage Vc VData-VDD_L of the first capacitor 180C.
  • the first scan signal Gate1 is VGL to close T1
  • the second scan signal Gate2 is VGH
  • T3 remains open.
  • the node m is in the Floating state.
  • VDD is pulled by VDD_L As high as VDD_H, the current flowing through T2 is:
  • the voltages of the nodes m / n / o are:
  • the scan period of a row of pixels of the display panel 101 includes an initialization period T1 set before the first period time.
  • the initialization period T1 the first scan signal Gate1 output by the drive module is low,
  • the second scan signal Gate2 is high level.
  • the scanning cycle of one row of pixels of the display panel 101 further includes a third cycle time T4 set after the second cycle time: within the third cycle time T4, the first scan signal Gate1 is low The second scan signal Gate2 is low.
  • the first scan signal Gate1 and the second scan signal Gate2 output by the drive module are both low-level VGL, and T1 and T3 are turned off at the same time.
  • the voltage of the node m is at a high potential.
  • T2 is turned on, node n can be charged to VDD_H by the opened T2, so that node o can still maintain a high potential after T3 is turned off.
  • the scanning cycle of one row of pixels of the display panel 101 further includes a third cycle time T4 set after the second cycle time T3: within the third cycle time T4, the first scan output by the driving module
  • the signal Gate1 is at a low level
  • the second scan signal Gate2 is at a low level.
  • the first scan signal Gate1 and the second scan signal Gate2 are both low-level VGL, and T1 and T3 are turned off at the same time.
  • the voltage of the node m is at a high potential, so that T2 is turned on, the node n can be charged to VDD_H by the opened T2, at which time node o can still maintain a high potential after T3 is closed.
  • a pixel driving circuit 110 of a display panel 101 includes: a pixel electrode 120; a first scan line to provide a first scan signal corresponding to a current pixel Gate1; the second scan line provides the second scan signal Gate2 corresponding to the current pixel; the supply voltage line 151 provides a supply voltage; the data line 140 cooperates with the first scan signal Gate1 to provide the current pixel data voltage; and the first Switching circuit 170, second transistor 161 and third switching circuit 190;
  • the gate terminal of the first switch circuit 170 is controlled to be connected to the first scan signal Gate1; the source terminal of the first switch circuit 170 is connected to the data line 140, and the drain terminal of the first switch circuit 170 is connected to the gate terminal of the second transistor 161 ;
  • the source of the second transistor 161 is electrically connected to the supply voltage line 151, the drain terminal of the second transistor 161 is electrically connected to the source terminal of the third switch circuit 190;
  • the gate terminal of the third switch circuit 190 is connected to the second
  • the scan signal Gate2 controls the connection, and the drain terminal of the third switch circuit 190 is electrically connected to the pixel electrode 120;
  • a first capacitor 180 is formed between the drain terminal of the first switching circuit 170 and the drain terminal of the second transistor 161; a storage capacitor Cst is formed between the drain terminal of the third switching circuit 190 and the array substrate of the display panel 101 A pixel capacitance Clc is formed with the color filter substrate of the display panel 101.
  • the scanning period of a row of pixels is divided into four time nodes T1, T2, T3, and T4.
  • T (T1 + T2 + T3 + T4)
  • T (T1 + T2 + T3 + T4)
  • T (T1 + T2 + T3 + T4)
  • ⁇ t, t is the number of gate lines, that is, one frame time
  • the Gate2 is pulled up to VGH, and the Data signal is started to be input at this time.
  • Gate1 maintains VHG to keep T3 on.
  • node m is in the Floating state.
  • VDD is pulled up from VDD_L to VDD_H.
  • the current flowing through T2 is.
  • the voltages of the nodes m / n / o are:
  • T is the time length of T3
  • Vth2 is the threshold voltage of T2
  • T4 is the last light-emitting stage
  • Gate1 and Gate2 are both VGL to turn off T1 and T3 at the same time, the voltage of node m is at a high potential, so that When T2 is turned on, node n can be charged to VDD_H by the opened T2. At this time, node o can still maintain a high potential after T3 is turned off, where k is a constant related to the mobility of the semiconductor layer.
  • k 1/2 ⁇ ⁇ ⁇ Cox ⁇ W / L
  • ⁇ is the electron mobility of the semiconductor layer
  • Cox is the capacitance per unit area of the MIS structure of the TFT device
  • W / L is the width-to-length ratio of the TFT channel.
  • the first scan line of the display panel 101 outputs the first scan signal Gate1 corresponding to the current pixel.
  • the first scan signal Gate1 is at a high level
  • the first switch circuit 170 is turned on, and the data line 140 is input through the first switch circuit 170
  • the data voltage VData reaches the output end of the first switching circuit 170
  • Vth2 is the threshold voltage of T2
  • the second scan signal Gate2 is set to a high level, and Vm charges the pixel electrode 120 through the third switching circuit 190, so that the pixel electrode 120 can maintain a data voltage related to the data voltage of the data line 140 within a frame period.
  • High pixel drive voltage at this time, the first scan signal Gate1 is set to a low level, so that the first switching circuit 170 disconnects the data line 140 and the amplifier circuit, preventing the second transistor 161 and the data line 140 from continuing The voltage of the pixel electrode 120 is affected.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • OLED Organic Light-Emitting Diode

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Abstract

本申请公开了一种显示面板的像素驱动电路和显示装置。包括：像素电极；数据线，提供当前像素的数据电压；供电电路，提供供电电压；放大电路，将数据线提供的数据电压放大输出到像素电极。

Description

一种显示面板的像素驱动电路和显示装置
本申请要求于2018年10月8日提交中国专利局、申请号为CN201821629477.6、发明名称为“一种显示面板的像素驱动电路和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板的像素驱动电路和显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地的构成现有技术。
随着科技的发展和进步，平板显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。平板显示器包括薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等。其中，薄膜晶体管液晶显示器通过控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面，具有机身薄、省电、无辐射等众多优点。而有机发光二极管显示器是利用有机电致发光二极管制成，具有自发光、响应时间短、清晰度与对比度高、可实现柔性显示与大面积全色显示等诸多优点。
显示面板是电压驱动型器件，但是我们之前掌握的技术中， 能达到实现显示面板穿透率的提升，降低功耗的驱动显示架构少之又少，无法达到最佳的显示效果。
技术问题
目前的显示面板中,驱动架构功耗都比较大,而且面板穿透率低。
技术解决方案
本申请是提供一种使加载于像素电极上的电压能大于数据线电压的驱动架构，实现显示面板穿透率的提升，降低功耗的显示面板的像素驱动电路和显示装置。
为实现上述目的，本申请提供了一种显示面板的像素驱动电路，包括：
像素电极；
第一扫描线，提供当前像素对应的第一扫描信号；
数据线，与所述第一扫描信号配合，提供当前像素的数据电压；
供电电路，提供供电电压；
放大电路，与所述数据线和供电电路电连接，所述放大电路的输出端与所述像素电极电连接,所述放大电路将所述数据线提供的数据电压放大输出到所述像素电极。
本申请还公开了一种显示面板的像素驱动电路，包括：
像素电极；
第一扫描线，提供当前像素对应的第一扫描信号；
第二扫描线,提供当前像素对应的第二扫描信号；
供电电压线，提供一供电电压；
数据线，与所述第一扫描信号配合，提供当前像素的数据电压；
第一开关电路、第二三极管及第三开关电路；
所述第一开关电路的栅极端与所述第一扫描信号控制连接；第一开关电路的源极端与所述数据线电连接，第一开关电路的漏极端连接到所述第二三极管的栅极端；
所述第二三极管的源极端与所述供电电压线电连接，所述第二三极管的漏极端与所述第三开关电路的源极端电连接；
所述第三开关电路的栅极端与所述第二扫描信号控制连接，所述第三开关电路的漏极端与所述像素电极的输入端电连接；
其中，所述第一开关电路的漏极端与所述第二三极管的漏极端之间形成有第一电容。
本申请还公开了一种显示装置，包括：
显示面板，包括如上任一所述的像素驱动电路；
驱动模块，驱动所述显示面板；
所述驱动模块输出第一扫描信号、供电电压和数据电压给所述显示面板；
在所述显示面板的一行像素的扫描周期内，所述驱动模块输出的第一扫描信号呈高电平，与所述数据线的数据电压配合，提供当前像素的数据电压给所述放大电路；所述供电电路的供电 电压呈高电平，为所述放大电路供电，所述放大电路将所述数据电压放大输出到所述像素电极。
相对于我们掌握的其他技术，本申请第一扫描线输出当前像素对应的第一扫描信号，数据线与第一扫描信号配合，输入数据电压的信号，提供当前像素的数据电压，供电电路在数据电压输入时对应开启高电平为放大电路供电，此时数据线输入的数据电压经放大电路输出到像素电极，以提供一个更高的像素驱动电压，对像素电极进行驱动，本方案在之前掌握的技术上进行改进，通过如此改进,使得像素驱动电压大于数据线本身的数据电压，提升面板的穿透率，降低功耗，实现了加载于像素电极的驱动电压大于数据线本身的驱动电压的可能，保证显示效果。
附图说明
所包括的附图用来提供对本申请实施例的理解，其构成了说明书的一部分，例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请实施例一种显示面板驱动架构的示意图；
图2是本申请实施例一种像素驱动电路模块的示意图；
图3是本申请实施例一种像素驱动电路模块的示意图；
图4是本申请实施例一种像素驱动电路结构的示意图；
图5是本申请实施例一种对应驱动时序的示意图。
本申请的实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通 技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、电路和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、电路、组件和/或其组合。
下面参考附图和较佳的实施例对本申请作说明。
如图2至图6所示，本申请公开了一种显示装置100，包括：显示面板101和驱动模块，驱动所述显示面板101。
所述显示面板101的一个像素驱动电路110，包括：像素电极120；第一扫描线，提供当前像素对应的第一扫描信号Gate1；数据线140，与第一扫描信号Gate1配合，提供当前像素的数据电压VData；供电电路150，提供供电电压VDD；放大电路160，与数据线140和供电电路150电连接，所述放大电路160的输出端与像素电极120电连接,放大电路160将数据线140提供的数据电压放大输出到像素电极120。
相对于如图1所示的方案来说，图1中的像素驱动电路110中，由扫描线Gate信号控制薄膜晶体管(Thin Film Transistor，TFT)开关，TFT开关与阵列基板上公共线(Array_COM)形成存储电容(Cst)与彩膜基板上公共线(CF_COM)形成像素电 容(Clc)该像素驱动电路110的显示面板在稳态时候的节点m的电压最大可以等于数据线140输入的数据线140电压VData；而本方案的第一扫描线输出当前像素对应的第一扫描信号Gate1，数据线140与第一扫描信号Gate1配合，输入数据电压的信号，提供当前像素的数据电压，供电电路150在数据电压输入时对应开启高电平为放大电路160供电，此时数据线140输入的数据电压经放大电路160输出到像素电极120，可以提供一个相对于数据线140输入的数据电压更高的像素驱动电压，对像素电极120进行驱动；进而，使得本方案可大幅降低数据线140上Data的电压值，进而降低了数据线140上电压的波动幅度，使得显示面板101可通过一较小的数据电压，借助放大电路160，即可满足显示面板101的功率要求，对显示面板101进行驱动，提升了显示面板101的穿透率，降低了显示面板101的功耗，实现了加载于像素电极的驱动电压大于数据线140本身的驱动电压的可能，保证显示效果。
基于上述像素驱动电路110的架构，所述的驱动模块在显示面板101的一行像素的扫描周期内，驱动模块输出的第一扫描信号Gate1呈高电平，与数据线140的数据电压配合，提供当前像素的数据电压给放大电路160；供电电路150的供电电压呈高电平，为放大电路160供电，放大电路160将数据电压放大输出到像素电极120。
当驱动模块输出呈高电平的第一扫描信号Gate1，数据线 140配合输出数据电压，供电电路150提供高电平的供电电压，为放大电路160供电，放大电路160此时将数据电压放大输出到像素电极120，实现加载于像素电极的驱动电压大于数据线140本身的驱动电压的可能，提升显示面板101的穿透率，降低功耗。
本实施例可选的，如图3所示，所述供电电路150包括供电电压线151，放大电路160包括第二三极管161，第二三极管161的栅极端与数据线140控制连接，第二三极管161的源极端与供电电压线151电连接，第二三极管161的漏极端与像素电极120控制连接，第二三极管161可以是薄膜晶体管(Thin Film Transistor，TFT)，也可以是具有同样功能的其他结构或者电路。
本方案中，放大电路160是一个放大三极管，即第二三极管T2，此处主要作用是放大，并非单纯的开关作用,当数据线140传来的信号较小时，通过T2放大，使之具有足够的能量来驱动执行机构，完成特定的工作。
本实施例可选的，像素驱动电路110还包括第一开关电路170，数据线140通过第一开关电路170与放大电路160电连接；数据线140与第一开关电路170的源极端电连接，第一开关电路170的漏极端与放大电路160控制连接；第一开关电路170的栅极端与显示面板101的第一扫描信号Gate1控制连接，第一开关电路170可以是薄膜晶体管(Thin Film Transistor，TFT)，也可以是具有同样功能的其他结构或者电路。
本方案中，当第一扫描信号Gate1为高电平时，第一开关 电路T1接通,此时数据线140将当前像素对应的数据电压提供给放大电路160，实现数据线140将当前像素对应的数据电压的输入,此处的第一开关电路170直接受第一扫描信号Gate1的控制,控制数据电压驱动电路的输入和断开。
本实施例可选的，第一开关电路170的漏极端与放大电路160的输出端之间形成有第一电容C。
本方案中，第一电容180形成在第一开关电路170的漏极端与放大电路160的输出端之间，这种像素驱动电路110使得当第一扫描信号Gate1输入为高电平时，数据电压为第一电容180充电，当第一扫描信号Gate1为低电平时，第一电容180维持电容两端的电压差，可以在放大电路160的输出端(n点)的电压放大时，同步将第一开关电路170的漏极端(m点)的电压上拉，维持并增强第一开关电路170的漏极端的电压。
参考图4和图5所示，作为本申请的另一实施例，与上述实施例不同的是像素驱动电路110还包括：第二扫描线，提供当前像素对应的第二扫描信号Gate2；第三开关电路190，第三开关电路190连接在放大电路160的输出端与像素电极120之间：第三开关电路190的栅极端与第二扫描线电连接，第三开关电路190的源极端与放大电路160的输出端电连接，第三开关电路190的漏极端与像素电极120电连接，第三开关电路190可以是薄膜晶体管(Thin Film Transistor，TFT)，也可以是具有同样功能的其他结构或者电路。
本方案中，在放大电路160与像素电极120之间也设置一个开关电路，也就是第三开关电路T3，在当前行扫描周期完成后断开和数据线140以及放大电路的连接，防止放大电路160和数据线140持续影响像素电极120的电压，使得像素电极120能在一帧周期内维持一与数据线140的数据电压相关的更高的像素驱动电压。
基于上述像素驱动电路110的架构，驱动模块还输出第二扫描信号Gate2；所述显示面板101的一行像素的扫描周期包括第一周期时间和第二周期时间；
在第一周期时间T2内，第一扫描信号Gate1为高电平，第二扫描信号Gate2为高电平；供电电压为低电平；数据线140输出对应当前像素的数据电压；
在第二周期时间T3内，第一扫描信号Gate1为低电平，第二扫描信号Gate2为高电平，供电电压为高电平。
本方案中，一行像素的扫描周期内，为了实现像素电极120能在一帧周期内维持一与数据线140的数据电压相关的更高的像素驱动电压，周期内各个时间段的工作是不尽相同的，第一周期T2，第一扫描信号Gate1和第二扫描信号Gate2同为高电平，供电电压为低电平，第一开关电路170和第三开关电路190打开，将第二三极管161拉高至VGH，同时开始输入Data信号，此时节点m的电压Vm＝VData，节点n和o的电压Vn＝Vo＝VDD_L，第一电容180C的电压Vc＝VData-VDD_L。T3时刻，电压拉高阶段，此时 第一扫描信号Gate1为VGL将T1关闭，第二扫描信号Gate2为VGH,T3保持打开,此时节点m为Floating(漂浮)状态，此时VDD由VDD_L拉高至VDD_H，此时流过T2的电流为；
节点m/n/o的电压分别为：
Figure PCTCN2018114064-appb-000001
Figure PCTCN2018114064-appb-000002
本实施例可选的，所述显示面板101的一行像素的扫描周期包括设置在第一周期时间之前的初始化周期T1，初始化周期T1内，驱动模块输出的第一扫描信号Gate1为低电平，第二扫描信号Gate2为高电平。
本方案中，在所述显示面板101的一行像素的扫描周期的第一周期时间之前还有初始化周期，此周期内进行初始化动作，此时T3打开，T1关闭，节点m在上一帧结束时处于高电平状态，这样可使第二三极管161打开，此时供电电压给予低电平信号VDD_L。在初始化周期时，节点n/o的电压Vn＝Vo＝VDD_L。其中，所述供电电压信号VDD是由驱动模块单独引线电连接至显示面板101，由驱动模块上的控制芯片给以信号，直接控制其高低电平。
本实施例可选的，所述显示面板101的一行像素的扫描周期还包括设置在第二周期时间之后的第三周期时间T4：在第三周期时间T4内，第一扫描信号Gate1为低电平，第二扫描信号Gate2为低电平。
本方案中，第三周期时间T4内，驱动模块输出的第一扫描信号Gate1和第二扫描信号Gate2都是低电平VGL，将T1、T3同时关闭，此时节点m的电压处于高电位，使得T2打开，节点n可被打开的T2充电至VDD_H，使得此时节点o在T3关闭后仍然能保持一高电位。
本实施例可选的，所述显示面板101的一行像素的扫描周期还包括设置在第二周期时间T3之后的第三周期时间T4：在第三周期时间T4内，驱动模块输出的第一扫描信号Gate1为低电平，第二扫描信号Gate2为低电平。
本方案中，第三周期时间内，第一扫描信号Gate1和第二扫描信号Gate2都为低电平VGL，将T1、T3同时关闭，此时节点m的电压处于高电位，使得T2打开，节点n可被打开的T2充电至VDD_H，此时节点o在T3关闭后仍然能保持一高电位。
作为本申请的又一实施例，参考图4至图5所示，公开了一种显示面板101的像素驱动电路110包括:像素电极120；第一扫描线，提供当前像素对应的第一扫描信号Gate1；第二扫描线,提供当前像素对应的第二扫描信号Gate2；供电电压线151，提供一供电电压；数据线140，与第一扫描信号Gate1配合，提供当前像素的数据电压；及第一开关电路170、第二三极管161及第三开关电路190；
第一开关电路170的栅极端与第一扫描信号Gate1控制连接；第一开关电路170的源极端与数据线140连接，第一开关电 路170的漏极端连接到第二三极管161的栅极端；第二三极管161的源极与供电电压线151电连接，第二三极管161的漏极端与第三开关电路190的源极端电连接；第三开关电路190的栅极端与第二扫描信号Gate2控制连接，第三开关电路190的漏极端与像素电极120电连接；
其中，第一开关电路170的漏极端与第二三极管161的漏极端之间形成有第一电容180；第三开关电路190的漏极端与显示面板101的阵列基板之间形成存储电容Cst，与显示面板101的彩膜基板形成像素电容Clc。
本方案中，在一行像素的扫描周期内，将一行像素的扫描周期分为T1、T2、T3、T4四个时间节点。需要说明的是，一帧时间(60HZ T＝1/60＝16.7ms，120HZ T＝8.33ms)T＝(T1+T2+T3+T4)·t，t为gate线数目，也就是一帧时间扫描的次数，例如，对于高清HD解析度1366*768的显示面板101来说，有768条gate线，t＝768，对应的T1+T2+T3+T4＝21.7μs(60HZ情况，也可以为120HZ，120HZ对应扫描t＝10.85μs)，对于全高清FHD解析度的显示面板101来说，t＝1080，对应的T1+T2+T3+T4＝15.4μs，对于4K的解析度的显示面板101来说，t＝2160，对应的T1+T2+T3+T4＝7.7μs。
本方案中，对于T1时间内，进行初始化动作，Gate1为高电平VGH，Gate2处于低电平VGL，此时T3打开，T1关闭，节点m在上一帧结束时处于高电平状态，这样可使T2打开，此时VDD给予低电平信号VDD_L(VDD是驱动模块由单独引线电连接至显示 面板101，由驱动模块上的控制芯片给以信号，直接控制其高低电平信号。)，故此时节点n/o的电压Vn＝Vo＝VDD_L；在T2时刻，将进行数据信号写入，此时将Gate2拉高至VGH，同时开始输入Data信号，此时节点m的电压Vm＝VData，此时Gate1保持VHG以使T3持续打开，此时节点n和o的电压Vn＝Vo＝VDD_L，此时电容C的电压Vc＝VData-VDD_L；T3时刻，是电压拉高阶段，此时Gate2为VGL将T1关闭，此时节点m为Floating(漂浮)状态，此时VDD由VDD_L拉高至VDD_H，此时流过T2的电流为。
节点m/n/o的电压分别为：
Figure PCTCN2018114064-appb-000003
Figure PCTCN2018114064-appb-000004
其中T为T3的时间长度，Vth2是T2的阈值电压；T4时刻是最后的发光阶段，此时，Gate1和Gate2都是VGL将T1、T3同时关闭，此时节点m的电压处于高电位，使得T2打开，节点n可被打开的T2充电至VDD_H，此时节点o在T3关闭后仍然能保持一高电位，其中k为半导体层迁移率相关的一个常数。k＝1/2·μ·Cox·W/L，μ为半导体层的电子迁移率，Cox为TFT器件MIS结构的单位面积电容，W/L为TFT沟道的宽长比。
所述显示面板101的第一扫描线输出当前像素对应的第一扫描信号Gate1，当第一扫描信号Gate1为高电平时，第一开关 电路170接通，数据线140经过第一开关电路170输入数据电压VData至第一开关电路170的输出端，供电电路150开启低电平VDD_L，此时数据电压为第一电容180充电，m点高电平，打开第二三极管161，n点为VDD_L；此时，第一电容180的电压为：VC＝VData-VDD_L；此时，第一扫描信号Gate1设置为低电平VDD_L，供电电路150开启高电平VDD_H为第二三极管161供电，对第二三极管161栅极端的输入放大，此时流过第二三极管T2的电流为，第二三极管161的输出端即节点n的电压为：
Figure PCTCN2018114064-appb-000005
Vth2是T2的阈值电压，k为半导体层迁移率相关的一个常数。k＝1/2·μ·Cox·W/L，μ为半导体层的电子迁移率，Cox为薄膜晶体管(Thin Film Transistor,TFT)器件MIS结构的单位面积电容，W/L为TFT沟道的宽长比。由于此时节点m为漂浮(Floating)状态，第一电容180维持电容两端的电压差，在放大电路160的输出端的电压放大时，同步将第一开关电路170的漏极端的电压上拉，维持并增强第一开关电路170的漏极端的电压，即：
Figure PCTCN2018114064-appb-000006
此时，将第二扫描信号Gate2设置为高电平，Vm通过第三开关电路190给像素电极120充电，使得像素电极120能在一帧周期内维持一与数据线140的数据电压相关的更高的像素驱动电 压；此时，将第一扫描信号Gate1设置为低电平，使得第一开关电路170断开数据线140和放大电路的连接，防止第二三极管161和数据线140持续影响像素电极120的电压。
本申请的技术方案可以广泛应薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)和有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等平板显示器。
以上内容是结合具体的可选实施方式对本申请所作的详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (19)

  1. 一种显示面板的像素驱动电路，包括：
    像素电极；
    第一扫描线，提供当前像素对应的第一扫描信号；
    数据线，与所述第一扫描信号配合，提供当前像素的数据电压；
    供电电路，提供供电电压；
    以及放大电路，与所述数据线和供电电路电连接，所述放大电路的输出端与所述像素电极电连接，所述放大电路将所述数据线提供的数据电压放大输出到所述像素电极。
  2. 如权利要求1所述的一种显示面板的像素驱动电路，其中，所述供电电路包括供电电压线，所述放大电路包括第二三极管。
  3. 如权利要求1所述的一种显示面板的像素驱动电路，其中，所述第二三极管的栅极端与所述数据线控制连接，所述第二三极管的源极端与所述供电电压线电连接，所述第二三极管的漏极端与像素电极控制连接。
  4. 如权利要求1所述的一种显示面板的像素驱动电路，其中，所述像素驱动电路包括：
    第一开关电路，所述数据线通过所述第一开关电路与所述放大电路控制连接。
  5. 如权利要求4所述的一种显示面板的像素驱动电路，其中，所述第一开关电路包括第一薄膜晶体管。
  6. 如权利要求5所述的一种显示面板的像素驱动电路，其中，所述数据线与所述第一薄膜晶体管的源极端电连接，所述第一薄膜晶体管的漏极端与所述放大电路控制连接；所述第一薄膜晶体管的栅极端与所述显示面板的第一扫描信号控制连接。
  7. 如权利要求4所述的一种显示面板的像素驱动电路，其中，所述第一开关电路的漏极端与所述放大电路的输出端之间形成有第一电容。
  8. 如权利要求1所述的一种显示面板的像素驱动电路，其中，所述像 素驱动电路还包括：
    第二扫描线，提供当前像素对应的第二扫描信号；以及
    第三开关电路，所述第三开关电路连接在所述放大电路的输出端与所述像素电极之间：
  9. 如权利要求8所述的一种显示面板的像素驱动电路，其中，所述第三开关电路包括第三薄膜晶体管，所述第三薄膜晶体管的栅极端与所述第二扫描线电连接，所述第三薄膜晶体管的源极端与所述放大电路的输出端电连接，所述第三薄膜晶体管的漏极端与所述像素电极的输入端电连接。
  10. 一种显示面板的像素驱动电路，包括：
    像素电极；
    第一扫描线，提供当前像素对应的第一扫描信号；
    第二扫描线，提供当前像素对应的第二扫描信号；
    供电电压线，提供一供电电压；
    数据线，与所述第一扫描信号配合，提供当前像素的数据电压；以及
    第一开关电路、第二三极管及第三开关电路；
    所述第一开关电路与所述第一扫描信号控制连接，并连通所述数据线电连接与所述第二三极管；
    所述第二三极管连通所述供电电压线和所述第三开关电路；
    所述第三开关电路与所述第二扫描信号控制连接，并与所述像素电极电连接。
  11. 如权利要求10所述的一种显示面板的像素驱动电路，其中，所述第一开关电路包括第一薄膜晶体管，所述第三开关电路包括第三薄膜晶体管；
    所述第一薄膜晶体管的栅极端与所述第一扫描信号控制连接；第一薄膜晶体管的源极端与所述数据线电连接，第一薄膜晶体管的漏极端连接到所述第二三极管的栅极端；
    所述第二三极管的源极端与所述供电电压线电连接，所述第二三极管的漏极端与所述第三薄膜晶体管的源极端电连接；
    所述第三薄膜晶体管的栅极端与所述第二扫描信号控制连接，所述第三薄膜晶体管的漏极端与所述像素电极的输入端电连接；
    所述第一开关电路的漏极端与所述第二三极管的漏极端之间形成有第 一电容。
  12. 一种显示装置，包括：
    显示面板；
    驱动模块，驱动所述显示面板；以及
    像素驱动电路，包括：
    像素电极；
    数据线，与所述第一扫描信号配合，提供当前像素的数据电压；
    供电电路，包括供电电压线，提供供电电压；以及
    放大电路，包括第二三极管，所述第二三极管的栅极端与所述数据线控制连接，所述第二三极管的源极端与所述供电电压线电连接，所述第二三极管的漏极端与像素电极控制连接，所述放大电路将所述数据线提供的数据电压放大输出到所述像素电极。
    所述驱动模块输出第一扫描信号、供电电压和数据电压给所述显示面板；
    在所述显示面板的一行像素的扫描周期内，所述驱动模块输出的第一扫描信号呈高电平，与所述数据线的数据电压配合，提供当前像素的数据电压给所述放大电路；所述供电电路的供电电压呈高电平，为所述放大电路供电，所述放大电路将所述数据电压放大输出到所述像素电极。
  13. 如权利要求12所述的一种显示装置，其中，所述像素驱动电路包括第一开关电路，所述数据线通过所述第一开关电路与所述放大电路控制连接；所述数据线与所述第一开关电路的源极端电连接，所述第一开关电路的漏极端与所述放大电路控制连接；所述第一开关电路的栅极端与所述显示面板的第一扫描信号控制连接。
  14. 如权利要求13所述的一种显示装置，其中，所述第一开关电路的漏极端与所述放大电路的输出端之间形成有第一电容。
  15. 如权利要求12所述的一种显示装置，其中，所述像素驱动电路还包括：
    第二扫描线，提供当前像素对应的第二扫描信号；
    第三开关电路，所述第三开关电路连接在所述放大电路的输出端与所述像素电极之间：所述第三开关电路的栅极端与所述第二扫描线电连接，所述第三开关电路的源极端与所述放大电路的输出端电连接，所述第三开关电路的漏极端与所述像素电极的输入端电连接。
  16. 如权利要求15所述的一种显示装置，其中，所述第一开关电路包括第一薄膜晶体管，所述第三开关电路包括第三薄膜晶体管；
    所述第一薄膜晶体管的栅极端与所述第一扫描信号控制连接；第一薄膜晶体管的源极端与所述数据线电连接，第一薄膜晶体管的漏极端连接到所述第二三极管的栅极端；
    所述第二三极管的源极端与所述供电电压线电连接，所述第二三极管的漏极端与所述第三薄膜晶体管的源极端电连接；
    所述第三薄膜晶体管的栅极端与所述第二扫描信号控制连接，所述第三薄膜晶体管的漏极端与所述像素电极的输入端电连接；
    所述第一开关电路的漏极端与所述第二三极管的漏极端之间形成有第一电容。
  17. 如权利要求12所述的一种显示装置，其中，所述驱动模块还输出第二扫描信号；所述显示面板的一行像素的扫描周期包括第一周期时间和第二周期时间；
    在所述第一周期时间内，所述驱动模块输出的第一扫描信号为高电平，所述驱动模块输出的第二扫描信号为高电平；所述供电电压为低电平；所述数据线输出对应当前像素的所述数据电压；
    在所述第二周期时间内，所述驱动模块输出的第一扫描信号为低电平，所述驱动模块输出的第二扫描信号为高电平，所述供电电压为高电平。
  18. 如权利要求12所述的一种显示装置，其中，所述显示面板的一行像素的扫描周期包括设置在所述第一周期时间之前的初始化周期，所述初始化周期内，所述驱动模块输出的第一扫描信号为低电平，所述驱动模块输出的第二扫描信号为高电平。
  19. 如权利要求12所述的一种显示装置，其中，所述显示面板的一行像素的扫描周期包括设置在所述第二周期时间之后的第三周期时间；在所述第三周期时间内，所述驱动模块输出的第一扫描信号为低电平，所述驱 动模块输出的第二扫描信号为低电平。
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KR20150077171A (ko) * 2013-12-27 2015-07-07 엘지디스플레이 주식회사 유기발광다이오드 표시장치와 그 구동 방법
CN105469743A (zh) * 2016-01-29 2016-04-06 深圳市华星光电技术有限公司 像素补偿电路、扫描驱动电路及平面显示装置
CN108269537A (zh) * 2016-12-30 2018-07-10 乐金显示有限公司 有机发光二极管显示设备

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