WO2016004679A1 - 像素电路、具备该像素电路的显示面板和显示器 - Google Patents

像素电路、具备该像素电路的显示面板和显示器 Download PDF

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Publication number
WO2016004679A1
WO2016004679A1 PCT/CN2014/086894 CN2014086894W WO2016004679A1 WO 2016004679 A1 WO2016004679 A1 WO 2016004679A1 CN 2014086894 W CN2014086894 W CN 2014086894W WO 2016004679 A1 WO2016004679 A1 WO 2016004679A1
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transistor
node
voltage
signal
gate
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PCT/CN2014/086894
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English (en)
French (fr)
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郭平昇
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深圳市华星光电技术有限公司
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Priority to US14/416,874 priority Critical patent/US9779658B2/en
Publication of WO2016004679A1 publication Critical patent/WO2016004679A1/zh

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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
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    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an Active Matrix Organic Light Emitting Diode (AMOLED) display, and more particularly to a pixel circuit, a display panel including the same, and a display.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • AMOLED Active Matrix Organic Light Emitting Diode
  • each pixel circuit of the AMOLED panel is equipped with a low temperature poly-Si Thin Film Transistor (LT P-Si TFT) and a charge storage capacitor, and a peripheral driving circuit of the AMOLED panel and The display array is integrated on the same glass substrate.
  • LT P-Si TFT low temperature poly-Si Thin Film Transistor
  • a laser scanning mode is widely used in a crystallization process, and due to the instability of the power of such a laser beam, a thin film transistor formed on a scanning line obtained by scanning using such a laser beam may have Defects of threshold voltages different from each other, which in turn cause problems in image quality of a plurality of pixel regions.
  • FIG. 1 is a schematic diagram of a structure (2T1C) of a pixel circuit 100 in a conventional OLED display technology.
  • the driving method of the pixel circuit 100 is as follows: in a state where the scanning line SL receives the scanning signal Vscan to turn on the thin film transistor T1, the data line DL receives the data signal Vdata, and the data signal Vdata is stored in the capacitor Cc via the thin film transistor T1. In a state where the scan line SL receives the scan signal Vscan to turn off the thin film transistor T1, the thin film transistor T2 is continuously turned on, and a voltage stored in the capacitor Cc is applied to the OLED of the pixel circuit to generate a drive. The OLED emits a driving current Ioled.
  • the phenomenon that the threshold voltage Vth of the thin film transistor T2 drifts occurs.
  • the magnitude of the driving current Ioled flowing through the OLED is directly affected. Based on this, for each pixel circuit in the OLED display technology, the current magnitude of the OLED flowing through each pixel circuit reflecting the same data signal Vdata may be different, which may cause the gray scale of the OLED in each pixel circuit to be Not the same, which in turn affects the uniformity of the display of the OLED panel.
  • the prior art provides a pixel circuit of a 3T1C structure with a compensation function, but it is only applicable to a large-sized OLED display with a driving mode of Simultaneous Emission (SE), which cannot be applied to the progressive mode.
  • SE Simultaneous Emission
  • PE Progressive Emission
  • One of the technical problems to be solved by the present invention is to provide a pixel circuit capable of solving the problem of threshold voltage shift, thereby extending circuit life, and the pixel circuit can be applied to a progressively driven OLED display, and can also be applied. In a synchronous illumination driven OLED display.
  • the present invention provides a pixel circuit comprising: a first transistor having a gate for receiving a scan signal, a source for receiving a data signal, a drain connected to the first node, and a second a transistor having a gate for receiving the scan signal, a source connected to the reference voltage, a drain connected to the second node, and a storage capacitor connected between the first node and the second node; a third transistor having a gate connected to the second node and a source connected to the first node; a fourth transistor having a gate for receiving a signal opposite to the scan signal, the source of which is coupled to a first voltage having a drain connected to the first node, a fifth transistor having a gate for receiving a light emitting signal, a source connected to a drain of the third transistor, and a light emitting component having an anode connected to the first A drain of a five transistor having a cathode connected to a second voltage, the second voltage being lower than the first voltage.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are PMOS type thin film transistors; the light emitting component is an organic light emitting diode .
  • a display panel including: a plurality of data lines; a plurality of scan lines orthogonally arranged with the plurality of data lines to form a plurality of pixel regions; and a plurality of pixel circuits, respectively Configured in each pixel area Within the domain, and each pixel circuit includes: a first transistor having a gate for receiving a scan signal, a source for receiving the data signal, a drain connected to the first node, and a second transistor having a gate for receiving The scan signal has a source connected to a reference voltage, a drain connected to the second node, a storage capacitor connected between the first node and the second node, and a third transistor having a gate connection To the second node, the source thereof is connected to the first node; the fourth transistor has a gate for receiving a signal opposite to the scan signal, a source connected to the first voltage, and a drain connected a fifth transistor having a gate for receiving an emission control signal, a source connected to a drain of
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are PMOS type thin film transistors; the light emitting component is an organic light emitting diode .
  • a display device includes: a display panel including: a plurality of data lines; and a plurality of scan lines orthogonally arranged with the plurality of data lines to form a plurality of pixel regions; a plurality of pixel circuits respectively disposed in the pixel region, wherein each of the pixel circuits includes: a first transistor having a gate for receiving a scan signal, a source for receiving the data signal, and a drain connected to the first a second transistor having a gate for receiving the scan signal, a source connected to the reference voltage, a drain connected to the second node, and a storage capacitor connected to the first node and the first a third transistor having a gate connected to the second node, a source connected to the first node, and a fourth transistor having a gate for receiving a signal opposite to the scan signal, a source connected to the first voltage, a drain connected to the first node, a fifth transistor having a gate for receiving the illuminating signal, a source connected to the
  • the display further includes: a source driving circuit connected to the plurality of data lines for providing the data signal; and a gate driving circuit connecting the plurality of scanning lines for providing a scan signal; a lookup table associated with storing different threshold voltage values and corrected data voltage values corresponding to different gray levels of each threshold voltage value; a data adjuster coupled to the lookup table and the source The image signals are adjusted between the pole drive circuits based on the obtained corrected data voltage values to obtain corresponding data signals.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are PMOS type thin film transistors; the light emitting component is an organic light emitting diode .
  • a threshold voltage compensation method for a pixel circuit comprising: providing a scan signal to cause said first transistor and said second transistor in a first interval Disconnect, provide one a precharge voltage precharging a stray capacitance in the pixel circuit; in a second interval, providing a scan signal to turn on the first transistor and the second transistor to turn off the fourth transistor Turning on, detecting, by the stray capacitance and the storage capacitor, a threshold voltage of the third transistor; and in a third interval, providing a scan signal to disconnect the first transistor and the second transistor, Outputting the threshold voltage of the third transistor detected by the stray capacitance, and adjusting the image signal by searching for the corrected data voltage value corresponding to the threshold voltage value, at the first interval, the second interval, and In the third interval, an illumination control signal is provided to cause the fifth transistor to be continuously turned on.
  • the method further includes: after writing the corresponding data signal to the pixel circuit, providing an illumination control signal to turn on the fifth transistor to achieve current shunting with the illumination assembly.
  • the pixel circuit of the embodiment of the invention has a simple structure and can compensate for the threshold voltage of the driving transistor in the pixel circuit. Moreover, due to the fourth transistor provided, the pixel circuit can be applied not only to SE-driven large-sized displays, but also to PE-driven small and medium-sized displays, and has a wide application range. In addition, due to the fifth transistor provided, no matter how the resistance of the OLED increases, the current flowing through the OLED does not change, increasing the service life of the circuit.
  • the threshold voltage compensation method in the embodiment of the present invention can solve the problem of image sticking and color unevenness caused by the threshold voltage shift, thereby improving the uniformity of the display panel.
  • FIG. 1 is a schematic structural diagram of a pixel circuit in a conventional OLED display technology
  • FIG. 2 is a schematic structural diagram of an AMOLED display according to an embodiment of the invention.
  • FIG. 3 is a schematic structural diagram of an AMOLED display panel according to an embodiment of the invention.
  • FIG. 4 is a schematic structural diagram of a pixel circuit of an AMOLED display panel according to an embodiment of the invention.
  • FIG. 5 is a schematic diagram of normal illumination of a pixel circuit after writing a data voltage according to an embodiment of the invention
  • FIG. 6 is an equivalent circuit diagram of the pixel circuit shown in FIG. 5;
  • FIG. 8 is a timing diagram of system compensation for a pixel region P according to an embodiment of the invention.
  • 9A to 9C are explanatory diagrams of switching states and current directions of the pixel circuit shown in FIG. 4 in different time periods during system compensation;
  • FIG. 10 is a schematic structural view of the source driving circuit 20 shown in FIG. 2;
  • FIG. 11 is a schematic diagram showing the internal configuration of the lookup table 40 shown in FIG. 2.
  • FIG. 2 is a schematic block diagram of an AMOLED display according to an embodiment of the invention.
  • the AMOLED display includes an AMOLED panel 10, a timing controller 30, and a source driving circuit 20.
  • the AMOLED display further includes a gate drive circuit (not shown).
  • the gate driving circuit provides a scan signal to the AMOLED panel 10.
  • the source driving circuit 20 supplies the voltage data Vdata to the AMOLED panel 10.
  • FIG. 3 is a schematic structural diagram of an AMOLED display panel 10 according to an embodiment of the invention.
  • the AMOLED panel 10 includes a plurality of scanning lines GL1 to GLn, a plurality of data lines DL1 to DLm, a plurality of first power supply lines PL1 to PLm, and a plurality of second power supply lines PL'1 to PL'm.
  • the AMOLED panel 10 further includes a plurality of signal lines (not shown in the drawings).
  • the plurality of pixel regions P shown in FIG. 3 are determined by orthogonally crossing the scan lines GL1 GL GLn and the data lines DL1 DL DLn, and these pixel regions P may be arranged in a matrix.
  • Each pixel area P is associated with a corresponding scan line, The data line, the first power line, and the second power line are connected.
  • each pixel region P receives a scan signal Scan, a data voltage Vdata, and a first power supply voltage (system high voltage) VDD and a second power supply voltage (system low voltage) VSS. More specifically, the scan signal Scan is supplied to the pixel region P through the scan lines GL1 to GLn, and the data voltage Vdata is supplied to the pixel region P through the data lines DL1 to DLn. At the same time, the system high voltage VDD and the system low voltage VSS are supplied to the pixel region P through the first power supply lines PL1 to PLm and the second power supply lines PL'1 to PL'm, respectively.
  • system high voltage VDD and the system low voltage VSS are supplied to the pixel region P through the first power supply lines PL1 to PLm and the second power supply lines PL'1 to PL'm, respectively.
  • the detection voltage Vsense includes the threshold voltage Vth of the pixel region obtained from the pixel region P.
  • the detection voltage Vsense is applied from the pixel region P to the outside, for example, to the source driving circuit 20 shown in FIG. 2 through the data lines DL1 to DLm, or to the detection controller independent of the source driving circuit 20.
  • FIG. 4 is a schematic diagram of a pixel circuit of an AMOLED display panel according to an embodiment of the present invention.
  • the pixel circuit of each pixel region P includes: first to fifth transistors T1 to T5, a storage capacitor Cst, and An organic light emitting diode OLED.
  • the capacitor Cload in FIG. 4 schematically represents the stray capacitance (parasitic capacitance) inside the circuit.
  • the first transistor T1 and the second transistor T2 are switching transistors for transmitting signals.
  • the third transistor T3 is a driving transistor for generating a driving current for driving the OLED.
  • the fourth transistor T4 is used to turn the system high voltage VDD on or off.
  • the fifth transistor T5 is used to reduce the effects of OLED degradation to increase the lifetime of the pixel circuit.
  • the storage capacitor Cst is mainly used to keep the data voltage Vdate constant for one frame period.
  • the OLED emits light of different brightness as the intensity of the driving current changes.
  • the OLED includes a red OLED that emits red light, a green OLED that emits green light, and a blue OLED that emits blue light.
  • the first to fifth transistors T1 to T5 may be turned on by a low level signal and turned off by a high level signal.
  • the high level can be a ground voltage or a voltage close to ground voltage.
  • the low voltage can be a voltage lower than the ground voltage. For example, low and high levels can be -10V and 0V, respectively.
  • the gate of the first transistor T1 is connected to the scan line GL to which the scan signal Scan is applied, the source of the first transistor T1 is connected to the data line DL, and the drain of the first transistor T1 is connected to the first node 1. .
  • the first transistor T1 can be turned on by the scan signal Scan applied to the scan line GL, and charges the data voltage Vdata for displaying a picture through the data line DL to the first node 1.
  • the first node 1 is a node that connects the drain of the first transistor T1, one end of the storage capacitor Cst, the source of the third transistor T3, and the drain of the fourth transistor T4.
  • the gate of the second transistor T2 is connected to the scan line GL that supplies the scan signal Scan.
  • the source of the second transistor T2 is connected to a reference line that supplies the reference voltage Vref.
  • the drain of the second transistor T2 is connected to the second node 2.
  • the second transistor T2 is turned on by the scan signal Scan applied to the scan line GL, and discharges the second node 2 to the reference voltage Vref.
  • the second node 2 is connected to the drain of the second transistor T2, the other end of the storage capacitor Cst, and the gate of the third transistor T3.
  • the storage capacitor Cst is connected between the first node and the second node.
  • the storage capacitor Cst changes the voltage of the second node 2 as the voltage of the first node 1 changes.
  • the gate of the third transistor T3 is connected to the second node.
  • the source of the third transistor T3 is connected to the drain of the fourth transistor T4.
  • the third transistor T3 generates a drive current that varies with the voltage of the second node. And, the third transistor T3 applies a driving current to the OLED. The OLED emits light by a current from the third transistor T3.
  • the gate of the fourth transistor T4 is connected to the scan line GL that supplies the scan signal Scan.
  • the source of the fourth transistor T4 is connected to the first power line PL (voltage VDD). It should be noted that, in this embodiment, the transistor T4 receives a reverse scan signal opposite to the scan signal Scan. Of course, in other embodiments, the scan signal Scan can also be directly received.
  • the pixel circuit of this embodiment is not only suitable for the OLED display with the driving mode of SE driving, but also for the driving mode of PE. Driven OLED display.
  • SE drive means that all pixel areas of the entire panel emit light together after all scanning signals are transmitted.
  • the progressive illuminating means that when the scanning signal Scan(N+1) is generated, the pixel corresponding to the scanning signal Scan N starts to emit light.
  • the fifth transistor T5 controls the on and off of the driving transistor T3 and the OLED.
  • the gate of the fifth transistor T5 is connected to the light emission control signal Em, the drain thereof is connected to the anode of the OLED, and the source thereof is connected to the drain of the driving transistor T3.
  • the cathode of the OLED is connected to the second power source line PL' (VSS).
  • an output resistor Rout (shown in FIG. 5) connected in parallel with the OLED is indirectly added to the pixel circuit.
  • Fig. 6 is an equivalent circuit diagram when the pixel circuit after the data voltage is written normally emits light. As shown in FIG. 6, since the output resistance Rout is connected in parallel with the OLED, the current of the OLED is Therefore, as long as the resistance Rout>>R OLED is output, the current flowing through the OLED is constant regardless of the increase in the resistance R OLED of the OLED , so that the life of the pixel circuit can be prolonged.
  • the resistance R OLED of the degraded OLED has an increasing tendency compared to that before the OLED is degraded, and therefore, the current flowing through the OLED is gradually reduced.
  • the fifth transistor T5 by providing the fifth transistor T5, the influence of the degradation of the OLED on the current flowing through the OLED can be reduced, and the life of the pixel circuit is prolonged. It should be noted that, in the process of driving the OLED to emit light, the fifth transistor T5 is turned on after each writing of the data voltage in the pixel region P.
  • FIG. 8 is a timing chart for threshold voltage compensation of the pixel circuits in the pixel region P shown in FIG.
  • the pixel circuit disposed in the pixel region is compensated according to three time intervals. During this compensation period, the light emission control signal Em continues to be in a low level state, so that the fifth transistor is Continuous conduction.
  • the first interval "9A" in the figure corresponds to the circuit state of FIG. 9A
  • the second interval "9B” corresponds to the circuit state of FIG. 9B
  • the third interval "9C” corresponds to the circuit state of FIG. 9C.
  • a precharge voltage is provided to precharge the stray capacitance Cload existing in the pixel circuit.
  • the threshold voltage Vth of the driving transistor is detected by the stray capacitance Cload and the storage capacitance Cst.
  • the threshold voltage of the driving transistor T3 detected by the stray capacitance Cload is output, and the image signal is adjusted by finding the corrected data voltage value corresponding to the current threshold voltage value.
  • a high-level scan signal Scan is supplied onto the scan line GL such that the first transistor T1 and the second transistor T2 are turned off.
  • a precharge voltage Vpre is supplied to precharge the stray capacitance Cload.
  • a low level scan signal Scan is supplied onto the scan line GL such that the first transistor T1 and the second transistor T2 are turned on.
  • the scan signal opposite to the scan signal Scan The fourth transistor T4 is turned off.
  • the precharge voltage Vpre charged to the stray capacitance Cload is charged to the first node 1 via the first transistor T1, and the reference voltage Vref is charged to the second node 2 through the second transistor T2.
  • . Then, the voltage Vs of the first node 1 is charged into the stray capacitance Cload through the first transistor T1. In other words, during this period, the threshold voltage Vth of the third transistor T3 is detected, and the voltage value of the final stray capacitance Cload is: Vcload Vref+
  • a high level scan signal Scan is supplied onto the scan line GL.
  • the high level of the scan signal Scan causes the first transistor T1 and the second transistor T2 to be turned off.
  • the voltage value of the stray capacitance Cload is output to an external system. For example, Vref+
  • FIG. 10 is a block diagram showing the structure of the source driving circuit 20 shown in FIG. 2.
  • the source driving circuit 20 includes a selector 21, a digital-to-analog converter (DAC) 23, and an analog-to-digital converter (ADC) 25.
  • DAC digital-to-analog converter
  • ADC analog-to-digital converter
  • the digital-to-analog converter 23 is capable of converting a digital signal corresponding to the digital signal R, G or B into a data voltage Vdata of an analog signal.
  • the analog-to-digital converter 25 converts the detection signal Vsense of the analog data obtained from the pixel region P into the detection information Vsense' of the digital signal.
  • the selector 21 is electrically connected to the digital to analog converter 23 or the analog to digital converter 25 through the data lines DL1 to DLn of the AMOLED panel 10.
  • the selector 21 When the OLED of the pixel region is normally illuminated, for example, the selector 21 has a low level in response to a certain selection signal, and is electrically connected to the digital-to-analog converter 23 through the data lines DL1 to DLm. In addition, when system compensation is performed on the pixel circuit, for example, the selector 21 may have a high level in response to the selection signal to be electrically connected to the analog-to-digital converter 25 through the data lines DL1 to DLm.
  • the detection signal Vsense as an analog signal is applied to the selector 21 through the data lines DL1 to DLn.
  • the selector 21 responds to the selection signal having a high level to electrically connect the analog-to-digital converter 25 through the data lines DL1 to DLm. Therefore, the analog signal Vsense is applied to the analog to digital converter 25. Further, the analog signal Vsense is converted into a digital signal Vsense' for the current threshold voltage Vth. The converted digital signal Vsense' is applied to the timing controller 30 in FIG.
  • the timing controller 30 includes a data adjuster 31.
  • the timing controller 30 receives the digital signal Vsense' for the threshold voltage, from the current threshold voltage value, from the lookup
  • the voltage value Vdata" corrected in the corresponding gray scale is obtained in the table (LUT) 40.
  • the lookup table 40 of the present embodiment associates different threshold voltage values and corrected data corresponding to different gray levels under the threshold voltage value. Voltage value. That is, the compensation method of the pixel circuit is directly compensated based on the threshold voltage Vth of the current third transistor T3 that is returned. Instead of performing the offset calculation based on the threshold voltage Vth of the read drive transistor as in the prior art, the offset value ⁇ Vth of the threshold voltage is obtained and compensated.
  • the threshold voltage Vth is compensated according to the offset value ⁇ Vth, and only the imaging spiking problem caused by the shift of the threshold voltage Vth can be reduced.
  • the method of the embodiment can not only solve the image sticking problem, but also solve the problem of the color spot caused by the shift of the threshold voltage Vth and increase the uniformity of the panel display.
  • the present embodiment does not require an offset calculator and an offset controller as compared with the prior art, which can reduce hardware resource consumption.
  • the data adjuster 31 adjusts based on the obtained corrected voltage value to obtain an image signal R'G'B'.
  • the corrected data voltage Vdata of a single frame is applied to the data adjuster 33.
  • the data adjuster 33 adjusts the first image signal RGB and outputs the adjusted second image signal R'G'B'. Then, the second image signal R'G'B' is applied to the OLED panel 10. Therefore, the compensated image shows no non-uniform brightness.
  • timing controller 30 is also used to generate some other control signals, and details are not described herein again.
  • the pixel circuit of this embodiment has a simple structure. Due to the fourth transistor provided, the pixel circuit can be applied not only to SE-driven large-size displays, but also to PE-driven small- and medium-sized displays, and has a wide application range. In addition, due to the fifth transistor provided, no matter how the resistance of the OLED increases, the current flowing through the OLED does not change, increasing the service life of the pixel circuit. Moreover, the threshold voltage compensation method of the present embodiment can simultaneously solve the image sticking and color spot problems caused by the threshold voltage shift, and enhance the uniformity of the display panel.

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Abstract

一种像素电路、具备该像素电路的显示面板和显示器，该像素电路包括：第一晶体管（T1）、第二晶体管（T2）、第三晶体管（T3）、第四晶体管（T4）和第五晶体管（T5）。具有阈值电压补偿功能的像素电路能够延长电路的寿命，该像素电路不仅适用于SE驱动的大尺寸的显示器，而且也适用于PE驱动的中小尺寸的显示器。

Description

像素电路、具备该像素电路的显示面板和显示器
本申请要求享有2014年7月7日提交的名称为“像素电路、具备该像素电路的显示面板和显示器”的中国专利申请CN201410321425.2的优先权，其全部内容通过引用并入本文中。
技术领域
本发明涉及显示器技术领域，尤其涉及有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)显示器，具体地说，是涉及一种像素电路、具备该像素电路的显示面板和显示器。
背景技术
继薄膜晶体管液晶显示器(TFT-LCD)之后，有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)面板被认为是最有发展前途的新一代显示面板。相比传统的液晶显示面板，AMOLED面板具有结构轻薄简单、自发光无需背光源、广视角、影像色泽美丽、可弯曲等优势。
一般，AMOLED面板的每个像素电路均配备有开关功能的低温多晶硅薄膜晶体管(Low Temperature Poly-Si Thin Film Transistor，LT P-Si TFT)和一个电荷存储电容，而且，AMOLED面板的外围驱动电路和显示阵列被集成在同一玻璃基板上。
在制作AMOLED面板的过程中，激光扫描模式被广泛应用在结晶工艺中，由于这种激光束的功率的不稳定性，导致形成在使用此种激光束扫描得到的扫描线上的薄膜晶体管可能具有彼此不同的阈值电压的缺陷，进而会引起多个像素区域的图像质量不一致的问题。
图1为现有的OLED显示技术中的像素电路100的结构(2T1C)示意图。有关像素电路100的驱动方法如下：在扫描线SL接收扫描信号Vscan而使薄膜晶体管T1导通的状态下，数据线DL接收数据信号Vdata，使该数据信号Vdata经由薄膜晶体管T1存储在电容Cc中；在扫描线SL接收扫描信号Vscan而使薄膜晶体管T1关闭的状态下，薄膜晶体管T2持续导通，而将存储在电容Cc的电压施加给该像素电路的OLED，以产生驱动 该OLED发光的驱动电流Ioled。
然而，在上述这种像素电路中，由于薄膜晶体管T2长时间处于正偏压驱动状态下，因此会产生薄膜晶体管T2的阈值电压Vth漂移的现象。一旦出现薄膜晶体管T2的阈值电压Vth漂移的情况，就会直接影响流经OLED的驱动电流Ioled的大小。基于此，对于OLED显示技术中的各像素电路而言，反映相同数据信号Vdata的流经各像素电路的OLED的电流大小会不相同，这样会导致各像素电路中的OLED所呈现的灰阶也不相同，进而影响OLED面板显示的均匀性。
为了解决上述问题，现有技术提供了一种具有补偿功能的3T1C结构的像素电路，但是其仅适用于驱动方式为同步发光(Simultaneous Emission，简称SE)的大尺寸的OLED显示器，不能应用在渐进发光(Progressive Emission，简称PE)驱动的OLED显示器中。
因此，如何解决上述问题乃业界所致力的课题之一。
发明内容
本发明所要解决的技术问题之一是需要提供一种像素电路，其能够解决阈值电压偏移的问题，进而延长电路寿命，并且该像素电路可以应用在渐进发光驱动的OLED显示器中，也可以应用在同步发光驱动的OLED显示器中。
为了解决上述技术问题，本发明提供了一种像素电路，包括：第一晶体管，其栅极用以接收扫描信号，其源极用以接收数据信号，其漏极连接至第一节点；第二晶体管，其栅极用以接收所述扫描信号，其源极连接至参考电压，其漏极连接至第二节点；存储电容，其连接在所述第一节点和所述第二节点之间；第三晶体管，其栅极连接至所述第二节点，其源极连接至所述第一节点；第四晶体管，其栅极用以接收与所述扫描信号相反的信号，其源极连接至第一电压，其漏极连接至所述第一节点；第五晶体管，其栅极用以接收发光信号，其源极连接所述第三晶体管的漏极；发光组件，其阳极连接所述第五晶体管的漏极，其阴极连接至第二电压，所述第二电压低于所述第一电压。
在一个实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管以及所述第五晶体管为PMOS型的薄膜晶体管；所述发光组件为有机发光二极管。
根据本发明另一方面，还提供了一种显示面板，包括：多条数据线；多条扫描线，与所述多条数据线正交交错配置形成多个像素区域；多个像素电路，分别配置于各个像素区 域内，且每个像素电路包括：第一晶体管，其栅极用以接收扫描信号，其源极用以接收数据信号，其漏极连接至第一节点；第二晶体管，其栅极用以接收所述扫描信号，其源极连接至参考电压，其漏极连接至第二节点；存储电容，其连接在所述第一节点和所述第二节点之间；第三晶体管，其栅极连接至所述第二节点，其源极连接至所述第一节点；第四晶体管，其栅极用以接收与所述扫描信号相反的信号，其源极连接至第一电压，其漏极连接至所述第一节点；第五晶体管，其栅极用以接收发光控制信号，其源极连接所述第三晶体管的漏极；发光组件，其阳极连接所述第五晶体管的漏极，其阴极连接至第二电压，所述第二电压低于所述第一电压。
在一个实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管以及所述第五晶体管为PMOS型的薄膜晶体管；所述发光组件为有机发光二极管。
根据本发明的另一方面，还提供了一种显示器，包括：显示面板，其包括：多条数据线；多条扫描线，与所述多条数据线正交交错配置形成多个像素区域；多个像素电路，分别配置于所述像素区域内，其中，每个像素电路包括：第一晶体管，其栅极用以接收扫描信号，其源极用以接收数据信号，其漏极连接至第一节点；第二晶体管，其栅极用以接收所述扫描信号，其源极连接至参考电压，其漏极连接至第二节点；存储电容，其连接在所述第一节点和所述第二节点之间；第三晶体管，其栅极连接至所述第二节点，其源极连接至所述第一节点；第四晶体管，其栅极用以接收与所述扫描信号相反的信号，其源极连接至第一电压，其漏极连接至所述第一节点；第五晶体管，其栅极用以接收发光信号，其源极连接所述第三晶体管的漏极；发光组件，其阳极连接所述第五晶体管的漏极，其阴极连接至第二电压，所述第二电压低于所述第一电压。
在一个实施例中，该显示器还包括：源极驱动电路，其连接所述多条数据线，用以提供所述数据信号；栅极驱动电路，其连接所述多条扫描线，用以提供所述扫描信号；查找表，其关联存储不同的阈值电压值和对应每个阈值电压值的不同灰阶的修正后的数据电压值；数据调整器，其连接在所述查找表和所述源极驱动电路之间，基于所得到的修正后的数据电压值对图像信号进行调整，以得到对应的数据信号。
在一个实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管以及所述第五晶体管为PMOS型的薄膜晶体管；所述发光组件为有机发光二极管。
根据本发明的另一方面，还提供了一种如上所述的像素电路的阈值电压补偿方法，包括：在第一间隔中，提供一扫描信号以使所述第一晶体管和所述第二晶体管断开，提供一 预充电电压对所述像素电路中的杂散电容进行预充电；在第二间隔中，提供一扫描信号以使所述第一晶体管和所述第二晶体管导通、使所述第四晶体管断开，通过所述杂散电容和所述存储电容来检测所述第三晶体管的阈值电压；在第三间隔中，提供一扫描信号以使所述第一晶体管和所述第二晶体管断开，将所述杂散电容检测到的所述第三晶体管的阈值电压输出，通过查找与阈值电压值对应的修正后的数据电压值对图像信号进行调整，在所述第一间隔、第二间隔和第三间隔中，提供一发光控制信号使所述第五晶体管持续导通。
在一个实施例中，该方法还包括：在对所述像素电路写入相应的数据信号后，提供一发光控制信号以使所述第五晶体管导通，实现与所述发光组件的电流分流。
与现有技术相比，本发明的一个或多个实施例可以具有如下优点：
本发明实施例的像素电路结构简单，可以补偿像素电路中的驱动晶体管的阈值电压。而且，由于所设置的第四晶体管，该像素电路不仅可以适用于SE驱动的大尺寸显示器，而且适用于PE驱动的中小尺寸显示器，其应用范围较广。另外，由于所设置的第五晶体管，不论OLED的电阻如何增加，流经OLED的电流都不变，增加了电路的使用寿命。
另外，本发明实施例的阈值电压补偿方法能够解决阈值电压偏移所产生的影像残留和色斑的问题，进而提高显示面板的均匀性。
本发明的其他优点、目标，和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书，权利要求书，以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例共同用于解释本发明，并不构成对本发明的限制。在附图中：
图1是现有的OLED显示技术中的像素电路的结构示意图；
图2是根据本发明一实施例的AMOLED显示器的结构示意图；
图3是根据本发明一实施例的AMOLED显示面板的结构示意图；
图4是根据本发明一实施例的AMOLED显示面板的像素电路的结构示意图；
图5是根据本发明一实施例的写完数据电压后的像素电路正常发光的示意图；
图6是图5所示像素电路的等效电路图；
图7是OLED在初始状态和经长时间操作退化后的电流电压的特性曲线图；
图8是根据本发明一实施例的对像素区域P进行系统补偿的时序图；
图9A至图9C是在系统补偿过程中不同时间段内图4所示像素电路的开关状态和电流走向说明图；
图10是图2所示的源极驱动电路20的结构示意图；
图11是图2所示的查找表40的内部配置示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明作进一步地详细说明。
需要说明的是，在本发明的实施例中，容易理解，当元件，例如基板、层、区域、薄膜或电极，形成在另一元件的“上”或“下”时，它可以直接在另一元件的上部或下部，或者存在一间隔元件、非直接地在位于另一元件的上部或下部。另外，为了清楚和便于说明，附图中的元件的尺寸和厚度可被放大、省略或简化，并且附图所示的元件大小不为元件的实际尺寸。
图2是根据本发明一实施例的AMOLED显示器的大概结构示意图。
请参考图2，该AMOLED显示器包括AMOLED面板10、时序控制器30、源极驱动电路20。另外，该AMOLED显示器还包括栅极驱动电路(未图示)。
其中，栅极驱动电路提供扫描信号至AMOLED面板10中。源极驱动电路20提供电压数据Vdata至AMOLED面板10中。
图3是根据本发明一实施例的AMOLED显示面板10的结构示意图。如图3所示，AMOLED面板10包括多条扫描线GL1～GLn，多条数据线DL1～DLm，多条第一电源线PL1～PLm和多条第二电源线PL′1～PL′m。另外，AMOLED面板10进一步包括多条信号线(未在图中示出)。
图3中所示的多个像素区域P由扫描线GL1～GLn和数据线DL1～DLn彼此正交交叉而确定，这些像素区域P可以被配置在矩阵中。每一个像素区域P均与对应的扫描线、 数据线、第一电源线和第二电源线连接。
如图3所示，每个像素区域P接收一扫描信号Scan、一数据电压Vdata以及第一电源供给电压(系统高电压)VDD和第二电源供给电压(系统低电压)VSS。更具体地，扫描信号Scan通过扫描线GL1～GLn被提供给像素区域P，数据电压Vdata通过数据线DL1～DLn被提供给像素区域P。同时，系统高电压VDD和系统低电压VSS分别通过第一电源线PL1～PLm和第二电源线PL′1～PL′m提供给像素区域P。
另外，检测电压Vsense包括从像素区域P获得的像素区域的阈值电压Vth。检测电压Vsense从像素区域P被施加到外部，例如通过数据线DL1～DLm施加到图2所示的源极驱动电路20中，或者施加到独立于源极驱动电路20的检测控制器中。
图4是根据本发明一实施例的AMOLED显示面板的像素电路示意图，如图4所示，每个像素区域P的像素电路包括：第一晶体管至第五晶体管T1～T5、一存储电容Cst和一有机发光二极管OLED。需要说明的是，图4中的电容Cload示意性地表示电路内部的杂散电容(寄生电容)。
其中，第一晶体管T1和第二晶体管T2是用于传递信号的开关晶体管。第三晶体管T3为用于产生驱动OLED的驱动电流的驱动晶体管。第四晶体管T4用来开启或关闭系统高电压VDD。第五晶体管T5用来降低OLED退化所带来的影响，以增加像素电路的寿命。
存储电容Cst主要用于保持数据电压Vdate在一个帧周期不变。
OLED随着驱动电流的强度变化而发射不同的亮度的光。该OLED包括发射红光的红色OLED、发射绿光的绿色OLED和发射蓝光的蓝色OLED。
这五个晶体管可以是PMOS型的薄膜晶体管。第一晶体管T1至第五晶体管T5可以被一低电平信号导通，被一高电平信号截止。高电平可以为一地电压或一接近地电压的电压。低电压可以为一比地电压低的电压。例如，低电平和高电平可以分别为-10V和0V。
如图4所示，第一晶体管T1的栅极连接至施加扫描信号Scan的扫描线GL，第一晶体管T1的源极连接至数据线DL，第一晶体管T1的漏极连接至第一节点1。
第一晶体管T1可以被施加在扫描线GL的扫描信号Scan开启，并使通过数据线DL的用于显示画面的数据电压Vdata充电至第一节点1。第一节点1为连接第一晶体管T1的漏极、存储电容Cst的一端、第三晶体管T3的源极以及第四晶体管T4的漏极的节点。
第二晶体管T2的栅极连接在提供扫描信号Scan的扫描线GL上。第二晶体管T2的源极被连接在提供参考电压Vref的参考线上。第二晶体管T2的漏极被连接在第二节点2上。第二晶体管T2通过施加在扫描线GL的扫描信号Scan而开启，并使第二节点2放电至参考电压Vref。第二节点2连接了第二晶体管T2的漏极、存储电容Cst的另一端以及第三晶体管T3的栅极。存储电容Cst连接在第一节点和第二节点之间。存储电容Cst使第二节点2的电压随着第一节点1的电压的变化而变化。
第三晶体管T3的栅极连接第二节点。第三晶体管T3的源极连接第四晶体管T4的漏极。
第三晶体管T3产生随第二节点电压变化的驱动电流。并且，第三晶体管T3将驱动电流施加至OLED中。OLED通过来自第三晶体管T3的电流来发光。
第四晶体管T4的栅极连接在提供扫描信号Scan的扫描线GL上。第四晶体管T4的源极连接第一电源线PL(电压VDD)。需要说明的是，在本实施例中，该晶体管T4接收到与扫描信号Scan相反的反向扫描信号
Figure PCTCN2014086894-appb-000001
当然，在其他实施例中，也可以直接接收扫描信号Scan。
在本实施例中，在检测第三晶体管T3的阈值电压期间，通过使第四晶体管T4断开间接关闭系统高电压VDD的方式，来避免系统高电压VDD对阈值电压补偿所带来的影响。相比现有技术的在系统补偿过程中必须直接关掉系统高电压VDD的这种方式，本实施例的像素电路不仅适用于驱动方式为SE驱动的OLED显示器，而且也适用于驱动方式为PE驱动的OLED显示器。所谓SE驱动是指在发送所有扫描信号完后，整个面板的所有像素区域一起发光。而渐进发光也就是在在扫描信号Scan(N+1)产生时，对应扫描信号Scan N的像素开始发光。
第五晶体管T5控制驱动晶体管T3与OLED的通断。该第五晶体管T5的栅极连接发光控制信号Em、其漏极连接至OLED的阳极、其源极与驱动晶体管T3的漏极连接。另外，OLED的阴极连接至第二电源线PL′(VSS)。
通过设置第五晶体管T5，间接地在像素电路中增加了一个与OLED并联的输出电阻Rout(如图5所示)。
图6是关于写完数据电压后的像素电路正常发光时的等效电路图。如图6所示，由于输出电阻Rout与OLED并联，使得OLED的电流为
Figure PCTCN2014086894-appb-000002
因此，只要 输出电阻Rout＞＞ROLED，那么不论OLED的电阻ROLED如何增加，流经OLED的电流均不变，这样就能够延长像素电路的寿命。
正如图7所示，相比OLED退化前，退化后的OLED的阻值ROLED呈增大趋势，因此，流经该OLED的电流会逐渐变小。在本发明实施例中，通过设置第五晶体管T5，能够降低OLED的退化对流经OLED的电流的影响，延长像素电路的寿命。需要说明的是，在驱动OLED发光的过程中，第五晶体管T5是在每次像素区域P写完数据电压之后导通的。
图8为对图4所示的像素区域P内像素电路进行阈值电压补偿的时序图。
如图8所示，在本实施例中是根据三个时间间隔来对配置在像素区域中的像素电路进行补偿，在这个补偿期间，发光控制信号Em持续处于低电平状态，使第五晶体管持续导通。图中的第一间隔“9A”与图9A的电路状态相对应，第二间隔“9B”与图9B的电路状态相对应，第三间隔“9C”与图9C的电路状态相对应。
其中，在第一间隔9A中，提供一预充电电压对该像素电路中存在的杂散电容Cload进行预充电。在第二间隔9B中，通过杂散电容Cload和存储电容Cst来检测驱动晶体管的阈值电压Vth。在第三间隔9C中，将杂散电容Cload检测到的驱动晶体管T3的阈值电压输出，通过查找与当前阈值电压值对应的修正后的数据电压值对图像信号进行调整。
下面将参考图8、图9A至图9C，详细说明在这三个期间中，像素区域中的像素电路的运作情况。
<第一间隔>
在第一间隔9A中，如图8所示，提供一高电平扫描信号Scan至扫描线GL上，使得第一晶体管T1和第二晶体管T2断开。并且，如图9A中的虚线所示，提供一预充电电压Vpre对杂散电容Cload进行预充电。
<第二间隔9B>
在第二间隔9B中，提供一低电平的扫描信号Scan到扫描线GL上，使得第一晶体管T1和第二晶体管T2导通。在此期间，与扫描信号Scan相反的扫描信号
Figure PCTCN2014086894-appb-000003
使第四晶体管T4断开。随后，充电至杂散电容Cload的预充电压Vpre经由第一晶体管T1充电至第一节点1处，而且参考电压Vref通过第二晶体管T2充电至第二节点2处。
而且，在第二间隔9B中，第一节点1的电压Vs(此时为Vpre)向第三晶体管T3充 电，直到第三晶体管T3达到阈值电压Vth。在第三晶体管T3达到阈值电压的一瞬间，第一节点1的电压Vs＝Vref+|Vth|。然后，第一节点1的电压Vs通过第一晶体管T1充电至杂散电容Cload中。换言之，在该期间，第三晶体管T3的阈值电压Vth被检测到，最终杂散电容Cload的电压值为：Vcload＝Vref+|Vth|。
<第三间隔9C>
在该期间，提供一高电平的扫描信号Scan到扫描线GL上，如图9C所示，扫描信号Scan的高电平使得第一晶体管T1和第二晶体管T2断开。杂散电容Cload的电压值被输出到外部系统中。例如，通过数据线DL将Vref+|Vth|作为检测信号Vsense施加到图10所示的选择器21中，通过选择器21提取出第三晶体管的阈值电压。
图10是图2所示的源极驱动电路20的结构示意图，该源极驱动电路20包括选择器21、数模转换器(DAC)23和模数转换器(ADC)25。
数模转换器23能够将对应数字信号R、G或B的数字信号转换成模拟信号的数据电压Vdata。
模数转换器25将从像素区域P得到的模拟数据的检测信号Vsense转换成数字信号的检测信息Vsense′。
选择器21通过AMOLED面板10的数据线DL1～DLn电连接至数模转换器23或模数转换器25。
在使像素区域的OLED正常发光时，例如，选择器21响应某一选择信号而具有低电平，通过数据线DL1～DLm被电连接至数模转换器23。另外，在对像素电路进行系统补偿时，例如选择器21可以响应选择信号而具有高电平，以通过数据线DL1～DLm被电连接至模数转换器25。
在第三间隔P3中，作为模拟信号的检测信号Vsense通过数据线DL1～DLn施加到选择器21中。选择器21响应具有高电平的选择信号以通过数据线DL1～DLm电连接模数转换器25。因此，模拟信号Vsense被施加到模数转换器25中。进一步，模拟信号Vsense被转换为针对当前阈值电压Vth的数字信号Vsense′。经转换的数字信号Vsense′被施加到图2中的时序控制器30中。
如图2所示，时序控制器30包括数据调整器31。
时序控制器30接收针对阈值电压的数字信号Vsense′，根据当前阈值电压值，从查找 表(LUT)40中得到在对应灰阶下修正后的电压数值Vdata"。
需要说明的是，与现有技术不同的是，本实施例的查找表40，如图11所示，其关联存储不同的阈值电压值和对应该阈值电压值下不同灰阶的修正后的数据电压值。也就是说，该像素电路的补偿方法是根据被返回来的当前第三晶体管T3的阈值电压Vth来直接进行补偿。而不是像现有技术那样，根据读回的驱动晶体管的阈值电压Vth，进行偏移计算，得到阈值电压的偏移值ΔVth来进行补偿。
现有技术中根据偏移值ΔVth来补偿阈值电压Vth，只能降低由阈值电压Vth偏移所带来的影像残留(imaging spiking)问题。而本实施例方法不仅可以解决影像残留问题，还可以解决由阈值电压Vth偏移所带来的色斑问题，增加面板显示的均匀度。
另外，由于该查找表内部的配置模式，本实施例相比现有技术来说，不需要偏移计算器和偏移控制器，这样可以降低硬体资源消耗。
数据调整器31基于所得到的修正后的电压数值进行调整得到图像信号R′G′B′。
例如，将单个帧的修正后的数据电压Vdata施加到数据调整器33中。这样，数据调整器33对第一图像信号RGB进行调整，输出调整后的第二图像信号R′G′B′。然后，第二图像信号R′G′B′被施加到OLED面板10中。因此，补偿后的图像显示不会出现非一致性的亮度。
当然，时序控制器30还用来产生一些其他的控制信号，在此不再赘述。
本实施例的像素电路结构简单，由于所设置的第四晶体管，该像素电路不仅可以适用于SE驱动的大尺寸显示器，而且适用于PE驱动的中小尺寸显示器，其应用范围较广。另外，由于所设置的第五晶体管，不论OLED的电阻如何增加，流经OLED的电流都不变，增加了像素电路的使用寿命。而且，本实施例的阈值电压补偿方法能够同时解决由阈值电压偏移所产生的影像残留和色斑问题，增强显示面板的均匀度。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉该技术的人员在本发明所公开的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (8)

  1. 一种像素电路，包括：
    第一晶体管，其栅极用以接收扫描信号，其源极用以接收数据信号，其漏极连接至第一节点；
    第二晶体管，其栅极用以接收所述扫描信号，其源极连接至参考电压，其漏极连接至第二节点；
    存储电容，其连接在所述第一节点和所述第二节点之间；
    第三晶体管，其栅极连接至所述第二节点，其源极连接至所述第一节点；
    第四晶体管，其栅极用以接收与所述扫描信号相反的信号，其源极连接至第一电压，其漏极连接至所述第一节点；
    第五晶体管，其栅极用以接收发光信号，其源极连接所述第三晶体管的漏极；
    发光组件，其阳极连接所述第五晶体管的漏极，其阴极连接至第二电压，所述第二电压低于所述第一电压。
  2. 根据权利要求1所述的像素电路，其中，
    所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管以及所述第五晶体管为PMOS型的薄膜晶体管；所述发光组件为有机发光二极管。
  3. 一种显示器，包括：
    显示面板，其包括：多条数据线；多条扫描线，与所述多条数据线正交交错配置形成多个像素区域；多个像素电路，分别配置于所述像素区域内，其中，每个像素电路包括：
    第一晶体管，其栅极用以接收扫描信号，其源极用以接收数据信号，其漏极连接至第一节点；
    第二晶体管，其栅极用以接收所述扫描信号，其源极连接至参考电压，其漏极连接至第二节点；
    存储电容，其连接在所述第一节点和所述第二节点之间；
    第三晶体管，其栅极连接至所述第二节点，其源极连接至所述第一节点；
    第四晶体管，其栅极用以接收与所述扫描信号相反的信号，其源极连接至第一电压，其漏极连接至所述第一节点；
    第五晶体管，其栅极用以接收发光信号，其源极连接所述第三晶体管的漏极；
    发光组件，其阳极连接所述第五晶体管的漏极，其阴极连接至第二电压，所述第二电压低于所述第一电压。
  4. 根据权利要求3所述的显示器，其中，还包括：
    源极驱动电路，其连接所述多条数据线，用以提供所述数据信号；
    栅极驱动电路，其连接所述多条扫描线，用以提供所述扫描信号；
    查找表，其关联存储不同的阈值电压值和对应每个阈值电压值的不同灰阶的修正后的数据电压值；
    数据调整器，其连接在所述查找表和所述源极驱动电路之间，基于所得到的修正后的数据电压值对图像信号进行调整，以得到对应的数据信号。
  5. 根据权利要求3所述的显示器，其中，
    所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管以及所述第五晶体管为PMOS型的薄膜晶体管；所述发光组件为有机发光二极管。
  6. 根据权利要求4所述的显示器，其中，
    所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管以及所述第五晶体管为PMOS型的薄膜晶体管；所述发光组件为有机发光二极管。
  7. 一种像素电路的阈值电压补偿方法，
    所述像素电路，包括：第一晶体管，其栅极用以接收扫描信号，其源极用以接收数据信号，其漏极连接至第一节点；第二晶体管，其栅极用以接收所述扫描信号，其源极连接 至参考电压，其漏极连接至第二节点；存储电容，其连接在所述第一节点和所述第二节点之间；第三晶体管，其栅极连接至所述第二节点，其源极连接至所述第一节点；第四晶体管，其栅极用以接收与所述扫描信号相反的信号，其源极连接至第一电压，其漏极连接至所述第一节点；第五晶体管，其栅极用以接收发光信号，其源极连接所述第三晶体管的漏极；发光组件，其阳极连接所述第五晶体管的漏极，其阴极连接至第二电压，所述第二电压低于所述第一电压，该补偿方法包括：
    在第一间隔中，提供一扫描信号以使所述第一晶体管和所述第二晶体管断开，提供一预充电电压对所述像素电路中的杂散电容进行预充电；
    在第二间隔中，提供一扫描信号以使所述第一晶体管和所述第二晶体管导通、使所述第四晶体管断开，通过所述杂散电容和所述存储电容来检测所述第三晶体管的阈值电压：
    在第三间隔中，提供一扫描信号以使所述第一晶体管和所述第二晶体管断开，将所述杂散电容检测到的所述第三晶体管的阈值电压输出，通过查找与阈值电压值对应的修正后的数据电压值对图像信号进行调整，
    在所述第一间隔、第二间隔和第三间隔中，提供一发光控制信号使所述第五晶体管持续导通。
  8. 根据权利要求7所述的阈值电压补偿方法，其中，还包括：
    在对所述像素电路写入相应的数据信号后，提供一发光控制信号以使所述第五晶体管导通，实现与所述发光组件的电流分流。
PCT/CN2014/086894 2014-07-07 2014-09-19 像素电路、具备该像素电路的显示面板和显示器 WO2016004679A1 (zh)

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