CN111192557A - 一种像素补偿电路及驱动方法 - Google Patents
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Abstract
一种像素补偿电路,包括薄膜晶体管T1、T2、T3、T4、T5,电容C1、C2;所述T1的源极与片上电压VDD连接,漏极与T4的源端连接,栅极与第一扫描信号连接;所述T2的栅极与第二扫描信号连接,源极接数据信号,漏极与T4的栅极和C1的一端连接,所述C1的另一端与T3的源极连接,T3的栅极与第二扫描信号连接,C1的另一端还通过C2与T4的漏极连接,T4的漏极还与发光子像素的正极连接,发光子像素的负极还与T3的漏极连接后接地或接片上低电压;发光子像素的正极还通过T5与Vsus连接,T5的栅极与第三扫描信号连接。上述技术方案藉由五个开关、实现像素补偿电路的运作,可以补偿驱动TFT的电压漂移,发光电流只与Vdata有关,以达到像素补偿和面板亮度均匀的效果。大大增加了OLED发光电流的稳定性。
Description
技术领域
本发明涉及液晶面板显示领域,尤其涉及一种液晶面板消除像素发光不稳定的电路设计。
背景技术
AMOLED面板自发光,与传统LCD相比更轻薄,可视角度高;但会有一些不良因子影响其发光亮度,如Vth漂移会使面板发光电流受到影响;另外本身OLED材料老化也会影响发光电流,进而影响发光亮度;同时本身金属走向的阻抗对发光电流产生不良影响,即I-Rdrop;这些不良因子对面板发光亮度有着很严重的影响。Pixel所占面积越小,同样面积大小的面板所容纳的Pixel数量越多,解析度就越高,画面质量越好。
由于AMOLED面板上的电压VDD于每个像素间都连接在一起,当驱动发光时,电压VDD上会有电流流过。考虑到VDD金属线本身具有阻抗,会有压降存在,造成每一像素的VDD会出现差异,导致不同像素间存在电流差异。如此一来,流经OLED的电流不同,所产生的亮度也不同,进而AMOLED面板不均匀。另外,由于制程的影响,每一像素中的薄膜晶体管的阈值电压均不相同,即使提供相同数值的电压Vdata,其所产生的电流仍然会有差异,这也将造成面板不均匀。此外,如果采用像素补偿电路对上述电压进行补偿,大部分补偿电路又会受限于扫描时间太短而影响补偿效果。
有鉴于此,如何消除VTH等不良因子对电流的影响,使发光电流只与写入的VDATA有关,以及如何通过减小Pixel所占面积来提高解析度,是一项重要课题。
发明内容
为此,需要提供一种能够解决液晶面板显示过程中,补偿显示电压使得显示效果更好的方法,
为实现上述目的,发明人提供了一种像素补偿电路,包括薄膜晶体管T1、T2、T3、T4、T5,电容C1、C2;所述T1的源极与片上电压VDD连接,漏极与T4的源端连接,栅极与第一扫描信号连接;所述T2的栅极与第二扫描信号连接,源极接数据信号,漏极与T4的栅极和C1的一端连接,所述C1的另一端与T3的源极连接,T3的栅极与第二扫描信号连接,C1的另一端还通过C2与T4的漏极连接,T4的漏极还与发光子像素的正极连接,发光子像素的负极还与T3的漏极连接后接地或接片上低电压;发光子像素的正极还通过T5与Vsus连接,T5的栅极与第三扫描信号连接。
进一步地,所述T1、T2、T3、T4、C1、C2设置于面板发光区子像素区内,T5逐行设置于面板的外围电路,与多个发光子像素的正极连接。
一种像素补偿电路驱动方法,适用于上述的像素补偿电路,方法包括重置阶段、补偿阶段、写入阶段和发光阶段;
重置阶段,第一扫描信号低电平,第二扫描信号及第三扫描信号高电平,数据信号写入参考电压;补偿阶段第一扫描信号及第二扫描信号高电平,第三扫描信号低电平,数据信号写入参考电压;写入阶段,第一扫描信号及第三扫描信号低电平,第二扫描信号高电平,数据信号写入参考电压加数据电压的和;发光阶段,第一扫描信号高电平,第二扫描信号及第三扫描信号低电平,数据信号写入参考电压。
区别于现有技术,上述技术方案本发明藉由五个开关、实现像素补偿电路的运作,可以补偿驱动TFT的电压漂移,发光电流只与Vdata有关,以达到像素补偿和面板亮度均匀的效果。大大增加了OLED发光电流的稳定性。
附图说明
图1为具体实施方式所述的像素补偿电路设计原理图;
图2为具体实施方式所述的重置阶段电路状态及信号示意图;
图3为具体实施方式所述的补偿阶段电路状态及信号示意图;
图4为具体实施方式所述的写入阶段电路状态及信号示意图;
图5为具体实施方式所述的发光阶段电路状态及信号示意图。
具体实施方式
为详细说明技术方案的技术内容、构造特征、所实现目的及效果,以下结合具体实施例并配合附图详予说明。
图1所示的实施例中,展示了一种像素补偿电路,包括薄膜晶体管T1、T2、T3、T4、T5,电容C1、C2;所述T1的源极与片上电压VDD连接,漏极与T4的源端连接,栅极与第一扫描信号连接;所述T2的栅极与第二扫描信号连接,源极接数据信号,漏极与T4的栅极和C1的一端连接,所述C1的另一端与T3的源极连接,T3的栅极与第二扫描信号连接,C1的另一端还通过C2与T4的漏极连接,T4的漏极还与发光子像素的正极连接,发光子像素的负极还与T3的漏极连接后接地或接片上低电压;发光子像素的正极还通过T5与Vsus连接,T5的栅极与第三扫描信号连接。该像素补偿电路的驱动原理如图2-图5所示,包括重置阶段、补偿阶段、写入阶段和发光阶段;
如图2重置阶段(Reset),第一扫描信号Scan1低电平,第二扫描信号Scan2及第三扫描信号Scan3高电平,数据信号写入参考电压。则有T2,T3打开,DATA讯号写入VREF电压,VA=VREF;VC=VSS;Scan3写入高电压,Scan1写入低电压,T5打开,T1关闭,VB=Vsus。
如图3补偿阶段(Comp)第一扫描信号Scan1及第二扫描信号Scan2高电平,第三扫描信号Scan3低电平,数据信号写入参考电压。则有T1打开,T5关闭,VDD写入使B点电压升高到VREF-VTH时,T4关闭,此时VB=VREF-VTH,即补偿到一个VTH;VA和VC保持不变,即VA=VREF,VC=VSS。
如图4写入阶段(Data In),第一扫描信号Scan1及第三扫描信号Scan3低电平,第二扫描信号Scan2高电平,数据信号写入参考电压加数据电压的和VREF+VDATA。则有T2和T3打开,VA=VREF+VDATA,VC保持在VSS电压,即VC=VSS,由于BC间电容的作用,B点电压保持不变,即VB=VREF-VTH。
如图5发光阶段(commission),第一扫描信号Scan1高电平,第二扫描信号Scan2及第三扫描信号Scan3低电平,数据信号写入参考电压。T2和T3关闭,发光二极管导通,VB=VOLED+VSS,由于BC间电容的作用,VC=VSS+VOLED+VSS-(VREF-VTH),由于AC间的电容作用,VA=VREF+VDATA+VOLED+VSS-(VREF-VTH)=VDATA+VOLED+VSS+VTH,那么VGS=VA-VB=VDATA+VTH,代入饱和区电流公式IOLED=1/2μnCOXW/L(VGS-VTH)2得到IOLED=1/2μnCOXW/L(VDATA)2(注μn为场效应迁移率,COX为单位面积的绝缘层电容;W/L为TFT沟道宽度比长度)。
从OLED发光电流公式可以了解OLED电流只与VDATA有关,与VTH无关,其他参数相对固定,达到了设计目的,可见上述补偿电路对TFT有很好的补偿效果。提升了面板的发光效果。
在其他如图1所示的进一步的实施例中,我们可以看到所述T1、T2、T3、T4、C1、C2设置于面板发光区子像素区内,T5逐行设置于面板的外围电路,同一行的多个发光子像素的正极通过T5控制Vsus电压的通断。这里的发光子像素我们可以看到,是例如R\G\B三色的子像素,其所在的面板功能区AA(Active Area)是发光区域,外围电路是其外周的非发光区域,可以用于设计走线等。将T5设置于外围电路能够有效减少功能区的子像素区域的元件数量,从而减少面积占用,提高面板的单位像素。同时每行仅使用一个TFT驱动,也能够减少相应的设计成本。
需要说明的是,尽管在本文中已经对上述各实施例进行了描述,但并非因此限制本发明的专利保护范围。因此,基于本发明的创新理念,对本文所述实施例进行的变更和修改,或利用本发明说明书及附图内容所作的等效结构或等效流程变换,直接或间接地将以上技术方案运用在其他相关的技术领域,均包括在本发明的专利保护范围之内。
Claims (3)
1.一种像素补偿电路,其特征在于,包括薄膜晶体管T1、T2、T3、T4、T5,电容C1、C2;所述T1的源极与片上电压VDD连接,漏极与T4的源端连接,栅极与第一扫描信号连接;所述T2的栅极与第二扫描信号连接,源极接数据信号,漏极与T4的栅极和C1的一端连接,所述C1的另一端与T3的源极连接,T3的栅极与第二扫描信号连接,C1的另一端还通过C2与T4的漏极连接,T4的漏极还与发光子像素的正极连接,发光子像素的负极还与T3的漏极连接后接地或接片上低电压;发光子像素的正极还通过T5与Vsus连接,T5的栅极与第三扫描信号连接。
2.根据权利要求1所述的像素补偿电路,其特征在于,所述T1、T2、T3、T4、C1、C2设置于面板发光区子像素区内,T5逐行设置于面板的外围电路,与多个发光子像素的正极连接。
3.一种像素补偿电路驱动方法,其特征在于,适用于权利要求1或2所述的像素补偿电路,方法包括重置阶段、补偿阶段、写入阶段和发光阶段;
重置阶段,第一扫描信号低电平,第二扫描信号及第三扫描信号高电平,数据信号写入参考电压;补偿阶段第一扫描信号及第二扫描信号高电平,第三扫描信号低电平,数据信号写入参考电压;写入阶段,第一扫描信号及第三扫描信号低电平,第二扫描信号高电平,数据信号写入参考电压加数据电压的和;发光阶段,第一扫描信号高电平,第二扫描信号及第三扫描信号低电平,数据信号写入参考电压。
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CN112599091A (zh) * | 2020-12-29 | 2021-04-02 | 福建华佳彩有限公司 | 一种补偿电路及驱动方法 |
CN113012639A (zh) * | 2021-02-25 | 2021-06-22 | 福建华佳彩有限公司 | 一种像素补偿电路及驱动方法 |
CN114822403A (zh) * | 2022-04-08 | 2022-07-29 | 福建华佳彩有限公司 | 一种像素结构的内部补偿电路及其控制方法 |
CN114927098A (zh) * | 2022-05-07 | 2022-08-19 | 重庆邮电大学 | 一种像素驱动电路及像素驱动方法 |
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