WO2020063145A1 - 一种快速低功耗单端接口 - Google Patents

一种快速低功耗单端接口 Download PDF

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WO2020063145A1
WO2020063145A1 PCT/CN2019/100233 CN2019100233W WO2020063145A1 WO 2020063145 A1 WO2020063145 A1 WO 2020063145A1 CN 2019100233 W CN2019100233 W CN 2019100233W WO 2020063145 A1 WO2020063145 A1 WO 2020063145A1
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push
output
input terminal
detection module
pull structure
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王磊
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南京观海微电子有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical

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  • the invention relates to a single-ended interface, in particular to a fast low-power single-ended interface.
  • the traditional single-ended interface includes two signal lines, a clock signal line and a data signal line.
  • the internal circuit of the data signal adopts an open drain structure, and the signal line is externally connected with a pull-up resistor.
  • the reason why the open-drain structure is used in addition to the pull-up resistor is to realize the sharing of the bus by multiple masters and to facilitate the checking of the bus status.
  • the high level of the data path is achieved by a pull-up resistor.
  • the low level is achieved by an internal pull-down circuit, but during pull-down, the pull-up resistor leaks current, consumes current, and slows down the falling edge time.
  • the present invention proposes a fast low-power single-ended interface, which adds a conflict detection module and a push-pull structure.
  • the technical solution adopted by the present invention is: a fast low-power single-ended interface, including a push-pull structure and a conflict detection module, and a data signal is output through the push-pull structure while using conflict detection
  • the module checks the bus status.
  • the push-pull structure includes a PMOS tube and an NMOS tube, the source of the PMOS tube is connected to the input voltage VDD, the drain of the PMOS tube is connected to the drain of the NMOS tube, and the connection point is the output signal VOUT, the source of the NMOS tube Ground voltage GND; conflict detection module output enable signal OE, output enable signal OE and input signal VIN of push-pull structure are connected to the control pole of PMOS tube after NAND gate; The input signal VIN of the push-pull structure is connected to the control electrode of the NMOS transistor after the NOR gate.
  • the conflict detection module includes two voltage comparators, a negative input terminal of the first voltage comparator is connected to a threshold V t1 , a positive input terminal is connected to the output signal VOUT of the host, and an output terminal is connected to one input of the first XOR gate
  • the negative input of the second voltage comparator is connected to the threshold V t2 , the positive input is connected to the output signal VOUT of the host, and the output is connected to one input of the second XOR gate; the other input of the first XOR gate and The other input terminal of the second XOR gate is connected to the input signal VIN in common, and the output of the two XOR gates passes an OR logic gate to output an enable signal OE.
  • the threshold value of the first voltage comparator is V t1
  • the threshold value of the second voltage comparator is V t2
  • V t1 ⁇ V t2 is V t1 .
  • the voltage comparator of the conflict detection module may also be replaced by inverters or Schmitt triggers with different thresholds.
  • FIG. 1 is a schematic diagram of a single-ended interface in the prior art
  • FIG. 2 is a schematic diagram of a fast low-power single-ended interface according to the present invention.
  • FIG. 3 is a schematic diagram of a conflict detection module.
  • the fast low-power single-ended interface adds MP1 to the original circuit to form a push-pull structure, and simultaneously adds a conflict detection module.
  • the conflict detection module prevents multiple masters from competing for the bus and cannot determine the bus status problem.
  • the bus status detection circuit structure is simpler.
  • the fast low-power single-ended interface includes a push-pull structure, a conflict detection module, and some basic logic gates.
  • the push-pull structure includes a PMOS tube MP1 and an NMOS tube MN1.
  • the source of the PMOS tube is connected to the input voltage VDD
  • the drain of the PMOS tube is connected to the drain of the NMOS tube, and its connection point is the output signal VOUT
  • the source of the NMOS tube is grounded to GND.
  • the conflict detection circuit module includes two comparators and some logic gates, and may also be inverters or Schmitt triggers with different thresholds.
  • the threshold value of the first voltage comparator is V t1
  • the threshold value of the second voltage comparator is V t2 , so that V t1 ⁇ V t2 .
  • the negative input terminal of the first voltage comparator is connected to the threshold V t1
  • the positive input terminal is connected to VOUT of the host
  • the output terminal is connected to one input terminal of the first XOR gate.
  • the negative voltage input terminal of the second voltage comparator is connected to the threshold V t2
  • the positive voltage input terminal is connected to VOUT of the host
  • the output terminal is connected to one input terminal of the second XOR gate.
  • the other input terminal of the first XOR gate and the other input terminal of the second XOR gate are commonly connected to the input signal VIN.
  • the outputs of the two XOR gates pass through an OR logic gate and become the output enable signal OE.
  • the output enable signal OE and the input signal VIN of the push-pull structure are connected to the control electrode of the PMOS transistor after the NAND gate.
  • the output enable signal OE is connected to the control electrode of the NMOS transistor MN1 through the NOR gate and the input signal VIN of the push-pull structure.
  • V OL ⁇ V t1 , V OH > V t2 When the collision detection circuit module works normally, V OL ⁇ V t1 , V OH > V t2 .
  • both masters are output.
  • One master pulls up MP1 and the other master pulls down MN1.
  • VOUT remains: V t1 ⁇ V CD ⁇ V t2 , the slave outputs a high-impedance state, giving up control of the bus, and the master regains the bus.
  • the bus in a normal state, has no pull-up and pull-down circuits at the same time.
  • the conflict detection module detects that VOUT is lower than V t1 and V t2 at the same time. Both Schmitt trigger outputs are low.
  • the conflict detection module detects that VOUT is higher than both V t1 and V t2 . Both Schmitt trigger outputs are high.
  • the bus In the abnormal state, the bus has the pull-up and pull-down circuits turned on at the same time, and the bus voltage V t1 ⁇ V CD ⁇ V t2 .
  • One of the two detection circuits outputs a high level and one outputs a low level, and the conflict status is established.
  • the invention uses a push-pull structure output terminal, which has no DC path power consumption at both logic high and low levels, and low power consumption; high operating frequency and at least one order of magnitude higher signal frequency.
  • a conflict detection module is added to prevent multiple masters from competing for the bus, and the problem of the bus status cannot be determined.
  • the structure of the bus status detection circuit is simpler.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

一种快速低功耗单端接口，包括推挽结构和冲突检测模块，推挽结构包括PMOS管和NMOS管，冲突检测电路模块包括两个比较器，也可以是不同阈值的反相器或者斯密特触发器。使用推挽结构输出端，在逻辑高电平和低电平都没有直流通路功耗，功耗低；工作频率高，信号频率至少高一个数量级。同时增设有冲突检测模块，避免多主机争夺总线，无法确定总线状态问题，总线状态检测电路结构更简单。

Description

一种快速低功耗单端接口 技术领域
本发明涉及一种单端接口，尤其涉及一种快速低功耗单端接口。
背景技术
传统的单端接口(I2C)，包含两条信号线，一条时钟信号线，一条数据信号线。如图1所示，数据信号的内部电路采用open drain结构，信号线外挂上拉电阻。之所以采用open drain结构外加上拉电阻是为了实现多主机共用总线，以及便于检查总线状态。
数据通路的高电平是靠上拉电阻实现的，导致上升沿不会很快，接口频率就会受限制，无法太快。低电平靠内部的下拉电路(open drain)实现，但下拉时，上拉电阻在漏电，消耗电流，还拖慢下降沿时间。这里有三个问题需要解决，一个是缩短上升沿时间；另一个是避免下降沿时，上拉通路导通；最后还有个问题是总线状态检测。
发明内容
发明目的：针对以上问题，本发明提出一种快速低功耗单端接口，增加了冲突检测模块和推挽结构。
技术方案：为实现本发明的目的，本发明所采用的技术方案是：一种快速低功耗单端接口，包括推挽结构和冲突检测模块，数据信号经推挽结构输出，同时使用冲突检测模块检查总线状态。
进一步地，所述推挽结构包括PMOS管和NMOS管，PMOS管的源极连接输入电压VDD，PMOS管的漏极连接NMOS管的漏极，其连接点为输出信号VOUT，NMOS管的源极接地电压GND；冲突检测模块输出使能信号OE，输出使能信号OE与推挽结构的输入信号VIN经与非门后连接到PMOS管的控制极；输出使能信号OE经非门，后与推挽结构的输入信号VIN经或非门后连接到NMOS管的控制极。
进一步地，所述冲突检测模块包括两个电压比较器，第一电压比较器的负极输入端连接阈值V t1，正极输入端连接主机的输出信号VOUT，输出端连接第一异或门的一个输入端；第二电压比较器的负极输入端连接阈值V t2，正极输入端连接主机的输出信号VOUT，输出端连接第二异或门的一个输入端；第一异或门的另一个输入端和第二异或门的另一个输入端共同连接输入信号VIN，两个异或门的输出通过一个或逻辑门后输出使能信号OE。
进一步地，第一电压比较器的阈值是V t1，第二电压比较器的阈值是V t2，V t1<V t2。
进一步地，所述冲突检测模块的电压比较器也可以使用阈值不同的反相器或斯密特触发器替代。
有益效果：与现有技术相比具有的优点：使用推挽结构输出端，在逻辑高电平和低 电平都没有直流通路功耗，功耗低；工作频率高，信号频率至少高一个数量级。有冲突检测模块，避免多主机争夺总线，无法确定总线状态问题，总线状态检测电路结构更简单。
附图说明
图1是现有技术中单端接口的示意图；
图2是本发明所述快速低功耗单端接口的示意图；
图3是冲突检测模块的示意图。
具体实施方式
下面结合附图和实施例对本发明的技术方案作进一步的说明。
如图2所示，本发明所述的快速低功耗单端接口，在原有电路基础上增加MP1，形成推挽结构，同时增加一个冲突检测模块。
用推挽结构，在逻辑高电平和低电平都没有直流通路功耗，功耗低且工作频率高。有冲突检测模块，避免多主机争夺总线，无法确定总线状态问题，总线状态检测电路结构更简单。
本发明所述的快速低功耗单端接口包括推挽结构、冲突检测模块及一些基本逻辑门，推挽结构包括PMOS管MP1和NMOS管MN1。PMOS管的源极连接输入电压VDD，PMOS管的漏极连接NMOS管的漏极，其连接点为输出信号VOUT，NMOS管的源极接地电压GND。
如图3所示，冲突检测电路模块包括两个比较器和一些逻辑门，也可以是不同阈值的反相器或者斯密特触发器。第一电压比较器的阈值是V t1，第二电压比较器的阈值是V t2，使V t1<V t2。第一电压比较器的负极输入端输入连接阈值V t1，正极输入端输入连接主机的VOUT，输出端连接第一异或门的一个输入端。第二电压比较器的负极输入端输入连接阈值V t2，正极输入端输入连接主机的VOUT，输出端连接第二异或门的一个输入端。第一异或门的另一个输入端和第二异或门的另一个输入端共同连接输入信号VIN，两个异或门的输出通过一个或逻辑门后成为输出使能信号OE。
如图2所示，输出使能信号OE与推挽结构的输入信号VIN经与非门后连接到PMOS管的控制极。输出使能信号OE经非门与推挽结构的输入信号VIN经或非门后连接到NMOS管MN1的控制极。
VIN是推挽结构的输入，逻辑上等于VOUT，也就是VIN＝1，MP1导通，MN1关断，VOUT＝1。同理VIN＝0，MP1关断，MN1导通，VOUT＝0。输出VOUT高阻态时，MP1，MN1都关断。
冲突检测电路模块正常工作时，V OL<V t1，V OH>V t2。当总线发生冲突时，两个主机都是输出状态，一个主机的上拉MP1打开，另一个主机的下拉MN1打开，此时VOUT 为V CD，V CD＝VDD*R MN1/(R MP1+R MN1)，调整电路使V t1<V CD<V t2。当进入冲突状态，VOUT保持为：V t1<V CD<V t2，从机输出高阻态，放弃对总线的控制，主机重新获得总线。
本发明所述的快速低功耗单端接口，在正常状态，总线没有上下拉电路同时导通，输出低电平时，冲突检测模块检测到VOUT同时低于V t1和V t2。两个Schmitt trigger输出都是低电平。输出高电平时，冲突检测模块检测到VOUT同时高于V t1和V t2。两个Schmitt trigger输出都是高电平。
异常状态下，总线有上下拉电路同时导通，总线电压V t1<V CD<V t2。两个检测电路一个输出高电平，一个输出低电平，冲突状态成立。
本发明使用推挽结构输出端，在逻辑高电平和低电平都没有直流通路功耗，功耗低；工作频率高，信号频率至少高一个数量级。同时增设有冲突检测模块，避免多主机争夺总线，无法确定总线状态问题，总线状态检测电路结构更简单。

Claims (5)

  1. 一种快速低功耗单端接口，其特征在于，包括推挽结构和冲突检测模块，数据信号经推挽结构输出，同时使用冲突检测模块检查总线状态。
  2. 根据权利要求1所述的快速低功耗单端接口，其特征在于，所述推挽结构包括PMOS管和NMOS管，PMOS管的源极连接输入电压VDD，PMOS管的漏极连接NMOS管的漏极，其连接点为输出信号VOUT，NMOS管的源极接地电压GND；
    冲突检测模块输出使能信号OE，输出使能信号OE与推挽结构的输入信号VIN经与非门后连接到PMOS管的控制极；输出使能信号OE经非门，后与推挽结构的输入信号VIN经或非门后连接到NMOS管的控制极。
  3. 根据权利要求2所述的快速低功耗单端接口，其特征在于，所述冲突检测模块包括两个电压比较器，第一电压比较器的负极输入端连接阈值V t1，正极输入端连接主机的输出信号VOUT，输出端连接第一异或门的一个输入端；
    第二电压比较器的负极输入端连接阈值V t2，正极输入端连接主机的输出信号VOUT，输出端连接第二异或门的一个输入端；
    第一异或门的另一个输入端和第二异或门的另一个输入端共同连接输入信号VIN，两个异或门的输出通过一个或逻辑门后输出使能信号OE。
  4. 根据权利要求3所述的快速低功耗单端接口，其特征在于，第一电压比较器的阈值是V t1，第二电压比较器的阈值是V t2，V t1<V t2。
  5. 根据权利要求3所述的快速低功耗单端接口，其特征在于，所述冲突检测模块的电压比较器也可以使用阈值不同的反相器或斯密特触发器替代。
PCT/CN2019/100233 2018-09-28 2019-08-12 一种快速低功耗单端接口 WO2020063145A1 (zh)

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CN110850770B (zh) * 2019-11-08 2021-05-11 航天柏克(广东)科技有限公司 一种多主机的快速判断和退出方法

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CN109104182A (zh) * 2018-09-28 2018-12-28 南京观海微电子有限公司 一种快速低功耗单端接口
CN209267548U (zh) * 2018-09-28 2019-08-16 南京观海微电子有限公司 一种快速低功耗单端接口

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