WO2020062829A1 - 一种鳍式超结功率半导体晶体管及其制备方法 - Google Patents

一种鳍式超结功率半导体晶体管及其制备方法 Download PDF

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WO2020062829A1
WO2020062829A1 PCT/CN2019/081807 CN2019081807W WO2020062829A1 WO 2020062829 A1 WO2020062829 A1 WO 2020062829A1 CN 2019081807 W CN2019081807 W CN 2019081807W WO 2020062829 A1 WO2020062829 A1 WO 2020062829A1
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body region
type body
epitaxial layer
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孙伟锋
刘斯扬
童鑫
钊雪会
徐浩
陆生礼
时龙兴
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Southeast University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H10D62/154—Dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H10D62/155—Shapes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts

Definitions

  • the invention relates to the technical field of power semiconductor devices, and in particular, to a fin-type super-junction power semiconductor transistor and a preparation method thereof.
  • MOSFETs power metal-oxide-semiconductor field-effect transistors
  • the concept of "super-junctions" was introduced in the early 1990s, replacing the traditional P-pillars and N-pillars with traditional ones.
  • the N drift region of the power device thereby effectively reducing the on-resistance and obtaining a lower on-power consumption.
  • the field effect transistor with super-junction structure has performed well in reducing the on-resistance, but still has not reached the ideal expectation.
  • the present invention proposes a fin-type super-junction power semiconductor transistor and a method for manufacturing the same, under the premise of ensuring breakdown voltage, further reducing the on-resistance, reducing the turn-on speed of the device, and reducing EMI noise.
  • the invention proposes a fin-type super-junction power semiconductor transistor capable of further reducing the on-resistance and effectively reducing the EMI noise of the device and a method for manufacturing the same in view of the above-mentioned shortcomings.
  • a fin-type super-junction power semiconductor transistor includes an N-type substrate, an N-type epitaxial layer is provided on the N-type substrate, and columnar first P-type body regions are respectively provided on both sides of the N-type epitaxial layer.
  • a second P-type body region is also provided on both sides in the N-type epitaxial layer.
  • the columnar first P-type body region and the second P-type body region on the same side are in contact with each other.
  • There is a first N-type heavily doped source region a third P-type body region is provided on the top of the N-type epitaxial layer, and a second N-type heavily doped source region is provided at each end of the third P-type body region.
  • gate polysilicon is provided on both sides of the third P-type body region, and the second P-type body region is covered under the gate polysilicon, and between the gate polysilicon and the second P-type body region, A gate oxide layer is provided between the N-type epitaxial layer and the third P-type body region.
  • the columnar first P-type body region, the second P-type body region, and a portion of the N-type epitaxial layer are lower than those of the third P-type body region. lower surface.
  • a fin-type super-junction power semiconductor transistor characterized in that the first N-type heavily doped source region on the surface of the second P-type body region ends at the outer boundary of the gate oxide layer,
  • the second P-type body region is synchronously convex to the outside of the transistor and has a pulse shape.
  • the first step first select an N-type silicon material as a substrate and epitaxially grow an N-type epitaxial layer;
  • the second step using a mask to selectively etch deep trenches on the N-type epitaxial layer, and backfill the P-type material to form a columnar first P-type body region;
  • Step 3 Etching the N-type epitaxial layer selectively to form a step-shaped epitaxial layer
  • the fourth step using a mask to selectively implant boron into the step-shaped N-type epitaxial layer, and form a second P-type body region and a third P-type body region after annealing;
  • Step 5 Use a mask to selectively implant ion arsenic or phosphorus on the surface of the second P-type body region to form a convex N-type heavily doped source region, and selectively implant ion arsenic or phosphorus on the surface of the third P-type body region to form N-type heavily doped source region;
  • Step 6 Boron is implanted on the upper surface of the columnar first P-type body region, the second P-type body region, and the third P-type body region with high energy (80KeV-200KeV) to form a P-type heavily doped semiconductor contact region;
  • the seventh step thermally growing on the surface of the N-type epitaxial layer to form a gate oxide layer, and then depositing a layer of polysilicon;
  • Step 8 Use a mask to etch excess polysilicon to form gate polysilicon
  • Ninth step deposit an oxide layer as a contact insulating layer, selectively etch the insulating layer, and form a contact hole on the surface of the N-type epitaxial layer;
  • Step 10 The source metal is deposited to form a good ohmic contact or Schottky contact with the second P-type body region and the third P-type body region.
  • the present invention has the following advantages:
  • the device of the present invention uses a fin gate polysilicon gate 10 to separate the P-type body region, so that it forms a second P-type body region 4 and a third P-type body region 5 which are separated from each other, thereby increasing the conductive channel, and further Reduce on-resistance.
  • the pillar-shaped first P-type body region is connected to the second P-type body region.
  • the gate polysilicon 10 in the device of the present invention separates the second P-type body region 4 and the third P-type body region 5 from each other.
  • the conductive channel of the device of the present invention is increased, so that the on-resistance of the device is further reduced, and the on-power consumption is reduced.
  • the outer boundary of the gate polysilicon 10 and the gate oxide layer 9 synchronously protrudes to the outside of the transistor with the boundary of the first N-type heavily doped source region 6 and has a pulse shape, which increases the gate-drain capacitance and effectively reduces The device EMI noise.
  • the contact area between the gate oxide layer 9 having a pulse shape and the N-type epitaxial layer 2 is increased, and the covering capacitance formed by the gate and the drain is increased, so that the total gate leakage capacity of the device is increased. Large, so the transistor turn-on speed is reduced, the rate of change of current and voltage with time is reduced, and the device EMI noise is reduced.
  • the device structure design process of the present invention retains the design process of the traditional trench metal oxide semiconductor field effect transistor structure, and has a simple process and high feasibility.
  • FIG. 1 shows a three-dimensional perspective view of a conventional trench superjunction power semiconductor transistor.
  • FIG. 2 is a three-dimensional perspective view of a novel fin-type super-junction power semiconductor transistor according to the present invention.
  • FIG. 3 to FIG. 8 are process flow diagrams of a method for preparing a novel fin-type super-junction power semiconductor transistor according to the present invention.
  • the device of the present invention uses fin-type gate polysilicon and a gate oxide layer to separate the second P-type body region and the third P-type body region from each other.
  • an inversion channel can be formed in the second P-type body region and the third P-type body region.
  • a large number of electrons flow from the source region to the drain through multiple conductive channels, and the forward conduction current increases and turns on. The resistance is further reduced.
  • the lower surface boundary of the gate polysilicon and the gate oxide layer in the device extends laterally toward the columnar first P-type body region along with the boundary of the N-type heavily doped source region, the contact area between the gate oxide layer and the N-type epitaxial layer increases.
  • the increase in the covered capacitance with the drain increases the total gate leakage capacitance of the device, so the transistor turn-on speed decreases, the rate of change of current and voltage with time decreases, and the EMI noise level of the device decreases.
  • the device preparation method retains a design process of a conventional trench metal oxide semiconductor field effect transistor structure, and has a simple process and high feasibility.
  • a fin-type super-junction power semiconductor transistor includes: an N-type substrate 1, an N-type epitaxial layer 2 is provided on the N-type substrate 1, and an N-type epitaxial layer 2 is provided.
  • a columnar first P-type body region 3 is provided on both sides of the inner side, and a second P-type body region 4 is provided on both sides of the N-type epitaxial layer 2.
  • the columnar first P-type body region 3 is located on the same side.
  • a first N-type heavily doped source region 6 is provided on the surface of the second P-type body region 4
  • a third P-type body region 5 is provided on top of the N-type epitaxial layer 2.
  • a second N-type heavily doped source region 7 is provided at both ends of the surface of the third P-type body region 5, and gate polysilicon 10 is provided on both sides of the third P-type body region 5, respectively, and the gate polysilicon is
  • the second P-type body region 4 is covered under 10, and a gate oxide layer 9 is provided between the gate polysilicon 10 and the second P-type body region 4, the N-type epitaxial layer 2 and the third P-type body region 5,
  • the columnar first P-type body region 3, the second P-type body region 4, and a portion of the N-type epitaxial layer 2 are lower than the lower surface of the third P-type body region 5.
  • the first N-type heavily doped source region 6 on the surface of the second P-type body region 4 stops at the outer boundary of the gate oxide layer 9, and the first N-type heavily doped source region 6 and the second P-type region
  • the body region 4 is synchronously convex to the outside of the transistor and has a pulse shape.
  • a method for manufacturing a fin-type super-junction power semiconductor transistor :
  • the first step first select an N-type silicon material as a substrate and epitaxially grow an N-type epitaxial layer;
  • the second step using a mask to selectively etch deep trenches on the N-type epitaxial layer, and backfill the P-type material to form a columnar first P-type body region;
  • Step 3 Etching the N-type epitaxial layer selectively to form a step-shaped epitaxial layer
  • the fourth step using a mask to selectively implant boron into the step-shaped N-type epitaxial layer, and form a second P-type body region and a third P-type body region after annealing;
  • Step 5 Use a mask to selectively implant ion arsenic or phosphorus on the surface of the second P-type body region to form a convex N-type heavily doped source region, and selectively implant ion arsenic or phosphorus on the surface of the third P-type body region to form N-type heavily doped source region;
  • Step 6 Boron is implanted on the upper surface of the columnar first P-type body region, the second P-type body region, and the third P-type body region with high energy (80kev-200kev) to form a P-type heavily doped semiconductor contact region;
  • the seventh step thermally growing on the surface of the N-type epitaxial layer to form a gate oxide layer, and then depositing a layer of polysilicon;
  • Step 8 Use a mask to etch excess polysilicon to form gate polysilicon
  • Ninth step deposit an oxide layer as a contact insulating layer, selectively etch the insulating layer, and form a contact hole on the surface of the N-type epitaxial layer;
  • Step 10 The source metal is deposited to form a good ohmic contact or Schottky contact with the second P-type body region and the third P-type body region.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

一种鳍式超结功率半导体晶体管及其制备方法，包括N型衬底(1)，在N型衬底(1)上设有N型外延层(2)，在N型外延层(2)内的两侧设有柱状第一P型体区(3)和第二P型体区(4)，在第二P型体区(4)表面设有第一N型重掺杂源区(6)，在N型外延层(2)顶部设有第三P型体区(5)，该区表面两端设有第二N型重掺杂源区(7)，第三P型体区(5)两侧分别设有栅极多晶硅(10)，且栅极多晶硅(10)下方覆盖第二P型体区(4)，柱状第一P型体区(3)、第二P型体区(4)及部分N型外延层(2)低于第三P型体区(5)下表面。第二P型体区(4)表面的第一N型重掺杂源区(6)止于栅氧化层(9)的外侧边界，第一N型重掺杂源区(6)与第二P型体区(4)向晶体管外侧同步外凸并呈脉冲形状，从而在保证击穿电压的前提下进一步降低导通电阻，降低器件EMI噪声。

Description

一种鳍式超结功率半导体晶体管及其制备方法 技术领域
本发明涉及功率半导体器件技术领域，具体涉及一种鳍式超结功率半导体晶体管及其制备方法。
背景技术
功率半导体器件作为电力电子系统中的核心元件，自20世纪70年代发明以来，一直是现代生活不可或缺的重要电子元件。过去三十年里，功率金属氧化物半导体场效应管(MOSFET)取得了飞跃式的发展，20世纪90年代初提出了“超结”的概念，利用相互交替的P柱与N柱代替传统的功率器件的N漂移区，从而有效降低了导通电阻，得到较低的导通功耗。相比于传统MOSFET，具有超结结构的场效应管虽然在降低导通电阻方面已经有不错的表现，但是仍然没有达到理想的预期。20世纪90年代末胡正明教授提出了鳍式场效应晶体管，鳍式结构的栅增大了沟道面积，加强了栅对沟道的控制。鉴于此，本发明提出一种鳍式超结功率半导体晶体管及其制备方法，在保证击穿电压的前提下进一步降低导通电阻，降低器件开启速度，降低EMI噪声。
发明内容
本发明针对上述不足提出了一种能够进一步降低导通电阻，并且有效降低器件EMI噪声的鳍式超结功率半导体晶体管及其制备方法。
本发明采用如下结构技术方案：
一种鳍式超结功率半导体晶体管，包括：N型衬底，在N型衬底上设有N型外延层，在N型外延层内的两侧分别设有柱状第一P型体区，在N型外延层内的两侧还分别设有第二P型体区，位于同侧的柱状第一P型体区和第二P型体区相触及，在第二P型体区表面设有第一N型重掺杂源区，在N型外延层的顶部设有第三P型体区，在第三P型体区表面两端分别设有第二N型重掺杂源区，其特征在于，第三P型体区的两侧分别设有栅极多晶硅，且所述栅极多晶硅的下方覆盖所述第二P型体区，在栅极多晶硅与第二P型体区、N型外延层及第三P型体区之间设有栅氧化层，所述柱状第一P型体区、第二P型体区及部分N型外延层低于第三P型体区的下表面。
一种鳍式超结功率半导体晶体管，其特征在于，第二P型体区表面的第一N型重掺杂源区止于栅氧化层的外侧边界，第一N型重掺杂源区与第二P型体区向晶体管外侧同步外凸并呈脉冲形状。
本发明提供如下方法技术方案：
第一步：首先选取N型硅材料作为衬底并外延生长N型外延层；
第二步：利用掩膜板在N型外延层上选择刻蚀出深沟槽，回填P型材料形成柱状第一P型体区；
第三步：选择性刻蚀N型外延层形成台阶形外延层；
第四步：利用掩膜板对台阶形N型外延层选择性注入硼，退火后形成第二P型体区和第三P型体区；
第五步：利用掩膜板在第二P型体区表面选择性注入离子砷或磷形成凸形N型重掺杂源区，在第三P型体区表面选择性注入离子砷或磷形成N型重掺杂源区；
第六步：在柱状第一P型体区、第二P型体区、第三P型体区上表面选择性高能量(80KeV～200KeV)注入硼形成P型重掺杂半导体接触区；
第七步：在N型外延层表面热生长形成栅氧化层，再淀积一层多晶硅；
第八步：利用掩膜板刻蚀多余的多晶硅形成栅极多晶硅；
第九步：淀积一层氧化层作为接触绝缘层，选择性刻蚀绝缘层，在N型外延层表面形成接触孔；
第十步：淀积制作源极金属，且源极金属与第二P型体区和第三P型体区形成良好的欧姆接触或肖特基接触。
与现有技术相比，本发明具有如下优点：
1.本发明器件利用鳍式栅极多晶硅栅10对P型体区分隔，使其形成相互分离的第二P型体区4与第三P型体区5，从而使导电沟道增加，进一步降低导通电阻。传统超结结构器件中，柱状第一P型体区与第二P型体区相连，器件导通时，只有第二P型体区内形成反型沟道，电子从N型重掺杂源区经过沟道流向漏极。本发明器件中栅极多晶硅10使第二P型体区4与第三P型体区5相互分离。器件导通时，第二P型体区4与第三P型体区5内分别形成横向和纵向反型沟道，大量电子从源极通过横向和纵向的多个导电沟道流向漏极，正向导通电流增加。因此，相比于传统超结结构器件，本发明器件导电沟道增加，使得器件导通电阻进一步降低，导通功耗降低。
2.本发明器件中栅极多晶硅10和栅氧化层9的外侧边界随第一N型重掺杂源区6边界向晶体管外侧同步外凸并呈脉冲形状，使得栅漏电容增大，有效降低了器件EMI噪声。与传统器件相比，本发明器件中，边界呈脉冲形状的栅氧化层9与N型外延层2的接触面积增加，栅极与漏极形成的覆盖电容增大，使得器件总栅漏电容增大，因此晶体管开启速度降低，电流与电压随时间的变化率降低，器件EMI噪声降低。
3.本发明器件结构设计工艺保留了传统沟槽金属氧化物半导体型场效应晶体管结构 的设计工艺，工艺简单，可行性高。
附图说明
图1所示为传统沟槽超结功率半导体晶体管的三维立体图。
图2所示为本发明提出的新型鳍式超结功率半导体晶体管的三维立体图。
图3～图8所示为本发明提出的新型鳍式超结功率半导体晶体管制备方法的工艺流程图。
具体实施方式
本发明器件利用鳍式栅极多晶硅和栅氧化层使第二P型体区与第三P型体区相互分离。器件导通时，第二P型体区与第三P型体区内均可形成反型沟道，大量电子从源区通过多个导电沟道流向漏极，正向导通电流增加，导通电阻进一步降低。并且，由于器件中栅极多晶硅和栅氧化层下表面边界随N型重掺杂源区边界横向向柱状第一P型体区延伸，栅氧化层与N型外延层的接触面积增加，栅极与漏极形成的覆盖电容增大，使得器件总栅漏电容增大，因此晶体管开启速度降低，电流与电压随时间的变化率降低，器件EMI噪声水平降低。所述器件制备方法保留了传统沟槽金属氧化物半导体型场效应晶体管结构的设计工艺，工艺简单，可行性高。
实施例1
下面结合图2，对本发明进行详细说明，一种鳍式超结功率半导体晶体管，包括：N型衬底1，在N型衬底1上设有N型外延层2，在N型外延层2内的两侧分别设有柱状第一P型体区3，在N型外延层2内的两侧还分别设有第二P型体区4，位于同侧的柱状第一P型体区3和第二P型体区4相触及，在第二P型体区4表面设有第一N型重掺杂源区6，在N型外延层2的顶部设有第三P型体区5，在第三P型体区5表面两端分别设有第二N型重掺杂源区7，第三P型体区5的两侧分别设有栅极多晶硅10，且所述栅极多晶硅10的下方覆盖所述第二P型体区4，在栅极多晶硅10与第二P型体区4、N型外延层2及第三P型体区5之间设有栅氧化层9，所述柱状第一P型体区3、第二P型体区4及部分N型外延层2低于第三P型体区5的下表面。在本实施例中，第二P型体区4表面的第一N型重掺杂源区6止于栅氧化层9的外侧边界，第一N型重掺杂源区6与第二P型体区4向晶体管外侧同步外凸并呈脉冲形状。
实施例2
下面结合图3～图8，对本发明进行详细说明，一种鳍式超结功率半导体晶体管的制备方法：
第一步：首先选取N型硅材料作为衬底并外延生长N型外延层；
第二步：利用掩膜板在N型外延层上选择刻蚀出深沟槽，回填P型材料形成柱状第一P型体区；
第三步：选择性刻蚀N型外延层形成台阶形外延层；
第四步：利用掩膜板对台阶形N型外延层选择性注入硼，退火后形成第二P型体区和第三P型体区；
第五步：利用掩膜板在第二P型体区表面选择性注入离子砷或磷形成凸形N型重掺杂源区，在第三P型体区表面选择性注入离子砷或磷形成N型重掺杂源区；
第六步：在柱状第一P型体区、第二P型体区、第三P型体区上表面选择性高能量(80kev～200kev)注入硼形成P型重掺杂半导体接触区；
第七步：在N型外延层表面热生长形成栅氧化层，再淀积一层多晶硅；
第八步：利用掩膜板刻蚀多余的多晶硅形成栅极多晶硅；
第九步：淀积一层氧化层作为接触绝缘层，选择性刻蚀绝缘层，在N型外延层表面形成接触孔；
第十步：淀积制作源极金属，且源极金属与第二P型体区和第三P型体区形成良好的欧姆接触或肖特基接触。

Claims (3)

  1. 一种鳍式超结功率半导体晶体管，包括：N型衬底(1)，在N型衬底(1)上设有N型外延层(2)，在N型外延层(2)内的两侧分别设有柱状第一P型体区(3)，在N型外延层(2)内的两侧还分别设有第二P型体区(4)，位于同侧的柱状第一P型体区(3)和第二P型体区(4)相触及，在第二P型体区(4)表面设有第一N型重掺杂源区(6)，在N型外延层(2)的顶部设有第三P型体区(5)，在第三P型体区(5)表面两端分别设有第二N型重掺杂源区(7)，其特征在于，第三P型体区(5)的两侧分别设有栅极多晶硅(10)，且所述栅极多晶硅(10)的下方覆盖所述第二P型体区(4)，在栅极多晶硅(10)与第二P型体区(4)、N型外延层(2)及第三P型体区(5)之间设有栅氧化层(9)，所述柱状第一P型体区(3)、第二P型体区(4)及部分N型外延层(2)低于第三P型体区(5)的下表面。
  2. 根据权利要求1所述的一种鳍式超结功率半导体晶体管，其特征在于，第二P型体区(4)表面的第一N型重掺杂源区(6)止于栅氧化层(9)的外侧边界，第一N型重掺杂源区(6)与第二P型体区(4)向晶体管外侧同步外凸并呈脉冲形状。
  3. 一种权利要求1所述的鳍式超结功率半导体晶体管的制备方法，其特征在于：
    第一步：首先选取N型硅材料作为衬底(1)并外延生长N型外延层；
    第二步：利用掩膜板在N型外延层上选择刻蚀出深沟槽，回填P型材料形成柱状第一P型体区(3)；
    第三步：选择性刻蚀N型外延层形成台阶形外延层(2)；
    第四步：利用掩膜板对台阶形N型外延层(2)选择性注入硼，退火后形成第二P型体区(4)和第三P型体区(5)；
    第五步：利用掩膜板在第二P型体区表面选择性注入离子砷或磷形成凸形N型重掺杂源区(6)，在第三P型体区表面选择性注入离子砷或磷形成N型重掺杂源区(7)；
    第六步：在柱状第一P型体区(3)、第二P型体区(4)、第三P型体区(5)上表面选择性高能量(80KeV～200KeV)注入硼形成P型重掺杂半导体接触区(8)；
    第七步：在N型外延层表面热生长形成栅氧化层，再淀积一层多晶硅；
    第八步：利用掩膜板刻蚀多余的多晶硅形成栅极多晶硅(10)；
    第九步：淀积一层氧化层作为接触绝缘层，选择性刻蚀绝缘层，在N型外延层表面形成接触孔；
    第十步：淀积制作源极金属，且源极金属与第二P型体区和第三P型体区形成良好的欧姆接触或肖特基接触。
PCT/CN2019/081807 2018-09-29 2019-04-08 一种鳍式超结功率半导体晶体管及其制备方法 Ceased WO2020062829A1 (zh)

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