WO2020049420A1 - 半導体装置、および半導体装置の作製方法 - Google Patents

半導体装置、および半導体装置の作製方法 Download PDF

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Publication number
WO2020049420A1
WO2020049420A1 PCT/IB2019/057266 IB2019057266W WO2020049420A1 WO 2020049420 A1 WO2020049420 A1 WO 2020049420A1 IB 2019057266 W IB2019057266 W IB 2019057266W WO 2020049420 A1 WO2020049420 A1 WO 2020049420A1
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Prior art keywords
oxide
conductor
insulator
transistor
semiconductor device
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PCT/IB2019/057266
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English (en)
French (fr)
Japanese (ja)
Inventor
高橋正弘
奥野直樹
金川朋賢
水上翔太
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to US17/272,400 priority Critical patent/US12062723B2/en
Priority to JP2020540872A priority patent/JP7287970B2/ja
Priority to KR1020257022169A priority patent/KR20250109789A/ko
Priority to KR1020217006924A priority patent/KR102830796B1/ko
Publication of WO2020049420A1 publication Critical patent/WO2020049420A1/ja
Anticipated expiration legal-status Critical
Priority to US18/795,876 priority patent/US20240395943A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • one embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.
  • a semiconductor device in this specification and the like refers to any device that can function by utilizing semiconductor characteristics.
  • a semiconductor device such as a transistor, a semiconductor circuit, an arithmetic device, and a storage device are one embodiment of a semiconductor device.
  • a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, an electronic device, or the like sometimes includes a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacturer, or a composition (composition of matter).
  • ICs integrated circuits
  • LSIs and ultra-LSIs composed of ICs of higher integration
  • Such an IC is mounted on a circuit board, for example, a printed wiring board, and is used as one of components of various electronic devices constituting a computer, an information terminal, a display device, an automobile, and the like.
  • AI artificial intelligence
  • Desktop computers laptop computers, tablet computers, smartphones, mobile phones, and the like are known as computers and information terminals.
  • a silicon-based semiconductor material is widely known as a semiconductor material used for a semiconductor element, but an oxide semiconductor is attracting attention as another material.
  • a transistor including an oxide semiconductor has extremely low leakage current in a non-conductive state.
  • a low-power-consumption CPU utilizing the characteristic of a transistor including an oxide semiconductor with low leakage current has been disclosed (see Patent Document 1).
  • One object of one embodiment of the present invention is to provide a semiconductor device having favorable electric characteristics and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity and a method for manufacturing the semiconductor device.
  • Another object is to suppress change in electric characteristics and improve reliability in a semiconductor device including a transistor including an oxide semiconductor. Another object is to provide a transistor including an oxide semiconductor with high on-state current. Another object is to provide a transistor including an oxide semiconductor with low off-state current. Another object is to provide a semiconductor device with reduced power consumption. Another object is to provide a semiconductor device with an improved operating frequency.
  • Another object is to provide a novel semiconductor device. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module.
  • One embodiment of the present invention is a semiconductor device including a first insulator, a first conductor over the first insulator, a second conductor, a first conductor, and a second conductor. And a second insulator on the first conductor, the second conductor, and the oxide, and a third conductor on the second insulator.
  • the side surface of the first conductor has a region in contact with one side surface of the oxide, and the side surface of the second conductor has a region in contact with the other side surface of the oxide;
  • the height of the top surface of the body, the height of the top surface of the second conductor, and the height of the top surface of the oxide are each approximately equal, and the conductivity of the first conductor is higher than the oxide, and Is a semiconductor device having higher conductivity than oxide.
  • each of the first conductor and the second conductor contains In and any one or more of Sn, W, Ti, and Si.
  • the first conductor and the second conductor may each include one or more of Zn, Ti, Ga, and Nb.
  • the oxide preferably contains In, an element M (M is Al, Ga, Y, or Sn), and Zn.
  • the carrier density of the first conductor and the second conductor is preferably higher than the carrier density of the oxide.
  • a first insulator is formed over a substrate, an oxide film is formed over the first insulator, a mask is formed over the oxide film by lithography, By removing an oxide film which does not overlap, an oxide is formed, a mask, a conductive film is formed to cover the oxide, and a part of the conductive film is isotropically etched to expose the side surface of the mask. Then, the conductive film on the mask is lifted off by removing the mask and removing the mask.
  • the conductive film is preferably formed by a sputtering method.
  • the film formation rate of the conductive film is smaller in the horizontal direction than in the vertical direction.
  • a semiconductor device having favorable electric characteristics and a manufacturing method thereof can be provided. Further, according to one embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity and a method for manufacturing the semiconductor device can be provided.
  • a transistor including an oxide semiconductor variation in electric characteristics can be suppressed and reliability can be improved. Further, a transistor including an oxide semiconductor with high on-state current can be provided. Further, a transistor including an oxide semiconductor with low off-state current can be provided. Further, a semiconductor device with reduced power consumption can be provided. Further, a semiconductor device with an improved operating frequency can be provided.
  • a novel semiconductor device can be provided.
  • a module including the semiconductor device can be provided.
  • an electronic device including the semiconductor device or the module can be provided.
  • FIG. 1A is a top view illustrating the semiconductor device. 1B and 1C are cross-sectional views illustrating a semiconductor device.
  • FIG. 2A is a top view illustrating the semiconductor device. 2B and 2C are cross-sectional views illustrating the semiconductor device.
  • FIG. 3A is a top view illustrating the semiconductor device. 3B and 3C are cross-sectional views illustrating the semiconductor device.
  • FIG. 4A is a top view illustrating the method for manufacturing the semiconductor device. 4B and 4C are cross-sectional views illustrating a method for manufacturing a semiconductor device.
  • FIG. 5A is a top view illustrating the method for manufacturing the semiconductor device. 5B and 5C are cross-sectional views illustrating a method for manufacturing a semiconductor device.
  • FIG. 6A is a top view illustrating the method for manufacturing the semiconductor device.
  • 6B and 6C are cross-sectional views illustrating a method for manufacturing a semiconductor device.
  • FIG. 7A is a top view illustrating the method for manufacturing the semiconductor device.
  • 7B and 7C are cross-sectional views illustrating a method for manufacturing a semiconductor device.
  • FIG. 8A is a top view illustrating the method for manufacturing the semiconductor device.
  • 8B and 8C are cross-sectional views illustrating a method for manufacturing a semiconductor device.
  • FIG. 9A is a top view illustrating the method for manufacturing the semiconductor device.
  • 9B and 9C are cross-sectional views illustrating a method for manufacturing a semiconductor device.
  • FIG. 10A is a top view illustrating the method for manufacturing the semiconductor device.
  • FIG. 10B and 10C are cross-sectional views illustrating a method for manufacturing a semiconductor device.
  • FIG. 11A is a top view illustrating the method for manufacturing the semiconductor device.
  • 11B and 11C are cross-sectional views illustrating a method for manufacturing a semiconductor device.
  • FIG. 12A is a top view illustrating the method for manufacturing the semiconductor device.
  • 12B and 12C are cross-sectional views illustrating a method for manufacturing a semiconductor device.
  • FIG. 13 illustrates an energy band structure of an oxide semiconductor.
  • FIG. 14 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention.
  • FIG. 15A is a block diagram illustrating a configuration example of a storage device.
  • FIG. 15A is a block diagram illustrating a configuration example of a storage device.
  • FIG. 15B is a schematic diagram illustrating a configuration example of a storage device.
  • 16A to 16H are circuit diagrams each illustrating a configuration example of a storage device.
  • FIG. 17A is a block diagram of a semiconductor device.
  • FIG. 17B is a schematic view of the semiconductor device.
  • 18A to 18E are schematic diagrams of a storage device.
  • 19A to 19F are diagrams illustrating electronic devices.
  • FIG. 20 is a graph showing the heat treatment time dependency of the sheet resistance value of indium tin oxide.
  • ⁇ ⁇ Particular components may be omitted in a top view (also referred to as a “plan view”), a perspective view, and the like to facilitate understanding of the invention.
  • a top view also referred to as a “plan view”
  • a perspective view and the like to facilitate understanding of the invention.
  • some hidden lines and the like may be omitted.
  • ordinal numbers given as first, second, and the like are used for convenience, and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.
  • ordinal numbers described in this specification and the like do not always coincide with ordinal numbers used for specifying one embodiment of the present invention.
  • connection relation is not limited to the predetermined connection relation, for example, the connection relation shown in the figure or the text, and it is assumed that anything other than the connection relation shown in the figure or the text is disclosed in the figure or the text.
  • X and Y are objects (for example, an apparatus, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, and the like).
  • an element for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.
  • an element capable of electrically connecting X and Y.
  • Elements, light emitting elements, loads, etc. are not connected between X and Y, and elements (for example, switches, transistors, capacitors, inductors, etc.) that enable electrical connection between X and Y ,
  • a resistance element, a diode, a display element, a light-emitting element, a load, etc. are connected via X and Y.
  • an element for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.
  • One or more elements, light-emitting elements, loads, etc. can be connected between X and Y.
  • the switch has a function of being turned on and off. That is, the switch is in a conductive state (on state) or non-conductive state (off state), and has a function of controlling whether a current flows or not. Alternatively, the switch has a function of selecting and switching a path through which current flows.
  • the case where X and Y are electrically connected includes the case where X and Y are directly connected.
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, or the like) that enables a functional connection between X and Y, a signal conversion Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit for changing signal potential level, etc.), voltage source, current source, switching Circuits, amplifier circuits (circuits that can increase signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, storage circuits, control circuits, etc.) One or more can be connected in between.
  • a logic circuit an inverter, a NAND circuit, a NOR circuit, or the like
  • X and Y are functionally connected. I do. Note that a case where X and Y are functionally connected includes a case where X and Y are directly connected and a case where X and Y are electrically connected.
  • a transistor is an element having at least three terminals including a gate, a drain, and a source.
  • a channel formation region is provided between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and between the source and the drain through the channel formation region. Current can flow through the Note that in this specification and the like, a channel formation region refers to a region through which current mainly flows.
  • the functions of the source and the drain may be switched when transistors having different polarities are used or when the direction of current changes in circuit operation. For this reason, in this specification and the like, the terms of source and drain may be used interchangeably.
  • a channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion of a semiconductor in which current flows when the transistor is on) and a gate overlap with each other, or a region where a channel is formed. , The distance between the source and the drain. Note that in one transistor, the channel length does not always have the same value in all regions. That is, the channel length of one transistor may not be determined to one value. Therefore, in this specification, a channel length is any one of values, a maximum value, a minimum value, or an average value in a region where a channel is formed.
  • the channel width refers to, for example, a region where a semiconductor (or a portion of a semiconductor in which current flows when a transistor is on) and a gate overlap each other, or a region where a channel is formed, in which a source and a drain face each other.
  • the length of the part where it is located in one transistor, the channel width does not always have the same value in all regions. That is, the channel width of one transistor may not be determined to one value. Therefore, in this specification, a channel width is any one of values, a maximum value, a minimum value, or an average value in a region where a channel is formed.
  • a channel width in a region where a channel is actually formed (hereinafter, also referred to as an “effective channel width”) and a channel width shown in a top view of the transistor (hereinafter, “apparent channel width”).
  • Channel width a channel width in a region where a channel is actually formed
  • apparent channel width a channel width shown in a top view of the transistor
  • the apparent channel width may be referred to as "enclosed channel width (SCW: Surrounded Channel Width)".
  • channel width sometimes refers to an enclosed channel width or an apparent channel width.
  • a simple term “channel width” may refer to an effective channel width. Note that the values of the channel length, channel width, effective channel width, apparent channel width, enclosing channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.
  • an impurity in a semiconductor refers to, for example, elements other than the main components of the semiconductor.
  • an element having a concentration of less than 0.1 atomic% can be regarded as an impurity.
  • DOS Density of State
  • examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor.
  • transition metals other than the main components such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • water may function as an impurity in some cases.
  • oxygen vacancies may be formed by entry of impurities, for example.
  • the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, and a Group 15 element other than oxygen and hydrogen.
  • a silicon oxynitride film has a higher oxygen content than nitrogen as its composition.
  • nitrogen preferably, 55 to 65 atomic% of oxygen, 1 to 20 atomic% of nitrogen, 25 to 35 atomic% of silicon, and 0.1 to 10 atomic% of hydrogen. It refers to those included in the concentration range.
  • a silicon nitride oxide film has a higher nitrogen content than oxygen as its composition.
  • nitrogen is 55 to 65 atomic%
  • oxygen is 1 to 20 atomic%
  • silicon is 25 to 35 atomic%
  • hydrogen is 0.1 to 10 atomic%. It refers to those included in the concentration range.
  • the term “film” and the term “layer” can be interchanged with each other.
  • the term “conductive layer” can be changed to the term “conductive film”.
  • the term “insulating film” may be changed to the term “insulating layer” in some cases.
  • the term “insulator” can be replaced with an insulating film or an insulating layer.
  • the term “conductor” can be referred to as a conductive film or a conductive layer.
  • the term “semiconductor” can be referred to as a semiconductor film or a semiconductor layer.
  • the transistors described in this specification and the like are field-effect transistors unless otherwise specified. Further, a transistor described in this specification and the like is an n-channel transistor unless otherwise specified. Therefore, the threshold voltage (also referred to as “Vth”) is higher than 0 V unless otherwise specified.
  • parallel refers to a state where two straight lines are arranged at an angle of ⁇ 10 ° or more and 10 ° or less. Therefore, a case where the angle is ⁇ 5 ° or more and 5 ° or less is included.
  • substantially parallel refers to a state in which two straight lines are arranged at an angle of ⁇ 30 ° or more and 30 ° or less.
  • “Vertical” means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, a case where the angle is 85 ° or more and 95 ° or less is also included.
  • substantially perpendicular refers to a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.
  • a barrier film refers to a film having a function of suppressing transmission of impurities such as hydrogen and oxygen, and is referred to as a conductive barrier film when the barrier film has conductivity. There is.
  • a metal oxide is a metal oxide in a broad sense.
  • the metal oxide is classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also referred to as an oxide semiconductor or simply OS), or the like.
  • an oxide semiconductor also referred to as an oxide semiconductor or simply OS
  • the metal oxide may be referred to as an oxide semiconductor in some cases. That is, the term "OS @ FET" can be referred to as a transistor including an oxide or an oxide semiconductor.
  • FIG. 1A is a top view of a semiconductor device including the transistor 200.
  • FIG. 1B and 1C are cross-sectional views of the semiconductor device.
  • FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • 1C is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some components are not illustrated in the top view in FIG. 1A for clarity.
  • the semiconductor device of one embodiment of the present invention includes the insulator 214 over the substrate (not illustrated), the transistor 200 over the insulator 214, the insulator 280 over the transistor 200, and the insulator 281 over the insulator 280. And The insulator 214, the insulator 280, and the insulator 281 function as an interlayer film. Further, the semiconductor device includes a conductor 240 (a conductor 240a and a conductor 240b) which is electrically connected to the transistor 200 and functions as a plug. Note that the insulator 241 (the insulator 241a and the insulator 241b) is provided in contact with a side surface of the conductor 240 functioning as a plug. In addition, a conductor 246 (a conductor 246a and a conductor 246b) which is electrically connected to the conductor 240 and functions as a wiring is provided over the insulator 281 and the conductor 240.
  • An insulator 241a is provided in contact with the inner walls of the openings of the insulator 272, the insulator 280, and the insulator 281.
  • a first conductor of the conductor 240a is provided in contact with a side surface of the insulator 241a.
  • a second conductor of body 240a is provided.
  • An insulator 241b is provided in contact with the inner walls of the openings of the insulator 272, the insulator 280, and the insulator 281; a first conductor of the conductor 240b is provided in contact with a side surface thereof;
  • a second conductor of body 240b is provided.
  • the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be approximately equal.
  • the transistor 200 has a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this.
  • a structure in which the conductor 240 is provided as a single layer or a stacked structure of three or more layers may be employed.
  • ordinal numbers may be given in the order of formation to distinguish them.
  • the transistor 200 includes an insulator 216 over the insulator 214, a conductor 205 arranged to be embedded in the insulator 216, an insulator 216 over the insulator 216, and an insulator over the conductor 205. 222; an insulator 224 on the insulator 222; a conductor 242a and a conductor 242b on the insulator 224; an oxide 230 disposed between the conductor 242a and the conductor 242b; There is an insulator 250 over the conductor 242b and the oxide 230, and a conductor 260 (a conductor 260a and a conductor 260b) over the insulator 250.
  • the side surface of the conductor 242a has a region in contact with one side surface of the oxide 230
  • the side surface of the conductor 242b has a region in contact with the other side surface of the oxide 230.
  • the height of the upper surface of the conductor 242a, the height of the upper surface of the conductor 242b, and the height of the upper surface of the oxide 230 are substantially equal to each other.
  • the insulator 222, the insulator 272, and the insulator 281 preferably have a function of suppressing diffusion of hydrogen (for example, at least one of a hydrogen atom and a hydrogen molecule). Further, the insulator 222, the insulator 272, and the insulator 281 preferably have a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules). For example, each of the insulator 222, the insulator 272, and the insulator 281 preferably has lower permeability to one or both of oxygen and hydrogen than the insulator 224.
  • Each of the insulator 222, the insulator 272, and the insulator 281 preferably has lower permeability to one or both of oxygen and hydrogen than the insulator 250. It is preferable that the insulator 222, the insulator 272, and the insulator 281 each have lower permeability to one or both of oxygen and hydrogen than the insulator 280.
  • the insulator 272 includes the top and side surfaces of the conductor 260, the side surface of the insulator 250, the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, and the top surface of the insulator 224. Is preferably in contact with. Accordingly, the insulator 280 is separated from the insulator 224 and the oxide 230 by the insulator 272. In addition, the insulator 272 suppresses transmission of one or both of oxygen and hydrogen from the insulator 280 to the conductor 260, whereby oxidation of the conductor 260 can be suppressed.
  • the transistor 200 has a single-layer structure of the oxide 230 in the channel formation region and in the vicinity thereof; however, the present invention is not limited to this.
  • a structure in which a two-layer structure or a stacked structure of three or more layers may be provided.
  • the conductor 260 is illustrated as having a two-layer structure; however, the present invention is not limited to this.
  • the conductor 260 may have a single-layer structure or a stacked structure of three or more layers.
  • the conductor 260 functions as a gate of the transistor 200, and the conductor 242a and the conductor 242b each function as a source or a drain.
  • a metal oxide functioning as an oxide semiconductor hereinafter, also referred to as an oxide semiconductor is preferably used for the oxide 230 including a channel formation region.
  • the transistor 200 including an oxide semiconductor in a channel formation region has extremely low leakage current (off current) in a non-conduction state; therefore, a semiconductor device with low power consumption can be provided.
  • An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200 included in a highly integrated semiconductor device.
  • an In-M-Zn oxide (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , Neodymium, hafnium, tantalum, tungsten, or magnesium, or a plurality thereof).
  • element M aluminum, gallium, yttrium, or tin is preferably used.
  • an In—Ga oxide or an In—Zn oxide may be used as the oxide 230.
  • a transistor including an oxide semiconductor when impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electric characteristics are likely to be changed and reliability may be deteriorated. Further, when oxygen vacancies are included in a region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies in a region where a channel is formed be reduced as much as possible. Accordingly, it is possible to provide a transistor in which fluctuation in electric characteristics is suppressed, stable electric characteristics are improved, and reliability is improved.
  • a conductive oxide is preferably used as the conductor 242 (the conductor 242a and the conductor 242b) which is provided so as to be in contact with both side surfaces of the oxide 230 and functions as a source or a drain.
  • the conductive oxide be a conductive oxide which does not depend only on oxygen vacancies but generates carriers by a substitutional impurity donor. That is, even if oxygen vacancies in the conductor 242 are repaired by excess oxygen, a decrease in carrier density in the conductor 242 can be suppressed. Therefore, the conductive oxide is considered to generate carriers even in a state where oxygen vacancies are small, so that the transistor can have high on-state characteristics.
  • the conductor 242 preferably contains one or more of tin, tungsten, titanium, and silicon, and indium.
  • tin tin
  • indium oxide containing tungsten oxide indium oxide containing tungsten oxide
  • indium zinc oxide containing tungsten oxide indium oxide containing titanium oxide
  • indium tin oxide containing titanium oxide indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • zinc oxide to which gallium is added, or titanium oxide to which niobium is added may be used.
  • the conductivity of the conductor 242 be higher than the conductivity of the oxide 230.
  • the carrier density of the conductor 242 is preferably higher than the carrier density of the oxide 230.
  • the transistor 200 of one embodiment of the present invention has a structure in which both side surfaces of the oxide 230 functioning as a channel formation region are sandwiched between conductors 242 functioning as a source or a drain as illustrated in FIG. 1B. Further, the height of the upper surface of the conductor 242 and the height of the upper surface of the oxide 230 are substantially equal. With such a structure, the shortest distance between the upper surface of the channel formation region of the oxide 230 and the conductor 260 functioning as a gate is approximately equal to the shortest distance between the conductor 242 and the conductor 260. A transistor with small parasitic capacitance can be provided.
  • the insulator 250 since a step is not formed or is small between the channel formation region of the oxide 230 and the conductor 260, the insulator 250 over the channel formation region of the oxide 230 and the conductor 242 Since the step can be provided with almost no step, the coverage of the insulator 250 is improved and the withstand voltage of the insulator 250 is improved, which is preferable.
  • the conductor 260 functioning as a gate covers the side and top surfaces of the oxide 230 in the channel formation region with the insulator 250 interposed therebetween, so that the electric field of the conductor 260 It is easy to act on the entire oxide 230 in the formation region.
  • the on-state current of the transistor 200 can be increased and frequency characteristics can be improved.
  • a semiconductor device including a transistor with a large on-state current can be provided.
  • a semiconductor device including a transistor having high frequency characteristics can be provided.
  • a semiconductor device including a transistor with low off-state current can be provided.
  • the following describes a detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention.
  • the conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. It is preferable that the conductor 205 be provided so as to be embedded in the insulator 216.
  • the conductor 260 may function as a first gate (also referred to as a top gate) in some cases.
  • the conductor 205 may function as a second gate (also referred to as a bottom gate) in some cases.
  • Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without changing the potential.
  • Vth of the transistor 200 can be made higher than 0 V and off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be smaller than when no negative potential is applied.
  • the conductor 205 is preferably provided to be larger than the oxide 230 as illustrated in FIG. 1A.
  • the conductor 205 preferably extends in a region outside an end portion of the oxide 230 intersecting with the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other with the insulator interposed outside the side surface of the oxide 230 in the channel width direction.
  • the conductor 205 is provided to be large, local charging (called charge-up) may be moderated in a process using plasma in a manufacturing process after the conductor 205 is formed. Note that one embodiment of the present invention is not limited to this.
  • the conductor 205 may overlap with at least the oxide 230 located between the conductor 242a and the conductor 242b.
  • the channel formation region can be electrically surrounded by an electric field of the conductor 260 having a function as the first gate and an electric field of the conductor 205 having a function of the second gate.
  • a structure of a transistor that electrically surrounds a channel formation region by an electric field of a first gate and a second gate is referred to as a surrounded-channel (S-channel) structure.
  • the conductor 205 has a lower layer film of the conductor 205 formed in contact with the inner wall of the opening of the insulator 216, and an upper layer film of the conductor 205 formed inside the lower layer film of the conductor 205.
  • the height of the upper surface of the conductor 205 and the height of the upper surface of the insulator 216 can be approximately the same.
  • the lower layer film of the conductor 205 suppresses diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2, and the like), and copper atoms. It is preferable to use a conductive material having a function of performing the above (the above-described impurity is hardly permeated). Alternatively, it is preferable to use a conductive material which has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the above oxygen is not easily transmitted).
  • the function of suppressing the diffusion of an impurity or oxygen refers to a function of suppressing the diffusion of any one or all of the impurity or the oxygen.
  • a conductor having such a function may be referred to as a conductive barrier film.
  • the lower layer of the conductor 205 has a function of suppressing diffusion of oxygen, it is possible to prevent the upper layer of the conductor 205 from being oxidized and lowering the conductivity.
  • the conductive material having a function of suppressing diffusion of oxygen for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used. Therefore, as the lower layer film of the conductor 205, the above conductive material may be a single layer or a stacked layer. Accordingly, diffusion of impurities such as hydrogen and water to the transistor 200 through the conductor 205 can be suppressed.
  • tantalum nitride and titanium nitride are used as the conductor 205a.
  • a conductive material mainly containing tungsten, copper, or aluminum be used for the upper layer film of the conductor 205.
  • tungsten is used for the upper layer of the conductor 205.
  • the oxide semiconductor, the insulator or the conductor located in the lower layer of the oxide semiconductor, and the insulator or the conductor located in the upper layer of the oxide semiconductor are formed in different films without opening to the air. It is preferable that the seeds be continuously formed because a substantially high-purity intrinsic oxide semiconductor film in which the concentration of impurities (in particular, hydrogen and water) is reduced can be formed.
  • an insulator 222, an insulator 224, and an oxide film to be the oxide 230 are sequentially formed over the insulator 216 and the conductor 205 in this order. do it.
  • the insulator 214, the insulator 272, and the insulator 281 function as barrier insulating films which prevent impurities such as water or hydrogen from entering the transistor 200 from the substrate side or from above. Therefore, the insulator 214, the insulator 272, and the insulator 281 can diffuse impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, and the like), and a copper atom. It is preferable to use an insulating material having a function of suppressing the above (the above-mentioned impurities are hardly permeated). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule) (the above-described oxygen is not easily transmitted).
  • oxygen for example, at least one of an oxygen atom and an oxygen molecule
  • impurities such as water or hydrogen from the substrate side to the transistor 200 side from the insulator 214
  • diffusion of oxygen contained in the insulator 224 and the like to the substrate side of the insulator 214 can be suppressed.
  • the insulator 272 aluminum oxide or the like can be used for the insulator 272. Accordingly, diffusion of impurities such as water or hydrogen from the insulator 280 and / or the conductor 246 which are provided over the insulator 272 to the transistor 200 side can be suppressed.
  • the insulator 214 and the insulator 281 may have a stacked structure.
  • a stacked structure of an aluminum oxide film and a silicon nitride film is preferably used for the insulator 214 and the insulator 281.
  • Oxygen can be supplied below the insulator 214 with the aluminum oxide film.
  • the silicon nitride film diffusion of impurities such as hydrogen and water which diffuse from the substrate side to the transistor 200 side can be suppressed.
  • oxygen can be supplied below the insulator 281. Further, diffusion of impurities such as hydrogen and water which diffuse from the outside to the transistor 200 side can be suppressed by the silicon nitride film.
  • the insulators 216 and 280 preferably have a lower dielectric constant than the insulator 214.
  • a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or Silicon oxide or the like having holes may be used as appropriate.
  • the insulator 222 and the insulator 224 have a function as a gate insulator.
  • the insulator 224 in contact with the oxide 230 release oxygen by heating.
  • oxygen released by heating may be referred to as excess oxygen.
  • the insulator 224 may be formed using silicon oxide or silicon oxynitride as appropriate.
  • an oxide material from which part of oxygen is released by heating as the insulator 224.
  • An oxide from which oxygen is released by heating means that the amount of desorbed oxygen molecules is 1.0 ⁇ 10 18 molecules / cm 3 or more, preferably 1.0 ⁇ 10 19 molecules in TDS (Thermal Desorption Spectroscopy) analysis. / Cm 3 or more, more preferably 2.0 ⁇ 10 19 molecules / cm 3 or more, or 3.0 ⁇ 10 20 molecules / cm 3 or more.
  • the surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C to 700 ° C, or 100 ° C to 400 ° C.
  • the insulator 222 preferably functions as a barrier insulating film for preventing impurities such as water or hydrogen from entering the transistor 200 from the substrate side.
  • the insulator 222 preferably has lower hydrogen permeability than the insulator 224.
  • the insulator 222 have a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the above-described oxygen is hardly transmitted).
  • the insulator 222 preferably has lower oxygen permeability than the insulator 224. It is preferable that the insulator 222 have a function of suppressing diffusion of oxygen and impurities because diffusion of oxygen included in the oxide 230 to a lower side than the insulator 222 can be reduced.
  • the conductor 205 can be prevented from reacting with oxygen included in the insulator 224 and the oxide 230.
  • an insulator containing an oxide of one or both of aluminum and hafnium which are insulating materials, may be used. It is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like as the insulator containing one or both oxides of aluminum and hafnium. In the case where the insulator 222 is formed using such a material, the insulator 222 suppresses release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230. Functions as a layer.
  • aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 222 is made of, for example, a so-called high such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr) TiO3 (BST).
  • An insulator containing a -k material may be used in a single layer or a stacked layer.
  • a problem such as a leak current may occur due to thinning of a gate insulator.
  • a high-k material for an insulator functioning as a gate insulator With the use of a high-k material for an insulator functioning as a gate insulator, reduction in gate potential at the time of transistor operation can be performed while the physical thickness is maintained.
  • the insulator 222 and the insulator 224 may have a stacked structure of two or more layers.
  • the structure is not limited to a laminated structure made of the same material, and may be a laminated structure made of different materials.
  • a metal oxide functioning as an oxide semiconductor is preferably used.
  • the off-state current of the transistor can be reduced. With the use of such a transistor, a semiconductor device with low power consumption can be provided.
  • the electron affinity or the energy level Ec at the bottom of the conduction band can be obtained from the ionization potential Ip, which is the difference between the vacuum level Evac and the energy Ev at the top of the valence band, and the energy gap Eg. .
  • the ionization potential Ip can be measured, for example, by using an ultraviolet photoelectron spectroscopy (UPS) device (Ultraviolet @ Photoelectron @ Spectroscopy).
  • UPS ultraviolet photoelectron spectroscopy
  • the energy gap Eg can be measured using, for example, a spectroscopic ellipsometer.
  • the insulator 250 functions as a gate insulator.
  • the insulator 250 is preferably provided in contact with the upper surface of the oxide 230c.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having holes is used. be able to.
  • silicon oxide and silicon oxynitride are preferable because they are stable against heat.
  • the insulator 250 is preferably formed using an insulator from which oxygen is released by heating.
  • an insulator from which oxygen is released by heating is provided as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to a channel formation region of the oxide 230b.
  • the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced.
  • the thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.
  • a metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppress oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses diffusion of oxygen, diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Further, oxidation of the conductor 260 due to oxygen of the insulator 250 can be suppressed.
  • the metal oxide has a function as part of a gate insulator. Therefore, in the case where silicon oxide, silicon oxynitride, or the like is used for the insulator 250, it is preferable that the metal oxide be a high-k material having a high relative dielectric constant.
  • the gate insulator has a stacked structure of the insulator 250 and the metal oxide, a stacked structure which is stable against heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during the operation of the transistor while maintaining the physical thickness of the gate insulator. Further, the equivalent oxide thickness (EOT) of the insulator functioning as a gate insulator can be reduced.
  • EOT equivalent oxide thickness
  • hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium, or a metal oxide containing two or more kinds may be used. it can.
  • the metal oxide may function as part of a gate in some cases.
  • a conductive material containing oxygen is preferably provided on the channel formation region side.
  • a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used.
  • a conductive material containing the above-described metal element and nitrogen may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • the conductor 260a is formed using a conductive material having a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, and the like), and a copper atom. Is preferred. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule).
  • the conductor 260a has a function of suppressing diffusion of oxygen, it is possible to prevent the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and lowering the conductivity.
  • the conductive material having a function of suppressing diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.
  • the conductor 260b be formed using a conductive material mainly containing tungsten, copper, or aluminum. Further, since the conductor 260 also functions as a wiring, a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductor 260b may have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the above conductive material.
  • the insulator 280 includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or vacancies as the insulator 280. It is preferable to have silicon oxide or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, a material such as silicon oxide, silicon oxynitride, or silicon oxide having a hole is preferable because a region containing oxygen which is released by heating can be easily formed.
  • the concentration of impurities such as water or hydrogen in the insulator 280 be reduced. Further, the upper surface of the insulator 280 may be planarized.
  • the insulator 281 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulator 280 from above.
  • an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used, for example.
  • the conductor 240a and the conductor 240b be formed using a conductive material mainly containing tungsten, copper, or aluminum. Further, the conductor 240a and the conductor 240b may have a stacked structure.
  • a conductive material having a function of suppressing transmission of impurities such as water or hydrogen is used for the conductor in contact with the insulator 281, the insulator 280, and the insulator 272.
  • a conductive material having a function of suppressing transmission of impurities such as water or hydrogen
  • a conductive material having a function of suppressing transmission of impurities such as water or hydrogen may be used in a single layer or a stacked layer.
  • oxygen added to the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b. Further, entry of impurities such as water or hydrogen from above the insulator 281 into the oxide 230 through the conductor 240a and the conductor 240b can be suppressed.
  • an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used, for example. Since the insulators 241a and 241b are provided in contact with the insulator 272, entry of impurities such as water or hydrogen from the insulator 280 or the like into the oxide 230 through the conductors 240a and 240b is suppressed. can do. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.
  • the conductor 246 (the conductor 246a and the conductor 246b) which functions as a wiring may be provided in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b.
  • the conductor 246 is preferably formed using a conductive material mainly containing tungsten, copper, or aluminum. Further, the conductor may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator.
  • FIG. 2A is a top view of a semiconductor device including the transistor 201.
  • FIG. 2B and 2C are cross-sectional views of the semiconductor device.
  • FIG. 2B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 2A, and is also a cross-sectional view of the transistor 201 in the channel length direction.
  • 2C is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 2A, and is also a cross-sectional view of the transistor 201 in the channel width direction. Note that some components are not illustrated in the top view of FIG. 2A for clarity.
  • the transistor 201 includes an insulator 216 over the insulator 214, a conductor 205 which is arranged to be embedded in the insulator 216, an insulator 222 over the insulator 216, and an insulator 222 over the conductor 205.
  • An insulator 224 over the insulator 222; a conductor 242a and a conductor 242b over the insulator 224; an oxide 230a provided between the conductor 242a and the conductor 242b; An oxide 230b disposed between the conductor 242a and the conductor 242b; an oxide 230c on the conductor 242a, the conductor 242b, and the oxide 230b; an insulator 250 on the oxide 230c; A conductor 260 over the insulator 250 (a conductor 260a and a conductor 260b).
  • the side surface of the conductor 242a has a region in contact with one side surface of the oxide 230a and the oxide 230b
  • the side surface of the conductor 242b has a region in contact with the other side surface of the oxide 230a and the oxide 230b.
  • the height of the upper surface of the conductor 242a, the height of the upper surface of the conductor 242b, and the height of the upper surface of the oxide 230b are substantially equal to each other.
  • an In-M-Zn oxide (the element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, It is preferable to use a metal oxide such as germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, or a plurality thereof.
  • the element M aluminum, gallium, yttrium, or tin is preferably used.
  • an In—Ga oxide or an In—Zn oxide may be used as the oxide 230.
  • a transistor including an oxide semiconductor when impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electric characteristics are likely to be changed and reliability may be deteriorated. Further, when oxygen vacancies are included in a region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies in a region where a channel is formed be reduced as much as possible. Accordingly, it is possible to provide a transistor in which fluctuation in electric characteristics is suppressed, stable electric characteristics are improved, and reliability is improved.
  • a conductive oxide can be used as the conductor 242 (the conductor 242a and the conductor 242b) which is provided so as to be in contact with both side surfaces of the oxide 230a and the oxide 230b and functions as a source and a drain.
  • the conductive oxide be a conductive oxide which does not depend only on oxygen vacancies but generates carriers by a substitutional impurity donor. That is, even if oxygen vacancies in the conductor 242 are repaired by excess oxygen, a decrease in carrier density in the conductor 242 can be suppressed. Therefore, the conductive oxide is considered to generate carriers even in a state where oxygen vacancies are small, so that the transistor can have high on-state characteristics.
  • the conductor 242 preferably contains one or more of tin, tungsten, titanium, and silicon, and indium.
  • tin tin
  • indium oxide containing tungsten oxide indium oxide containing tungsten oxide
  • indium zinc oxide containing tungsten oxide indium oxide containing titanium oxide
  • indium tin oxide containing titanium oxide indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • zinc oxide to which gallium is added, or titanium oxide to which niobium is added may be used.
  • the conductivity of the conductor 242 is preferably higher than the conductivity of the oxide 230a and the oxide 230b.
  • the carrier density of the conductor 242 is preferably higher than the carrier densities of the oxides 230a and 230b.
  • the transistor 201 which is one embodiment of the present invention has a structure in which the oxide 230b which functions as a channel formation region is sandwiched between conductors 242 which function as sources or drains as illustrated in FIG. 2B.
  • the height of the upper surface of the conductor 242 and the height of the upper surface of the oxide 230b are substantially equal.
  • the shortest distance between the upper surface of the channel formation region of the oxide 230b and the conductor 260 functioning as a gate is approximately equal to the shortest distance between the conductor 242 and the conductor 260.
  • a transistor with small parasitic capacitance can be provided.
  • the insulator 250 since a step is not formed or is small between the channel formation region of the oxide 230b and the conductor 260, the insulator 250 over the channel formation region of the oxide 230b and the conductor 242 Since the step can be provided with almost no step, the coverage of the insulator 250 is improved and the withstand voltage of the insulator 250 is improved, which is preferable.
  • the height of the bottom surface of the conductor 260 in a region where the oxide 230a and the oxide 230b and the conductor 260 do not overlap with each other with reference to the bottom surface of the insulator 224 is the oxide 230b Is preferably located at a position lower than the height of the bottom surface of.
  • the difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxide 230b and the conductor 260 do not overlap with each other is 0 nm to 100 nm, preferably 3 nm to 50 nm. Or less, more preferably 5 nm or more and 20 nm or less.
  • a conductor 260 functioning as a gate is configured to cover the side surfaces of the oxides 230a and 230b in the channel formation region and the top surface of the oxide 230b with the insulator 250 interposed therebetween.
  • the electric field of the conductor 260 easily acts on the entire oxide 230a and oxide 230b in the channel formation region. Therefore, the on-state current of the transistor 201 can be increased and frequency characteristics can be improved.
  • a semiconductor device including a transistor with a large on-state current can be provided.
  • a semiconductor device including a transistor having high frequency characteristics can be provided.
  • a semiconductor device including a transistor with low off-state current can be provided.
  • the oxide 230 includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b.
  • the oxide 230a is provided below the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed.
  • the oxide 230c is provided over the oxide 230b, diffusion of impurities into the oxide 230b from a structure formed above the oxide 230c can be suppressed.
  • the oxide 230 preferably has a stacked structure of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is larger than that in the metal oxide used for the oxide 230b. Is preferred. Further, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than that in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than that in the metal oxide used for the oxide 230a. As the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.
  • the oxide 230b preferably has crystallinity.
  • a CAAC-OS c-axis / aligned / crystalline / oxide / semiconductor
  • An oxide having crystallinity, such as a CAAC-OS has a high density of impurities and defects (such as oxygen vacancies), high crystallinity, and a dense structure. Therefore, extraction of oxygen from the oxide 230b by the source or the drain can be suppressed. Accordingly, even when heat treatment is performed, extraction of oxygen from the oxide 230b can be reduced, so that the transistor 201 is stable at a high temperature (a so-called thermal budget) in a manufacturing process.
  • the energy of the bottom of the conduction band of the oxide 230a and the oxide 230c be higher than the energy of the bottom of the conduction band of the oxide 230b.
  • the electron affinity of the oxide 230a and the oxide 230c be smaller than the electron affinity of the oxide 230b.
  • the energy level at the bottom of the conduction band changes gradually.
  • the energy level at the bottom of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c changes continuously or forms a continuous junction.
  • the defect state density of a mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c may be reduced.
  • the oxide 230c has a stacked structure
  • the main path of the carriers is the oxide 230b.
  • the density of defect states at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, influence of carrier scattering due to interface scattering is small, and the transistor 201 can have high on-state current and high frequency characteristics.
  • the oxide 230c has a stacked structure
  • a constituent element of the oxide 230c It is expected to suppress diffusion to More specifically, since the oxide 230c has a stacked structure and an oxide containing no In is located above the stacked structure, In that can diffuse to the insulator 250 side can be suppressed. Since the insulator 250 functions as a gate insulator, when In is diffused, the transistor has poor characteristics. Therefore, by forming the oxide 230c to have a stacked structure, a highly reliable semiconductor device can be provided. Note that for the structure, effects, and the like of the transistor 201, the transistor 200 can be referred to.
  • a substrate over which the transistor 200 and the transistor 201 are formed for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used.
  • the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate formed using silicon and germanium, and a compound semiconductor substrate formed using silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide.
  • a semiconductor substrate having an insulator region inside the above-described semiconductor substrate for example, an SOI (Silicon On Insulator) substrate.
  • the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • a substrate including a metal nitride, a substrate including a metal oxide, and the like are given.
  • a substrate provided with a conductor or a semiconductor on an insulator substrate a substrate provided with a conductor or an insulator on a semiconductor substrate, a substrate provided with a semiconductor or an insulator on a conductor substrate, and the like.
  • a substrate in which an element is provided may be used.
  • Elements provided on the substrate include a capacitor, a resistor, a switch, a light-emitting element, a storage element, and the like.
  • insulator examples include oxides, nitrides, oxynitrides, nitrided oxides, metal oxides, metal oxynitrides, and metal nitrided oxides having insulating properties.
  • a high-k material is used for an insulator functioning as a gate insulator, a voltage can be reduced during operation of a transistor while a physical thickness is maintained.
  • a material having a low relative dielectric constant for an insulator functioning as an interlayer film parasitic capacitance generated between wirings can be reduced. Therefore, a material may be selected according to the function of the insulator.
  • Examples of the insulator having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, and silicon and hafnium. Oxynitride or nitride containing silicon and hafnium.
  • Insulators having a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and voids. There is silicon oxide having a hole, resin, or the like.
  • a transistor including an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen.
  • the insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium.
  • Lanthanum, neodymium, hafnium, or an insulator containing tantalum may be used as a single layer or a stacked layer.
  • an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen
  • a metal oxide such as tantalum oxide, or a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride can be used.
  • the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen which is released by heating.
  • the oxide 230 oxygen vacancies in the oxide 230 can be compensated.
  • ⁇ Conductor> Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum It is preferable to use a metal element selected from the above, an alloy containing the above-described metal element as a component, an alloy in which the above-described metal elements are combined, or the like.
  • tantalum nitride, titanium nitride, tungsten nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, and the like Preferably, it is used.
  • tantalum nitride, titanium nitride, nitride containing titanium nitride and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are oxidized.
  • a conductive material which is difficult to be used or a material which maintains conductivity even when oxygen is absorbed is preferable.
  • a semiconductor having high electric conductivity represented by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a plurality of conductive layers formed using the above materials may be stacked.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined may be employed.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed.
  • a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.
  • a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are used for a conductor functioning as a gate may be used.
  • a conductive material containing oxygen is preferably provided on the channel formation region side.
  • a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used.
  • a conductive material containing the above-described metal element and nitrogen may be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • indium gallium zinc oxide containing nitrogen may be used.
  • Metal oxide As the oxide 230, a metal oxide that functions as an oxide semiconductor is preferably used. Hereinafter, metal oxides applicable to the oxide 230 according to the present invention will be described.
  • the metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition, it is preferable that aluminum, gallium, yttrium, tin, or the like be contained in addition thereto. In addition, one or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be included.
  • the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc is considered.
  • the element M is aluminum, gallium, yttrium, tin, or the like.
  • Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.
  • a combination of a plurality of the aforementioned elements may be used as the element M.
  • a metal oxide containing nitrogen may be collectively referred to as a metal oxide. Further, a metal oxide containing nitrogen may be referred to as metal oxynitride.
  • An oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • the non-single-crystal oxide semiconductor include a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS, a pseudo-amorphous oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.
  • Semiconductors include a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS, a pseudo-amorphous oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.
  • the CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in an ab plane direction and has a strain.
  • the strain refers to a region where the orientation of the lattice arrangement changes between a region where the lattice arrangement is uniform and a region where another lattice arrangement is uniform in a region where a plurality of nanocrystals are connected.
  • Nanocrystals are basically hexagonal, but are not limited to regular hexagons, and may be non-regular hexagons.
  • distortion may have a lattice arrangement such as a pentagon and a heptagon.
  • a lattice arrangement such as a pentagon and a heptagon.
  • the CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter, an In layer) and a layer containing elements M, zinc, and oxygen (hereinafter, a (M, Zn) layer) are stacked. It tends to have a structure (also called a layered structure).
  • indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be referred to as an (In, M, Zn) layer.
  • indium in the In layer is replaced with the element M, it can be referred to as an (In, M) layer.
  • CAAC-OS is a metal oxide with high crystallinity.
  • the CAAC-OS it is difficult to confirm a clear crystal grain boundary; thus, it can be said that electron mobility due to the crystal grain boundary is not easily reduced.
  • the crystallinity of a metal oxide may be reduced due to entry of impurities, generation of defects, or the like; therefore, the CAAC-OS is a metal oxide with few impurities and defects (such as oxygen vacancy (VO: oxygen vacancy)). It can also be said. Therefore, a metal oxide having a CAAC-OS has stable physical properties. Therefore, the metal oxide including the CAAC-OS is resistant to heat and has high reliability.
  • the nc-OS has a periodic atomic arrangement in a minute region (for example, a region from 1 nm to 10 nm inclusive, particularly a region from 1 nm to 3 nm inclusive).
  • a minute region for example, a region from 1 nm to 10 nm inclusive, particularly a region from 1 nm to 3 nm inclusive.
  • the nc-OS may not be distinguished from an a-like @ OS or an amorphous oxide semiconductor depending on an analysis method.
  • indium-gallium-zinc oxide which is a kind of metal oxide including indium, gallium, and zinc
  • IGZO indium-gallium-zinc oxide
  • a smaller crystal for example, the above-described nanocrystal
  • a large crystal here, a crystal of several mm or a crystal of several cm.
  • it may be structurally stable.
  • ⁇ A-like ⁇ OS is a metal oxide having a structure between an nc-OS and an amorphous oxide semiconductor.
  • a-like @ OS has voids or low density regions. That is, a-like @ OS has lower crystallinity than the nc-OS and the CAAC-OS.
  • Oxide semiconductors have various structures, each having different characteristics.
  • the oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like @ OS, an nc-OS, and a CAAC-OS.
  • the concentration of an alkali metal or an alkaline earth metal in a metal oxide obtained by SIMS is set to 1 ⁇ 10 18 atoms. / Cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • ⁇ ⁇ Hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • oxygen vacancy When hydrogen enters the oxygen vacancy, electrons serving as carriers are generated in some cases. Further, part of hydrogen may bond with oxygen which is bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor including a metal oxide containing hydrogen is likely to have normally-on characteristics.
  • the hydrogen concentration obtained by SIMS is less than 1 ⁇ 10 20 atoms / cm 3 , preferably less than 1 ⁇ 10 19 atoms / cm 3 , more preferably 5 ⁇ 10 18 atoms / cm 3. It is set to less than 3 , more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • a thin film with high crystallinity As a metal oxide used for a semiconductor of a transistor. With the use of the thin film, stability or reliability of the transistor can be improved.
  • the thin film include a single crystal metal oxide thin film and a polycrystalline metal oxide thin film.
  • forming a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide on a substrate requires a high-temperature or laser heating step. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.
  • FIG. 2B is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 201 in the channel length direction.
  • (C) of each drawing is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in (A), and is also a cross-sectional view of the transistor 201 in the channel width direction. Note that some components are not illustrated in the top view of FIG.
  • a substrate (not shown) is prepared, and the insulator 214 is formed over the substrate.
  • the insulator 214 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD: pulsed laser deposition method), or a molecular beam epitaxy (MBE) method. (Atomic Layer Deposition) method or the like.
  • the CVD method can be classified into a plasma CVD (Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. Further, the method can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on a used raw material gas.
  • a plasma CVD Pullasma Enhanced CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the thermal CVD method is a film formation method capable of reducing plasma damage to an object to be processed because plasma is not used.
  • a wiring, an electrode, an element (eg, a transistor or a capacitor) included in a semiconductor device may be charged up by receiving charge from plasma. At this time, the accumulated charges may destroy wirings, electrodes, elements, and the like included in the semiconductor device.
  • a thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased.
  • a plasma film having few defects can be obtained because plasma damage does not occur during film formation.
  • the ALD method utilizes the self-controlling property of atoms and can deposit atoms one by one, so that an extremely thin film can be formed, a film can be formed on a structure having a high aspect ratio, There are effects such as film formation with few defects such as holes, film formation with excellent coverage, and film formation at a low temperature.
  • the ALD method also includes a PEALD (Plasma Enhanced ALD) method which is a film formation method using plasma. Utilization of plasma makes it possible to form a film at a lower temperature, which is preferable in some cases.
  • Some precursors used in the ALD method contain impurities such as carbon. Therefore, a film formed by an ALD method may contain more impurities such as carbon than a film formed by another film formation method.
  • the impurities can be quantified by using X-ray photoelectron spectroscopy (XPS: X-ray @ Photoelectron @ Spectroscopy).
  • the CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a reaction on the surface of an object to be processed. Therefore, the film formation method is less affected by the shape of the object to be processed and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio.
  • the ALD method since the ALD method has a relatively low film formation rate, it may be preferable to use the ALD method in combination with another film formation method such as a CVD method with a high film formation rate.
  • the composition of the obtained film can be controlled by the flow rate ratio of the source gas.
  • a film having an arbitrary composition can be formed depending on a flow rate ratio of a source gas.
  • a film whose composition is continuously changed can be formed by changing the flow ratio of the source gas while forming the film.
  • silicon nitride is formed as the insulator 214 by a CVD method.
  • an insulator such as silicon nitride which does not easily transmit copper, as the insulator 214, even when a metal which easily diffuses, such as copper, is used as a conductor in a layer (not illustrated) below the insulator 214, Diffusion of the metal into an upper layer through the insulator 214 can be suppressed.
  • an insulator such as silicon nitride through which an impurity such as water or hydrogen does not easily pass, diffusion of an impurity such as water or hydrogen from a layer below the insulator 214 can be suppressed.
  • the insulator 214 may have a two-layer structure.
  • aluminum oxide may be formed over silicon nitride.
  • the insulator 216 is formed over the insulator 214.
  • the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an opening reaching the insulator 214 is formed in the insulator 216.
  • the opening includes, for example, a groove and a slit. In some cases, a region where an opening is formed is referred to as an opening.
  • the opening may be formed by wet etching, but dry etching is more preferable for fine processing.
  • an insulator which functions as an etching stopper film when the insulator 216 is etched to form a groove is preferably selected.
  • the insulator 214 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.
  • a conductive film to be the conductor 205 is formed.
  • the conductive film preferably includes a conductor having a function of suppressing transmission of oxygen.
  • tantalum nitride, tungsten nitride, titanium nitride, or the like can be used.
  • a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum tungsten alloy can be used.
  • the conductive film to be the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film serving as the conductor 205 has a multilayer structure.
  • tantalum nitride is formed by a sputtering method, and titanium nitride is stacked on the tantalum nitride.
  • a conductive film over the conductive film to be the conductor 205 is formed.
  • the conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a low-resistance conductive material such as copper is formed as a conductive film over the conductive film to be the conductor 205.
  • an upper layer of the conductive film to be the conductor 205 and part of a lower layer of the conductive film to be the conductor 205 are removed, so that the insulator 216 is exposed.
  • the conductive film serving as the conductor 205 remains only in the opening.
  • the conductor 205 having a flat top surface can be formed (see FIG. 4). Note that part of the insulator 216 may be removed by the CMP treatment.
  • a conductive film to be the conductor 205 is formed over the insulator 214.
  • the conductive film to be the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film serving as the conductor 205 can be a multilayer film. In this embodiment, tungsten is formed as a conductive film to be the conductor 205.
  • the conductive film to be the conductive material 205 is processed by lithography to form the conductive material 205.
  • a resist mask is formed by removing or leaving the exposed region using a developing solution.
  • a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape.
  • a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens to perform exposure.
  • an electron beam or an ion beam may be used instead of the above-described light.
  • the resist mask can be removed by dry etching such as ashing, wet etching, wet etching after dry etching, or dry etching after wet etching.
  • a hard mask made of an insulator or a conductor may be used instead of the resist mask.
  • an insulating film or a conductive film serving as a hard mask material is formed over the conductive film serving as the conductor 205, a resist mask is formed thereover, and the hard mask material is etched to have a desired shape.
  • a hard mask can be formed.
  • the etching of the conductive film to be the conductor 205 may be performed after removing the resist mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during the etching.
  • the hard mask may be removed by etching.
  • the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask.
  • a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used.
  • the capacitively coupled plasma etching apparatus having the parallel plate type electrode may be configured to apply a high frequency power to one of the parallel plate type electrodes.
  • a configuration in which a plurality of different high-frequency power sources are applied to one of the parallel plate electrodes may be employed.
  • a configuration in which a high-frequency power source having the same frequency is applied to each of the parallel plate electrodes may be employed.
  • a configuration may be employed in which high-frequency power sources having different frequencies are applied to the respective parallel plate electrodes.
  • a dry etching apparatus having a high-density plasma source can be used.
  • an inductively coupled plasma (ICP) etching apparatus or the like can be used.
  • an insulating film to be the insulator 216 is formed over the insulator 214 and the conductor 205.
  • the insulating film to be the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxide is formed by a CVD method.
  • the thickness of the insulating film serving as the insulator 216 is preferably greater than or equal to the thickness of the conductor 205.
  • the thickness of the conductor 205 is 1, the thickness of the insulating film to be the insulator 216 is 1 or more and 3 or less.
  • the thickness of the conductor 205 is 150 nm, and the thickness of the insulating film which is to be the insulator 216 is 350 nm.
  • CMP treatment is performed on the insulating film to be the insulator 216, so that part of the insulating film to be the insulator 216 is removed and the surface of the conductor 205 is exposed. As a result, the conductor 205 and the insulator 216 having a flat top surface can be formed.
  • the above is a different method for forming the conductor 205.
  • an insulator 222 is formed over the insulator 216 and the conductor 205.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Note that it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like as the insulator containing one or both oxides of aluminum and hafnium.
  • An insulator including an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water.
  • the insulator 222 has a barrier property to hydrogen and water, diffusion of hydrogen and water contained in a structure provided around the transistor 201 to the inside of the transistor 201 through the insulator 222 is suppressed, Generation of oxygen vacancies in the oxides 230a, 230b, and 230c can be suppressed.
  • the insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 224 is formed over the insulator 222.
  • the insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the heat treatment may be performed at a temperature of 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C.
  • the heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more.
  • the heat treatment may be performed in a reduced pressure state.
  • heat treatment is performed in a nitrogen or inert gas atmosphere, and then heat treatment is performed in an atmosphere including an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to supplement desorbed oxygen. Good.
  • the treatment is continuously performed at 400 ° C. for one hour in an oxygen atmosphere.
  • impurities such as water and hydrogen contained in the insulator 224 can be removed.
  • the heat treatment may be performed after the insulator 222 is formed.
  • the above-described heat treatment conditions can be used.
  • a plasma treatment containing oxygen may be performed under reduced pressure.
  • the plasma treatment containing oxygen it is preferable to use an apparatus having a power supply for generating high-density plasma using microwaves, for example.
  • a power supply for applying RF (Radio Frequency) to the substrate side may be provided.
  • high-density plasma high-density oxygen radicals can be generated.
  • RF Radio Frequency
  • oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224. it can.
  • plasma treatment including oxygen may be performed to supplement desorbed oxygen. Note that by appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In that case, the heat treatment may not be performed.
  • aluminum oxide may be formed over the insulator 224 by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulator 224.
  • CMP planarization of the surface of the insulator 224 and planarization of the surface of the insulator 224 can be performed.
  • the end point of the CMP can be easily detected.
  • part of the insulator 224 may be polished by CMP to reduce the thickness of the insulator 224; however, the thickness may be adjusted when the insulator 224 is formed.
  • aluminum oxide be formed over the insulator 224 by a sputtering method because oxygen can be added to the insulator 224.
  • an oxide film 230A1 and an oxide film 230B1 are sequentially formed on the insulator 224 (see FIG. 4).
  • the oxide film is preferably formed continuously without exposure to the air environment.
  • impurities or moisture from the atmospheric environment can be prevented from being attached to the oxide film 230A1 and the oxide film 230B1, and the vicinity of the interface between the oxide film 230A1 and the oxide film 230B1 can be reduced. Can be kept clean.
  • the oxide films 230A1 and 230B1 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide films 230A1 and 230B1 are formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas.
  • excess oxygen in the oxide film to be formed can be increased.
  • the above In-M-Zn oxide target can be used.
  • part of oxygen contained in a sputtering gas may be supplied to the insulator 224 when the oxide film 230A1 is formed. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230A1 may be 70% or more, preferably 80% or more, and more preferably 100%.
  • the oxide film 230B1 is formed by a sputtering method
  • the proportion of oxygen contained in a sputtering gas is greater than or equal to 1% and less than or equal to 30%, preferably greater than or equal to 5% and less than or equal to 20%
  • an oxygen-deficient oxide semiconductor is formed. It is formed.
  • a transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility.
  • the film may be formed with the proportion of oxygen contained in the sputtering gas being 70% or more, preferably 80% or more, more preferably 100%. In this case, a part of oxygen contained in the sputtering gas may be supplied to the oxide film 230A1, which is preferable.
  • heat treatment may be performed.
  • the above-described heat treatment conditions can be used.
  • impurities such as water and hydrogen in the oxide film 230A1 and the oxide film 230B1 can be removed.
  • the treatment is continuously performed at 400 ° C. for one hour in an oxygen atmosphere.
  • a film to be the hard mask 244 is formed.
  • the film to be the hard mask 244 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a film to be the hard mask 244 a film in which the hard mask 244 is hardly etched when the oxide film 230A1 and the oxide film 230B1 are processed in a subsequent step is preferable.
  • silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tungsten, molybdenum, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, or the like can be used.
  • the film to be the hard mask 244 is processed by lithography to form the hard mask 244.
  • the oxide films 230A1 and 230B1 are processed to form oxides 230A2 and 230B2. Note that in this step, the thickness of a region of the insulator 224 which does not overlap with the oxide film 230A2 may be small (see FIG. 5).
  • a conductive film 242A is formed to cover the insulator 224 and the hard mask 244 (see FIG. 6).
  • the conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the deposition rate in the horizontal direction is preferably lower than the deposition rate in the vertical direction. Assuming that the deposition rate in the vertical direction is 1, the deposition rate in the horizontal direction is preferably 0.5 or less.
  • the conductive film 242A is formed by, for example, a bias sputtering method in which a film is formed while applying a potential to a substrate, or a collimated sputtering in which a shield plate (a collimator) having a hole is inserted between a substrate and a target to control the film forming direction. Or a long throw sputtering method in which the distance between the substrate and the target is long.
  • the conductive film 242A preferably contains one or more of tin, tungsten, titanium, and silicon, and indium.
  • indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added.
  • Indium tin oxide may be used.
  • zinc oxide to which gallium is added or titanium oxide to which niobium is added may be used. In this embodiment mode, indium tin oxide is used.
  • a part of the conductive film 242A is isotropically etched (isotropically etched). This etching is performed so that the upper surface of the conductor 242B and the upper surface of the oxide 232B2 have substantially the same height, and the conductive film 242A on the side surface of the hard mask 244 is removed. Thus, a conductor 242B is formed over the insulator 224, and a conductor 242C is formed over the hard mask 244 (see FIG. 7).
  • a dry etching method or a wet etching method can be used.
  • the hard mask 244 is etched from the side. This etching is preferably performed under such a condition that the conductor 242B is etched at a lower speed so that the conductor 242B is hardly etched as compared with the etching rate of the hard mask 244.
  • FIG. 8 shows the hard mask 244 being etched.
  • the conductor 242C on the hard mask is lifted off by etching the entire hard mask 244.
  • the height of the upper surface of the oxide 230B2 is substantially equal to the height of the upper surface of the conductor 242B (see FIG. 9).
  • the oxide 230A2, the oxide 230B2, and the conductor 242B are processed by lithography to form the oxide 230a, the oxide 230c, the conductor 242a, and the conductor 242b.
  • the oxide 230a, the oxide 230b, the conductor 242a, and the conductor 242b are formed so that at least a part thereof overlaps with the conductor 205.
  • the thickness of a region of the insulator 224 which does not overlap with the oxide 230a may be thin.
  • the thickness of a region of the insulator 224 which does not overlap with the oxide 230a, the conductor 242a, and the conductor 242b may be small (see FIG. 10).
  • first heat treatment may be performed. It is preferable that the first heat treatment be performed in an atmosphere containing oxygen. Alternatively, the first heat treatment may be performed under reduced pressure and an oxide film to be the oxide 230c may be formed continuously without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b and the like can be removed, and the moisture concentration and the hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced.
  • the temperature of the first heat treatment is preferably from 100 ° C to 400 ° C, more preferably from 150 ° C to 350 ° C. In this embodiment mode, the first heat treatment is performed at a temperature of 200 ° C and under reduced pressure.
  • an oxide film to be the oxide 230c is formed (see FIG. 11).
  • the oxide film to be the oxide 230c can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film to be the oxide 230c the atomic ratio of Ga to In is preferably larger than the atomic ratio of Ga to In in the oxide 230b.
  • the oxide film to be the oxide 230c may be stacked.
  • the proportion of oxygen contained in the sputtering gas of the oxide film to be the oxide 230c may be 70% or more, preferably 80% or more, and more preferably 100%.
  • a second heat treatment may be performed.
  • the second heat treatment may be performed under reduced pressure and an insulating film to be the insulator 250 may be continuously formed without exposure to the air.
  • moisture and hydrogen adsorbed on the surface of the oxide film to be the oxide 230c are removed, and moisture in the oxide film to be the oxides 230a, 230b, and 230c is further reduced.
  • the concentration and the hydrogen concentration can be reduced.
  • the temperature of the second heat treatment is preferably from 100 ° C to 400 ° C. In this embodiment, the temperature of the second heat treatment is set to 200 ° C.
  • an insulating film to be the insulator 250 is formed (see FIG. 11).
  • the insulating film serving as the insulator 250 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • silicon oxynitride is preferably formed by a CVD method.
  • the temperature at which the insulating film to be the insulator 250 is formed is preferably higher than or equal to 250 ° C. and lower than 450 ° C., particularly, about 350 ° C.
  • a conductive film to be the conductor 260a and the conductor 260b is formed.
  • the conductive film to be the conductor 260a and the conductor 260b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a CVD method it is preferable to use a CVD method.
  • a conductive film to be the conductor 260a is formed by an ALD method
  • a conductive film to be a conductor 260b is formed by a CVD method (see FIG. 11).
  • an oxide film to be the oxide 230c, an insulating film to be the insulator 250, a conductive film to be the conductor 260a, and a conductive film to be the conductor 260b are processed by lithography, so that the oxide 230c, the insulator 250, The conductor 260 (the conductor 260a and the conductor 260b) is formed.
  • the conductor 260 is formed so that at least a part thereof overlaps with the conductor 205. (See FIG. 11).
  • a third heat treatment may be performed.
  • the third heat treatment can be performed in a nitrogen atmosphere or an atmosphere containing oxygen. It is preferable that the third heat treatment be performed in an atmosphere containing nitrogen and oxygen.
  • the proportion of oxygen is preferably 5% or more and 20% or less of the total of nitrogen and oxygen.
  • the temperature of the third heat treatment is preferably from 300 ° C to 450 ° C, more preferably from 300 ° C to 400 ° C. Typically, a temperature of 350 ° C. or near it is suitable.
  • the heat treatment time is 100 hours or less, preferably 1 hour to 48 hours. Typically, a processing time of 24 hours or a time in the vicinity thereof is preferable.
  • heat treatment By performing the heat treatment, the concentration of moisture and the concentration of hydrogen in the oxide 230, the insulator 250, and the insulator 280 can be reduced, so that the carrier density of a channel formation region of the oxide 230 can be reduced.
  • heat treatment is performed at 350 ° C. for 24 hours in a nitrogen atmosphere. Note that the heat treatment is preferably performed under such a condition that the conductor 260 is not oxidized by the third heat treatment.
  • an insulator 272 is formed to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242a, the conductor 242b, and the conductor 260 (see FIG. 11).
  • the insulator 272 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film having a function of suppressing transmission of oxygen is preferably used.
  • aluminum oxide, silicon nitride, silicon oxide, or gallium oxide may be formed by a sputtering method or an ALD method.
  • the insulator 272 may have a two-layer structure. For example, an aluminum oxide film may be formed by a sputtering method and then an aluminum oxide film may be formed by an ALD method.
  • the defect is reduced by the aluminum oxide formed by the ALD method with excellent coverage. It is preferable because it can be closed.
  • an insulating film to be the insulator 280 is formed over the insulator 272.
  • the insulating film to be the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • CMP treatment is performed on the insulating film to be the insulator 280, so that the insulator 280 having a flat top surface is formed (see FIG. 12).
  • a fourth heat treatment may be performed.
  • the fourth heat treatment is preferably performed under reduced pressure and an insulating film to be the insulator 281 is formed over the insulator 280 without exposure to the air.
  • Such treatment is preferable because moisture and hydrogen adsorbed on the surface of the insulator 280 and the like can be removed.
  • the insulating film to be the insulator 281 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 281 may have a two-layer structure.
  • an aluminum oxide film may be formed by a sputtering method, and then a silicon nitride film may be formed by a sputtering method.
  • a silicon nitride film may be formed by a sputtering method.
  • a fifth heat treatment may be performed.
  • treatment is performed at 400 ° C. for one hour in a nitrogen atmosphere.
  • oxygen added by the formation of the insulator 281 can be injected into the insulator 280.
  • the oxygen can be injected into the oxide 230a and the oxide 230b through the oxide 230c.
  • openings are formed in the insulator 272, the insulator 280, and the insulator 281 to reach the conductors 242a and 242b (see FIG. 2).
  • the formation of the opening may be performed using a lithography method.
  • an insulating film to be the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see FIG. 2).
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film having a function of suppressing transmission of oxygen is preferably used as the insulating film to be the insulator 241.
  • aluminum oxide or silicon nitride is preferably formed by an ALD method.
  • the anisotropic etching may be performed by, for example, a dry etching method.
  • a conductive film to be the conductor 240a and the conductor 240b is formed. It is preferable that the conductive film to be the conductor 240a and the conductor 240b have a stacked structure including a conductor having a function of suppressing transmission of impurities such as water and hydrogen. For example, a stack of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be used.
  • the conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • part of the conductive film to be the conductor 240a and the conductor 240b is removed, so that the insulator 281 is exposed.
  • the conductive film remains only in the opening, so that the conductor 240a and the conductor 240b having a flat top surface can be formed (see FIG. 2).
  • part of the insulator 281 may be removed by the CMP treatment.
  • the conductive film to be the conductor 246 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film serving as the conductor 246 is processed by lithography to form the conductor 246a in contact with the upper surface of the conductor 240a and the conductor 246b in contact with the upper surface of the conductor 240b (see FIG. 2).
  • a semiconductor device including the transistor 201 illustrated in FIG. 2 can be manufactured.
  • FIG. 3A is a top view of a semiconductor device including the transistor 200.
  • FIG. 3B and 3C are cross-sectional views of the semiconductor device.
  • FIG. 3B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 3A, and is also a cross-sectional view of the transistor 200 in the channel length direction.
  • 3C is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 3A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some components are not illustrated in the top view of FIG. 3A for clarity.
  • the structure of the transistor 200 will be described with reference to FIGS. Note that also in this item, as a material for forming the transistor 200, the material described in detail in ⁇ Structural Example 1 of Semiconductor Device> can be used.
  • the transistor 200 includes an insulator 216 over the insulator 214, a conductor 205 which is arranged to be embedded in the insulator 216, an insulator 222 over the insulator 216, and an insulator 222 over the conductor 205.
  • the insulator 224 on the insulator 222; the oxide 230 on the insulator 224; the conductor 242a and the conductor 242b on the oxide 230; and the conductor 242a, the conductor 242b, and the
  • the semiconductor device includes the insulator 250 and the conductor 260 (the conductor 260a and the conductor 260b) over the insulator 250.
  • the side surface of the conductor 242a and the bottom surface of the conductor 242a have a region in contact with the oxide 230
  • the side surface of the conductor 242b and the bottom surface of the conductor 242b have a region in contact with the oxide 230.
  • the height of the upper surface of the conductor 242a, the height of the upper surface of the conductor 242b, and the height of the upper surface of the oxide 230 are substantially equal to each other.
  • the semiconductor device shown in FIG. 3 is different from the semiconductor device shown in ⁇ Structural Example 1 of Semiconductor Device> (see FIG. 1) in the shape of oxide 230.
  • the step of forming an oxide film to be the oxide 230 by a lithography method half-etching is performed without completely removing the oxide film to be the oxide 230, whereby the oxide 230 having such a shape can be formed.
  • the bottom surface of the conductor 242 functioning as a source or a drain be in contact with the oxide 230 because the short-channel effect of the transistor 200 can be suppressed in some cases.
  • the semiconductor device illustrated in FIG. 1 can be referred to.
  • FIG. 14 illustrates an example of a semiconductor device (a memory device) which is one embodiment of the present invention.
  • the semiconductor device of one embodiment of the present invention includes the transistor 200, the transistor 300, and the capacitor 100.
  • the transistor 200 is provided over the transistor 300.
  • the capacitor 100 is provided over the transistor 300 and the transistor 200. ing. Note that as the transistor 200, the transistor 200 and the transistor 201 described in the above embodiment can be used.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, stored data can be held for a long time by using the transistor 200 in a memory device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.
  • the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the. Further, the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .
  • the memory devices illustrated in FIG. 14 can be arranged in a matrix to form a memory cell array.
  • the transistor 300 is provided over the substrate 311 and has a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 which is part of the substrate 311, and a transistor 313 functioning as a source or a drain. It has a resistance region 314a and a low resistance region 314b.
  • the transistor 300 may be either a p-channel transistor or an n-channel transistor.
  • a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape.
  • the conductor 316 is provided so as to cover the side surface and the top surface of the semiconductor region 313 with the insulator 315 interposed therebetween.
  • the conductor 316 may be formed using a material whose work function is adjusted.
  • Such a transistor 300 is also called a FIN transistor because it utilizes a projection of a semiconductor substrate.
  • an insulator may be provided in contact with an upper portion of the projection and functioning as a mask for forming the projection.
  • transistor 300 illustrated in FIG. 14 is an example, and there is no limitation on the structure, and an appropriate transistor may be used depending on a circuit configuration and a driving method.
  • the capacitor 100 is provided above the transistor 200.
  • the capacitor 100 includes a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric.
  • the conductor 112 provided over the conductor 246 and the conductor 110 can be formed at the same time.
  • the conductor 112 functions as a plug or a wiring which is electrically connected to the capacitor 100, the transistor 200, or the transistor 300.
  • the conductor 112 and the conductor 110 have a single-layer structure; however, the structure is not limited to this, and a stacked structure of two or more layers may be used.
  • a conductor having a barrier property and a conductor having high adhesion to a conductor having a high conductivity may be formed between a conductor having a barrier property and a conductor having a high conductivity.
  • the insulator 130 is formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. Or the like may be used, and they can be provided in a stacked or single layer.
  • the capacitor 100 has an insulator with a high dielectric constant (high-k), so that sufficient capacitance can be secured. Since the capacitor 100 has an insulator with a large dielectric strength, the dielectric strength is improved, and the capacitance is improved. Electrostatic breakdown of the element 100 can be suppressed.
  • Gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium are given as insulators of a high dielectric constant (high-k) material (a material having a high relative dielectric constant).
  • high-k high dielectric constant
  • materials having high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon and nitrogen. There is silicon oxide added, silicon oxide having pores, or a resin.
  • a wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided between the structures. Further, a plurality of wiring layers can be provided depending on the design.
  • a conductor having a function as a plug or a wiring may be given the same reference numeral by combining a plurality of structures.
  • a wiring and a plug that is electrically connected to the wiring may be integrated. That is, a part of the conductor functions as a wiring and a part of the conductor functions as a plug in some cases.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films.
  • a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, a conductor 330, or the like is embedded. Note that the conductor 328 and the conductor 330 function as plugs or wirings.
  • the insulator functioning as an interlayer film may also function as a flattening film that covers unevenness below the insulator.
  • the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.
  • CMP chemical mechanical polishing
  • a wiring layer may be provided over the insulator 326 and the conductor 330.
  • an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked.
  • a conductor 356 is formed over the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 functions as a plug or a wiring.
  • the conductor 210, the conductor (the conductor 205) included in the transistor 200, and the like are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216.
  • the conductor 218 functions as a plug or a wiring which is electrically connected to the capacitor 100 or the transistor 300.
  • an insulator 150 is provided over the conductor 120 and the insulator 130.
  • a material having a low relative dielectric constant for an insulator functioning as an interlayer film parasitic capacitance generated between wirings can be reduced. Therefore, a material may be selected according to the function of the insulator.
  • the insulator 150, the insulator 212, the insulator 352, the insulator 354, or the like preferably includes an insulator having a low relative dielectric constant.
  • the insulator includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having holes.
  • the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having holes.
  • a resin Since silicon oxide and silicon oxynitride are thermally stable, they can be combined with a resin to have a stacked structure that is thermally stable and has a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, and the like), polyimide, polycarbonate, and acryl.
  • a transistor including an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen. Therefore, an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen can be used for the insulator 210, the insulator 350, and the like.
  • Examples of the insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. , Lanthanum, neodymium, hafnium, or an insulator containing tantalum may be used as a single layer or a stacked layer.
  • an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen
  • a metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.
  • Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium.
  • a material containing at least one metal element selected from ruthenium and the like can be used.
  • a semiconductor having high electric conductivity, represented by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • a metal material, an alloy material, a metal nitride material, a metal oxide material, or the like formed using the above materials can be given.
  • a high melting point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and it is preferable to use tungsten.
  • a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, wiring resistance can be reduced.
  • an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor in some cases.
  • an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.
  • an insulator 276 may be provided between the insulator 224 containing excess oxygen and the conductor 245.
  • the insulator 224 and the transistor 200 can have a structure in which the insulator 224 and the transistor 200 are sealed with an insulator having a barrier property.
  • provision of the insulator 276 can prevent excess oxygen included in the insulator 224 from being absorbed by the conductor 245.
  • diffusion of hydrogen which is an impurity to the transistor 200 through the conductor 245 can be suppressed.
  • an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferably used.
  • impurities such as water or hydrogen and oxygen
  • a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride can be used.
  • a transistor including an oxide as a semiconductor (hereinafter, may be referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are used with reference to FIGS.
  • a storage device (hereinafter, may be referred to as an OS memory device) that is located will be described.
  • An OS memory device is a storage device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a nonvolatile memory.
  • FIG. 15A illustrates an example of a configuration of an OS memory device.
  • the storage device 1400 includes a peripheral circuit 1411 and a memory cell array 1470.
  • the peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
  • the column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like.
  • the precharge circuit has a function of precharging a wiring.
  • the sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is a wiring connected to a memory cell included in the memory cell array 1470, and will be described later in detail.
  • the amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440.
  • the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.
  • a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are externally supplied to the storage device 1400. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are externally input to the storage device 1400.
  • the address signal ADDR is input to a row decoder and a column decoder, and WDATA is input to a write circuit.
  • the control logic circuit 1460 processes an external input signal (CE, WE, RE) to generate a control signal for a row decoder and a column decoder.
  • CE is a chip enable signal
  • WE is a write enable signal
  • RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and another control signal may be input as needed.
  • the memory cell array 1470 has a plurality of memory cells MC and a plurality of wirings arranged in a matrix. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, and the like. Further, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC included in one row, and the like.
  • FIG. 15A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane
  • the present embodiment is not limited to this.
  • a memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411.
  • a structure in which a sense amplifier is provided so as to overlap below the memory cell array 1470 may be employed.
  • FIG. 16 illustrates a configuration example of a memory cell applicable to the above-described memory cell MC.
  • [DOSRAM] 16A to 16C show circuit configuration examples of a DRAM memory cell.
  • a DRAM including a memory cell of one OS transistor and one capacitor may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).
  • the memory cell 1471 illustrated in FIG. 16A includes a transistor M1 and a capacitor CA. Note that the transistor M1 has a gate (sometimes called a front gate) and a back gate.
  • a first terminal of the transistor M1 is connected to a first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, and a back gate of the transistor M1. Are connected to the wiring BGL.
  • the second terminal of the capacitor CA is connected to the wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. It is preferable that a low-level potential be applied to the wiring CAL during data writing and data reading.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed.
  • the memory cell MC may have a structure in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL as in the memory cell 1472 illustrated in FIG. 16B.
  • the memory cell MC may be a single-gate transistor, that is, a memory cell including a transistor M1 without a back gate, like the memory cell 1473 illustrated in FIG. 16C.
  • the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA.
  • the leakage current of the transistor M1 can be extremely low. That is, the written data can be held for a long time by the transistor M1, so that the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leak current is extremely low, multi-valued data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.
  • [NOSRAM] 16D to 16H show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor.
  • the memory cell 1474 illustrated in FIG. 16D includes a transistor M2, a transistor M3, and a capacitor CB.
  • the transistor M2 has a front gate (which may be simply referred to as a gate) and a back gate.
  • a storage device including a gain cell memory cell including an OS transistor as the transistor M2 may be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).
  • a first terminal of the transistor M2 is connected to a first terminal of the capacitor CB, a second terminal of the transistor M2 is connected to a wiring WBL, a gate of the transistor M2 is connected to a wiring WOL, and a back gate of the transistor M2.
  • the second terminal of the capacitor CB is connected to the wiring CAL.
  • a first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to a first terminal of the capacitor CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. It is preferable that a low-level potential be applied to the wiring CAL during data writing, data holding, and data reading.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate.
  • the memory cell MC may have a structure in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL as in a memory cell 1475 illustrated in FIG. 16E.
  • the memory cell MC may be a single-gate transistor, that is, a memory cell including a transistor M2 without a back gate, like the memory cell 1476 illustrated in FIG. 16F.
  • the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined as one wiring BIL as in a memory cell 1477 illustrated in FIG. 16G.
  • the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB.
  • the leakage current of the transistor M2 can be extremely low.
  • the written data can be held for a long time by the transistor M2, so that the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leakage current is extremely low, multi-valued data or analog data can be held in the memory cell 1474. The same applies to memory cells 1475 to 1477.
  • the transistor M3 may be a transistor including silicon in a channel formation region (hereinafter, may be referred to as a Si transistor).
  • the conductivity type of the Si transistor may be an n-channel type or a p-channel type.
  • the Si transistor may have higher field-effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a reading transistor.
  • the transistor M2 can be provided so as to be stacked over the transistor M3; therefore, the area occupied by the memory cell can be reduced and the memory device can be highly integrated.
  • the transistor M3 may be an OS transistor.
  • OS transistors are used for the transistors M2 and M3, a circuit can be formed using the memory cell array 1470 using only n-type transistors.
  • FIG. 16H shows an example of a gain cell type memory cell having three transistors and one capacitor.
  • the memory cell 1478 illustrated in FIG. 16H includes transistors M4 to M6 and a capacitor CC.
  • the capacitor CC is provided as appropriate.
  • the memory cell 1478 is electrically connected to the wirings BIL, RWL, WWL, BGL, and GNDL.
  • the wiring GNDL is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.
  • the transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.
  • the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, respectively.
  • the transistors M4 to M6 may be OS transistors.
  • a circuit can be formed using the memory cell array 1470 using only n-type transistors.
  • the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC.
  • the leakage current of the transistor M4 can be extremely low.
  • peripheral circuit 1411 the memory cell array 1470, and the like described in this embodiment are not limited to the above. Arrangement or function of these circuits and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.
  • FIGS. 4 An example of a chip 1200 in which the semiconductor device of the present invention is mounted is described with reference to FIGS.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • SoC system-on-chip
  • a chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog operation units 1213, one or more memory controllers 1214, one or more interfaces 1215. , One or more network circuits 1216 and the like.
  • CPU Central Processing Unit
  • GPU Graphics Processing Unit
  • the chip 1200 is provided with bumps (not shown), and is connected to the first surface of a printed circuit board (PCB) 1201 as shown in FIG. 17B.
  • a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201, and are connected to the motherboard 1203.
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221, a flash memory 1222, or the like.
  • a storage device such as a DRAM 1221, a flash memory 1222, or the like.
  • the DOSRAM described in the above embodiment can be used as the DRAM 1221.
  • the NOSRAM described in the above embodiment can be used for the flash memory 1222.
  • the CPU 1211 preferably has a plurality of CPU cores.
  • the GPU 1212 preferably has a plurality of GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the above-described NOSRAM or DOSRAM can be used.
  • the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and product-sum operation. By providing the GPU 1212 with an image processing circuit or a product-sum operation circuit using the oxide semiconductor of the present invention, image processing and product-sum operation can be performed with low power consumption.
  • the CPU 1211 and the GPU 1212 are provided on the same chip, wiring between the CPU 1211 and the GPU 1212 can be shortened, data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, After the calculation by the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.
  • the analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the above-described product-sum operation circuit may be provided in the analog operation unit 1213.
  • the memory controller 1214 includes a circuit functioning as a controller of the DRAM 1221 and a circuit functioning as an interface of the flash memory 1222.
  • the interface 1215 has an interface circuit with an externally connected device such as a display device, a speaker, a microphone, a camera, and a controller.
  • the controller includes a mouse, a keyboard, a game controller, and the like.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface or the like can be used as such an interface.
  • the network circuit 1216 has a network circuit such as a LAN (Local Area Network). Further, a circuit for network security may be provided.
  • LAN Local Area Network
  • the above-described circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the number of manufacturing processes does not need to be increased, and the chip 1200 can be manufactured at low cost.
  • the PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be referred to as a GPU module 1204.
  • the GPU module 1204 Since the GPU module 1204 has the chip 1200 using the SoC technology, its size can be reduced. In addition, since it is excellent in image processing, it is preferably used for portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines.
  • a product-sum operation circuit using the GPU 1212 allows a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief network ( Since operations such as DBN) can be performed, the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.
  • DNN deep neural network
  • CNN convolutional neural network
  • RNN recursive neural network
  • DBM deep Boltzmann machine
  • DBM deep Boltzmann machine
  • the semiconductor device described in the above embodiment is, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording and playback device, and a navigation system).
  • the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor device described in the above embodiment is applied to various types of removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
  • FIG. 18 schematically illustrates some configuration examples of the removable storage device.
  • the semiconductor device described in any of the above embodiments is processed into a packaged memory chip, and used for various storage devices and removable memories.
  • FIG. 18A is a schematic view of a USB memory.
  • the USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a board 1104.
  • the substrate 1104 is housed in the housing 1101.
  • a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1105 or the like of the substrate 1104.
  • FIG. 18B is a schematic diagram of the external appearance of the SD card
  • FIG. 18C is a schematic diagram of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111, a connector 1112, and a board 1113.
  • the substrate 1113 is housed in the housing 1111.
  • a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113.
  • the capacity of the SD card 1110 can be increased.
  • a wireless chip having a wireless communication function may be provided over the substrate 1113.
  • data can be read from and written to the memory chip 1114 by wireless communication between the host device and the SD card 1110.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1114 or the like of the substrate 1113.
  • FIG. 18D is a schematic diagram of the external appearance of the SSD
  • FIG. 18E is a schematic diagram of the internal structure of the SSD.
  • the SSD 1150 includes a housing 1151, a connector 1152, and a board 1153.
  • the substrate 1153 is housed in the housing 1151.
  • a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used.
  • the capacity of the SSD 1150 can be increased.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1154 or the like of the substrate 1153.
  • the semiconductor device can be used for a processor such as a CPU or a GPU or a chip.
  • FIG. 19 illustrates a specific example of an electronic device including a processor or a chip such as a CPU or a GPU according to one embodiment of the present invention.
  • the GPU or the chip according to one embodiment of the present invention can be mounted on various electronic devices.
  • the electronic device include a relatively large game machine such as a television device, a desktop or notebook personal computer, a monitor for a computer, a digital signage (digital signage), and a large game machine such as a pachinko machine.
  • a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, a sound reproducing device, and the like can be given.
  • artificial intelligence can be mounted on the electronic device.
  • the electronic device of one embodiment of the present invention may include an antenna. By receiving a signal with the antenna, an image, information, or the like can be displayed on the display portion.
  • the antenna may be used for wireless power transmission.
  • the electronic device of one embodiment of the present invention includes sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, (Including a function of measuring voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of executing various software (programs), a wireless communication It can have a function, a function of reading a program or data recorded on a recording medium, and the like.
  • FIG. 19 illustrates an example of an electronic device.
  • FIG. 19A illustrates a mobile phone (smartphone), which is a type of information terminal.
  • the information terminal 5500 includes a housing 5510 and a display portion 5511.
  • a touch panel is provided in the display portion 5511 as an input interface, and buttons are provided in the housing 5510.
  • the information terminal 5500 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • the application using artificial intelligence include an application that recognizes a conversation and displays the content of the conversation on a display portion 5511, and recognizes characters, graphics, and the like input by a user on a touch panel provided in the display portion 5511, An application displayed on the display portion 5511, an application for performing biometric authentication such as a fingerprint or a voiceprint, and the like can be given.
  • FIG. 19B illustrates a desktop information terminal 5300.
  • the desktop information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention.
  • applications using artificial intelligence include design support software, text correction software, menu automatic generation software, and the like.
  • a new artificial intelligence can be developed.
  • the electronic device is illustrated in FIGS. 19A and 19B by taking a smartphone and a desktop information terminal as examples, but information terminals other than the smartphone and the desktop information terminal can be applied.
  • Examples of the information terminal other than the smartphone and the desktop information terminal include a PDA (Personal Digital Assistant), a notebook information terminal, and a workstation.
  • FIG. 19C shows an electric refrigerator-freezer 5800 which is an example of the electric appliance.
  • the electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a refrigerator door 5803, and the like.
  • the electric refrigerator-freezer 5800 having artificial intelligence can be realized.
  • the electric refrigerator-freezer 5800 has a function of automatically generating menus based on the ingredients stored in the electric refrigerator-freezer 5800, the expiration date of the ingredients, and the like, and is stored in the electric refrigerator-freezer 5800. It can have a function of automatically adjusting the temperature to the food material.
  • the electric refrigerator was described as an electric appliance, but other electric appliances include, for example, a vacuum cleaner, a microwave oven, an electronic oven, a rice cooker, a water heater, an IH cooker, a water server, and an air conditioner including an air conditioner. Utensils, washing machines, dryers, audiovisual equipment and the like.
  • FIG. 19D illustrates a portable game machine 5200 which is an example of a game machine.
  • the portable game machine includes a housing 5201, a display portion 5202, a button 5203, and the like.
  • the portable game machine 5200 By applying the GPU or chip of one embodiment of the present invention to the portable game machine 5200, the portable game machine 5200 with low power consumption can be realized.
  • heat generation from a circuit can be reduced by low power consumption, so that influence of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced.
  • the portable game machine 5200 having artificial intelligence can be realized.
  • the expression of the progress of the game, the behavior of the creature appearing in the game, the phenomenon occurring in the game, etc. is determined by the program of the game, but by applying artificial intelligence to the portable game machine 5200, Thus, expressions that are not limited to game programs are possible. For example, it is possible to express such a content that a player asks a question, a progress of a game, a time, a behavior of a person appearing in the game changes.
  • a game player when a game requiring a plurality of players is performed on the portable game machine 5200, a game player can be configured as an anthropomorphic person by artificial intelligence. Can play games.
  • FIG. 19D illustrates a portable game machine as an example of a game machine; however, a game machine to which the GPU or the chip of one embodiment of the present invention is applied is not limited thereto.
  • a game machine to which the GPU or the chip of one embodiment of the present invention is applied for example, a stationary game machine for home use, an arcade game machine installed in an entertainment facility (a game center, an amusement park, or the like), or a sport facility Pitching machine for batting practice.
  • the GPU or the chip of one embodiment of the present invention can be applied to an automobile which is a mobile object and a periphery of a driver's seat of the automobile.
  • FIG. 19E1 shows a car 5700 which is an example of a moving object
  • FIG. 19E2 is a diagram showing the vicinity of a windshield in the cabin of the car.
  • FIG. 19E2 illustrates a display panel 5701 attached to a pillar, in addition to a display panel 5701, a display panel 5702, and a display panel 5703 attached to a dashboard.
  • the display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, an air-conditioning setting, and the like. Further, display items, layout, and the like displayed on the display panel can be appropriately changed according to the user's preference, so that design can be improved.
  • the display panels 5701 to 5703 can also be used as lighting devices.
  • the field of view (blind spot) blocked by the pillar can be complemented. That is, by displaying an image from an imaging device provided outside the automobile 5700, blind spots can be compensated for and safety can be improved. In addition, by displaying an image that complements the invisible part, it is possible to more naturally confirm safety without a sense of incongruity.
  • the display panel 5704 can be used as a lighting device.
  • the GPU or the chip of one embodiment of the present invention can be used as a component of artificial intelligence
  • the chip or the chip can be used for an automatic driving system of an automobile 5700, for example. Further, the chip can be used in a system for performing road guidance, danger prediction, and the like.
  • the display panels 5701 to 5704 may be configured to display information such as road guidance and danger prediction.
  • a car is described as an example of a moving body, but the moving body is not limited to a car.
  • a moving object includes a train, a monorail, a ship, a flying object (a helicopter, an unmanned aerial vehicle (drone), an airplane, a rocket), and the like.
  • the chip of one embodiment of the present invention is applied to these moving objects.
  • a system using artificial intelligence can be provided.
  • the GPU or the chip of one embodiment of the present invention can be applied to a broadcast system.
  • FIG. 19F schematically shows data transmission in a broadcasting system. Specifically, FIG. 19F illustrates a path until a radio wave (broadcast signal) transmitted from the broadcast station 5680 reaches a television receiver (TV) 5600 in each home.
  • the TV 5600 includes a receiving device (not shown), and a broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the receiving device.
  • the antenna 5650 is a UHF (Ultra High Frequency) antenna, but a BS / 110 ° CS antenna, a CS antenna, or the like can be used as the antenna 5650.
  • UHF Ultra High Frequency
  • the radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and the radio tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B.
  • a terrestrial TV broadcast can be viewed on the TV 5600 by receiving the radio wave 5675B with the antenna 5650.
  • the broadcasting system is not limited to terrestrial broadcasting shown in FIG. 19F, but may be satellite broadcasting using artificial satellites, data broadcasting using an optical line, or the like.
  • the broadcast system described above may be a broadcast system using artificial intelligence by applying the chip of one embodiment of the present invention.
  • the broadcast data is transmitted from the broadcast station 5680 to the TV 5600 of each home, the broadcast data is compressed by the encoder.
  • the decoder of the receiving device included in the TV 5600 decodes the broadcast data. Restore is performed.
  • artificial intelligence for example, a display pattern included in a display image can be recognized by motion compensation prediction, which is one of the compression methods of an encoder.
  • motion compensation prediction which is one of the compression methods of an encoder.
  • an image interpolation process such as up-conversion can be performed in the restoration of the broadcast data by the decoder.
  • the above-described broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcast data increases.
  • a recording device having artificial intelligence may be provided in the TV 5600.
  • the program that suits the user's preference can be automatically recorded by making the artificial intelligence of the recording device learn the user's preference.
  • samples A to C having the conductor 242 were manufactured, and the change in the sheet resistance of the conductor 242 due to the heat treatment was evaluated.
  • silicon oxide was formed with a thickness of 100 nm on a silicon wafer by thermal oxidation.
  • a 300-nm-thick silicon oxynitride film was formed over the silicon oxide film by a CVD method.
  • oxygen was implanted into the silicon oxynitride using an ion implantation apparatus.
  • the oxygen ion implantation conditions were an acceleration energy of 60 keV and an ion implantation amount of 2.0 ⁇ 10 16 / cm 2 .
  • indium tin oxide was formed as the conductor 242 by a sputtering method.
  • the film was formed at 2 kW at a substrate temperature of 200 ° C.
  • the thickness of sample A was 5 nm
  • the thickness of sample B was 10 nm
  • the thickness of sample C was 20 nm.
  • FIG. 20 shows a graph of the heat treatment time dependence of the sheet resistance value of indium tin oxide of Samples A, B, and C.
  • the sheet resistance value of the sample that was not subjected to the heat treatment (the heat treatment time was 0 hour) varied depending on the thickness of the indium tin oxide (5 nm, 10 nm, and 20 nm).
  • the sheet resistance value of any of the samples ( nm, 10 nm, and 20 nm) is from 1.0 ⁇ 10 3 ( ⁇ / sq.) To 2.0 ⁇ 10 3. ( ⁇ / sq.).
  • the sheet resistance value of any sample is from 2.0 ⁇ 10 3 ( ⁇ / sq.) To 4.0 ⁇ 10 3. ( ⁇ / sq.).
  • the conductors are oxidized under the influence of oxygen, and the sheet resistance of the conductor is increased.However, the indium tin oxide used in this embodiment is in contact with the lower surface of the indium tin oxide by heat treatment. It has been found that the influence of oxygen diffused from the disposed excess oxygen-containing silicon oxynitride is suppressed, and a low sheet resistance value is maintained.
  • indium tin oxide used in this example can function as a source and a drain of the transistor of one embodiment of the present invention.

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  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
PCT/IB2019/057266 2018-09-07 2019-08-29 半導体装置、および半導体装置の作製方法 Ceased WO2020049420A1 (ja)

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KR1020257022169A KR20250109789A (ko) 2018-09-07 2019-08-29 반도체 장치
KR1020217006924A KR102830796B1 (ko) 2018-09-07 2019-08-29 반도체 장치 및 반도체 장치의 제작 방법
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