WO2020030114A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2020030114A1
WO2020030114A1 PCT/CN2019/099995 CN2019099995W WO2020030114A1 WO 2020030114 A1 WO2020030114 A1 WO 2020030114A1 CN 2019099995 W CN2019099995 W CN 2019099995W WO 2020030114 A1 WO2020030114 A1 WO 2020030114A1
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region
conductivity type
substrate
semiconductor device
implantation
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French (fr)
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金华俊
孙贵鹏
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority to US17/265,565 priority Critical patent/US11552164B2/en
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H10D30/0285—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs using formation of insulating sidewall spacers
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
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    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1404—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase
    • H10P32/1406—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase by ion implantation
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device, and also relates to a method for manufacturing a semiconductor device.
  • a source region and a body lead-out region of a semiconductor device may be disposed in a well region.
  • a traditional arrangement method is that the source region and the body lead-out region are both strips extending along the width direction of the conductive channel, so as to be aligned in the length direction of the conductive channel, but this will cause the device to have a smaller size in the length direction of the conductive communication. Big.
  • a semiconductor device includes: a substrate; a well region provided in the substrate having a second conductivity type; a source region provided in the well region having a first conductivity type; the first conductivity type and The second conductivity type is the opposite conductivity type; the body lead-out region provided in the well region has the second conductivity type, and the source region and the body lead-out region are alternately arranged in the direction of the width of the conductive channel to form a conductive pattern.
  • a first region extending in the channel width direction, and two sides of the first region are borders where an edge of a source region and an edge of a body lead-out region are alternately arranged; and a conductive auxiliary region having a first conductivity type and provided at At least one side of the first region is in direct contact with the boundary, and the contacted portion includes an edge of at least one source region on the boundary and an edge of at least one body lead-out region on the boundary.
  • a method for manufacturing a semiconductor device includes: photolithographically forming a well region implantation window on a substrate; and implanting ions of a first conductivity type and ions of a second conductivity type into a substrate through the well region implantation window, said The first conductivity type and the second conductivity type are opposite conductivity types; thermal diffusion causes the implanted ions of the second conductivity type to form a well region, and the implanted ions of the first conductivity type form a second region; and A source region and a body lead-out region are formed in the well region; wherein the source region and the body lead-out region are alternately arranged in the width direction of the conductive channel to form a first region extending in the width direction of the conductive channel, and the first Both sides of a region are borders where the edges of the source region and the edges of the body lead-out region are alternately arranged, and the first region and a part of the second region overlap, and the second region is located in the first region.
  • a part on the outer side is used as
  • FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment
  • FIG. 2 is a schematic cross-sectional structure diagram of the semiconductor device shown in FIG. 1;
  • FIG. 3 is a schematic cross-sectional structure view of the semiconductor device shown in FIG. 1 at another position;
  • FIG. 4 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment
  • FIG. 5 is a schematic diagram of a step of forming a polysilicon of a semiconductor device at an edge of an insulating layer
  • FIG. 6 is a structural diagram of an N + lithographic plate in an embodiment
  • FIG. 7 is a layout of a semiconductor device in an embodiment
  • FIG. 8 is a flowchart of a method of manufacturing a semiconductor device in another embodiment.
  • P + type is simply referred to as P-type with heavy doping concentration.
  • P-type doping concentration P-type represents lightly doped P-type
  • N + type represents heavily doped N-type
  • N-type represents medium-doped N-type
  • N-type represents lightly-doped N type.
  • FIG. 1 is a schematic diagram of a planar structure of a semiconductor device in an embodiment
  • FIG. 2 and FIG. 3 are schematic diagrams of sectional structures at two different positions in FIG. 1, respectively.
  • the semiconductor device includes a substrate, a well region 120, a source region 122, a body lead-out region 124, and a conductive auxiliary region 126.
  • a high-voltage well region 110 is further formed in the substrate.
  • the well region 120 is formed in the high-voltage well region 110.
  • the well region 120 has a second conductivity type.
  • the source region 122 is disposed in the well region 120 and has a first conductivity type.
  • the body lead-out region 124 is disposed in the well region 120 and has a second conductivity type.
  • the semiconductor device is an N-channel device, the first conductivity type is an N-type, and the second conductivity type is a P-type.
  • the semiconductor device may also be a P-channel device, the first conductivity type It is P-type, and the second conductivity type is N-type.
  • the source regions 122 and the body lead-out regions 124 are alternately arranged in the width direction of the conductive channel to form a first region extending in the width direction of the conductive channel.
  • the two sides of the first region are the edges of the source region 122 and A boundary where the edges of the body lead-out area 124 are alternately arranged.
  • the conductive auxiliary region 126 has a first conductivity type and is provided on at least one side of the first region. In FIG. 1, it is provided on the right side of the first region.
  • the conductive auxiliary region 126 borders the right side of the first region in FIG. 1.
  • the direct contact, and the contacted portion includes an edge of at least one source region 122 on the boundary and an edge of at least one body lead-out region 124 on the boundary.
  • the source regions 122 and the body lead-out regions 124 are alternately arranged along the width direction of the conductive channel, which can reduce the size of the device in the length direction of the conductive channel. And by providing a conductive auxiliary region 126 on one side of the source region 122 and the body lead-out region 124, conductive current can flow to the source region through the conductive auxiliary region 126, optimizing the current path of the device, and compensating the body of the second conductivity type. The current loss caused by the existence of the lead-out region can reduce the on-resistance (Rdson) of the device.
  • Ron on-resistance
  • the semiconductor device further includes a drain region 130 and a gate 140, the first region is located on one side of the gate 140, and the drain region 130 is located on the other side of the gate 140.
  • the gate 140 is a polysilicon gate, and an insulating layer 142 is further disposed under the polysilicon gate.
  • the material of the insulating layer 142 is silicon oxide, such as silicon dioxide.
  • the conductive auxiliary region 126 is located under the polysilicon gate and the insulating layer 142.
  • the doping concentration of the conductive auxiliary region 126 is less than the doping concentration of the source region 122.
  • the conductive auxiliary region 126 is an N- region
  • the source region 122 is an N + region.
  • the source region 122 is an N-type heavily doped (NSD) region
  • the body lead-out region 124 is a P-type heavily doped (PSD) region.
  • the high-voltage well region 110 is a high-voltage N-well (HN).
  • the conductive auxiliary region 126 is performed by using the same lithographic plate as the well region 120, that is, the conductive auxiliary region 126 and the well region 120 are both implanted through the photolithography and formed by implantation. Ion implantation is performed in the window, and then the conductive auxiliary region 126 and the well region 120 are formed (thermal diffusion can be performed after implantation, and the implanted ions form the conductive auxiliary region 126 / well region 120 after thermal diffusion). For example, after the implantation window is formed using the photolithography, the ions of the second conductivity type are implanted to form the well region 120, and the ions of the first conductivity type are implanted to form the conductive auxiliary region 126.
  • the step of implanting ions of the first conductivity type will inevitably form a doped region of the first conductivity type in a larger area (because its size is determined by the implantation window of the well region 120, and the well region 120 is more Large), for convenience of description, the region corresponding to the doped region of the first conductivity type is referred to as a second region below.
  • the second region is partially overlapped with the source region 122 and the body lead-out region 124. See FIG. 2 and FIG. 3.
  • the part that overlaps the source region 122 and the second region is the region 126a, and the part that overlaps with the body lead-out region 124 is a region. 126b, a portion on the outer side of the first region is a conductive auxiliary region 126.
  • the doping concentration of the first conductivity type ions in the region 126a will be different from the doping concentration of the first conductivity type ions in other parts of the source region 122, and the doping concentration of the first conductivity type ions in the region 126b will be different from the bulk extraction.
  • ions of a first conductivity type are implanted to form a conductive auxiliary region 126, the implantation energy of which is between 15keV-50keV.
  • the implanted ions are arsenic (As) ions.
  • FIG. 4 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment, including the following steps:
  • a well region implantation window is formed on the substrate by photolithography.
  • the implantation window is formed using photolithography using a well region reticle.
  • a high-voltage well region may be formed on the substrate, for example, a high-voltage N-well, and then step S410 may be performed.
  • the semiconductor device is an N-channel device, the first conductivity type is an N-type, and the second conductivity type is a P-type. In other embodiments, the semiconductor device may also be a P-channel device, the first conductivity type It is P-type, and the second conductivity type is N-type.
  • S430 The thermal diffusion forms a well region and a second region.
  • step S420 the implanted ions of the second conductivity type form a well region after thermal diffusion, and the implanted ions of the first conductivity type form a second region after thermal diffusion.
  • both the well region and the second region are formed in a high-voltage well region.
  • the source regions and the body lead-out regions are alternately arranged in the width direction of the conductive channel to form a first region extending in the width direction of the conductive channel.
  • the two sides of the first region are borders where the edges of the source region and the edges of the body lead-out region are alternately arranged.
  • the conductive auxiliary region, where the conductive auxiliary region directly contacts the boundary includes an edge of at least one source region on the boundary and an edge of at least one body lead-out region on the boundary.
  • the implantation of the conductive auxiliary region uses the same implantation window as the well region, that is, the implantation window formed after the well region is lithographically used for both the implantation of the well region and the implantation of the conductive auxiliary region.
  • the formation of the conductive auxiliary region does not need to increase the photolithography plate, which is beneficial to control the production cost.
  • the method before step S410, further includes the steps of forming a polysilicon layer on the substrate and etching the polysilicon layer to form a polysilicon gate.
  • the ion implantation of the first conductivity type in S420 uses a smaller implantation energy, and the implantation does not penetrate the polysilicon layer into the underlying substrate.
  • the implantation energy is between 15keV-50keV.
  • the implanted ions are arsenic (As) ions.
  • the conductive auxiliary region is diffused under the polysilicon layer after the etching along the length of the conductive channel through thermal diffusion, for example, under the polysilicon gate.
  • step S440 is photolithography and forms a source region and a body lead-out region by ion implantation. Specifically, the source region is implanted with ions of the first conductivity type, and the lead-out region of the ion conductivity is formed with the second conductivity type.
  • step S440 in which the source region 222 and the body lead-out region (not shown in FIG. 5) are formed by ion implantation after photolithography, after the photolithography step is coated with photoresist, the photoresist will cover the gate 240, then The photoresist will also form a step at A.
  • This step will cause the exposure light to be refracted at the photoresist step when the photolithography step is exposed.
  • the refracted exposure light will also affect the areas we do not want to develop, thus
  • the injection window of step S440 is deformed.
  • the refraction occurring at the photoresist step will cause the exposure light to irradiate the photoresist in the body lead-out area, which will cause the photoresist originally blocked in the body lead-out area.
  • the coverage area is reduced, so that the implantation area of the source region becomes larger and the implantation area of the body lead-out region decreases.
  • the reduction of the implanted area of the body lead-out area is equivalent to the reduction of the total dose of implanted body lead-out area, which will cause the aforementioned parasitic NPN to turn on, thereby affecting the conduction characteristics of the device.
  • the inventor redesigned the layout of the device, and specifically redesigned the photoresist used in the source region ion implantation in step S440.
  • the N + photoresist 100 includes a first implantation region 20 and a second implantation region 10 separated from each other.
  • the photoresist is used with a positive resist.
  • the first implantation region 20 and the second implantation region 10 are lithographic Light transmission area.
  • the N + photoresist 100 further includes a light-shielding region 32 between the first implantation region 20 and the second implantation region 10.
  • the first implantation region 20 is used to form a source region
  • the second implantation region 10 is used to form a drain region.
  • the first implantation region 20 includes a plurality of PSD regions 22 inside, and the PSD region 22 is also a light-shielding region of the photolithographic plate. After the photolithography is performed using the N + photoresist 100, the PSD region 22 causes the photoresist to block the body lead-out region and prevents the first conductive type ion from being implanted.
  • FIG. 7 is a layout of a corresponding semiconductor device. Please refer to FIG. 5, FIG. 6, FIG. 7, FIG. 5, FIG. 6, and FIG. 7 are both left-right symmetrical (axisymmetric) structures.
  • the area 340 in FIG. 7 corresponds to FIG. 5.
  • the gate 240, the region 330 corresponds to the drain region 230, the region 322 corresponds to the source region 222, the region 320 corresponds to the well region 220, and the region 352 corresponds to the insulating layer 252; and, the region 330 in FIG. 7 corresponds to the first Two implantation regions 10, region 322 corresponds to the first implantation region 20, and region 324 corresponds to the PSD region 22.
  • the semiconductor device shown in FIG. 5 is an N-channel semiconductor device.
  • a high voltage well region (HN) 210 is also formed in the substrate, a drain 230 is an N + drain, and is an N-type heavily doped region (NSD).
  • the source is 222 is an N + source and is an N-type heavily doped region (NSD)
  • the well region 220 is a P-type doped region (PB)
  • the gate 240 includes a polysilicon gate.
  • the N + photoresist 100 has a light-shielding region 32 between the first implantation region 20 and the second implantation region 10, the light-shielding region 32 prevents the exposure light from irradiating the photoresist step (the step is located at (Above step A in FIG. 5), avoiding light refraction at the step of the photoresist, and thus reducing the implantation area of the body lead-out area, thereby ensuring the conduction characteristics and self-protection capability of the device.
  • FIG. 8 is a flowchart of a method of manufacturing a semiconductor device according to another embodiment, including steps:
  • an insulating layer is formed on the substrate.
  • the material of the insulating layer is silicon oxide, such as silicon dioxide.
  • a polysilicon layer is formed on the substrate and the multiple insulating layers.
  • the polysilicon layer can be formed by a deposition process.
  • the polysilicon layer is etched to form a polysilicon gate.
  • polysilicon field plates can also be formed.
  • a portion of the polysilicon remaining after the etching is completed is located on the insulating layer 252, and a portion of the polysilicon extends beyond the edge of the insulating layer 252 to the substrate, thereby forming a step A at the edge of the insulating layer.
  • a well region implantation window is formed by photolithography on the substrate.
  • a high voltage well region may be formed on the substrate before step S840, for example, a high voltage N well may be formed.
  • the implanted ions of the second conductivity type are used to form a well region, and the implanted ions of the first conductivity type are used to form a second region.
  • thermal diffusion forms a well region and a second region.
  • step S860 the implanted ions of the second conductivity type form a well region after thermal diffusion, and the implanted ions of the first conductivity type form a second region after thermal diffusion.
  • both the well region and the second region are formed in a high-voltage well region.
  • a source region and a body lead-out region are respectively formed by ion implantation.
  • the photoresist covers the gate 240, so it is easy to form a photoresist step at the step A as well.
  • N + photoresist 100 is used for photolithography.
  • the light-shielding region 32 will prevent the exposure light from irradiating the photoresist step, avoiding the light refracting at the photoresist step, and avoiding the injection area of the body lead-out area. This reduces the conduction characteristics and self-protection capabilities of the device.
  • the source regions and the body lead-out regions are alternately arranged in the width direction of the conductive channel to form a first region extending in the width direction of the conductive channel.
  • the two sides of the first region are borders where the edges of the source region and the edges of the body lead-out region are alternately arranged.
  • the conductive auxiliary region, where the conductive auxiliary region directly contacts the boundary includes an edge of at least one source region on the boundary and an edge of at least one body lead-out region on the boundary.

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种半导体器件及其制造方法，所述半导体器件包括：衬底；设于衬底中的阱区(120)，具有第二导电类型；设于所述阱区(120)中的源极区(122)，具有第一导电类型；设于所述阱区(120)中的体引出区(124)，具有第二导电类型，所述源极区(122)和体引出区(124)在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域，所述第一区域的两侧为源极区(122)的边缘和体引出区(124)的边缘交替排列而成的边界；导电辅助区(126)，具有第一导电类型，设于所述第一区域的至少一侧，与所述边界直接接触，且接触的部位包括所述边界上至少一个源极区的边缘和边界上至少一个体引出区的边缘。

Description

半导体器件及其制造方法 技术领域
本发明涉及半导体制造领域，特别是涉及一种半导体器件，还涉及一种半导体器件的制造方法。
背景技术
半导体器件的源极区和体引出区可以设置在阱区中。一种传统的设置方式是源极区和体引出区均为沿导电沟道宽度方向延伸的条形，从而在导电沟道长度方向上排列，但这样会导致器件在导电沟通长度方向的尺寸较大。
发明内容
基于此，有必要提供一种半导体器件及其制造方法。
一种半导体器件，包括：衬底；设于衬底中的阱区，具有第二导电类型；设于所述阱区中的源极区，具有第一导电类型，所述第一导电类型和第二导电类型为相反的导电类型；设于所述阱区中的体引出区，具有第二导电类型，所述源极区和体引出区在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域，所述第一区域的两侧为源极区的边缘和体引出区的边缘交替排列而成的边界；及导电辅助区，具有第一导电类型，设于所述第一区域的至少一侧，与所述边界直接接触，且接触的部位包括所述边界上至少一个源极区的边缘和边界上至少一个体引出区的边缘。
一种半导体器件的制造方法，包括：在衬底上光刻形成阱区注入窗口；通过所述阱区注入窗口向衬底内注入第一导电类型的离子和第二导电类型的离子，所述第一导电类型和第二导电类型为相反的导电类型；热扩散使注入的所述第二导电类型的离子形成阱区，注入的所述第一导电类型的离子形成 第二区域；及在所述阱区中形成源极区和体引出区；其中，所述源极区和体引出区在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域，所述第一区域的两侧为源极区的边缘和体引出区的边缘交替排列而成的边界，所述第一区域和所述第二区域的一部分重合，所述第二区域位于所述第一区域外的一侧的部位作为导电辅助区，所述导电辅助区与所述边界直接接触的部位包括所述边界上至少一个源极区的边缘和边界上至少一个体引出区的边缘。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中半导体器件的平面结构示意图；
图2是图1所示半导体器件的剖面结构示意图；
图3是图1所示半导体器件在另一位置的剖面结构示意图；
图4是一实施例中半导体器件的制造方法的流程图；
图5是半导体器件的多晶硅在绝缘层边缘处形成台阶的示意图；
图6是一实施例中N+光刻版的结构图；
图7是一实施例中半导体器件的版图；
图8是另一实施例中半导体器件的制造方法的流程图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来 实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中半导体器件的平面结构示意图，图2和图3分别是图1两个不同位置的剖面结构示意图。请一并参照图1、图2、图3，在该实施例中，半导体器件包括衬底、阱区120、源极区122、体引出区124、导电辅助区126。在图1所示的实施例中，衬底中还形成有高压阱区110，阱区120是形成于高压阱区110中，阱区120具有第二导电类型。源极区122设于阱区120中，具有第一导电类型。体引出区124设于阱区120中，具有第二导电类型。在一个实施例中，半导体器件为N沟道器件，第一导电类型为N型，第二导电类型为P型；在其他实施例中，半导体器件也可以为P沟道器件，第一导电类型为P型，第二导电类型为N型。
参照图1，源极区122和体引出区124在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域，第一区域的两侧为源极区122的边缘和体引出区124的边缘交替排列而成的边界。导电辅助区126具有第一导电类型，设于第一区域的至少一侧，在图1中是设于第一区域的右侧；导电辅助区126在图1中与第一区域的右侧边界直接接触，且接触的部位包括边界上至少一个源极区122的边缘和边界上至少一个体引出区124的边缘。
上述半导体器件，源极区122和体引出区124沿导电沟道宽度方向交替 排列，可以减小器件在导电沟道长度方向的尺寸。并且通过在源极区122和体引出区124的一侧设置导电辅助区126，导电电流可以通过导电辅助区126流到源极区，优化了器件的电流路径，补偿了第二导电类型的体引出区的存在导致的电流损失，能够降低器件的导通电阻(Rdson)。
在一个实施例中，半导体器件还包括漏极区130和栅极140，第一区域位于栅极140的一侧，漏极区130位于栅极140的另一侧。在一个实施例中，栅极140为多晶硅栅，多晶硅栅下方还设有绝缘层142。在一个实施例中，绝缘层142的材质为硅氧化物，例如二氧化硅。
在一个实施例中，导电辅助区126位于多晶硅栅和绝缘层142的下方。
在一个实施例中，导电辅助区126的掺杂浓度小于源极区122的掺杂浓度。在图1所示实施例中，导电辅助区126为N-区，源极区122为N+区。
在一个实施例中，源极区122为N型重掺杂(NSD)区域，体引出区124为P型重掺杂(PSD)区域。
在图1所示实施例中，高压阱区110为高压N阱(HN)。
为了简化制造工艺，在一个实施例中，导电辅助区126是与阱区120采用同一张光刻版进行，即导电辅助区126和阱区120都是通过该光刻版光刻后形成的注入窗口进行离子注入，之后形成导电辅助区126和阱区120(注入后可以进行热扩散，注入的离子在热扩散后形成导电辅助区126/阱区120)。例如可以使用该光刻版光刻形成注入窗口后，先注入第二导电类型的离子，以形成阱区120，之后再注入第一导电类型的离子，以形成导电辅助区126。如此一来，该注入第一导电类型的离子的步骤必然会在较大的区域内形成第一导电类型的掺杂区(因为其大小是阱区120的注入窗口决定的，而阱区120较大)，为便于描述，以下将该第一导电类型的掺杂区对应的区域记为第二区域。该第二区域会与源极区122和体引出区124部分重合，参见图2和图3，第二区域与源极区122重合的部分为区域126a，与体引出区124重合的部分为区域126b，位于第一区域外一侧的部分为导电辅助区126。区域126a的第一导电类型离子的掺杂浓度会不同于源极区122的其他部分的第 一导电类型离子的掺杂浓度，区域126b的第一导电类型离子的掺杂浓度会不同于体引出区124的其他部分的第一导电类型离子的掺杂浓度，但由于第二区域是浓度较低的注入，因此不会对源极区122和体引出区124内部的电性能造成明显的影响。
在一个实施例中，注入第一导电类型的离子以形成导电辅助区126，其注入能量在15keV-50keV之间。在一个实施例中，注入的离子为砷(As)离子。
还有必要提供一种半导体器件的制造方法，可以用于制造以上任一实施例的半导体器件。图4是一实施例中半导体器件的制造方法的流程图，包括以下步骤：
S410，在衬底上光刻形成阱区注入窗口。
使用阱区光刻版光刻形成注入窗口。在一个实施例中，可以先在衬底上形成高压阱区，例如可以是高压N阱，然后再进行步骤S410。
S420，通过阱区注入窗口向衬底内注入第一和第二导电类型的离子。
注入的第二导电类型的离子用于形成阱区，注入的第一导电类型的离子用于形成第二区域。在一个实施例中，半导体器件为N沟道器件，第一导电类型为N型，第二导电类型为P型；在其他实施例中，半导体器件也可以为P沟道器件，第一导电类型为P型，第二导电类型为N型。
S430，热扩散形成阱区和第二区域。
步骤S420注入的第二导电类型的离子热扩散后形成阱区，注入的第一导电类型的离子热扩散后形成第二区域。在一个实施例中，阱区和第二区域均是形成于高压阱区中。
S440，在阱区中形成源极区和体引出区。
源极区和体引出区在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域。第一区域的两侧为源极区的边缘和体引出区的边缘交替排列而成的边界，第一区域和第二区域的一部分重合，第二区域位于第一区域外的一侧的部位作为导电辅助区，导电辅助区与边界直接接触的部 位包括边界上至少一个源极区的边缘和边界上至少一个体引出区的边缘。
上述半导体器件的制造方法，导电辅助区的注入采用与阱区相同的注入窗口，即阱区光刻后形成的注入窗口既用于阱区的注入，又用于导电辅助区的注入。导电辅助区的形成不需要增加光刻版，利于控制生产成本。
在一个实施例中，步骤S410之前，还包括在衬底上形成多晶硅层及刻蚀多晶硅层形成多晶硅栅的步骤。S420中第一导电类型的离子注入采用较小的注入能量，该注入不会穿透多晶硅层进入下方的衬底。在一个实施例中，注入能量在15keV-50keV之间。在一个实施例中，注入的离子为砷(As)离子。导电辅助区通过热扩散沿导电沟道长度方向扩散至刻蚀后的多晶硅层下方，例如是多晶硅栅的下方。
在一个实施例中，步骤S440是光刻并通过离子注入形成源极区和体引出区，具体是注入第一导电类型的离子形成源极区，注入第二导电类型的离子形成体引出区。
发明人在实际生产制造中发现，有时候器件的导通特性会出现问题。发明人经实验研究，认为该导通特性的问题是第一区域的源极区和体引出区发生了寄生NPN三极管开启的现象，且发明人认为，导致寄生NPN三极管开启的其中一个原因，是体引出区的实际注入剂量小于设计注入剂量。
参见图5，栅极240下方存在一定厚度的绝缘层252作为场板，由于栅极240的多晶硅会越过绝缘层252一侧的边缘延伸至衬底上，绝缘层252边缘与衬底的高度差就会导致此处形成台阶A。对于步骤S440采用光刻后离子注入形成源极区222和体引出区(图5中未示)的实施例，该光刻步骤涂覆光刻胶后，光刻胶会覆盖栅极240，那么光刻胶同样会在A处形成台阶，该台阶会导致该光刻步骤曝光时，曝光光线在光刻胶台阶处发生折射，折射的曝光光线会导致我们不希望显影的区域也受到影响，从而使得步骤S440的注入窗口变形。具体地，对于光刻胶为正胶的实施例，光刻胶台阶处发生的折射会导致曝光光线照射到体引出区的光刻胶，这样就会导致原本挡在体引出区的光刻胶覆盖的面积减小，从而源极区注入面积变大、体引出区注入面积 减小。体引出区注入面积减小相当于体引出区注入总的剂量减小，就会导致前述的寄生的NPN开启，从而影响器件的导通特性。
为了解决这一问题，发明人重新设计了器件的版图，具体是对步骤S440中源极区离子注入使用的光刻版进行重新设计。参见图6，N+光刻版100包括相互分离的第一注入区20和第二注入区10，该光刻版配合正胶使用，第一注入区20和第二注入区10是光刻版的透光区。N+光刻版100还包括位于第一注入区20和第二注入区10之间的遮光区32，第一注入区20用于形成源极区，第二注入区10用于形成漏极区。第一注入区20内部包括多个PSD区22，PSD区22也是光刻版的遮光区。使用N+光刻版100光刻后，PSD区22会使得光刻胶将体引出区挡住，不让第一导电类型离子注入。
图7是相应的半导体器件版图，请一并参见图5、图6、图7，图5、图6、图7均为左右对称(轴对称)的结构，图7中的区域340对应图5中的栅极240，区域330对应漏极区230，区域322对应源极区222，区域320对应阱区220，区域352对应绝缘层252；并且，图7中的区域330对应图6中的第二注入区10，区域322对应第一注入区20，区域324对应PSD区22。图5所示半导体器件为N沟道半导体器件，在衬底中还形成有高压阱区(HN)210，漏极230为N+漏极，且为N型重掺杂区(NSD)，源极222为N+源极，且为N型重掺杂区(NSD)，阱区220为P型掺杂区(PB)，栅极240包括多晶硅栅。
由于N+光刻版100在第一注入区20和第二注入区10之间设置了遮光区32，在光刻曝光时，遮光区32会阻止曝光光线照射到光刻胶的台阶(该台阶位于图5中台阶A的上方)，避免了光线在光刻胶的台阶处发生折射，也就避免了体引出区注入面积的减小，从而能够确保器件的导通特性以及自保护能力。
图8是另一实施例中半导体器件的制造方法的流程图，包括步骤：
S810，在衬底上形成绝缘层。
在一个实施例中，绝缘层的材质为硅氧化物，例如二氧化硅。
S820，在衬底和多绝缘层上形成多晶硅层。
多晶硅层可以用淀积工艺形成。
S830，刻蚀多晶硅层形成多晶硅栅。
除了多晶硅栅，还可以形成多晶硅场板。在图5所示的实施例中，刻蚀完成后剩余的多晶硅部分位于绝缘层252上、部分越过绝缘层252一侧的边缘延伸至衬底上，从而在绝缘层的边缘处形成台阶A。
S840，在衬底上光刻形成阱区注入窗口。
在一个实施例中，步骤S840之前可以先在衬底上形成高压阱区，例如可以是高压N阱。
S850，通过阱区注入窗口向衬底内注入第一和第二导电类型的离子。
注入的第二导电类型的离子用于形成阱区，注入的第一导电类型的离子用于形成第二区域。
S860，热扩散形成阱区和第二区域。
步骤S860注入的第二导电类型的离子热扩散后形成阱区，注入的第一导电类型的离子热扩散后形成第二区域。在一个实施例中，阱区和第二区域均是形成于高压阱区中。
S870，在阱区中形成源极区和体引出区。
在一个实施例中，是光刻形成注入窗口后，通过离子注入分别形成源极区和体引出区。
涂胶后，光刻胶覆盖在栅极240上，所以容易在台阶A处也形成光刻胶台阶。本步骤使用N+光刻版100进行光刻，遮光区32会阻止曝光光线照射到光刻胶的台阶处，避免了光线在光刻胶的台阶处发生折射，也就避免了体引出区注入面积的减小，从而能够确保器件的导通特性以及自保护能力。
源极区和体引出区在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域。第一区域的两侧为源极区的边缘和体引出区的边缘交替排列而成的边界，第一区域和第二区域的一部分重合，第二区域位于第一区域外的一侧的部位作为导电辅助区，导电辅助区与边界直接接触的部位包括边界上至少一个源极区的边缘和边界上至少一个体引出区的边缘。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体器件，包括：
    衬底；
    设于衬底中的阱区，具有第二导电类型；
    设于所述阱区中的源极区，具有第一导电类型，所述第一导电类型和第二导电类型为相反的导电类型；
    设于所述阱区中的体引出区，具有第二导电类型，所述源极区和体引出区在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域，所述第一区域的两侧为源极区的边缘和体引出区的边缘交替排列而成的边界；及
    导电辅助区，具有第一导电类型，设于所述第一区域的至少一侧，与所述边界直接接触，且接触的部位包括所述边界上至少一个源极区的边缘和边界上至少一个体引出区的边缘。
  2. 根据权利要求1所述的半导体器件，其中，所述导电辅助区的掺杂浓度小于所述源极区的掺杂浓度。
  3. 根据权利要求1所述的半导体器件，其中，还包括漏极区和栅极，所述第一区域位于所述栅极的一侧，所述漏极区位于所述栅极的另一侧。
  4. 根据权利要求1所述的半导体器件，其中，还包括设于所述阱区中的第二区域，所述第二区域与所述源极区、体引出区部分重合，所述第二区域与所述导电辅助区是在同一步离子注入工艺和热扩散工艺中形成。
  5. 根据权利要求3所述的半导体器件，其中，所述栅极为多晶硅栅，所述多晶硅栅下方还设有绝缘层。
  6. 根据权利要求5所述的半导体器件，其中，所述导电辅助区位于多晶硅栅和绝缘层的下方。
  7. 根据权利要求1所述的半导体器件，其中，所述第一导电类型为N型，所述第二导电类型为P型。
  8. 一种半导体器件的制造方法，包括：
    在衬底上光刻形成阱区注入窗口；
    通过所述阱区注入窗口向衬底内注入第一导电类型的离子和第二导电类型的离子，所述第一导电类型和第二导电类型为相反的导电类型；
    热扩散使注入的所述第二导电类型的离子形成阱区，注入的所述第一导电类型的离子形成第二区域；及
    在所述阱区中形成源极区和体引出区；其中，所述源极区和体引出区在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域，所述第一区域的两侧为源极区的边缘和体引出区的边缘交替排列而成的边界，所述第一区域和所述第二区域的一部分重合，所述第二区域位于所述第一区域外的一侧的部位作为导电辅助区，所述导电辅助区与所述边界直接接触的部位包括所述边界上至少一个源极区的边缘和边界上至少一个体引出区的边缘。
  9. 根据权利要求8所述的方法，其中，所述通过所述阱区注入窗口向衬底内注入第一导电类型的离子的步骤中，注入能量在15keV-50keV之间。
  10. 根据权利要求8所述的方法，所述通过所述阱区注入窗口向衬底内注入第一导电类型的离子的步骤中，注入的离子为砷离子。
  11. 根据权利要求8所述的方法，其中，所述在衬底上光刻形成阱区注入窗口的步骤之前，还包括在所述衬底上形成多晶硅层及刻蚀所述多晶硅层形成多晶硅栅的步骤。
  12. 根据权利要求11所述的方法，其中，所述在所述衬底上形成多晶硅层及刻蚀所述多晶硅层形成多晶硅栅的步骤之前，还包括在所述衬底上形成绝缘层的步骤，刻蚀完成后剩余的多晶硅部分位于所述绝缘层上、部分越过所述绝缘层一侧的边缘延伸至所述衬底上；
    所述在所述阱区中形成源极区和体引出区的步骤，包括使用第一光刻版进行光刻形成第一导电类型离子注入窗口，然后通过所述第一导电类型离子注入窗口向衬底内注入第一导电类型的离子；其中，所述第一光刻版包括相 互分离的第一注入区和第二注入区，所述第一注入区和第二注入区是透光区，所述第一光刻版还包括位于第一注入区和第二注入区之间的遮光区，所述第一注入区用于形成源极区，所述第二注入区用于形成漏极区。
  13. 根据权利要求11所述的方法，还包括通过热扩散使得所述导电辅助区沿导电沟道长度方向扩散至所述多晶硅栅的下方的步骤。
  14. 根据权利要求12所述的方法，其中，所述使用第一光刻版进行光刻的步骤中，涂覆的光刻胶在所述绝缘层一侧的边缘上方形成台阶，所述遮光区用于在光刻曝光时阻止曝光光线照射到所述台阶。
  15. 根据权利要求12所述的方法，其中，所述使用第一光刻版进行光刻的步骤中，采用的光刻胶是正胶。
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