CN110828540B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

Info

Publication number
CN110828540B
CN110828540B CN201810914285.8A CN201810914285A CN110828540B CN 110828540 B CN110828540 B CN 110828540B CN 201810914285 A CN201810914285 A CN 201810914285A CN 110828540 B CN110828540 B CN 110828540B
Authority
CN
China
Prior art keywords
region
substrate
conductivity type
regions
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810914285.8A
Other languages
English (en)
Other versions
CN110828540A (zh
Inventor
金华俊
孙贵鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Fab2 Co Ltd
Original Assignee
CSMC Technologies Fab2 Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Fab2 Co Ltd filed Critical CSMC Technologies Fab2 Co Ltd
Priority to CN201810914285.8A priority Critical patent/CN110828540B/zh
Priority to PCT/CN2019/099995 priority patent/WO2020030114A1/zh
Priority to US17/265,565 priority patent/US11552164B2/en
Publication of CN110828540A publication Critical patent/CN110828540A/zh
Application granted granted Critical
Publication of CN110828540B publication Critical patent/CN110828540B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明涉及一种半导体器件及其制造方法，所述半导体器件包括：衬底；设于衬底中的阱区，具有第二导电类型；设于所述阱区中的源极区，具有第一导电类型；设于所述阱区中的体引出区，具有第二导电类型，所述源极区和体引出区在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域，所述第一区域的两侧为源极区的边缘和体引出区的边缘交替排列而成的边界；导电辅助区，具有第一导电类型，设于所述第一区域的至少一侧，与所述边界直接接触，且接触的部位包括所述边界上至少一个源极区的边缘和边界上至少一个体引出区的边缘。本发明在源极区和体引出区的一侧设置导电辅助区，能够降低器件的导通电阻。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体制造领域，特别是涉及一种半导体器件，还涉及一种半导体器件的制造方法。
背景技术
半导体器件的源极区和体引出区可以设置在阱区中。一种传统的设置方式是源极区和体引出区均为沿导电沟道宽度方向延伸的条形，从而在导电沟道长度方向上排列，但这样会导致器件在导电沟通长度方向的尺寸较大。
发明内容
基于此，有必要提供一种半导体器件及其制造方法。
一种半导体器件，包括：衬底；设于衬底中的阱区，具有第二导电类型；设于所述阱区中的源极区，具有第一导电类型，所述第一导电类型和第二导电类型为相反的导电类型；设于所述阱区中的体引出区，具有第二导电类型，所述源极区和体引出区在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域，所述第一区域的两侧为源极区的边缘和体引出区的边缘交替排列而成的边界；及导电辅助区，具有第一导电类型，设于所述第一区域的至少一侧，与所述边界直接接触，且接触的部位包括所述边界上至少一个源极区的边缘和边界上至少一个体引出区的边缘。
在其中一个实施例中，所述导电辅助区的掺杂浓度小于所述源极区的掺杂浓度。
在其中一个实施例中，还包括漏极区和栅极，所述第一区域位于所述栅极的一侧，所述漏极区位于所述栅极的另一侧。
在其中一个实施例中，还包括设于所述阱区中的第二区域，所述第二区域与所述源极区、体引出区部分重合，所述第二区域与所述导电辅助区是在同一步离子注入工艺和热扩散工艺中形成。
一种半导体器件的制造方法，包括：在衬底上光刻形成阱区注入窗口；通过所述阱区注入窗口向衬底内注入第一导电类型的离子和第二导电类型的离子，所述第一导电类型和第二导电类型为相反的导电类型；热扩散使注入的所述第二导电类型的离子形成阱区，注入的所述第一导电类型的离子形成第二区域；及在所述阱区中形成源极区和体引出区；其中，所述源极区和体引出区在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域，所述第一区域的两侧为源极区的边缘和体引出区的边缘交替排列而成的边界，所述第一区域和所述第二区域的一部分重合，所述第二区域位于所述第一区域外的一侧的部位作为导电辅助区，所述导电辅助区与所述边界直接接触的部位包括所述边界上至少一个源极区的边缘和边界上至少一个体引出区的边缘。
在其中一个实施例中，所述通过所述阱区注入窗口向衬底内注入第一导电类型的离子的步骤中，注入能量在15keV-50keV之间。
在其中一个实施例中，所述在衬底上光刻形成阱区注入窗口的步骤之前，还包括在所述衬底上形成多晶硅层及刻蚀所述多晶硅层形成多晶硅栅的步骤。
在其中一个实施例中，所述在所述衬底上形成多晶硅层及刻蚀所述多晶硅层形成多晶硅栅的步骤之前，还包括在所述衬底上形成绝缘层的步骤，刻蚀完成后剩余的多晶硅部分位于所述绝缘层上、部分越过所述绝缘层一侧的边缘延伸至所述衬底上；所述在所述阱区中形成源极区和体引出区的步骤，包括使用第一光刻版进行光刻形成第一导电类型离子注入窗口，然后通过所述第一导电类型离子注入窗口向衬底内注入第一导电类型的离子；其中，所述第一光刻版包括相互分离的第一注入区和第二注入区，所述第一注入区和第二注入区是透光区，所述第一光刻版还包括位于第一注入区和第二注入区之间的遮光区，所述第一注入区用于形成源极区，所述第二注入区用于形成漏极区。
在其中一个实施例中，所述使用第一光刻版进行光刻的步骤中，涂覆的光刻胶在所述绝缘层一侧的边缘上方形成台阶，所述遮光区用于在光刻曝光时阻止曝光光线照射到所述台阶。
在其中一个实施例中，所述使用第一光刻版进行光刻的步骤中，采用的光刻胶是正胶。
上述半导体器件，源极区和体引出区沿导电沟道宽度方向交替排列，可以减小器件在导电沟道长度方向的尺寸。并且在源极区和体引出区的一侧设置导电辅助区，导电电流可以通过导电辅助区流到源极区，优化了器件的电流路径，补偿了第二导电类型的体引出区的存在导致的电流损失，能够降低器件的导通电阻(Rdson)。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中半导体器件的平面结构示意图；
图2是图1所示半导体器件的剖面结构示意图；
图3是图1所示半导体器件在另一位置的剖面结构示意图；
图4是一实施例中半导体器件的制造方法的流程图；
图5是半导体器件的多晶硅在绝缘层边缘处形成台阶的示意图；
图6是一实施例中N+光刻版的结构图；
图7是一实施例中半导体器件的版图；
图8是另一实施例中半导体器件的制造方法的流程图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中半导体器件的平面结构示意图，图2和图3分别是图1两个不同位置的剖面结构示意图。请一并参照图1、图2、图3，在该实施例中，半导体器件包括衬底、阱区120、源极区122、体引出区124、导电辅助区126。在图1所示的实施例中，衬底中还形成有高压阱区110，阱区120是形成于高压阱区110中，阱区120具有第二导电类型。源极区122设于阱区120中，具有第一导电类型。体引出区124设于阱区120中，具有第二导电类型。在一个实施例中，半导体器件为N沟道器件，第一导电类型为N型，第二导电类型为P型；在其他实施例中，半导体器件也可以为P沟道器件，第一导电类型为P型，第二导电类型为N型。
参照图1，源极区122和体引出区124在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域，第一区域的两侧为源极区122的边缘和体引出区124的边缘交替排列而成的边界。导电辅助区126具有第一导电类型，设于第一区域的至少一侧(在图1中是设于第一区域的右侧)，与第一区域的右侧边界直接接触，且接触的部位包括边界上至少一个源极区122的边缘和边界上至少一个体引出区124的边缘。
上述半导体器件，源极区122和体引出区124沿导电沟道宽度方向交替排列，可以减小器件在导电沟道长度方向的尺寸。并且通过在源极区122和体引出区124的一侧设置导电辅助区126，导电电流可以通过导电辅助区126流到源极区，优化了器件的电流路径，补偿了第二导电类型的体引出区的存在导致的电流损失，能够降低器件的导通电阻(Rdson)。
在一个实施例中，半导体器件还包括漏极区130和栅极140，第一区域位于栅极140的一侧，漏极区130位于栅极140的另一侧。在一个实施例中，栅极140为多晶硅栅，多晶硅栅下方还设有绝缘层142。在一个实施例中，绝缘层142的材质为硅氧化物，例如二氧化硅。
在一个实施例中，导电辅助区126位于多晶硅栅和绝缘层142的下方。
在一个实施例中，导电辅助区126的掺杂浓度小于源极区122的掺杂浓度。在图1所示实施例中，导电辅助区126为N-区，源极区122为N+区。
在一个实施例中，源极区122为N型重掺杂(NSD)区域，体引出区124为P型重掺杂(PSD)区域。
在图1所示实施例中，高压阱区110为高压N阱(HN)。
为了简化制造工艺，在一个实施例中，导电辅助区126是与阱区120采用同一张光刻版进行，即导电辅助区126和阱区120都是通过该光刻版光刻后形成的注入窗口进行离子注入，之后形成导电辅助区126和阱区120(注入后可以进行热扩散，注入的离子在热扩散后形成导电辅助区126/阱区120)。例如可以使用该光刻版光刻形成注入窗口后，先注入第二导电类型的离子，以形成阱区120，之后再注入第一导电类型的离子，以形成导电辅助区126。如此一来，该注入第一导电类型的离子的步骤必然会在较大的区域内形成第一导电类型的掺杂区(因为其大小是阱区120的注入窗口决定的，而阱区120较大)，为便于描述，以下将该第一导电类型的掺杂区对应的区域记为第二区域。该第二区域会与源极区122和体引出区124部分重合，参见图2和图3，第二区域与源极区122重合的部分为区域126a，与体引出区124重合的部分为区域126b，位于第一区域外一侧的部分为导电辅助区126。区域126a的第一导电类型离子的掺杂浓度会不同于源极区122的其他部分的第一导电类型离子的掺杂浓度，区域126b的第一导电类型离子的掺杂浓度会不同于体引出区124的其他部分的第一导电类型离子的掺杂浓度，但由于第二区域是浓度较低的注入，因此不会对源极区122和体引出区124内部的电性能造成明显的影响。
在一个实施例中，注入第一导电类型的离子以形成导电辅助区126，其注入能量在15keV-50keV之间。在一个实施例中，注入的离子为砷(As)离子。
还有必要提供一种半导体器件的制造方法，可以用于制造以上任一实施例的半导体器件。图4是一实施例中半导体器件的制造方法的流程图，包括以下步骤：
S410，在衬底上光刻形成阱区注入窗口。
使用阱区光刻版光刻形成注入窗口。在一个实施例中，可以先在衬底上形成高压阱区，例如可以是高压N阱，然后再进行步骤S410。
S420，通过阱区注入窗口向衬底内注入第一和第二导电类型的离子。
注入的第二导电类型的离子用于形成阱区，注入的第一导电类型的离子用于形成第二区域。在一个实施例中，半导体器件为N沟道器件，第一导电类型为N型，第二导电类型为P型；在其他实施例中，半导体器件也可以为P沟道器件，第一导电类型为P型，第二导电类型为N型。
S430，热扩散形成阱区和第二区域。
步骤S420注入的第二导电类型的离子热扩散后形成阱区，注入的第一导电类型的离子热扩散后形成第二区域。在一个实施例中，阱区和第二区域均是形成于高压阱区中。
S440，在阱区中形成源极区和体引出区。
源极区和体引出区在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域。第一区域的两侧为源极区的边缘和体引出区的边缘交替排列而成的边界，第一区域和第二区域的一部分重合，第二区域位于第一区域外的一侧的部位作为导电辅助区，导电辅助区与边界直接接触的部位包括边界上至少一个源极区的边缘和边界上至少一个体引出区的边缘。
上述半导体器件的制造方法，导电辅助区的注入采用与阱区相同的注入窗口，即阱区光刻后形成的注入窗口既用于阱区的注入，又用于导电辅助区的注入。导电辅助区的形成不需要增加光刻版，利于控制生成成本。
在一个实施例中，步骤S410之前，还包括在衬底上形成多晶硅层及刻蚀多晶硅层形成多晶硅栅的步骤。S420中第一导电类型的离子注入采用较小的注入能量，该注入不会穿透多晶硅层进入下方的衬底。在一个实施例中，注入能量在15keV-50keV之间。在一个实施例中，注入的离子为砷(As)离子。导电辅助区通过热扩散沿导电沟道长度方向扩散至刻蚀后的多晶硅层下方，例如是多晶硅栅的下方。
在一个实施例中，步骤S440是光刻并通过离子注入形成源极区和体引出区，具体是注入第一导电类型的离子形成源极区，注入第二导电类型的离子形成体引出区。
发明人在实际生产制造中发现，有时候器件的导通特性会出现问题。发明人经实验研究，认为该导通特性的问题是第一区域的源极区和体引出区发生了寄生NPN三极管开启的现在，且发明人认为，导致寄生NPN三极管开启的其中一个原因，是体引出区的实际注入剂量小于设计注入剂量。
参见图5，栅极240下方存在一定厚度的绝缘层252作为场板，由于栅极240的多晶硅会越过绝缘层252一侧的边缘延伸至衬底上，绝缘层252边缘与衬底的高度差就会导致此处形成台阶A。对于步骤S440采用光刻后离子注入形成源极区222和体引出区(图5中未示)的实施例，该光刻步骤涂覆光刻胶后，光刻胶会覆盖栅极240，那么光刻胶同样会在A处形成台阶，该台阶会导致该光刻步骤曝光时，曝光光线在光刻胶台阶处发生折射，折射的曝光光线会导致我们不希望显影的区域也受到影响，从而使得步骤S440的注入窗口变形。具体地，对于光刻胶为正胶的实施例，光刻胶台阶处发生的折射会导致曝光光线照射到体引出区的光刻胶，这样就会导致原本挡在体引出区的光刻胶覆盖的面积减小，从而源极区注入面积变大、体引出区注入面积减小。体引出区注入面积减小相当于体引出区注入总的剂量减小，就会导致前述的寄生的NPN开启，从而影响器件的导通特性。
为了解决这一问题，发明人重新设计了器件的版图，具体是对步骤S440中源极区离子注入使用的光刻版进行重新设计。参见图6，N+光刻版100包括相互分离的第一注入区20和第二注入区10，该光刻版配合正胶使用，第一注入区20和第二注入区10是光刻版的透光区。N+光刻版100还包括位于第一注入区20和第二注入区10之间的遮光区32，第一注入区20用于形成源极区，第二注入区10用于形成漏极区。第一注入区20内部包括多个PSD区22，PSD区22也是光刻版的遮光区。使用N+光刻版100光刻后，PSD区22会使得光刻胶将体引出区挡住，不让第一导电类型离子注入。
图7是相应的半导体器件版图，请一并参见图5、图6、图7，图5、图6、图7均为左右对称(轴对称)的结构，图7中的区域340对应图5中的栅极240，区域330对应漏极区230，区域322对应源极区222，区域320对应阱区220，区域352对应绝缘层252；并且，图7中的区域330对应图6中的第二注入区10，区域322对应第一注入区20，区域324对应PSD区22。图5所示半导体器件为N沟道半导体器件，在衬底中还形成有高压阱区(HN)210，漏极230为N+漏极，且为N型重掺杂区(NSD)，源极222为N+源极，且为N型重掺杂区(NSD)，阱区220为P型掺杂区(PB)，栅极240包括多晶硅栅。
由于N+光刻版100在第一注入区20和第二注入区10之间设置了遮光区32，在光刻曝光时，遮光区32会阻止曝光光线照射到光刻胶的台阶(该台阶位于图5中台阶A的上方)，避免了光线在光刻胶的台阶处发生折射，也就避免了体引出区注入面积的减小，从而能够确保器件的导通特性以及自保护能力。
图8是另一实施例中半导体器件的制造方法的流程图，包括步骤：
S810，在衬底上形成绝缘层。
在一个实施例中，绝缘层的材质为硅氧化物，例如二氧化硅。
S820，在衬底和多绝缘层上形成多晶硅层。
多晶硅层可以用淀积工艺形成。
S830，刻蚀多晶硅层形成多晶硅栅。
除了多晶硅栅，还可以形成多晶硅场板。在图5所示的实施例中，刻蚀完成后剩余的多晶硅部分位于绝缘层252上、部分越过绝缘层252一侧的边缘延伸至衬底上，从而在绝缘层的边缘处形成台阶A。
S840，在衬底上光刻形成阱区注入窗口。
在一个实施例中，步骤S840之前可以先在衬底上形成高压阱区，例如可以是高压N阱。
S850，通过阱区注入窗口向衬底内注入第一和第二导电类型的离子。
注入的第二导电类型的离子用于形成阱区，注入的第一导电类型的离子用于形成第二区域。
S860，热扩散形成阱区和第二区域。
步骤S860注入的第二导电类型的离子热扩散后形成阱区，注入的第一导电类型的离子热扩散后形成第二区域。在一个实施例中，阱区和第二区域均是形成于高压阱区中。
S870，在阱区中形成源极区和体引出区。
在一个实施例中，是光刻形成注入窗口后，通过离子注入分别形成源极区和体引出区。
涂胶后，光刻胶覆盖在栅极240上，所以容易在台阶A处也形成光刻胶台阶。本步骤使用N+光刻版100进行光刻，遮光区32会阻止曝光光线照射到光刻胶的台阶处，避免了光线在光刻胶的台阶处发生折射，也就避免了体引出区注入面积的减小，从而能够确保器件的导通特性以及自保护能力。
源极区和体引出区在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域。第一区域的两侧为源极区的边缘和体引出区的边缘交替排列而成的边界，第一区域和第二区域的一部分重合，第二区域位于第一区域外的一侧的部位作为导电辅助区，导电辅助区与边界直接接触的部位包括边界上至少一个源极区的边缘和边界上至少一个体引出区的边缘。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (2)

1.一种半导体器件的制造方法，包括：
在衬底上光刻形成阱区注入窗口；
通过所述阱区注入窗口向衬底内注入第一导电类型的离子和第二导电类型的离子，所述第一导电类型和第二导电类型为相反的导电类型；
热扩散使注入的所述第二导电类型的离子形成阱区，注入的所述第一导电类型的离子形成第二区域；及
在所述阱区中形成源极区和体引出区；其中，所述源极区和体引出区在导电沟道宽度方向上交替排列从而形成沿导电沟道宽度方向延伸的第一区域，所述第一区域的两侧为源极区的边缘和体引出区的边缘交替排列而成的边界，所述第一区域和所述第二区域的一部分重合，所述第二区域位于所述第一区域外的一侧的部位作为导电辅助区，所述导电辅助区与所述边界直接接触的部位包括所述边界上至少一个源极区的边缘和边界上至少一个体引出区的边缘；
所述在衬底上光刻形成阱区注入窗口的步骤之前，还包括在所述衬底上形成多晶硅层及刻蚀所述多晶硅层形成多晶硅栅的步骤；
所述在所述衬底上形成多晶硅层及刻蚀所述多晶硅层形成多晶硅栅的步骤之前，还包括在所述衬底上形成绝缘层的步骤，刻蚀完成后剩余的多晶硅部分位于所述绝缘层上、部分越过所述绝缘层一侧的边缘延伸至所述衬底上；
所述在所述阱区中形成源极区和体引出区的步骤，包括使用第一光刻版进行光刻形成第一导电类型离子注入窗口，然后通过所述第一导电类型离子注入窗口向衬底内注入第一导电类型的离子；其中，所述第一光刻版包括相互分离的第一注入区和第二注入区，所述第一注入区和第二注入区是透光区，所述第一光刻版还包括位于第一注入区和第二注入区之间的第一遮光区，所述第一注入区用于形成源极区，所述第二注入区用于形成漏极区，所述第一注入区内部设有多个第二遮光区；所述使用第一光刻版进行光刻的步骤中，采用的光刻胶是正胶，涂覆的光刻胶在所述绝缘层一侧的边缘上方形成台阶，所述第一遮光区用于在光刻曝光时阻止曝光光线照射到所述台阶；各所述第二遮光区用于在所述第一光刻版光刻后使得光刻胶将所述体引出区挡住，不让第一导电类型离子注入。
2.根据权利要求1所述的半导体器件的制造方法，其特征在于，所述通过所述阱区注入窗口向衬底内注入第一导电类型的离子的步骤中，注入能量在15keV-50keV之间。
CN201810914285.8A 2018-08-10 2018-08-10 半导体器件及其制造方法 Active CN110828540B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201810914285.8A CN110828540B (zh) 2018-08-10 2018-08-10 半导体器件及其制造方法
PCT/CN2019/099995 WO2020030114A1 (zh) 2018-08-10 2019-08-09 半导体器件及其制造方法
US17/265,565 US11552164B2 (en) 2018-08-10 2019-08-09 Semiconductor device and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810914285.8A CN110828540B (zh) 2018-08-10 2018-08-10 半导体器件及其制造方法

Publications (2)

Publication Number Publication Date
CN110828540A CN110828540A (zh) 2020-02-21
CN110828540B true CN110828540B (zh) 2022-03-11

Family

ID=69413244

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810914285.8A Active CN110828540B (zh) 2018-08-10 2018-08-10 半导体器件及其制造方法

Country Status (3)

Country Link
US (1) US11552164B2 (zh)
CN (1) CN110828540B (zh)
WO (1) WO2020030114A1 (zh)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012156205A (ja) * 2011-01-24 2012-08-16 Asahi Kasei Electronics Co Ltd 半導体装置、半導体装置の製造方法
CN103022131A (zh) * 2011-09-21 2013-04-03 拉碧斯半导体株式会社 半导体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6867083B2 (en) * 2003-05-01 2005-03-15 Semiconductor Components Industries, Llc Method of forming a body contact of a transistor and structure therefor
CN101359687B (zh) * 2007-07-30 2010-06-09 联华电子股份有限公司 金属氧化物半导体元件
US9449968B2 (en) * 2013-12-27 2016-09-20 Infineon Technologies Austria Ag Method for manufacturing a semiconductor device and a semiconductor device
CN103779415B (zh) * 2014-01-20 2016-03-02 张家港凯思半导体有限公司 平面型功率mos器件及其制造方法
DE102015106683B4 (de) * 2015-04-29 2021-11-25 Infineon Technologies Ag Halbleitervorrichtung mit einem feldeffekttransistor und verfahren zum herstellen der halbleitervorrichtung
CN206133181U (zh) * 2016-11-01 2017-04-26 合肥鑫晟光电科技有限公司 一种掩膜板
US9831338B1 (en) * 2017-02-10 2017-11-28 Nxp Usa, Inc. Alternating source region arrangement
CN106981518A (zh) * 2017-03-30 2017-07-25 电子科技大学 一种具有超结结构的soi横向高压器件

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012156205A (ja) * 2011-01-24 2012-08-16 Asahi Kasei Electronics Co Ltd 半導体装置、半導体装置の製造方法
CN103022131A (zh) * 2011-09-21 2013-04-03 拉碧斯半导体株式会社 半导体装置

Also Published As

Publication number Publication date
US20210242305A1 (en) 2021-08-05
WO2020030114A1 (zh) 2020-02-13
CN110828540A (zh) 2020-02-21
US11552164B2 (en) 2023-01-10

Similar Documents

Publication Publication Date Title
US10032903B2 (en) Threshold voltage adjustment of a transistor
US5510279A (en) Method of fabricating an asymmetric lightly doped drain transistor device
US7745294B2 (en) Methods of manufacturing trench isolated drain extended MOS (demos) transistors and integrated circuits therefrom
TWI415223B (zh) Semiconductor device and manufacturing method thereof
US20070228463A1 (en) Self-aligned complementary ldmos
CN108695389B (zh) 具有低导通电阻的半导体器件结构及其制造方法
US20100213517A1 (en) High voltage semiconductor device
WO1981000931A1 (en) Cmos p-well selective implant method,and a device made therefrom
US6297082B1 (en) Method of fabricating a MOS transistor with local channel ion implantation regions
US10950489B2 (en) Devices and methods for radiation hardening integrated circuits using shallow trench isolation
US8604522B2 (en) Field effect type semiconductor device and method for manufacturing the same
US20190088780A1 (en) Demos transistor and method of manufacturing the same
US8093663B2 (en) Semiconductor device, method of fabricating the same, and patterning mask utilized by the method
US6525380B2 (en) CMOS with a fixed charge in the gate dielectric
KR100847827B1 (ko) 고전압 트랜지스터의 제조 방법
CN110828540B (zh) 半导体器件及其制造方法
EP1142014B1 (en) A method of manufacturing a peripheral transistor of a non-volatile memory
CN112466950B (zh) 一种抗边缘漏电soi mos结构及其形成方法
CN107919280B (zh) 不同电压器件的集成制造方法
USRE44430E1 (en) PMOS depletable drain extension made from NMOS dual depletable drain extensions
WO2009041741A1 (ja) Ｄｍｏｓトランジスタ及びその製造方法
TWI781289B (zh) 製造高電壓半導體裝置的方法
CN112466953B (zh) 一种h型体接触soi mosfet器件及其制作方法
CN116266608A (zh) 功率半导体器件和制造功率半导体器件的方法
JPH06232153A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant