WO2020026770A1 - Cleaning bath - Google Patents

Cleaning bath Download PDF

Info

Publication number
WO2020026770A1
WO2020026770A1 PCT/JP2019/027758 JP2019027758W WO2020026770A1 WO 2020026770 A1 WO2020026770 A1 WO 2020026770A1 JP 2019027758 W JP2019027758 W JP 2019027758W WO 2020026770 A1 WO2020026770 A1 WO 2020026770A1
Authority
WO
WIPO (PCT)
Prior art keywords
side wall
wall portion
cylindrical side
cassette
semiconductor layer
Prior art date
Application number
PCT/JP2019/027758
Other languages
French (fr)
Japanese (ja)
Inventor
真悟 渡邉
崇 口山
Original Assignee
株式会社カネカ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社カネカ filed Critical 株式会社カネカ
Priority to JP2020533392A priority Critical patent/JP7053838B2/en
Priority to CN201980050101.0A priority patent/CN112514033B/en
Publication of WO2020026770A1 publication Critical patent/WO2020026770A1/en

Links

Images

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B08CLEANING
    • B08BCLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B3/00Cleaning by methods involving the use or presence of liquid or steam
    • B08B3/04Cleaning involving contact with liquid
    • B08B3/10Cleaning involving contact with liquid with additional treatment of the liquid or of the object being cleaned, e.g. by heat, by electricity or by vibration
    • B08B3/12Cleaning involving contact with liquid with additional treatment of the liquid or of the object being cleaned, e.g. by heat, by electricity or by vibration by sonic or ultrasonic vibrations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting

Definitions

  • the technology disclosed in this specification relates to a cleaning bath for ultrasonically treating a semiconductor substrate.
  • Patent Literature 1 a substrate (in Patent Literature 1, a transparent substrate of a liquid crystal display element) is held in a cassette, and the substrate held in the cassette is immersed together with the cassette in a processing solution in a cleaning bath. The substrate is subjected to ultrasonic treatment.
  • the patterning step includes a thin film peeling step.
  • the yield of the step is dramatically improved.
  • the cassette immersed in the processing solution in the cleaning bath is usually only placed on the bottom wall of the cleaning bath. For this reason, the cassette may move by being vibrated by the ultrasonic waves in the cleaning bath, and the ultrasonic processing may not be performed properly.
  • a standing wave may be generated in the processing liquid in the cleaning bath depending on the shape of the cleaning bath and the cassette.
  • unevenness in the sound pressure due to the standing wave causes uneven cleaning, and particularly, a semiconductor substrate having a small thickness (for example, a semiconductor substrate for a solar cell) has an antinode portion (a high sound pressure) of the standing wave. Part) and is easily damaged.
  • the technology disclosed herein has been made in view of such a point, and an object thereof is to provide a cleaning bath that can favorably perform ultrasonic treatment of a semiconductor substrate regardless of the shape of a cassette. is there.
  • the cleaning bath is a cleaning bath for ultrasonically treating the semiconductor substrate in a state where the semiconductor substrate held in the cassette is immersed in the processing liquid to be stored together with the cassette.
  • a cylindrical side wall that rises from the wall and stores the processing liquid therein, and the cassette immersed in the processing liquid moves in the in-plane direction of the bottom wall and in the direction crossing the in-plane direction.
  • a stopping portion for stopping wherein in the cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion, a part of the inner side surface of the cylindrical side wall portion in the circumferential direction is curved and the remaining portion is straight. It is.
  • the ultrasonic treatment of the semiconductor substrate is favorably performed regardless of the shape and the installation position of the cassette, and the semiconductor substrate having a small thickness (for example, a semiconductor substrate for a solar cell) is ultrasonically treated. Also, the semiconductor substrate is not damaged.
  • FIG. 3 is a plan view showing a cleaning tub according to an exemplary embodiment together with a cassette. It is sectional drawing which cut
  • FIG. 3 is a cross-sectional view taken along the line III-III of FIG. 1.
  • FIG. 3 is a perspective view showing a cassette holding semiconductor substrates.
  • FIG. 2 is a schematic sectional view partially showing a solar cell.
  • FIG. 4 is a bottom view showing the back principal surface of the crystal substrate constituting the solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 3 is a view corresponding to FIG. 2, showing another shape of the inner side surface of the cylindrical side wall portion.
  • FIG. 7 is a view corresponding to FIG.
  • FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion.
  • FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion.
  • FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion.
  • FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion.
  • FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion.
  • FIGS. 1-3 show a cleaning tub 21 according to an exemplary embodiment.
  • the cleaning bath 21 is provided with at least one (in the present embodiment, a plurality of) semiconductor substrates 57 (see FIG. 4) held in the cassette 51 immersed in the processing liquid to be stored together with the cassette 51, at least. This is for subjecting one (plural) semiconductor substrates 57 to ultrasonic treatment.
  • the semiconductor substrate 57 is a semiconductor substrate for the solar cell 10.
  • FIG. 3 the illustration of the semiconductor substrate 57 is omitted.
  • the solar cell 10 uses a crystal substrate 11 made of silicon (Si).
  • Crystal substrate 11 has two main surfaces 11S (11SU, 11SB) facing each other.
  • the main surface on which light is incident is referred to as a front main surface 11SU
  • the main surface on the opposite side is referred to as a back main surface 11SB.
  • the front-side main surface 11SU is a light-receiving side that is a side that more actively receives light than the back-side main surface 11SB
  • the back-side main surface 11SB is a side that does not actively receive light and is a non-light-receiving side.
  • the solar cell 10 is a so-called heterojunction crystalline silicon solar cell, and is a back-contact type (backside electrode type) solar cell in which an electrode layer is disposed on the back main surface 11SB.
  • the solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12 (12U, 12p, 12n), a conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 ( Transparent electrode layer 17 and metal electrode layer 18).
  • members individually corresponding to the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be given “p” or “n” at the end of the reference numerals.
  • Crystal substrate 11 may be a semiconductor substrate formed of single-crystal silicon or a semiconductor substrate (single-crystal silicon substrate) formed of polycrystalline silicon.
  • a single crystal silicon substrate will be described as an example.
  • the conductivity type of the crystal substrate 11 may be an n-type single crystal silicon substrate into which impurities (for example, phosphorus (P) atoms) for introducing electrons into silicon atoms have been introduced, and holes may be used for silicon atoms.
  • impurities for example, phosphorus (P) atoms
  • holes may be used for silicon atoms.
  • an impurity for example, a boron (B) atom
  • the crystal substrate 11 has a texture structure TX (concave) formed of peaks (convex) and valleys (concave) on the surfaces of the two main surfaces 11S. (A first texture structure).
  • the texture structure TX is formed, for example, by anisotropic etching using the difference between the etching rate of the (100) plane and the etching rate of the (111) plane of the crystal substrate 11. Can be formed.
  • the size of the irregularities in the texture structure TX can be defined, for example, by the number of vertices (mountains).
  • the range is preferably 50,000 / mm 2 or more and 100,000 / mm 2 or less, and in particular, 70,000 / mm 2 or more and 85,000 / mm 2 or less. Is preferably within the range.
  • the thickness of the crystal substrate 11 may be 250 ⁇ m or less.
  • the measurement direction when measuring the thickness of the crystal substrate 11 is a direction perpendicular to the average plane of the crystal substrate 11 (the average plane means a plane of the entire substrate that does not depend on the texture structure TX). Therefore, hereinafter, this vertical direction, that is, the direction in which the thickness is measured is referred to as the thickness direction (also the thickness direction of the semiconductor substrate 57).
  • the thickness of the crystal substrate 11 is preferably at least 50 ⁇ m, more preferably at least 70 ⁇ m.
  • the thickness of the crystal substrate 11 is determined by the unevenness of the front main surface 11SU and the rear main surface 11SB. It is represented by the distance between straight lines connecting the convex vertices (vertices facing each other in the thickness direction) in the structure.
  • the intrinsic semiconductor layer 12 (12U, 12p, 12n) covers both main surfaces 11S (11SU, 11SB) of the crystal substrate 11, thereby performing surface passivation while suppressing diffusion of impurities into the crystal substrate 11.
  • intrinsic (i-type) is not limited to complete intrinsic without conductive impurities, but includes “weak” containing a small amount of n-type impurities or p-type impurities as long as the silicon-based layer can function as an intrinsic layer. Also encompasses "n-type” or "weak p-type” substantially intrinsic layers.
  • the intrinsic semiconductor layer 12 (12U, 12p, 12n) is not essential, and may be appropriately formed as needed.
  • the material of the intrinsic semiconductor layer 12 is not particularly limited, but may be an amorphous silicon-based material, and may be a hydrogenated amorphous silicon-based thin film containing silicon and hydrogen (a-Si: H thin film). There may be.
  • amorphous used herein refers to a long-period, non-ordered structure, that is, a structure that is not only completely disordered but also has a short-period order.
  • the thickness of the intrinsic semiconductor layer 12 is not particularly limited, but may be 2 nm or more and 20 nm or less. When the thickness is 2 nm or more, the effect as a passivation layer for the crystal substrate 11 is enhanced, and when the thickness is 20 nm or less, a decrease in conversion characteristics caused by an increase in resistance can be suppressed.
  • the method of forming the intrinsic semiconductor layer 12 is not particularly limited, but a plasma enhanced chemical vapor deposition (CVD) method is used. According to this method, passivation of the substrate surface can be effectively performed while suppressing diffusion of impurities into single crystal silicon. In addition, in the case of the plasma CVD method, by changing the hydrogen concentration in the layer of the intrinsic semiconductor layer 12 in the thickness direction, it is possible to form an energy gap profile that is effective for carrier recovery.
  • CVD plasma enhanced chemical vapor deposition
  • the conditions for forming a thin film by the plasma CVD method include, for example, a substrate temperature of 100 ° C. to 300 ° C., a pressure of 20 Pa to 2600 Pa, and a high-frequency power density of 0.003 W / cm 2 to 0.5 W / cm 2 or less.
  • a silicon-containing gas such as monosilane (SiH 4 ) and disilane (Si 2 H 6 ), or a mixture of these gases with hydrogen (H 2 ) May be mixed gas.
  • a gas containing a different kind of element such as methane (CH 4 ), ammonia (NH 3 ), or monogermane (GeH 4 ) is added to the above gas, and silicon carbide (SiC), silicon nitride (SiN)
  • SiC silicon carbide
  • SiN silicon nitride
  • the energy gap of the thin film may be appropriately changed.
  • Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13n. As shown in FIG. 5, the p-type semiconductor layer 13p is formed on a part of the back-side main surface 11SB of the crystal substrate 11 via the intrinsic semiconductor layer 12p. The n-type semiconductor layer 13n is formed on another part of the back-side main surface of the crystal substrate 11 via the intrinsic semiconductor layer 12n. That is, the intrinsic semiconductor layer 12 is interposed between the p-type semiconductor layer 13p and the crystal substrate 11 and between the n-type semiconductor layer 13n and the crystal substrate 11 as an intermediate layer that plays a role of passivation.
  • Each thickness of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n is not particularly limited, but may be 2 nm or more and 20 nm or less.
  • the thickness is 2 nm or more, the effect as a passivation layer for the crystal substrate 11 is enhanced, and when the thickness is 20 nm or less, a decrease in conversion characteristics caused by an increase in resistance can be suppressed.
  • the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are arranged such that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are electrically separated from each other on the back main surface 11SB of the crystal substrate 11.
  • the width of the conductive type semiconductor layer 13 may be 50 ⁇ m or more and 3000 ⁇ m or less, and may be 80 ⁇ m or more and 800 ⁇ m or less (note that the width of the semiconductor layer and the width of an electrode layer described later are the same unless otherwise specified.
  • the length of a portion of each of the layered layers is intended to be, for example, the length in a direction perpendicular to the extending direction of the linear portion by patterning).
  • the width of the p-type semiconductor layer 13p may be smaller than that of the n-type semiconductor layer 13n.
  • the width of the p-type semiconductor layer 13p may be 0.5 to 0.9 times the width of the n-type semiconductor layer 13n, or 0.6 to 0.8 times. Is also good.
  • the p-type semiconductor layer 13p is a silicon layer to which a p-type dopant (boron or the like) is added, and may be formed of amorphous silicon from the viewpoint of suppressing impurity diffusion or suppressing series resistance.
  • the n-type semiconductor layer 13n is a silicon layer to which an n-type dopant (such as phosphorus) is added, and may be formed of an amorphous silicon layer, similarly to the p-type semiconductor layer 13p.
  • a silicon-containing gas such as monosilane (SiH 4 ) or disilane (Si 2 H 6 ), or a mixed gas of a silicon-based gas and hydrogen (H 2 ) may be used.
  • a dopant gas diborane (B 2 H 6 ) or the like can be used for forming the p-type semiconductor layer 13p, and phosphine (PH 3 ) or the like can be used for forming the n-type semiconductor layer.
  • a mixed gas obtained by diluting a dopant gas with a source gas may be used.
  • the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be compounded.
  • the low reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10.
  • the material of the low reflective layer 14 is not particularly limited as long as it is a light-transmitting material that transmits light.
  • silicon oxide (SiO x ), silicon nitride (SiN x ), zinc oxide (ZnO), or oxide Titanium (TiO x ) is exemplified.
  • the low reflective layer 14 may be coated with a resin material in which nanoparticles of an oxide such as zinc oxide or titanium oxide are dispersed.
  • the electrode layer 15 is formed so as to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, respectively, and is electrically connected to each conductive semiconductor layer 13. Thereby, the electrode layer 15 functions as a transport layer for guiding carriers generated in the p-type semiconductor layer 13p or the n-type semiconductor layer 13n.
  • the electrode layer 15 may be formed only of a highly conductive metal. Further, from the viewpoint of electrical connection with the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or from the viewpoint of suppressing the diffusion of atoms of the metal as the electrode material into the two semiconductor layers 13p and 13n, the transparent material is used.
  • the electrode layer 15 made of a conductive oxide may be provided between the metal electrode layer and the p-type semiconductor layer 13p and between the metal electrode layer and the n-type semiconductor layer 13n.
  • the electrode layer 15 formed of a transparent conductive oxide is referred to as a transparent electrode layer 17, and the metal electrode layer 15 is referred to as a metal electrode layer 18.
  • an electrode layer formed on the back of the comb in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n each having a comb shape. May be referred to as a bus bar portion, and an electrode layer formed on the comb teeth portion may be referred to as a finger portion.
  • the material of the transparent electrode layer 17 is not particularly limited.
  • the thickness of the transparent electrode layer 17 may be 20 nm or more and 200 nm or less.
  • a method for forming a transparent electrode layer suitable for this thickness for example, a physical vapor deposition (PVD) method such as a sputtering method, or a metal organic compound utilizing a reaction between an organometallic compound and oxygen or water is used.
  • PVD physical vapor deposition
  • MOCVD Metal-Organic Chemical Vapor Deposition
  • the material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver (Ag), copper (Cu), aluminum (Al), and nickel (Ni).
  • the thickness of the metal electrode layer 18 may be 1 ⁇ m or more and 80 ⁇ m or less.
  • a method for forming the metal electrode layer 18 having a suitable thickness a printing method in which a material paste is printed by inkjet printing or screen printing, or a plating method is used.
  • the present invention is not limited to this, and when a vacuum process is employed, a vapor deposition or sputtering method may be employed.
  • the width of the comb-tooth portion of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be substantially equal to the width of the metal electrode layer 18 formed on the comb-tooth portion.
  • the width of the metal electrode layer 18 may be smaller than the width of the comb teeth.
  • the width of the metal electrode layer 18 may be wider than the width of the comb portion as long as the configuration prevents leakage current between the metal electrode layers 18.
  • the passivation and conduction of each junction surface are performed in a state where the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low reflection layer 14, and the electrode layer 15 are stacked on the back main surface 11SB of the crystal substrate 11.
  • a predetermined annealing process is performed for the purpose of suppressing generation of defect levels at the type semiconductor layer 13 and the interface thereof, and crystallization of the transparent conductive oxide in the transparent electrode layer 17.
  • the annealing process according to the present embodiment includes, for example, an annealing process in which the crystal substrate 11 on which the above-described layers are formed is placed in an oven heated to 150 ° C. or more and 200 ° C. or less.
  • the atmosphere in the oven may be air, and if hydrogen or nitrogen is used as the atmosphere, more effective annealing can be performed.
  • the annealing may be an RTA (Rapid Thermal Annealing) process in which the crystal substrate 11 on which each layer is formed is irradiated with infrared rays by an infrared heater.
  • a crystal substrate 11 having a texture structure TX on each of a front main surface 11SU and a back main surface 11SB is prepared.
  • an intrinsic semiconductor layer 12U is formed on the front main surface 11SU of the crystal substrate 11.
  • the antireflection layer 14 is formed on the formed intrinsic semiconductor layer 12U.
  • silicon nitride (SiN x ) or silicon oxide (SiO x ) having a suitable light absorption coefficient and refractive index is used from the viewpoint of a light confinement effect of confining incident light.
  • an intrinsic semiconductor layer 12p using, for example, i-type amorphous silicon is formed on the back-side main surface 11SB of the crystal substrate 11.
  • a p-type semiconductor layer 13p is formed on the formed intrinsic semiconductor layer 12p.
  • p-type semiconductor layer 13p with intrinsic semiconductor layer 12p interposed is formed on back main surface 11SB, which is one main surface of crystal substrate 11.
  • a plurality of lift-off layers LF (first lift-off layer LF1 and second lift-off layer LF2) are formed on the formed p-type semiconductor layer 13p.
  • a first lift-off layer LF1 and a second lift-off layer LF2 containing silicon-based thin film materials having different densities are sequentially laminated and formed.
  • the first lift-off layer LF1 is formed on the p-type semiconductor layer 13p
  • the second lift-off layer LF2 is formed on the first lift-off layer LF1.
  • the second lift-off layer LF2, the first lift-off layer LF1, and the p-type semiconductor layer 13p are patterned. Thereby, the p-type semiconductor layer 13p is selectively removed, and a non-formed region NA where the p-type semiconductor layer 13p is not formed is generated.
  • the second lift-off layer LF2, the first lift-off layer LF1, and the p-type semiconductor layer 13p remain in a region that is not etched on the back main surface 11SB of the crystal substrate 11.
  • Such a patterning step is realized by a photolithography method, for example, by forming a resist film (not shown) having a predetermined pattern on the second lift-off layer LF2 and etching a region masked by the formed resist film. I do.
  • a photolithography method for example, by forming a resist film (not shown) having a predetermined pattern on the second lift-off layer LF2 and etching a region masked by the formed resist film. I do.
  • a resist film not shown
  • etching solution used in the step shown in FIG. 10 for example, a mixed solution of hydrofluoric acid and an oxidizing solution (for example, hydrofluoric nitric acid) or a solution in which ozone is dissolved in hydrofluoric acid (hereinafter, ozone / hydrofluoric acid) Acid solution).
  • the etching agent that contributes to the etching of the lift-off layer LF is hydrogen fluoride.
  • the patterning here is not limited to wet etching using an etching solution.
  • the patterning may be, for example, dry etching or pattern printing using an etching paste or the like.
  • the intrinsic semiconductor layer including the second lift-off layer LF2, the first lift-off layer LF1, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p is formed on the back-side main surface 11SB of the crystal substrate 11.
  • 12n and the n-type semiconductor layer 13n are sequentially formed.
  • the stacked film of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n is formed on the non-formation region NA, on the surface and side surface (end surface) of the second lift-off layer LF2, and on the first lift-off layer LF1 and the p-type semiconductor. It is formed on the side surface (end surface) of the layer 13p and the intrinsic semiconductor layer 12p.
  • the etching solution used in the lift-off step includes, for example, a solution containing hydrofluoric acid as a main component.
  • the etching solution attached to the crystal substrate 11 is removed by using a rinsing liquid (this step is called a rinsing step).
  • a rinsing liquid for example, a liquid obtained by adding a liquid property adjusting agent for adjusting the surface tension as described later is used based on pure water.
  • the surface tension of the etching solution and the rinsing solution used in the lift-off step and the rinsing step is preferably from 25 mN / m to 70 mN / m, and more preferably from 30 mN / m to 60 mN / m.
  • the lift-off step proceeds smoothly due to the high wettability to the p-type semiconductor layer 13p and the lift-off layer LF, and further, the n-type semiconductor layer 13n and the intrinsic The semiconductor layer 12n is easily aggregated in the etching solution and the rinsing liquid.
  • the particles are agglomerated and the particles become large, so that the re-adhesion of the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n to the crystal substrate 11 is suppressed. Further, when the etching solution or the rinsing liquid is circulated, the removal of the particles is facilitated by filtering. As described above, fine separation and suspended matter do not convect in the liquid for a long time, so that both productivity and yield are improved.
  • separation grooves are formed on the back main surface 11SB of the crystal substrate 11, that is, on each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by, for example, a sputtering method using a mask.
  • the transparent electrode layer 17 (17p, 17n) is formed so as to give 25.
  • the transparent electrode layer 17 (17p, 17n) may be formed as follows instead of the sputtering method. For example, a transparent conductive oxide film is formed on the entire back surface 11SB without using a mask, and then the transparent conductive oxide film is formed on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by photolithography.
  • It may be formed by performing etching to leave a conductive oxide film.
  • a leak current is less likely to occur.
  • a linear metal electrode layer 18 (18p, 18n) is formed on the transparent electrode layer 17 using, for example, a mesh screen (not shown) having openings.
  • the back junction solar cell 10 is formed.
  • ultrasonic treatment is performed using the cleaning bath 21 in which the processing liquid is stored, whereby the n-type semiconductor layer 13 n and the intrinsic semiconductor layer 12 n are removed. Peeling becomes more reliable.
  • the processing liquid in the cleaning bath 21 is an etching solution used in the lift-off step in the lift-off step, and a rinsing liquid in the rinsing step.
  • the semiconductor substrate 57 held in the cassette 51 is the semiconductor substrate in the state shown in FIG. 11 or FIG.
  • the semiconductor substrate 57 has a substantially rectangular shape when viewed from the thickness direction.
  • the cassette 51 is formed of a resin-made tubular body 52, and the cleaning tub is placed such that the tubular axis direction of the tubular body 52 is the vertical direction. 21 is immersed in the processing solution.
  • the tubular body 52 is not limited to a resin, and may be, for example, a metal.
  • the cassette 51 (the tubular body 52) will be described as being in the posture (the posture immersed in the processing liquid) disposed in the cleaning bath 21.
  • the shape of the cross section of the cylindrical body 52 orthogonal to the cylindrical axis direction is substantially rectangular.
  • the direction in which the long side of the rectangle of the cross section extends is called the longitudinal direction
  • the direction in which the short side of the rectangle extends is the short direction.
  • the cross-sectional shape of the tubular body 52 is not limited to a substantially rectangular shape, and may be any shape.
  • the size of the cassette 51 may be such that the cassette 51 is disposed inside the cleaning bath 21 such that the cylindrical axis of the cylindrical body 52 is in the vertical direction, and is immersed in the processing liquid in the cleaning bath 21. Any size is possible if possible.
  • the cylindrical body 52 has an outer peripheral surface 52a exposed outside the cylindrical body 52 and an inner peripheral surface 52b forming a space inside the cylindrical body 52.
  • the inner peripheral surface 52b of the tubular body 52 extends straight in the tubular axis direction (vertical direction) of the tubular body 52 over the entirety of the tubular body 52 in the tubular axis direction.
  • the outer peripheral surface 52a of the cylindrical body 52 has a cylindrical axially extending portion 52c extending in the cylindrical axis direction of the cylindrical body 52 and the cylindrical body 52 so that the thickness of the cylindrical body 52 increases toward the upper side. And an inclined portion 52d inclined with respect to the cylinder axis direction.
  • the tubular axially extending portion 52c is provided only at the lower end of the outer peripheral surface 52a of the tubular body 52, and the inclined portion 52d is provided at a portion above the tubular axially extending portion 52c.
  • the inclined portion 52d By the inclined portion 52d, a large thickness of the upper end surface of the tubular body 52 is ensured, and the pushing of the tubular body 52 by the second blocking piece 42 described later is favorably performed.
  • the entirety of the outer peripheral surface 52a of the cylindrical body 52 in the cylinder axis direction may extend straight in the cylindrical axis direction (vertical direction) of the cylindrical body 52, similarly to the inner peripheral surface 52b.
  • a plurality of holding projections 52e for holding the semiconductor substrate 57 are provided on two portions of the inner peripheral surface 52b of the cylindrical body 52 facing each other in the short direction so as to be arranged in the longitudinal direction.
  • the distance between the holding projections 52e adjacent to each other in the longitudinal direction in each portion is substantially the same as the thickness of the semiconductor substrate 57 (in FIG. 4, exaggerated for simplicity), In the meantime, the semiconductor substrate 57 is held in an upright posture extending vertically.
  • a substrate supporting portion 52f (see FIG. 3) that supports the semiconductor substrate 57 by contacting the lower surface of the semiconductor substrate 57 is provided at a lower end portion between the adjacent holding projections 52e on each surface.
  • the configuration for holding the semiconductor substrate 57 is an example, and another configuration may be employed.
  • the posture of the semiconductor substrate 57 held by the cassette 51 may be any posture, for example, may be a posture inclined with respect to the vertical direction. Further, the surface of the semiconductor substrate 57 may be oriented in any direction.
  • the washing tub 21 includes a bottom wall portion 22 extending in the horizontal direction, and a cylindrical side wall portion 23 that rises upward from a peripheral portion of the bottom wall portion 22 and stores therein a processing liquid. It is formed in a bottomed cylindrical shape. That is, the cylindrical side wall 23 is formed so as to rise in a direction crossing the in-plane direction of the bottom wall 22.
  • the cylinder axis direction of the cylindrical side wall 23 coincides with the vertical direction (that is, in the present embodiment, the direction of intersection with the in-plane direction of the bottom wall 22 is the vertical direction).
  • the washing tub 21 is also made of resin like the tubular body 52.
  • the washing tub 21 is not limited to resin, but may be metal, for example.
  • the inner side surface of the cylindrical side wall portion 23 has two straight lines 23a parallel to each other and two straight lines 23a.
  • a shape including an arc-shaped curve 23b whose center of curvature is located inside the cylindrical side wall portion 23 and connects the one side end portions and the other side end portions hereinafter, referred to as a stadium shape.
  • the outer side surface of the cylindrical side wall portion 23 has the same shape as the inner side surface. Note that an arc-shaped curve may be used instead of the arc-shaped curve 23b.
  • the cleaning bath 21 is arranged in the vertical direction (intersecting direction with respect to the in-plane direction of the bottom wall portion 22) of the cassette 51 immersed in the processing liquid, and in the horizontal direction (the in-plane direction of the bottom wall portion 22) intersecting with the vertical direction. )
  • the restricting unit 30 includes a first restricting unit 31 that restricts the lateral movement of the cassette 51 and a second restricting unit 41 that restricts the vertical movement of the cassette 51. Note that, in the case where the movement of the cassette 51 in the vertical direction can also be stopped by the first stopping portion 31, the stopping portion 30 may have only the first stopping portion 31. Similarly, when the movement of the cassette 51 in the horizontal direction can be suppressed by the second restraining portion 41, the restraining portion 30 may include only the second restraining portion 41.
  • the plurality of first stoppers 31 are provided so as to be arranged in a circumferential direction around the outer periphery of the cassette 51 (tubular body 52) immersed in the processing liquid.
  • four) first stopping pieces 32 are included.
  • the four first stopping pieces 32 are provided on the bottom wall 22 of the washing tub 21, and are located at corners of a virtual rectangle 35 corresponding to the outer shape line of the lower end surface of the tubular body 52.
  • Each first stopping piece 32 has a mating surface 32a that matches each corner (the outer surface of the cassette 51) of the cylindrical axially extending portion 52c, and a receiving surface that receives the vicinity of the corner at the lower end surface of the cylindrical body 52. 32b.
  • the height position of the upper end surface of the cylindrical body 52 is lower than the height position of the processing liquid level.
  • the receiving surface 32b has a role of forming a gap between the lower end surface of the cylindrical body 52 and the bottom wall 22 of the cleaning bath 21 to promote the inflow and outflow of the processing liquid to the inside of the cylindrical body 52.
  • a slight gap is actually generated therebetween, and the inner wall of the cylindrical body 52 is Inflow and outflow of the processing liquid are performed.
  • the four first stopping pieces 32 are moved by a moving mechanism 36 (see FIG. 3) such as a motor that moves the first stopping pieces 32 so as to be detachable from and attached to the cassette 51 immersed in the processing liquid.
  • a moving mechanism 36 such as a motor that moves the first stopping pieces 32 so as to be detachable from and attached to the cassette 51 immersed in the processing liquid.
  • the moving mechanism 36 is provided on the lower surface of the bottom wall portion 22 and, for example, connects the two first stopping pieces 32 of each set located on each diagonal line of the virtual square 35 to each other. It is moved along the diagonal on the bottom wall portion 22 so as to be separated.
  • the detailed configuration of the moving mechanism 36 is omitted.
  • the four first stopping pieces 32 are brought close to the cassette 51 by the moving mechanism 36, and the matching surfaces 32a abut against the four corners of the cylindrical axially extending portion 52c to press the cylindrical body 52 inward. I do. As a result, the movement of the cassette 51 in the lateral direction is suppressed. Depending on the pressing force of the four first blocking pieces 32 against the cylindrical body 52, the movement of the cassette 51 in the vertical direction can be restrained by the four first blocking pieces 32.
  • the four first stopping pieces 32 are separated from the cassette 51 by the moving mechanism 36. At this time, each first stopping piece 32 moves by such an amount that the receiving surface 32b does not come off the lower end surface of the tubular body 52. Thereby, the cassette 51 can be easily taken in and out of the cleaning bath 21.
  • the first stopper 32 does not necessarily need to be configured to be movable, but may be fixed to the bottom wall 22.
  • the first stopping piece 32 is positioned such that the lower surface of the cylindrical body 52 is in contact with the receiving surface 32b and the mating surface 32a substantially abuts the corner of the cylindrical axially extending portion 52c. Is provided. Further, only a part of the plurality of first restraining pieces 32 may be configured to be movable.
  • the first blocking piece 32 may be provided on the cylindrical side wall 23 via a support member.
  • the first blocking piece 32 may be configured to be able to be separated from and connected to the cassette 51 immersed in the processing liquid via the support member.
  • the number of the first stoppers 32, the number of the first stoppers 32 configured to be detachable from the cassette 51, and the moving direction when the first stoppers 32 are configured to be movable It differs depending on the cross-sectional shape of the cylindrical body 52, and is appropriately set so that the lateral movement of the cassette 51 can be restrained.
  • the position of the cassette 51 with respect to the washing tub 21 as viewed from above (the position of the first blocking piece 32) is usually the center of the washing tub 21, but may be anywhere in the washing tub 21.
  • the washing tub 21 further includes a top surface portion 24 rotatably mounted on the cylindrical side wall portion 23 via a rotation mechanism 25.
  • the top surface portion 24 is divided into two divided portions 24a in a direction orthogonal to the two stadium-shaped straight lines 23a.
  • a hinge shaft 24b is provided at an end of the divided portion 24a on the side of the straight line 23a so as to penetrate in the direction in which the straight line 23a extends.
  • the hinge shaft 24b is fixed to the dividing portion 24a, and is rotatably supported by a hinge shaft support portion 23c provided at a portion corresponding to the straight line 23a at the upper end of the cylindrical side wall portion 23.
  • the two divided portions 24a are rotated by the rotation of respective hinge shafts 24b to open and close an opening at the upper end of the washing tub 21, like a double door.
  • the rotation mechanism 25 has, for example, one motor connected to the hinge shaft 24b of the two divided portions 24a via a speed reduction mechanism.
  • the hinge shafts 24b of the divided portions 24a rotate in opposite directions, and the two divided portions 24a rotate.
  • the two divided portions 24a do not cover all the portions of the opening at the upper end of the cleaning tub 21, but can also cover all the portions of the opening.
  • the second restraining portion 41 includes a second restraining piece 42 provided so as to face the bottom wall portion 22 and to change the distance from the bottom wall portion 22.
  • a second restraining piece 42 provided so as to face the bottom wall portion 22 and to change the distance from the bottom wall portion 22.
  • two second stopping pieces 42 are respectively provided at the distal ends (ends opposite to the hinge shaft 24 b) of the two divided portions 24 a on the top surface portion 24. (A total of four), and the interval between the two divided portions 24a and the bottom wall portion 22 is changed with the rotation of the two divided portions 24a via the rotation mechanism 25.
  • each second stopping piece 42 may be formed of an elastic member such as rubber.
  • the portion where the second stopper 41 presses the tubular body 52 may be anywhere on the upper end surface of the tubular body 52.
  • An ultrasonic transmitter 61 for transmitting ultrasonic waves to the treatment liquid stored in the cleaning bath 21 is attached to the outer surface of the cylindrical side wall 23 of the cleaning bath 21.
  • the mounting position of the ultrasonic transmitter 61 may be any position in the circumferential direction on the outer surface of the cylindrical side wall portion 23. However, in consideration of ease of mounting, a flat portion (stadium) on the outer surface of the cylindrical side wall portion 23 is taken into consideration. (Corresponding to the straight line 23a of the shape).
  • the axis direction of the ultrasonic waves transmitted from the ultrasonic transmitter 61 is the horizontal direction.
  • the ultrasonic wave transmitted from the ultrasonic wave transmitter 61 is reflected on the inner side surface of the cylindrical side wall portion 23 of the cleaning bath 21 and the outer peripheral surface 52 a of the cylindrical body 52. No matter how many times this reflection is repeated, the ultrasonic wave transmitted from the ultrasonic wave transmitter 61 will have the same transmission angle at the position where the transmission was started as at the time when the transmission was started due to the stadium shape of the washing tub 21. Will not return. That is, the trajectory of the ultrasonic wave is not a periodic trajectory, but a so-called chaotic trajectory. This is true regardless of the shape of the cassette 51. As a result, no standing wave is generated in the processing liquid, and a uniform sound field is formed in the processing liquid.
  • the semiconductor substrate 57 is ultrasonically treated with the treatment liquid in which such a uniform sound field is formed.
  • the movement of the cassette 51 in the vertical and horizontal directions is restricted by the first and second restricting pieces 32 and 42, and the inside of the cylindrical side wall 23 of the cleaning bath 21 is restricted. Since the side surface has a stadium shape such that a standing wave does not occur in the processing liquid, the ultrasonic processing of the semiconductor substrate 57 is performed favorably. Further, since no standing wave is generated in the processing liquid, even if the semiconductor substrate 57 for the solar cell 10 having a small thickness is subjected to ultrasonic treatment, the semiconductor substrate 57 is not damaged. This suppresses the performance degradation of the solar cell 10 due to the dangling bond of silicon.
  • the shape of the inner side surface of the cylindrical side wall 23 is not limited to the stadium shape. Irrespective of the shape of the cassette 51, in the cross section orthogonal to the cylinder axis direction of the cylindrical side wall 23, one of the circumferential directions of the inner side surface of the cylindrical side wall 23 is set so that the ultrasonic trajectory becomes a chaotic trajectory. What is necessary is just to make a part into a curve and to make the remainder straight. In this case, in the cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion 23, one or more curves on the inner side surface of the cylindrical side wall portion 23 are preferably provided, and are preferably arc-shaped or arc-shaped curves. .
  • the center of curvature of the at least one arc-shaped or arc-shaped curve may be located inside the cylindrical side wall 23 or may be located outside the cylindrical side wall 23.
  • the center of curvature of some of the plurality of arc-shaped or arc-shaped curves is located inside the cylindrical side wall portion 23, and the center of curvature of the remaining curves is outside the cylindrical side wall portion 23. It may be located.
  • the inner side surface of the cylindrical side wall portion 23 may be formed in a substantially D-shape in a cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion 23.
  • the curve on the inner side surface of the cylindrical side wall portion 23 is an arc-shaped or arcuate curve whose center of curvature is located inside the cylindrical side wall portion 23.
  • the inner side surface of the cylindrical side wall portion 23 may be formed in any one of the shapes shown in FIGS.
  • the shape of FIG. 17 there are two curved surfaces on the inner surface of the cylindrical side wall portion 23, and the curved surface has an arc shape, and the center of curvature of the one curved line is located inside the cylindrical side wall portion 23.
  • the center of curvature of another arcuate curve is located outside the cylindrical side wall 23. 14 to 19, the illustration of the first stop piece 32 is omitted.
  • the semiconductor substrate 57 for the solar cell 10 is subjected to the ultrasonic treatment in the cleaning bath 21.
  • the present invention is not limited to this.
  • a bathtub 21 can be used.

Abstract

A cleaning bath (21) for subjecting a semiconductor substrate (57) retained in a cassette (51) to ultrasonic treatment is provided with: a bottom wall portion (22); a tubular side wall portion (23) which rises from the bottom wall portion (22) and inside which a treatment liquid is stored; and an inhibiting portion (30) which inhibits movement of the cassette (51), immersed in the treatment liquid, in an in-plane direction of the bottom wall portion (22) and in an intersecting direction with respect to the in-plane direction. In a cross section perpendicular to the direction of a tubular axis of the tubular side wall portion (23), a part, in a perimetrical direction, of an inside surface of the tubular side wall portion (23) is a curve, and the remainder thereof is a straight line.

Description

洗浄浴槽Washing tub
 本明細書で開示される技術は、半導体基板を超音波処理する洗浄浴槽に関する。 The technology disclosed in this specification relates to a cleaning bath for ultrasonically treating a semiconductor substrate.
 従来より、半導体基板を洗浄浴槽の処理液に浸漬させて超音波処理するために、半導体基板をカセットに保持することが知られている。例えば特許文献1では、基板(特許文献1では、液晶表示素子の透明基板)をカセットに保持し、このカセットに保持された基板を、カセットと共に、洗浄浴槽の処理液に浸漬させた状態で、基板を超音波処理するようにしている。 Conventionally, it has been known to hold a semiconductor substrate in a cassette in order to immerse the semiconductor substrate in a processing solution in a cleaning bath and perform ultrasonic treatment. For example, in Patent Literature 1, a substrate (in Patent Literature 1, a transparent substrate of a liquid crystal display element) is held in a cassette, and the substrate held in the cassette is immersed together with the cassette in a processing solution in a cleaning bath. The substrate is subjected to ultrasonic treatment.
特開平6-138437号公報JP-A-6-138437
 ところで、シリコンウエハ上に製膜された薄膜のパターニングを、リフトオフ法によって行う場合、このパターニングの工程には、薄膜の剥離工程が含まれる。この剥離工程に超音波処理を導入した場合、工程の歩留まりが飛躍的に改善する。 In the case where a thin film formed on a silicon wafer is patterned by a lift-off method, the patterning step includes a thin film peeling step. When an ultrasonic treatment is introduced into the peeling step, the yield of the step is dramatically improved.
 しかし、超音波処理を行う際、洗浄浴槽の処理液に浸漬されるカセットは、通常、洗浄浴槽の底壁部上に置かれるだけである。このため、洗浄浴槽内でカセットが超音波により振動することで移動して、超音波処理を良好に行うことができなくなる可能性がある。 However, when performing the ultrasonic treatment, the cassette immersed in the processing solution in the cleaning bath is usually only placed on the bottom wall of the cleaning bath. For this reason, the cassette may move by being vibrated by the ultrasonic waves in the cleaning bath, and the ultrasonic processing may not be performed properly.
 また、たとえカセットの移動を制止したとしても、洗浄浴槽及びカセットの形状によっては、洗浄浴槽内の処理液中に定在波が生じる場合がある。この場合、定在波による音圧の不均一によって、洗浄ムラが生じるとともに、特に厚さが薄い半導体基板(例えば太陽電池用の半導体基板)は、定在波の腹の部分(音圧が高い部分)によって押圧されてダメージを受け易い。 Even if the movement of the cassette is stopped, a standing wave may be generated in the processing liquid in the cleaning bath depending on the shape of the cleaning bath and the cassette. In this case, unevenness in the sound pressure due to the standing wave causes uneven cleaning, and particularly, a semiconductor substrate having a small thickness (for example, a semiconductor substrate for a solar cell) has an antinode portion (a high sound pressure) of the standing wave. Part) and is easily damaged.
 ここに開示する技術は、斯かる点に鑑みてなされたものであり、その目的とするところは、カセットの形状に関係なく、半導体基板の超音波処理を良好に行える洗浄浴槽を提供することにある。 The technology disclosed herein has been made in view of such a point, and an object thereof is to provide a cleaning bath that can favorably perform ultrasonic treatment of a semiconductor substrate regardless of the shape of a cassette. is there.
 前記の目的を達成するために、以下の洗浄浴槽が提供される。 洗浄 In order to achieve the above object, the following washing tub is provided.
 この洗浄浴槽は、カセットに保持された半導体基板を、前記カセットと共に、貯留する処理液に浸漬させた状態で、前記半導体基板を超音波処理する洗浄浴槽であって、底壁部と、前記底壁部から立ち上がり、内部に前記処理液を貯留する筒状側壁部と、前記処理液に浸漬された前記カセットの、前記底壁部の面内方向及び前記面内方向に対する交差方向への移動を制止する制止部とを備え、前記筒状側壁部の筒軸方向に直交する断面において、前記筒状側壁部の内側面の周方向の一部が曲線とされかつ残部が直線とされているものである。 The cleaning bath is a cleaning bath for ultrasonically treating the semiconductor substrate in a state where the semiconductor substrate held in the cassette is immersed in the processing liquid to be stored together with the cassette. A cylindrical side wall that rises from the wall and stores the processing liquid therein, and the cassette immersed in the processing liquid moves in the in-plane direction of the bottom wall and in the direction crossing the in-plane direction. A stopping portion for stopping, wherein in the cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion, a part of the inner side surface of the cylindrical side wall portion in the circumferential direction is curved and the remaining portion is straight. It is.
 前記洗浄浴槽によると、カセットの形状及び設置位置に関係なく、半導体基板の超音波処理が良好に行われるとともに、厚さが薄い半導体基板(例えば太陽電池用の半導体基板)を超音波処理しても、半導体基板にダメージを与えることがない。 According to the cleaning bath, the ultrasonic treatment of the semiconductor substrate is favorably performed regardless of the shape and the installation position of the cassette, and the semiconductor substrate having a small thickness (for example, a semiconductor substrate for a solar cell) is ultrasonically treated. Also, the semiconductor substrate is not damaged.
例示的な実施形態に係る洗浄浴槽をカセットと共に示す平面図である。FIG. 3 is a plan view showing a cleaning tub according to an exemplary embodiment together with a cassette. 洗浄浴槽をその筒軸方向に直交する面(水平面)に沿って切断した断面図である。It is sectional drawing which cut | disconnected the washing tub along the surface (horizontal surface) orthogonal to the cylinder axis direction. 図1のIII-III線に沿って切断した断面図である。FIG. 3 is a cross-sectional view taken along the line III-III of FIG. 1. 半導体基板を保持したカセットを示す斜視図である。FIG. 3 is a perspective view showing a cassette holding semiconductor substrates. 太陽電池を部分的に示す模式的な断面図である。FIG. 2 is a schematic sectional view partially showing a solar cell. 太陽電池を構成する結晶基板の裏側主面を示す底面図である。FIG. 4 is a bottom view showing the back principal surface of the crystal substrate constituting the solar cell. 太陽電池の製造方法の一工程を示す図5相当図である。FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell. 太陽電池の製造方法の一工程を示す図5相当図である。FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell. 太陽電池の製造方法の一工程を示す図5相当図である。FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell. 太陽電池の製造方法の一工程を示す図5相当図である。FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell. 太陽電池の製造方法の一工程を示す図5相当図である。FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell. 太陽電池の製造方法の一工程を示す図5相当図である。FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell. 太陽電池の製造方法の一工程を示す図5相当図である。FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell. 筒状側壁部の内側面の別の形状を示す図2相当図である。FIG. 3 is a view corresponding to FIG. 2, showing another shape of the inner side surface of the cylindrical side wall portion. 筒状側壁部の内側面の更に別の形状を示す図2相当図である。FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion. 筒状側壁部の内側面の更に別の形状を示す図2相当図である。FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion. 筒状側壁部の内側面の更に別の形状を示す図2相当図である。FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion. 筒状側壁部の内側面の更に別の形状を示す図2相当図である。FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion. 筒状側壁部の内側面の更に別の形状を示す図2相当図である。FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion.
 以下、例示的な実施形態を図面に基づいて詳細に説明する。 Hereinafter, exemplary embodiments will be described in detail with reference to the drawings.
 図1~図3は、例示的な実施形態に係る洗浄浴槽21を示す。この洗浄浴槽21は、カセット51に保持された少なくとも1つ(本実施形態では、複数)の半導体基板57(図4参照)を、カセット51と共に、貯留する処理液に浸漬させた状態で、少なくとも1つ(複数)の半導体基板57を超音波処理するものである。本実施形態では、半導体基板57は、太陽電池10用の半導体基板である。尚、図3では、半導体基板57の記載を省略している。 FIGS. 1-3 show a cleaning tub 21 according to an exemplary embodiment. The cleaning bath 21 is provided with at least one (in the present embodiment, a plurality of) semiconductor substrates 57 (see FIG. 4) held in the cassette 51 immersed in the processing liquid to be stored together with the cassette 51, at least. This is for subjecting one (plural) semiconductor substrates 57 to ultrasonic treatment. In the present embodiment, the semiconductor substrate 57 is a semiconductor substrate for the solar cell 10. In FIG. 3, the illustration of the semiconductor substrate 57 is omitted.
 ここで、太陽電池10の構成について、図5及び図6に基づいて説明する。太陽電池10は、シリコン(Si)製の結晶基板11を用いている。結晶基板11は、互いに対向する2つの主面11S(11SU、11SB)を有している。ここでは、光が入射する主面を表側主面11SUと呼び、これとは反対側の主面を裏側主面11SBと呼ぶ。表側主面11SUは、裏側主面11SBよりも積極的に受光させる側であって受光側とされ、裏側主面11SBは、積極的に受光させない側であって非受光側とされる。 Here, the configuration of the solar cell 10 will be described with reference to FIGS. The solar cell 10 uses a crystal substrate 11 made of silicon (Si). Crystal substrate 11 has two main surfaces 11S (11SU, 11SB) facing each other. Here, the main surface on which light is incident is referred to as a front main surface 11SU, and the main surface on the opposite side is referred to as a back main surface 11SB. The front-side main surface 11SU is a light-receiving side that is a side that more actively receives light than the back-side main surface 11SB, and the back-side main surface 11SB is a side that does not actively receive light and is a non-light-receiving side.
 太陽電池10は、いわゆるヘテロ接合結晶シリコン太陽電池であって、電極層を裏側主面11SBに配置したバックコンタクト型(裏面電極型)太陽電池である。 The solar cell 10 is a so-called heterojunction crystalline silicon solar cell, and is a back-contact type (backside electrode type) solar cell in which an electrode layer is disposed on the back main surface 11SB.
 太陽電池10は、結晶基板11、真性半導体層12(12U、12p、12n)、導電型半導体層13(p型半導体層13p、n型半導体層13n)、低反射層14、及び電極層15(透明電極層17、金属電極層18)を含む。 The solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12 (12U, 12p, 12n), a conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 ( Transparent electrode layer 17 and metal electrode layer 18).
 以下では、便宜上、p型半導体層13p又はn型半導体層13nに個別に対応する部材には、参照符号の末尾に「p」又は「n」を付すことがある。 In the following, for convenience, members individually corresponding to the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be given “p” or “n” at the end of the reference numerals.
 結晶基板11は、単結晶シリコンで形成された半導体基板であってもよく、多結晶シリコンで形成された半導体基板(単結晶シリコン基板)であってもよい。以下では、単結晶シリコン基板を例に挙げて説明する。 Crystal substrate 11 may be a semiconductor substrate formed of single-crystal silicon or a semiconductor substrate (single-crystal silicon substrate) formed of polycrystalline silicon. Hereinafter, a single crystal silicon substrate will be described as an example.
 結晶基板11の導電型は、シリコン原子に対して電子を導入する不純物(例えば、リン(P)原子)を導入されたn型単結晶シリコン基板であってもよく、シリコン原子に対して正孔を導入する不純物(例えば、ホウ素(B)原子)を導入されたp型単結晶シリコン基板であってもよい。以下では、キャリア寿命が長いといわれるn型の単結晶基板を例に挙げて説明する。 The conductivity type of the crystal substrate 11 may be an n-type single crystal silicon substrate into which impurities (for example, phosphorus (P) atoms) for introducing electrons into silicon atoms have been introduced, and holes may be used for silicon atoms. May be a p-type single crystal silicon substrate into which an impurity (for example, a boron (B) atom) for introducing GaAs is introduced. Hereinafter, an n-type single crystal substrate which has a long carrier lifetime will be described as an example.
 図7に示すように、結晶基板11は、受光した光を閉じこめておくという観点から、2つの主面11Sの表面に、山(凸)と谷(凹)とから構成されるテクスチャ構造TX(第1テクスチャ構造)を有していてもよい。なお、テクスチャ構造TX(凹凸面)は、例えば、結晶基板11における面方位が(100)面のエッチングレートと、面方位が(111)面のエッチングレートとの差を応用した異方性エッチングによって形成することができる。 As shown in FIG. 7, from the viewpoint of confining the received light, the crystal substrate 11 has a texture structure TX (concave) formed of peaks (convex) and valleys (concave) on the surfaces of the two main surfaces 11S. (A first texture structure). The texture structure TX (irregular surface) is formed, for example, by anisotropic etching using the difference between the etching rate of the (100) plane and the etching rate of the (111) plane of the crystal substrate 11. Can be formed.
 テクスチャ構造TXにおける凹凸の大きさとして、例えば、頂点(山)の数で定義することが可能である。本実施形態においては、光取り込みと生産性との観点から、50000個/mm以上100000個/mm以下の範囲であることが好ましく、特には70000個/mm以上85000個/mm以下の範囲であると好ましい。 The size of the irregularities in the texture structure TX can be defined, for example, by the number of vertices (mountains). In the present embodiment, from the viewpoints of light intake and productivity, the range is preferably 50,000 / mm 2 or more and 100,000 / mm 2 or less, and in particular, 70,000 / mm 2 or more and 85,000 / mm 2 or less. Is preferably within the range.
 結晶基板11の厚さは、250μm以下であってもよい。なお、結晶基板11の厚さを測定する場合の測定方向は、結晶基板11の平均面(平均面とは、テクスチャ構造TXに依存しない基板全体としての面を意味する)に対する垂直方向である。そこで、以下、この垂直方向、すなわち、厚さを測定する方向を厚さ方向(半導体基板57の厚さ方向でもある)とする。 The thickness of the crystal substrate 11 may be 250 μm or less. The measurement direction when measuring the thickness of the crystal substrate 11 is a direction perpendicular to the average plane of the crystal substrate 11 (the average plane means a plane of the entire substrate that does not depend on the texture structure TX). Therefore, hereinafter, this vertical direction, that is, the direction in which the thickness is measured is referred to as the thickness direction (also the thickness direction of the semiconductor substrate 57).
 結晶基板11の厚さが過度に小さいと、機械的強度の低下が生じたり、外光(太陽光)が十分に吸収されず、短絡電流密度が減少したりする。このため、結晶基板11の厚さは、50μm以上が好ましく、70μm以上がより好ましい。ここで、結晶基板11の両主面11S(11SU、11SB)にテクスチャ構造TXが形成されている場合には、結晶基板11の厚さは、表側主面11SU及び裏側主面11SBのそれぞれの凹凸構造における凸の頂点(厚さ方向に互いに対向する頂点)を結んだ直線間の距離で表される。 (4) If the thickness of the crystal substrate 11 is excessively small, the mechanical strength is reduced, or external light (sunlight) is not sufficiently absorbed, and the short-circuit current density is reduced. Therefore, the thickness of crystal substrate 11 is preferably at least 50 μm, more preferably at least 70 μm. Here, when the texture structure TX is formed on both main surfaces 11S (11SU, 11SB) of the crystal substrate 11, the thickness of the crystal substrate 11 is determined by the unevenness of the front main surface 11SU and the rear main surface 11SB. It is represented by the distance between straight lines connecting the convex vertices (vertices facing each other in the thickness direction) in the structure.
 真性半導体層12(12U、12p、12n)は、結晶基板11の両主面11S(11SU、11SB)を覆うことによって、結晶基板11への不純物の拡散を抑えつつ、表面パッシベーションを行う。なお、「真性(i型)」とは、導電性不純物を含まない完全な真性に限られず、シリコン系層が真性層として機能し得る範囲で微量のn型不純物又はp型不純物を含む「弱n型」又は「弱p型」の実質的に真性である層をも包含する。 (4) The intrinsic semiconductor layer 12 (12U, 12p, 12n) covers both main surfaces 11S (11SU, 11SB) of the crystal substrate 11, thereby performing surface passivation while suppressing diffusion of impurities into the crystal substrate 11. Note that the term “intrinsic (i-type)” is not limited to complete intrinsic without conductive impurities, but includes “weak” containing a small amount of n-type impurities or p-type impurities as long as the silicon-based layer can function as an intrinsic layer. Also encompasses "n-type" or "weak p-type" substantially intrinsic layers.
 真性半導体層12(12U、12p、12n)は、必須ではなく、必要に応じて、適宜形成すればよい。 (4) The intrinsic semiconductor layer 12 (12U, 12p, 12n) is not essential, and may be appropriately formed as needed.
 真性半導体層12の材料は、特に限定されないが、非晶質シリコン系材料であってもよく、薄膜としてシリコンと水素とを含む水素化非晶質シリコン系薄膜(a-Si:H薄膜)であってもよい。なお、ここでいう非晶質とは、長周期で秩序を有していない構造であり、すなわち、完全な無秩序なだけでなく、短周期で秩序を有しているものも含まれる。 The material of the intrinsic semiconductor layer 12 is not particularly limited, but may be an amorphous silicon-based material, and may be a hydrogenated amorphous silicon-based thin film containing silicon and hydrogen (a-Si: H thin film). There may be. Note that the term “amorphous” used herein refers to a long-period, non-ordered structure, that is, a structure that is not only completely disordered but also has a short-period order.
 真性半導体層12の厚さは、特に限定されないが、2nm以上20nm以下であってもよい。厚さが2nm以上であると、結晶基板11に対するパッシベーション層としての効果が高まり、厚さが20nm以下であると、高抵抗化により生じる変換特性の低下を抑えられるためである。 厚 The thickness of the intrinsic semiconductor layer 12 is not particularly limited, but may be 2 nm or more and 20 nm or less. When the thickness is 2 nm or more, the effect as a passivation layer for the crystal substrate 11 is enhanced, and when the thickness is 20 nm or less, a decrease in conversion characteristics caused by an increase in resistance can be suppressed.
 真性半導体層12の形成方法は、特に限定されないが、プラズマCVD(Plasma enhancedChemical Vapor Deposition)法が用いられる。この方法によると、単結晶シリコンへの不純物の拡散を抑制しつつ、基板表面のパッシベーションを有効に行える。また、プラズマCVD法であれば、真性半導体層12における層中の水素濃度をその厚さ方向で変化させることにより、キャリアの回収を行う上で有効なエネルギーギャッププロファイルの形成をも行える。 The method of forming the intrinsic semiconductor layer 12 is not particularly limited, but a plasma enhanced chemical vapor deposition (CVD) method is used. According to this method, passivation of the substrate surface can be effectively performed while suppressing diffusion of impurities into single crystal silicon. In addition, in the case of the plasma CVD method, by changing the hydrogen concentration in the layer of the intrinsic semiconductor layer 12 in the thickness direction, it is possible to form an energy gap profile that is effective for carrier recovery.
 なお、プラズマCVD法による薄膜の製膜条件としては、例えば、基板温度が100℃以上300℃以下、圧力が20Pa以上2600Pa以下、及び高周波のパワー密度が0.003W/cm以上0.5W/cm以下であってもよい。 The conditions for forming a thin film by the plasma CVD method include, for example, a substrate temperature of 100 ° C. to 300 ° C., a pressure of 20 Pa to 2600 Pa, and a high-frequency power density of 0.003 W / cm 2 to 0.5 W / cm 2 or less.
 薄膜の形成に使用する原料ガスとしては、真性半導体層12の場合は、モノシラン(SiH)及びジシラン(Si)等のシリコン含有ガス、又は、それらのガスと水素(H)とを混合したガスであってもよい。 As the raw material gas used for forming the thin film, in the case of the intrinsic semiconductor layer 12, a silicon-containing gas such as monosilane (SiH 4 ) and disilane (Si 2 H 6 ), or a mixture of these gases with hydrogen (H 2 ) May be mixed gas.
 なお、上記のガスに、メタン(CH)、アンモニア(NH)、又はモノゲルマン(GeH)等の異種の元素を含むガスを添加して、シリコンカーバイド(SiC)、シリコンナイトライド(SiN)又はシリコンゲルマニウム(SIGe)等のシリコン化合物を形成することにより、薄膜のエネルギーギャップを適宜変更してもよい。 Note that a gas containing a different kind of element such as methane (CH 4 ), ammonia (NH 3 ), or monogermane (GeH 4 ) is added to the above gas, and silicon carbide (SiC), silicon nitride (SiN) By forming a silicon compound such as x ) or silicon germanium (SIGe), the energy gap of the thin film may be appropriately changed.
 導電型半導体層13としては、p型半導体層13pとn型半導体層13nとが挙げられる。図5に示すように、p型半導体層13pは、結晶基板11の裏側主面11SBの一部に真性半導体層12pを介して形成される。n型半導体層13nは、結晶基板11の裏側主面の他の一部に真性半導体層12nを介して形成される。すなわち、p型半導体層13pと結晶基板11との間、及びn型半導体層13nと結晶基板11との間に、それぞれパッシベーションの役割を果たす中間層として真性半導体層12が介在する。 (4) Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13n. As shown in FIG. 5, the p-type semiconductor layer 13p is formed on a part of the back-side main surface 11SB of the crystal substrate 11 via the intrinsic semiconductor layer 12p. The n-type semiconductor layer 13n is formed on another part of the back-side main surface of the crystal substrate 11 via the intrinsic semiconductor layer 12n. That is, the intrinsic semiconductor layer 12 is interposed between the p-type semiconductor layer 13p and the crystal substrate 11 and between the n-type semiconductor layer 13n and the crystal substrate 11 as an intermediate layer that plays a role of passivation.
 p型半導体層13p及びn型半導体層13nの各厚さは、特に限定されないが、2nm以上20nm以下であってもよい。厚さが2nm以上であると、結晶基板11に対するパッシベーション層としての効果が高まり、厚さが20nm以下であると、高抵抗化により生じる変換特性の低下を抑えられるためである。 Each thickness of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n is not particularly limited, but may be 2 nm or more and 20 nm or less. When the thickness is 2 nm or more, the effect as a passivation layer for the crystal substrate 11 is enhanced, and when the thickness is 20 nm or less, a decrease in conversion characteristics caused by an increase in resistance can be suppressed.
 p型半導体層13p及びn型半導体層13nは、結晶基板11の裏側主面11SBにおいて、p型半導体層13pとn型半導体層13nとが電気的に分離されるように配置される。導電型半導体層13の幅は、50μm以上3000μm以下であってよく、80μm以上800μm以下であってもよい(なお、半導体層の幅及び後述の電極層の幅は、特に断りがない限り、パターン化された各層の一部分の長さで、パターン化により、例えば線状になった一部分の延び方向と直交する方向の長さを意図する)。 The p-type semiconductor layer 13p and the n-type semiconductor layer 13n are arranged such that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are electrically separated from each other on the back main surface 11SB of the crystal substrate 11. The width of the conductive type semiconductor layer 13 may be 50 μm or more and 3000 μm or less, and may be 80 μm or more and 800 μm or less (note that the width of the semiconductor layer and the width of an electrode layer described later are the same unless otherwise specified. The length of a portion of each of the layered layers is intended to be, for example, the length in a direction perpendicular to the extending direction of the linear portion by patterning).
 結晶基板11内で生成した光励起子(キャリア)が導電型半導体層13を介して取り出される場合、正孔は電子よりも有効質量が大きい。このため、輸送損を低減させるという観点から、p型半導体層13pがn型半導体層13nよりも幅が狭くてもよい。例えば、p型半導体層13pの幅は、n型半導体層13nの幅の0.5倍以上0.9倍以下であってもよく、また、0.6倍以上0.8倍以下であってもよい。 (4) When photoexcitons (carriers) generated in the crystal substrate 11 are extracted through the conductive semiconductor layer 13, holes have a larger effective mass than electrons. Therefore, from the viewpoint of reducing transport loss, the width of the p-type semiconductor layer 13p may be smaller than that of the n-type semiconductor layer 13n. For example, the width of the p-type semiconductor layer 13p may be 0.5 to 0.9 times the width of the n-type semiconductor layer 13n, or 0.6 to 0.8 times. Is also good.
 p型半導体層13pは、p型のドーパント(ホウ素等)が添加されたシリコン層であって、不純物拡散の抑制又は直列抵抗の抑制という観点から、非晶質シリコンで形成されてもよい。一方、n型半導体層13nは、n型のドーパント(リン等)が添加されたシリコン層であって、p型半導体層13pと同様に、非晶質シリコン層で形成されてもよい。 The p-type semiconductor layer 13p is a silicon layer to which a p-type dopant (boron or the like) is added, and may be formed of amorphous silicon from the viewpoint of suppressing impurity diffusion or suppressing series resistance. On the other hand, the n-type semiconductor layer 13n is a silicon layer to which an n-type dopant (such as phosphorus) is added, and may be formed of an amorphous silicon layer, similarly to the p-type semiconductor layer 13p.
 導電型半導体層13の原料ガスとしては、モノシラン(SiH)若しくはジシラン(Si)等のシリコン含有ガス、又はシリコン系ガスと水素(H)との混合ガスを用いてもよい。ドーパントガスには、p型半導体層13pの形成にはジボラン(B)等を用いることができ、n型半導体層の形成にはホスフィン(PH)等を用いることができる。また、ホウ素(B)又はリン(P)といった不純物の添加量は微量でよいため、ドーパントガスを原料ガスで希釈した混合ガスを用いてもよい。 As the raw material gas for the conductive semiconductor layer 13, a silicon-containing gas such as monosilane (SiH 4 ) or disilane (Si 2 H 6 ), or a mixed gas of a silicon-based gas and hydrogen (H 2 ) may be used. As the dopant gas, diborane (B 2 H 6 ) or the like can be used for forming the p-type semiconductor layer 13p, and phosphine (PH 3 ) or the like can be used for forming the n-type semiconductor layer. Further, since the amount of impurities such as boron (B) or phosphorus (P) may be very small, a mixed gas obtained by diluting a dopant gas with a source gas may be used.
 また、p型半導体層13p又はn型半導体層13nのエネルギーギャップの調整のために、メタン(CH)、二酸化炭素(CO)、アンモニア(NH)又はモノゲルマン(GeH)等の異種の元素を含むガスを添加することにより、p型半導体層13p又はn型半導体層13nが化合物化されてもよい。 Further, in order to adjust the energy gap of the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, different kinds of substances such as methane (CH 4 ), carbon dioxide (CO 2 ), ammonia (NH 3 ), and monogermane (GeH 4 ) are used. By adding a gas containing the element described above, the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be compounded.
 低反射層14は、太陽電池10が受けた光の反射を抑制する層である。低反射層14の材料には、光を透過する透光性の材料であれば、特に限定されないが、例えば、酸化ケイ素(SiO)、窒化ケイ素(SiN)、酸化亜鉛(ZnO)又は酸化チタン(TiO)が挙げられる。また、低反射層14の形成方法としては、例えば、酸化亜鉛又は酸化チタン等の酸化物のナノ粒子を分散させた樹脂材料で塗布してもよい。 The low reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10. The material of the low reflective layer 14 is not particularly limited as long as it is a light-transmitting material that transmits light. For example, silicon oxide (SiO x ), silicon nitride (SiN x ), zinc oxide (ZnO), or oxide Titanium (TiO x ) is exemplified. As a method for forming the low reflective layer 14, for example, the low reflective layer 14 may be coated with a resin material in which nanoparticles of an oxide such as zinc oxide or titanium oxide are dispersed.
 電極層15は、p型半導体層13p又はn型半導体層13nをそれぞれ覆うように形成されて、各導電型半導体層13と電気的に接続される。これにより、電極層15は、p型半導体層13p又はn型半導体層13nに生じるキャリアを導く輸送層として機能する。 The electrode layer 15 is formed so as to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, respectively, and is electrically connected to each conductive semiconductor layer 13. Thereby, the electrode layer 15 functions as a transport layer for guiding carriers generated in the p-type semiconductor layer 13p or the n-type semiconductor layer 13n.
 なお、電極層15は、導電性が高い金属のみで形成されてもよい。また、p型半導体層13p及びn型半導体層13nとのそれぞれの電気的な接合の観点から、又は電極材料である金属の両半導体層13p、13nに対する原子の拡散を抑制するという観点から、透明導電性酸化物で構成された電極層15を、金属製の電極層とp型半導体層13pとの間及び金属製の電極層とn型半導体層13nとの間にそれぞれ設けてもよい。 The electrode layer 15 may be formed only of a highly conductive metal. Further, from the viewpoint of electrical connection with the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or from the viewpoint of suppressing the diffusion of atoms of the metal as the electrode material into the two semiconductor layers 13p and 13n, the transparent material is used. The electrode layer 15 made of a conductive oxide may be provided between the metal electrode layer and the p-type semiconductor layer 13p and between the metal electrode layer and the n-type semiconductor layer 13n.
 本実施形態においては、透明導電性酸化物で形成される電極層15を透明電極層17と称し、金属製の電極層15を金属電極層18と称する。また、図6に示す結晶基板11の裏側主面11SBの底面図に示すように、それぞれ櫛歯形状を持つp型半導体層13p及びn型半導体層13nにおいて、櫛背部上に形成される電極層をバスバー部と称し、櫛歯部上に形成される電極層をフィンガ部と称することがある。 In the present embodiment, the electrode layer 15 formed of a transparent conductive oxide is referred to as a transparent electrode layer 17, and the metal electrode layer 15 is referred to as a metal electrode layer 18. As shown in the bottom view of the back main surface 11SB of the crystal substrate 11 shown in FIG. 6, an electrode layer formed on the back of the comb in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n each having a comb shape. May be referred to as a bus bar portion, and an electrode layer formed on the comb teeth portion may be referred to as a finger portion.
 透明電極層17は、材料としては特に限定されないが、例えば、酸化亜鉛(ZnO)若しくは酸化インジウム(InO)、又は酸化インジウムに種々の金属酸化物、例えば酸化チタン(TiO)、酸化スズ(SnO)、酸化タングステン(WO)若しくは酸化モリブデン(MoO)等を1重量%以上10重量%以下の濃度で添加した透明導電性酸化物が挙げられる。 The material of the transparent electrode layer 17 is not particularly limited. For example, zinc oxide (ZnO) or indium oxide (InO x ), or various metal oxides such as titanium oxide (TiO x ), tin oxide ( A transparent conductive oxide to which SnO), tungsten oxide (WO x ), molybdenum oxide (MoO x ), or the like is added at a concentration of 1% by weight or more and 10% by weight or less is given.
 透明電極層17の厚さは、20nm以上200nm以下であってもよい。この厚さに好適な透明電極層の形成方法には、例えば、スパッタ法等の物理気相堆積(PVD:physical Vapor Deposition)法、又は有機金属化合物と酸素又は水との反応を利用した金属有機化学気相堆積法(MOCVD:Metal-Organic Chemical Vapor Deposition)法等が挙げられる。 The thickness of the transparent electrode layer 17 may be 20 nm or more and 200 nm or less. As a method for forming a transparent electrode layer suitable for this thickness, for example, a physical vapor deposition (PVD) method such as a sputtering method, or a metal organic compound utilizing a reaction between an organometallic compound and oxygen or water is used. Chemical vapor deposition (MOCVD: Metal-Organic Chemical Vapor Deposition), and the like.
 金属電極層18は、材料としては特に限定されないが、例えば、銀(Ag)、銅(Cu)、アルミニウム(Al)又はニッケル(Ni)等が挙げられる。 The material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver (Ag), copper (Cu), aluminum (Al), and nickel (Ni).
 金属電極層18の厚さは、1μm以上80μm以下であってもよい。この厚さに好適な金属電極層18の形成方法には、材料ペーストをインクジェットによる印刷若しくはスクリーン印刷する印刷法、又はめっき法が挙げられる。但し、これには限定されず、真空プロセスを採用する場合には、蒸着又はスパッタリング法を採用してもよい。 厚 The thickness of the metal electrode layer 18 may be 1 μm or more and 80 μm or less. As a method for forming the metal electrode layer 18 having a suitable thickness, a printing method in which a material paste is printed by inkjet printing or screen printing, or a plating method is used. However, the present invention is not limited to this, and when a vacuum process is employed, a vapor deposition or sputtering method may be employed.
 p型半導体層13p及びn型半導体層13nにおける櫛歯部の幅と、該櫛歯部の上に形成される金属電極層18の幅とは、同程度であってもよい。但し、櫛歯部の幅と比べて、金属電極層18の幅が狭くてもよい。また、金属電極層18同士のリーク電流が防止される構成であれば、櫛歯部の幅と比べて、金属電極層18の幅が広くてもよい。 (4) The width of the comb-tooth portion of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be substantially equal to the width of the metal electrode layer 18 formed on the comb-tooth portion. However, the width of the metal electrode layer 18 may be smaller than the width of the comb teeth. In addition, the width of the metal electrode layer 18 may be wider than the width of the comb portion as long as the configuration prevents leakage current between the metal electrode layers 18.
 本実施形態においては、結晶基板11の裏側主面11SBの上に、真性半導体層12、導電型半導体層13、低反射層14及び電極層15を積層した状態で、各接合面のパッシベーション、導電型半導体層13及びその界面における欠陥準位の発生の抑制、並びに透明電極層17における透明導電性酸化物の結晶化を目的として、所定のアニール処理を施す。 In this embodiment, the passivation and conduction of each junction surface are performed in a state where the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low reflection layer 14, and the electrode layer 15 are stacked on the back main surface 11SB of the crystal substrate 11. A predetermined annealing process is performed for the purpose of suppressing generation of defect levels at the type semiconductor layer 13 and the interface thereof, and crystallization of the transparent conductive oxide in the transparent electrode layer 17.
 本実施形態に係るアニール処理には、例えば、上記の各層を形成した結晶基板11を150℃以上200℃以下に過熱したオーブンに投入して行うアニール処理が挙げられる。この場合、オーブン内の雰囲気は、大気でもよく、さらには、雰囲気として水素又は窒素を用いると、より効果的なアニール処理を行うことができる。また、このアニール処理は、各層を形成した結晶基板11に、赤外線ヒータにより赤外線を照射させるRTA(Rapid Thermal Annealing)処理であってもよい。 The annealing process according to the present embodiment includes, for example, an annealing process in which the crystal substrate 11 on which the above-described layers are formed is placed in an oven heated to 150 ° C. or more and 200 ° C. or less. In this case, the atmosphere in the oven may be air, and if hydrogen or nitrogen is used as the atmosphere, more effective annealing can be performed. The annealing may be an RTA (Rapid Thermal Annealing) process in which the crystal substrate 11 on which each layer is formed is irradiated with infrared rays by an infrared heater.
 以下、太陽電池10の製造方法について、図7~図13を参照しながら説明する。 Hereinafter, a method for manufacturing the solar cell 10 will be described with reference to FIGS.
 まず、図7に示すように、表側主面11SU及び裏側主面11SBにそれぞれテクスチャ構造TXを有する結晶基板11を準備する。 First, as shown in FIG. 7, a crystal substrate 11 having a texture structure TX on each of a front main surface 11SU and a back main surface 11SB is prepared.
 次に、図8に示すように、結晶基板11の表側主面11SUの上に、例えば真性半導体層12Uを形成する。続いて、形成した真性半導体層12Uの上に反射防止層14を形成する。反射防止層14には、入射光を閉じ込める光閉じ込め効果の観点から、適した光吸収係数及び屈折率を有するシリコンナイトライド(SiN)又はシリコンオキサイド(SiO)が用いられる。 Next, as shown in FIG. 8, for example, an intrinsic semiconductor layer 12U is formed on the front main surface 11SU of the crystal substrate 11. Subsequently, the antireflection layer 14 is formed on the formed intrinsic semiconductor layer 12U. As the antireflection layer 14, silicon nitride (SiN x ) or silicon oxide (SiO x ) having a suitable light absorption coefficient and refractive index is used from the viewpoint of a light confinement effect of confining incident light.
 次に、図9に示すように、結晶基板11の裏側主面11SBの上に、例えばi型非晶質シリコンを用いた真性半導体層12pを形成する。続いて、形成した真性半導体層12pの上に、p型半導体層13pを形成する。これにより、結晶基板11における一方の主面である裏側主面11SBの上に、真性半導体層12pを介在させたp型半導体層13pが形成される。 Next, as shown in FIG. 9, an intrinsic semiconductor layer 12p using, for example, i-type amorphous silicon is formed on the back-side main surface 11SB of the crystal substrate 11. Subsequently, a p-type semiconductor layer 13p is formed on the formed intrinsic semiconductor layer 12p. Thus, p-type semiconductor layer 13p with intrinsic semiconductor layer 12p interposed is formed on back main surface 11SB, which is one main surface of crystal substrate 11.
 その後、その形成したp型半導体層13pの上に、複数層のリフトオフ層LF(第1リフトオフ層LF1及び第2リフトオフ層LF2)を形成する。具体的には、p型半導体層13pの上に、互いの密度が異なるシリコン系薄膜材料を含む第1リフトオフ層LF1及び第2リフトオフ層LF2を順次積層して形成する。これにより、第1リフトオフ層LF1がp型半導体層13pの上に形成され、第2リフトオフ層LF2が第1リフトオフ層LF1の上に形成される。 {After that, a plurality of lift-off layers LF (first lift-off layer LF1 and second lift-off layer LF2) are formed on the formed p-type semiconductor layer 13p. Specifically, on the p-type semiconductor layer 13p, a first lift-off layer LF1 and a second lift-off layer LF2 containing silicon-based thin film materials having different densities are sequentially laminated and formed. Thus, the first lift-off layer LF1 is formed on the p-type semiconductor layer 13p, and the second lift-off layer LF2 is formed on the first lift-off layer LF1.
 次に、図10に示すように、結晶基板11の裏側主面11SBにおいて、第2リフトオフ層LF2、第1リフトオフ層LF1及びp型半導体層13pをパターニングする。これにより、p型半導体層13pが選択的に除去されて、p型半導体層13pの形成されない非形成領域NAが生じる。一方、結晶基板11の裏側主面11SBでエッチングされなかった領域には、少なくとも第2リフトオフ層LF2、第1リフトオフ層LF1及びp型半導体層13pが残る。 Next, as shown in FIG. 10, on the back main surface 11SB of the crystal substrate 11, the second lift-off layer LF2, the first lift-off layer LF1, and the p-type semiconductor layer 13p are patterned. Thereby, the p-type semiconductor layer 13p is selectively removed, and a non-formed region NA where the p-type semiconductor layer 13p is not formed is generated. On the other hand, at least the second lift-off layer LF2, the first lift-off layer LF1, and the p-type semiconductor layer 13p remain in a region that is not etched on the back main surface 11SB of the crystal substrate 11.
 このようなパターニング工程は、フォトリソグラフィ法、例えば所定のパターンを有するレジスト膜(不図示)を第2リフトオフ層LF2の上に形成し、形成したレジスト膜によってマスクされた領域をエッチングすることにより実現する。図10に示す場合は、真性半導体層12p、p型半導体層13p、第1リフトオフ層LF1、及び第2リフトオフ層LF2の各層をパターニングすることにより、結晶基板11の裏側主面11SBの一部の領域に非形成領域NA、すなわち裏側主面11SBの露出領域が生じる。 Such a patterning step is realized by a photolithography method, for example, by forming a resist film (not shown) having a predetermined pattern on the second lift-off layer LF2 and etching a region masked by the formed resist film. I do. In the case shown in FIG. 10, by patterning each of the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, the first lift-off layer LF1, and the second lift-off layer LF2, a part of the back-side main surface 11SB of the crystal substrate 11 is partially patterned. In the region, a non-formed region NA, that is, an exposed region of the back main surface 11SB is generated.
 図10に示す工程で使用するエッチング溶液として、例えばフッ化水素酸と酸化性溶液との混合溶液(例えばフッ硝酸)、又は、オゾンをフッ化水素酸に溶解させた溶液(以下、オゾン/フッ酸液という)が挙げられる。また、リフトオフ層LFのエッチングに寄与するエッチング剤はフッ化水素である。なお、ここでのパターニングは、エッチング溶液を用いたウエットエッチングには限定されない。パターニングは、例えばドライエッチングであってもよく、エッチングペースト等を用いたパターン印刷であってもよい。 As an etching solution used in the step shown in FIG. 10, for example, a mixed solution of hydrofluoric acid and an oxidizing solution (for example, hydrofluoric nitric acid) or a solution in which ozone is dissolved in hydrofluoric acid (hereinafter, ozone / hydrofluoric acid) Acid solution). The etching agent that contributes to the etching of the lift-off layer LF is hydrogen fluoride. The patterning here is not limited to wet etching using an etching solution. The patterning may be, for example, dry etching or pattern printing using an etching paste or the like.
 次に、図11に示すように、第2リフトオフ層LF2、第1リフトオフ層LF1、p型半導体層13p及び真性半導体層12pを含め、結晶基板11の裏側主面11SBの上に、真性半導体層12n及びn型半導体層13nを順次形成する。これにより、真性半導体層12nとn型半導体層13nとの積層膜が、非形成領域NA上と、第2リフトオフ層LF2の表面及び側面(端面)上と、第1リフトオフ層LF1、p型半導体層13p及び真性半導体層12pの側面(端面)上とに形成される。 Next, as shown in FIG. 11, the intrinsic semiconductor layer including the second lift-off layer LF2, the first lift-off layer LF1, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p is formed on the back-side main surface 11SB of the crystal substrate 11. 12n and the n-type semiconductor layer 13n are sequentially formed. Thereby, the stacked film of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n is formed on the non-formation region NA, on the surface and side surface (end surface) of the second lift-off layer LF2, and on the first lift-off layer LF1 and the p-type semiconductor. It is formed on the side surface (end surface) of the layer 13p and the intrinsic semiconductor layer 12p.
 次に、図12に示すように、エッチング溶液を用いて、積層した第1リフトオフ層LF1及び第2リフトオフ層LF2を除去することにより、第2リフトオフ層LF2の上に堆積したn型半導体層13n及び真性半導体層12nを結晶基板11から除去する(この工程をリフトオフ工程と称する)。なお、このリフトオフ工程に使用するエッチング溶液としては、例えばフッ化水素酸を主成分とする溶液が挙げられる。 Next, as shown in FIG. 12, the n-type semiconductor layer 13n deposited on the second lift-off layer LF2 by removing the stacked first lift-off layer LF1 and the second lift-off layer LF2 using an etching solution. Then, the intrinsic semiconductor layer 12n is removed from the crystal substrate 11 (this step is called a lift-off step). The etching solution used in the lift-off step includes, for example, a solution containing hydrofluoric acid as a main component.
 その後、リンス液を用いて、結晶基板11に付着しているエッチング溶液を除去する(この工程をリンス工程と称する)。リンス工程では、リフトオフ工程で完全に除去できなかった、リフトオフ層LFを覆うn型半導体層13n及び真性半導体層12nを除去する。リンス液としては、例えば純水をベースとして、後述の如く表面張力を調整するための液性調整剤を添加したものを用いる。 (4) Thereafter, the etching solution attached to the crystal substrate 11 is removed by using a rinsing liquid (this step is called a rinsing step). In the rinsing step, the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n that cover the lift-off layer LF and are not completely removed in the lift-off step are removed. As the rinsing liquid, for example, a liquid obtained by adding a liquid property adjusting agent for adjusting the surface tension as described later is used based on pure water.
 リフトオフ工程及びリンス工程に用いるエッチング溶液及びリンス液の表面張力は、25mN/m以上70mN/m以下であることが好ましく、特に30mN/m以上60mN/m以下であることが好ましい。表面張力をこの範囲内にすることにより、p型半導体層13p及びリフトオフ層LFに対する高い濡れ性により、リフトオフ工程がスムーズに進み、さらに、リフトオフ工程及びリンス工程で剥離したn型半導体層13n及び真性半導体層12nが、エッチング溶液及びリンス液中で凝集し易くなる。その結果、凝集して粒子が大きくなることにより、n型半導体層13n及び真性半導体層12nの結晶基板11への再付着が抑制される。また、エッチング溶液又はリンス液を循環させた際に、フィルタリングにより粒子の除去が容易となる。このように、微細な剥離及び浮遊物が液中に長時間対流することがなくなるので、生産性及び歩留まりが共に向上する。 (4) The surface tension of the etching solution and the rinsing solution used in the lift-off step and the rinsing step is preferably from 25 mN / m to 70 mN / m, and more preferably from 30 mN / m to 60 mN / m. By setting the surface tension within this range, the lift-off step proceeds smoothly due to the high wettability to the p-type semiconductor layer 13p and the lift-off layer LF, and further, the n-type semiconductor layer 13n and the intrinsic The semiconductor layer 12n is easily aggregated in the etching solution and the rinsing liquid. As a result, the particles are agglomerated and the particles become large, so that the re-adhesion of the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n to the crystal substrate 11 is suppressed. Further, when the etching solution or the rinsing liquid is circulated, the removal of the particles is facilitated by filtering. As described above, fine separation and suspended matter do not convect in the liquid for a long time, so that both productivity and yield are improved.
 次に、図13に示すように、結晶基板11における裏側主面11SBの上、すなわち、p型半導体層13p及びn型半導体層13nのそれぞれに、例えば、マスクを用いたスパッタリング法により、分離溝25を生じさせるように透明電極層17(17p、17n)を形成する。なお、透明電極層17(17p、17n)の形成は、スパッタリング法に代えて、以下のようにしてもよい。例えば、マスクを用いずに透明導電性酸化物膜を裏側主面11SB上の全面に製膜し、その後、フォトリソグラフィ法により、p型半導体層13p上及びn型半導体層13n上にそれぞれ透明導電性酸化物膜を残すエッチングを行って形成してもよい。ここで、p型半導体層13pとn型半導体層13nとを互いに分離絶縁する分離溝25を形成することにより、リーク電流が発生し難くなる。 Next, as shown in FIG. 13, separation grooves are formed on the back main surface 11SB of the crystal substrate 11, that is, on each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by, for example, a sputtering method using a mask. The transparent electrode layer 17 (17p, 17n) is formed so as to give 25. The transparent electrode layer 17 (17p, 17n) may be formed as follows instead of the sputtering method. For example, a transparent conductive oxide film is formed on the entire back surface 11SB without using a mask, and then the transparent conductive oxide film is formed on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by photolithography. It may be formed by performing etching to leave a conductive oxide film. Here, by forming the separation groove 25 for separating and insulating the p-type semiconductor layer 13p and the n-type semiconductor layer 13n from each other, a leak current is less likely to occur.
 その後、透明電極層17の上に、例えば開口部を有するメッシュスクリーン(不図示)を用いて、線状の金属電極層18(18p、18n)を形成する。 Then, a linear metal electrode layer 18 (18p, 18n) is formed on the transparent electrode layer 17 using, for example, a mesh screen (not shown) having openings.
 こうして、裏面接合型の太陽電池10が形成される。この太陽電池10の形成過程におけるリフトオフ工程及び/又はリンス工程において、処理液が貯留された洗浄浴槽21を用いて超音波処理が行われ、これにより、n型半導体層13n及び真性半導体層12nの剥離がより確実なものとなる。洗浄浴槽21内の処理液としては、リフトオフ工程では、当該リフトオフ工程に使用するエッチング溶液であり、リンス工程では、リンス液である。本実施形態において、カセット51に保持される半導体基板57は、図11又は図12の状態にある半導体基板(結晶基板11に、真性半導体層12p、p型半導体層13p、真性半導体層12n、n型半導体層13n等が積層されたもの)である。本実施形態では、半導体基板57は、その厚さ方向から見て、略矩形状をなしている。 Thus, the back junction solar cell 10 is formed. In the lift-off step and / or the rinsing step in the process of forming the solar cell 10, ultrasonic treatment is performed using the cleaning bath 21 in which the processing liquid is stored, whereby the n-type semiconductor layer 13 n and the intrinsic semiconductor layer 12 n are removed. Peeling becomes more reliable. The processing liquid in the cleaning bath 21 is an etching solution used in the lift-off step in the lift-off step, and a rinsing liquid in the rinsing step. In the present embodiment, the semiconductor substrate 57 held in the cassette 51 is the semiconductor substrate in the state shown in FIG. 11 or FIG. 12 (the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, the intrinsic semiconductor layer 12n, n (Where the semiconductor layer 13n and the like are stacked). In the present embodiment, the semiconductor substrate 57 has a substantially rectangular shape when viewed from the thickness direction.
 図3及び図4に示すように、本実施形態では、カセット51は、樹脂製の筒状体52で構成されていて、筒状体52の筒軸方向が上下方向となるように、洗浄浴槽21内の処理液に浸漬される。なお、筒状体52は樹脂製に限らず、例えば金属製であってもよい。以下、カセット51(筒状体52)については、洗浄浴槽21内に配置される姿勢(処理液に浸漬される姿勢)にあるとして説明する。 As shown in FIGS. 3 and 4, in the present embodiment, the cassette 51 is formed of a resin-made tubular body 52, and the cleaning tub is placed such that the tubular axis direction of the tubular body 52 is the vertical direction. 21 is immersed in the processing solution. Note that the tubular body 52 is not limited to a resin, and may be, for example, a metal. Hereinafter, the cassette 51 (the tubular body 52) will be described as being in the posture (the posture immersed in the processing liquid) disposed in the cleaning bath 21.
 筒状体52をその筒軸方向に直交する断面(水平方向に沿って切断した断面)の形状は、略長方形状とされている。筒状体52について、その断面の長方形の長辺が延びる方向を、長手方向といい、長方形の短辺が延びる方向を、短手方向という。なお、筒状体52の断面形状は、略長方形状に限られるものではなく、どのような形状であってもよい。また、カセット51の大きさは、カセット51を、洗浄浴槽21の内部に筒状体52の筒軸方向が上下方向となるように配置して、洗浄浴槽21内の処理液に浸漬させることが可能であれば、どのような大きさであってもよい。 断面 The shape of the cross section of the cylindrical body 52 orthogonal to the cylindrical axis direction (cross section cut along the horizontal direction) is substantially rectangular. With respect to the tubular body 52, the direction in which the long side of the rectangle of the cross section extends is called the longitudinal direction, and the direction in which the short side of the rectangle extends is the short direction. The cross-sectional shape of the tubular body 52 is not limited to a substantially rectangular shape, and may be any shape. The size of the cassette 51 may be such that the cassette 51 is disposed inside the cleaning bath 21 such that the cylindrical axis of the cylindrical body 52 is in the vertical direction, and is immersed in the processing liquid in the cleaning bath 21. Any size is possible if possible.
 筒状体52は、筒状体52の外側に表出する外周面52aと、筒状体52の内側に空間を形成する内周面52bとを有する。筒状体52の内周面52bは、筒状体52の筒軸方向の全体に亘って、筒状体52の筒軸方向(上下方向)に真っ直ぐに延びている。一方、筒状体52の外周面52aは、筒状体52の筒軸方向に延びる筒軸方向延設部52cと、筒状体52の厚さが上側ほど厚くなるように筒状体52の筒軸方向に対して傾斜した傾斜部52dとで構成されている。筒軸方向延設部52cは、筒状体52の外周面52aにおける下端部のみに設けられ、傾斜部52dは、筒軸方向延設部52cよりも上側の部分に設けられている。傾斜部52dによって、筒状体52の上端面の厚さが大きく確保されて、後述の第2の制止片42による筒状体52の押圧が良好に行われる。なお、筒状体52の外周面52aの筒軸方向の全体が、内周面52bと同様に、筒状体52の筒軸方向(上下方向)に真っ直ぐに延びていてもよい。 The cylindrical body 52 has an outer peripheral surface 52a exposed outside the cylindrical body 52 and an inner peripheral surface 52b forming a space inside the cylindrical body 52. The inner peripheral surface 52b of the tubular body 52 extends straight in the tubular axis direction (vertical direction) of the tubular body 52 over the entirety of the tubular body 52 in the tubular axis direction. On the other hand, the outer peripheral surface 52a of the cylindrical body 52 has a cylindrical axially extending portion 52c extending in the cylindrical axis direction of the cylindrical body 52 and the cylindrical body 52 so that the thickness of the cylindrical body 52 increases toward the upper side. And an inclined portion 52d inclined with respect to the cylinder axis direction. The tubular axially extending portion 52c is provided only at the lower end of the outer peripheral surface 52a of the tubular body 52, and the inclined portion 52d is provided at a portion above the tubular axially extending portion 52c. By the inclined portion 52d, a large thickness of the upper end surface of the tubular body 52 is ensured, and the pushing of the tubular body 52 by the second blocking piece 42 described later is favorably performed. The entirety of the outer peripheral surface 52a of the cylindrical body 52 in the cylinder axis direction may extend straight in the cylindrical axis direction (vertical direction) of the cylindrical body 52, similarly to the inner peripheral surface 52b.
 筒状体52の内周面52bにおいて短手方向に互いに対向する2つの部分に、半導体基板57を保持する複数の保持用突起部52eが長手方向に並ぶようにそれぞれ設けられている。その各部分において長手方向に相隣接する保持用突起部52eの間の間隔が、半導体基板57の厚さ(図4では、分かり易くするために誇張して描いている)と略同じとされ、その間に半導体基板57が上下方向に延びた起立した姿勢で保持される。また、各面において相隣接する保持用突起部52eの間の下端部に、半導体基板57の下面が当接して半導体基板57を支持する基板支持部52f(図3参照)が設けられている。半導体基板57の保持の構成は、一例であり、その他の構成を採用してもよい。また、カセット51に保持される半導体基板57の姿勢は、どのような姿勢であってもよく、例えば、上下方向に対して傾斜した姿勢であってもよい。さらに、半導体基板57の面がどの方向を向いていてもよい。 複数 A plurality of holding projections 52e for holding the semiconductor substrate 57 are provided on two portions of the inner peripheral surface 52b of the cylindrical body 52 facing each other in the short direction so as to be arranged in the longitudinal direction. The distance between the holding projections 52e adjacent to each other in the longitudinal direction in each portion is substantially the same as the thickness of the semiconductor substrate 57 (in FIG. 4, exaggerated for simplicity), In the meantime, the semiconductor substrate 57 is held in an upright posture extending vertically. Further, a substrate supporting portion 52f (see FIG. 3) that supports the semiconductor substrate 57 by contacting the lower surface of the semiconductor substrate 57 is provided at a lower end portion between the adjacent holding projections 52e on each surface. The configuration for holding the semiconductor substrate 57 is an example, and another configuration may be employed. The posture of the semiconductor substrate 57 held by the cassette 51 may be any posture, for example, may be a posture inclined with respect to the vertical direction. Further, the surface of the semiconductor substrate 57 may be oriented in any direction.
 洗浄浴槽21は、水平方向に延びる底壁部22と、底壁部22の周縁部から上側に立ち上がり、内部に処理液を貯留する筒状側壁部23とを備えていて、上側が開口された有底筒状に形成されている。すなわち、底壁部22の面内方向に対して交差する方向に立ち上がるように筒状側壁部23が形成される。筒状側壁部23の筒軸方向は上下方向に一致している(すなわち、本実施形態では、底壁部22の面内方向に対する交差方向は上下方向であるといえる)。洗浄浴槽21も、筒状体52と同様に、樹脂製である。洗浄浴槽21も、樹脂製に限らず、例えば金属製であってもよい。 The washing tub 21 includes a bottom wall portion 22 extending in the horizontal direction, and a cylindrical side wall portion 23 that rises upward from a peripheral portion of the bottom wall portion 22 and stores therein a processing liquid. It is formed in a bottomed cylindrical shape. That is, the cylindrical side wall 23 is formed so as to rise in a direction crossing the in-plane direction of the bottom wall 22. The cylinder axis direction of the cylindrical side wall 23 coincides with the vertical direction (that is, in the present embodiment, the direction of intersection with the in-plane direction of the bottom wall 22 is the vertical direction). The washing tub 21 is also made of resin like the tubular body 52. The washing tub 21 is not limited to resin, but may be metal, for example.
 筒状側壁部23の筒軸方向に直交する断面(水平方向に沿って切断した断面)において、筒状側壁部23の内側面の周方向の一部が曲線とされかつ残部が直線とされている。本実施形態では、図2に示すように、筒状側壁部23の筒軸方向に直交する断面において、筒状側壁部23の内側面は、互いに平行な2つの直線23aと、2つの直線23aの一側端部同士及び他側端部同士を連結する、曲率中心が筒状側壁部23の内側に位置する円弧状の曲線23bとを含む形状(以下、スタジアム形状という)とされている。本実施形態では、筒状側壁部23の外側面も、内側面と同様の形状とされている。尚、円弧状の曲線23bに代えて、弓状の曲線としてもよい。 In the cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion 23 (cross section cut along the horizontal direction), a part of the inner side surface of the cylindrical side wall portion 23 in the circumferential direction is curved and the remaining portion is straight. I have. In the present embodiment, as shown in FIG. 2, in a cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion 23, the inner side surface of the cylindrical side wall portion 23 has two straight lines 23a parallel to each other and two straight lines 23a. A shape including an arc-shaped curve 23b whose center of curvature is located inside the cylindrical side wall portion 23 and connects the one side end portions and the other side end portions (hereinafter, referred to as a stadium shape). In the present embodiment, the outer side surface of the cylindrical side wall portion 23 has the same shape as the inner side surface. Note that an arc-shaped curve may be used instead of the arc-shaped curve 23b.
 洗浄浴槽21は、処理液に浸漬されたカセット51の上下方向(底壁部22の面内方向に対する交差方向)、及び上下方向に交差する方向である横方向(底壁部22の面内方向)への移動を制止する制止部30を更に備えている。本実施形態では、制止部30は、カセット51の横方向への移動を制止する第1の制止部31と、カセット51の上下方向への移動を制止する第2の制止部41とを有する。なお、第1の制止部31によりカセット51の上下方向への移動も制止できる場合には、制止部30は、第1の制止部31のみを有していてもよい。同様に、第2の制止部41によりカセット51の横方向の移動も制止できる場合には、制止部30は、第2の制止部41のみを有していてもよい。 The cleaning bath 21 is arranged in the vertical direction (intersecting direction with respect to the in-plane direction of the bottom wall portion 22) of the cassette 51 immersed in the processing liquid, and in the horizontal direction (the in-plane direction of the bottom wall portion 22) intersecting with the vertical direction. ) Is further provided. In the present embodiment, the restricting unit 30 includes a first restricting unit 31 that restricts the lateral movement of the cassette 51 and a second restricting unit 41 that restricts the vertical movement of the cassette 51. Note that, in the case where the movement of the cassette 51 in the vertical direction can also be stopped by the first stopping portion 31, the stopping portion 30 may have only the first stopping portion 31. Similarly, when the movement of the cassette 51 in the horizontal direction can be suppressed by the second restraining portion 41, the restraining portion 30 may include only the second restraining portion 41.
 本実施形態では、第1の制止部31は、図2に示すように、処理液に浸漬されたカセット51(筒状体52)の外側周囲において周方向に並ぶように設けられた複数(本実施形態では、4つ)の第1の制止片32を含む。4つの第1の制止片32は、洗浄浴槽21の底壁部22上に設けられていて、筒状体52の下端面の外形ラインに対応した仮想の四角形35の角部に位置する。各第1の制止片32は、筒軸方向延設部52cの各角部(カセット51の外側表面)に合致する合致面32aと、筒状体52の下端面における角部近傍を受ける受け面32bとを有している。 In the present embodiment, as shown in FIG. 2, the plurality of first stoppers 31 are provided so as to be arranged in a circumferential direction around the outer periphery of the cassette 51 (tubular body 52) immersed in the processing liquid. In the embodiment, four) first stopping pieces 32 are included. The four first stopping pieces 32 are provided on the bottom wall 22 of the washing tub 21, and are located at corners of a virtual rectangle 35 corresponding to the outer shape line of the lower end surface of the tubular body 52. Each first stopping piece 32 has a mating surface 32a that matches each corner (the outer surface of the cassette 51) of the cylindrical axially extending portion 52c, and a receiving surface that receives the vicinity of the corner at the lower end surface of the cylindrical body 52. 32b.
 筒状体52の下端面が受け面32bに接触しているとき、筒状体52の上端面の高さ位置は、処理液の液面の高さ位置よりも低い。受け面32bは、筒状体52の下端面と洗浄浴槽21の底壁部22との間に隙間を形成して、筒状体52の内側に対する処理液の流出入を促進させる役割を有する。なお、受け面32bがなくて、筒状体52の下端面が底壁部22に直に接触していたとしても、実際には、その間に僅かな隙間が生じ、筒状体52の内側に対する処理液の流出入がなされる。但し、筒状体52が第2の制止部41により押圧される場合、筒状体52を長期に亘って使用すると、筒状体52の変形により隙間がなくなる可能性があるので、受け面32bを設けることが好ましい。 と き When the lower end surface of the cylindrical body 52 is in contact with the receiving surface 32b, the height position of the upper end surface of the cylindrical body 52 is lower than the height position of the processing liquid level. The receiving surface 32b has a role of forming a gap between the lower end surface of the cylindrical body 52 and the bottom wall 22 of the cleaning bath 21 to promote the inflow and outflow of the processing liquid to the inside of the cylindrical body 52. In addition, even if the lower end surface of the cylindrical body 52 is in direct contact with the bottom wall portion 22 without the receiving surface 32b, a slight gap is actually generated therebetween, and the inner wall of the cylindrical body 52 is Inflow and outflow of the processing liquid are performed. However, in the case where the cylindrical body 52 is pressed by the second stopping portion 41, if the cylindrical body 52 is used for a long period of time, there is a possibility that a gap may be eliminated due to the deformation of the cylindrical body 52. Is preferably provided.
 4つの第1の制止片32は、第1の制止片32を、処理液に浸漬されたカセット51に対して離接可能に移動させるモータ等の移動機構36(図3参照)によって、移動させられる。本実施形態では、移動機構36は、底壁部22の下面に設けられていて、例えば、仮想の四角形35の各対角線上に位置する各組の2つの第1の制止片32同士を、互いに離接するように、底壁部22上で当該対角線に沿って移動させる。なお、移動機構36の詳細構成については省略する。 The four first stopping pieces 32 are moved by a moving mechanism 36 (see FIG. 3) such as a motor that moves the first stopping pieces 32 so as to be detachable from and attached to the cassette 51 immersed in the processing liquid. Can be In the present embodiment, the moving mechanism 36 is provided on the lower surface of the bottom wall portion 22 and, for example, connects the two first stopping pieces 32 of each set located on each diagonal line of the virtual square 35 to each other. It is moved along the diagonal on the bottom wall portion 22 so as to be separated. The detailed configuration of the moving mechanism 36 is omitted.
 4つの第1の制止片32は、移動機構36によってカセット51に近接して合致面32aが筒軸方向延設部52cの4つの角部にそれぞれ当接して筒状体52をその内側に押圧する。これにより、カセット51の横方向への移動が制止される。4つの第1の制止片32の筒状体52に対する押圧力によっては、4つの第1の制止片32によりカセット51の上下方向への移動も制止することが可能になる。一方、カセット51を洗浄浴槽21に対して出し入れする際には、4つの第1の制止片32が移動機構36によってカセット51から離れる。このとき、各第1の制止片32は、その受け面32bが筒状体52の下端面から外れないような量だけ移動する。これにより、カセット51の洗浄浴槽21に対する出し入れが容易になる。 The four first stopping pieces 32 are brought close to the cassette 51 by the moving mechanism 36, and the matching surfaces 32a abut against the four corners of the cylindrical axially extending portion 52c to press the cylindrical body 52 inward. I do. As a result, the movement of the cassette 51 in the lateral direction is suppressed. Depending on the pressing force of the four first blocking pieces 32 against the cylindrical body 52, the movement of the cassette 51 in the vertical direction can be restrained by the four first blocking pieces 32. On the other hand, when the cassette 51 is moved in and out of the cleaning bath 21, the four first stopping pieces 32 are separated from the cassette 51 by the moving mechanism 36. At this time, each first stopping piece 32 moves by such an amount that the receiving surface 32b does not come off the lower end surface of the tubular body 52. Thereby, the cassette 51 can be easily taken in and out of the cleaning bath 21.
 なお、第1の制止片32は、必ずしも移動可能に構成されている必要はなく、底壁部22に固定されていてもよい。この場合、第1の制止片32は、筒状体52の下端面を受け面32bに当接させた状態で合致面32aが筒軸方向延設部52cの角部に略当接するような位置に設けられる。また、複数の第1の制止片32のうちの一部の第1の制止片32のみを移動可能に構成してもよい。 The first stopper 32 does not necessarily need to be configured to be movable, but may be fixed to the bottom wall 22. In this case, the first stopping piece 32 is positioned such that the lower surface of the cylindrical body 52 is in contact with the receiving surface 32b and the mating surface 32a substantially abuts the corner of the cylindrical axially extending portion 52c. Is provided. Further, only a part of the plurality of first restraining pieces 32 may be configured to be movable.
 さらに、第1の制止片32は、底壁部22に設けられる代わりに、筒状側壁部23に支持部材を介して設けられていてもよい。この場合、第1の制止片32が、その支持部材を介して、処理液に浸漬されたカセット51に対して離接可能に構成されてもよい。 Furthermore, instead of being provided on the bottom wall 22, the first blocking piece 32 may be provided on the cylindrical side wall 23 via a support member. In this case, the first blocking piece 32 may be configured to be able to be separated from and connected to the cassette 51 immersed in the processing liquid via the support member.
 第1の制止片32の数、カセット51に対して離接可能に構成される第1の制止片32の数、及び、第1の制止片32を移動可能に構成した場合の移動方向は、筒状体52の断面形状により異なり、カセット51の横方向への移動を制止できるように適宜に設定される。 The number of the first stoppers 32, the number of the first stoppers 32 configured to be detachable from the cassette 51, and the moving direction when the first stoppers 32 are configured to be movable, It differs depending on the cross-sectional shape of the cylindrical body 52, and is appropriately set so that the lateral movement of the cassette 51 can be restrained.
 また、上側から見た洗浄浴槽21に対するカセット51の位置(第1の制止片32の位置)は、通常は、洗浄浴槽21の中央部とされるが、洗浄浴槽21のどこであってもよい。 The position of the cassette 51 with respect to the washing tub 21 as viewed from above (the position of the first blocking piece 32) is usually the center of the washing tub 21, but may be anywhere in the washing tub 21.
 洗浄浴槽21は、筒状側壁部23に対して回動機構25を介して回動可能に装着された天面部24を更に備えている。天面部24は、スタジアム形状の2つの直線23aに直交する方向において、2つの分割部24aに分割されている。各分割部24aの直線23a側の端部には、ヒンジ軸24bが、直線23aが延びる方向に貫通するように設けられている。ヒンジ軸24bは、分割部24aに固定されているとともに、筒状側壁部23の上端における直線23aに対応する部分に設けられたヒンジ軸支持部23cに回動可能に支持されている。2つの分割部24aは、両開きのドアのように、それぞれのヒンジ軸24bの回動によって回動して、洗浄浴槽21の上端の開口を開閉する。回動機構25は、詳細な構成は省略するが、例えば、2つの分割部24aのヒンジ軸24bに対して減速機構を介して連結された1つのモータを有し、このモータの回転により2つの分割部24aのヒンジ軸24bが互いに逆向きに回動して、2つの分割部24aが回動する。なお、本実施形態では、2つの分割部24aは、洗浄浴槽21の上端の開口の全ての部分を覆っていないが、開口の全ての部分を覆うことも可能である。 The washing tub 21 further includes a top surface portion 24 rotatably mounted on the cylindrical side wall portion 23 via a rotation mechanism 25. The top surface portion 24 is divided into two divided portions 24a in a direction orthogonal to the two stadium-shaped straight lines 23a. A hinge shaft 24b is provided at an end of the divided portion 24a on the side of the straight line 23a so as to penetrate in the direction in which the straight line 23a extends. The hinge shaft 24b is fixed to the dividing portion 24a, and is rotatably supported by a hinge shaft support portion 23c provided at a portion corresponding to the straight line 23a at the upper end of the cylindrical side wall portion 23. The two divided portions 24a are rotated by the rotation of respective hinge shafts 24b to open and close an opening at the upper end of the washing tub 21, like a double door. Although a detailed configuration is omitted, the rotation mechanism 25 has, for example, one motor connected to the hinge shaft 24b of the two divided portions 24a via a speed reduction mechanism. The hinge shafts 24b of the divided portions 24a rotate in opposite directions, and the two divided portions 24a rotate. In the present embodiment, the two divided portions 24a do not cover all the portions of the opening at the upper end of the cleaning tub 21, but can also cover all the portions of the opening.
 第2の制止部41は、底壁部22に対向しかつ底壁部22との間隔が変化するように設けられた第2の制止片42を含む。具体的に、図1及び図3に示すように、第2の制止片42は、天面部24における2つの分割部24aの先端部(ヒンジ軸24bとは反対側の端部)にそれぞれ2つずつ(合計4つ)設けられていて、2つの分割部24aの回動機構25を介した回動に伴って、底壁部22との間隔が変化するように構成されている。 The second restraining portion 41 includes a second restraining piece 42 provided so as to face the bottom wall portion 22 and to change the distance from the bottom wall portion 22. Specifically, as shown in FIG. 1 and FIG. 3, two second stopping pieces 42 are respectively provided at the distal ends (ends opposite to the hinge shaft 24 b) of the two divided portions 24 a on the top surface portion 24. (A total of four), and the interval between the two divided portions 24a and the bottom wall portion 22 is changed with the rotation of the two divided portions 24a via the rotation mechanism 25.
 回動機構25によって2つの分割部24aが洗浄浴槽21の上端の開口を閉じたときに、4つの第2の制止片41が、筒状体52の上端面における短辺に対応する部分に当接して筒状体52を下向きに押圧する。これにより、カセット51の上下方向への移動が制止される。4つの第2の制止片42の筒状体52に対する押圧力によっては、第2の制止片42によりカセット51の横方向への移動も制止することが可能になる。各第2の制止片42は、ゴム等の弾性部材で構成してもよい。なお、第2の制止片41が筒状体52を押圧する部分は、筒状体52の上端面のどこであってもよい。 When the two divided portions 24 a close the opening at the upper end of the washing tub 21 by the rotating mechanism 25, the four second stopping pieces 41 contact the portion corresponding to the short side of the upper end surface of the tubular body 52. Then, the cylindrical body 52 is pressed downward. As a result, the movement of the cassette 51 in the vertical direction is restricted. Depending on the pressing force of the four second blocking pieces 42 against the cylindrical body 52, the movement of the cassette 51 in the horizontal direction can be restrained by the second blocking pieces 42. Each second stopping piece 42 may be formed of an elastic member such as rubber. The portion where the second stopper 41 presses the tubular body 52 may be anywhere on the upper end surface of the tubular body 52.
 洗浄浴槽21の筒状側壁部23の外側面には、洗浄浴槽21に貯留された処理液に超音波を発信する超音波発信器61が取り付けられている。超音波発信器61の取付位置は、筒状側壁部23の外側面において周方向のどの位置でもよいが、取り付け易さを考慮して、筒状側壁部23の外側面における平面の部分(スタジアム形状の直線23aに対応する部分)であることが好ましい。本実施形態では、超音波発信器61から発信される超音波の軸線方向は、水平方向である。 超 An ultrasonic transmitter 61 for transmitting ultrasonic waves to the treatment liquid stored in the cleaning bath 21 is attached to the outer surface of the cylindrical side wall 23 of the cleaning bath 21. The mounting position of the ultrasonic transmitter 61 may be any position in the circumferential direction on the outer surface of the cylindrical side wall portion 23. However, in consideration of ease of mounting, a flat portion (stadium) on the outer surface of the cylindrical side wall portion 23 is taken into consideration. (Corresponding to the straight line 23a of the shape). In the present embodiment, the axis direction of the ultrasonic waves transmitted from the ultrasonic transmitter 61 is the horizontal direction.
 超音波発信器61から発信された超音波は、洗浄浴槽21の筒状側壁部23の内側面及び筒状体52の外周面52aで反射される。この反射をいくら繰り返しても、洗浄浴槽21のスタジアム形状によって、超音波発信器61から発信された超音波は、その発信が開始された位置でその開始されたときと同じ発信角度になるように戻ることはない。すなわち、超音波の軌道は、周期的な軌道にはならず、いわゆるカオス的な軌道となる。このことは、カセット51がどのような形状であっても成り立つ。この結果、処理液中に定在波が生じることはなく、処理液中に均一な音場が形成される。このような均一な音場が形成された処理液により、半導体基板57が超音波処理される。 The ultrasonic wave transmitted from the ultrasonic wave transmitter 61 is reflected on the inner side surface of the cylindrical side wall portion 23 of the cleaning bath 21 and the outer peripheral surface 52 a of the cylindrical body 52. No matter how many times this reflection is repeated, the ultrasonic wave transmitted from the ultrasonic wave transmitter 61 will have the same transmission angle at the position where the transmission was started as at the time when the transmission was started due to the stadium shape of the washing tub 21. Will not return. That is, the trajectory of the ultrasonic wave is not a periodic trajectory, but a so-called chaotic trajectory. This is true regardless of the shape of the cassette 51. As a result, no standing wave is generated in the processing liquid, and a uniform sound field is formed in the processing liquid. The semiconductor substrate 57 is ultrasonically treated with the treatment liquid in which such a uniform sound field is formed.
 したがって、本実施形態では、第1の制止片32及び第2の制止片42によりカセット51の上下方向及び横方向への移動が制止されているとともに、洗浄浴槽21の筒状側壁部23の内側面が、処理液中に定在波が生じないようなスタジアム形状とされているので、半導体基板57の超音波処理が良好に行われる。また、処理液中に定在波が生じないことから、厚さが薄い、太陽電池10用の半導体基板57を超音波処理しても、半導体基板57にダメージを与えることがない。これにより、シリコンのダングリングボンドによる太陽電池10の性能低下が抑制される。 Therefore, in the present embodiment, the movement of the cassette 51 in the vertical and horizontal directions is restricted by the first and second restricting pieces 32 and 42, and the inside of the cylindrical side wall 23 of the cleaning bath 21 is restricted. Since the side surface has a stadium shape such that a standing wave does not occur in the processing liquid, the ultrasonic processing of the semiconductor substrate 57 is performed favorably. Further, since no standing wave is generated in the processing liquid, even if the semiconductor substrate 57 for the solar cell 10 having a small thickness is subjected to ultrasonic treatment, the semiconductor substrate 57 is not damaged. This suppresses the performance degradation of the solar cell 10 due to the dangling bond of silicon.
 筒状側壁部23の内側面の形状は、スタジアム形状には限られない。カセット51の形状に関係なく、超音波の軌道がカオス的な軌道になるように、筒状側壁部23の筒軸方向に直交する断面において、筒状側壁部23の内側面の周方向の一部が曲線とされかつ残部が直線とされればよい。この場合、筒状側壁部23の筒軸方向に直交する断面において、筒状側壁部23の内側面における曲線は、単数又は複数設けられていて、円弧状又は弓状の曲線であることが好ましい。そして、少なくとも1つの円弧状又は弓状の曲線の曲率中心は、筒状側壁部23の内側に位置していてもよく、筒状側壁部23の外側に位置していてもよい。或いは、複数の円弧状又は弓状の曲線のうちの一部の曲線の曲率中心が、筒状側壁部23の内側に位置し、残りの曲線の曲率中心が、筒状側壁部23の外側に位置していてもよい。 形状 The shape of the inner side surface of the cylindrical side wall 23 is not limited to the stadium shape. Irrespective of the shape of the cassette 51, in the cross section orthogonal to the cylinder axis direction of the cylindrical side wall 23, one of the circumferential directions of the inner side surface of the cylindrical side wall 23 is set so that the ultrasonic trajectory becomes a chaotic trajectory. What is necessary is just to make a part into a curve and to make the remainder straight. In this case, in the cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion 23, one or more curves on the inner side surface of the cylindrical side wall portion 23 are preferably provided, and are preferably arc-shaped or arc-shaped curves. . The center of curvature of the at least one arc-shaped or arc-shaped curve may be located inside the cylindrical side wall 23 or may be located outside the cylindrical side wall 23. Alternatively, the center of curvature of some of the plurality of arc-shaped or arc-shaped curves is located inside the cylindrical side wall portion 23, and the center of curvature of the remaining curves is outside the cylindrical side wall portion 23. It may be located.
 具体的には、図14に示すように、筒状側壁部23の筒軸方向に直交する断面において、筒状側壁部23の内側面が略D字状に形成されていてもよい。この場合、筒状側壁部23の内側面の曲線は、曲率中心が筒状側壁部23の内側に位置する円弧状又は弓状の曲線である。 Specifically, as shown in FIG. 14, the inner side surface of the cylindrical side wall portion 23 may be formed in a substantially D-shape in a cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion 23. In this case, the curve on the inner side surface of the cylindrical side wall portion 23 is an arc-shaped or arcuate curve whose center of curvature is located inside the cylindrical side wall portion 23.
 或いは、筒状側壁部23の筒軸方向に直交する断面において、筒状側壁部23の内側面が、図15~図19のいずれか1つの形状に形成されていてもよい。図17の形状では、筒状側壁部23の内側面の曲線は、2つあって、弓状とされ、その1つの弓状の曲線の曲率中心が筒状側壁部23の内側に位置する一方、もう1つの弓状の曲線の曲率中心が筒状側壁部23の外側に位置する。なお、図14~図19では、第1の制止片32の記載は省略している。 Alternatively, in a cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion 23, the inner side surface of the cylindrical side wall portion 23 may be formed in any one of the shapes shown in FIGS. In the shape of FIG. 17, there are two curved surfaces on the inner surface of the cylindrical side wall portion 23, and the curved surface has an arc shape, and the center of curvature of the one curved line is located inside the cylindrical side wall portion 23. The center of curvature of another arcuate curve is located outside the cylindrical side wall 23. 14 to 19, the illustration of the first stop piece 32 is omitted.
 本発明は、前記実施形態に限られるものではなく、請求の範囲の主旨を逸脱しない範囲で代用が可能である。 The present invention is not limited to the above embodiment, and may be substituted without departing from the scope of the claims.
 例えば、前記実施形態では、洗浄浴槽21により太陽電池10用の半導体基板57を超音波処理したが、これには限らず、太陽電池以外の用途の半導体基板を超音波処理する場合にも、洗浄浴槽21を用いることができる。 For example, in the embodiment described above, the semiconductor substrate 57 for the solar cell 10 is subjected to the ultrasonic treatment in the cleaning bath 21. However, the present invention is not limited to this. A bathtub 21 can be used.
 上述の実施形態は単なる例示に過ぎず、本発明の範囲を限定的に解釈してはならない。本発明の範囲は請求の範囲によって定義され、請求の範囲の均等範囲に属する変形や変更は、全て本発明の範囲内のものである。 The above embodiments are merely examples, and the scope of the present invention should not be limitedly interpreted. The scope of the present invention is defined by the claims, and all modifications and changes that fall within the equivalent scope of the claims are within the scope of the present invention.
  21  洗浄浴槽
  22  底壁部
  23  筒状側壁部
  24  天面部
  30  制止部
  31  第1の制止部
  32  第1の制止片
  41  第2の制止部
  42  第2の制止片
  51  カセット
  57  半導体基板
DESCRIPTION OF SYMBOLS 21 Cleaning bath 22 Bottom wall part 23 Cylindrical side wall part 24 Top surface part 30 Restriction part 31 1st restriction part 32 1st restriction piece 41 2nd restriction part 42 2nd restriction piece 51 Cassette 57 Semiconductor substrate

Claims (12)

  1.  カセットに保持された半導体基板を、前記カセットと共に、貯留する処理液に浸漬させた状態で、前記半導体基板を超音波処理する洗浄浴槽であって、
     底壁部と、
     前記底壁部から立ち上がり、内部に前記処理液を貯留する筒状側壁部と、
     前記処理液に浸漬された前記カセットの、前記底壁部の面内方向及び前記面内方向に対する交差方向への移動を制止する制止部とを備え、
     前記筒状側壁部の筒軸方向に直交する断面において、前記筒状側壁部の内側面の周方向の一部が曲線とされかつ残部が直線とされている、洗浄浴槽。
    A cleaning bath for ultrasonically treating the semiconductor substrate while the semiconductor substrate held in the cassette is immersed in the processing liquid to be stored together with the cassette,
    A bottom wall,
    A cylindrical side wall that rises from the bottom wall and stores the processing liquid therein;
    The cassette immersed in the treatment liquid, comprising:
    A washing tub in which, in a cross section orthogonal to a cylinder axis direction of the cylindrical side wall portion, a part of the inner side surface of the cylindrical side wall portion in the circumferential direction is curved and the remaining portion is straight.
  2.  前記制止部は、前記カセットの前記面内方向への移動を制止する第1の制止部と、前記カセットの前記交差方向への移動を制止する第2の制止部とを有する、請求項1に記載の洗浄浴槽。 2. The stopping device according to claim 1, wherein the stopping unit includes a first stopping unit that stops movement of the cassette in the in-plane direction, and a second stopping unit that stops movement of the cassette in the cross direction. 3. Wash tub as described.
  3.  前記第1の制止部は、前記処理液に浸漬された前記カセットの外側周囲において周方向に並ぶように設けられた複数の第1の制止片を含む、請求項2に記載の洗浄浴槽。 The cleaning bath tub according to claim 2, wherein the first stopping portion includes a plurality of first stopping pieces provided so as to be arranged in a circumferential direction around the outside of the cassette immersed in the processing liquid.
  4.  前記複数の第1の制止片のうちの少なくとも一部が、前記処理液に浸漬された前記カセットに対して離接可能に構成されている、請求項3に記載の洗浄浴槽。 4. The cleaning bath according to claim 3, wherein at least a part of the plurality of first stopper pieces is configured to be detachable from the cassette immersed in the processing liquid. 5.
  5.  前記複数の第1の制止片は、前記カセットの表面に合致する合致面を有する、請求項3又は4に記載の洗浄浴槽。 The washing tub according to claim 3 or 4, wherein the plurality of first stopping pieces have a matching surface that matches a surface of the cassette.
  6.  前記第2の制止部は、前記底壁部に対向しかつ前記底壁部との間隔が変化するように設けられた第2の制止片を含む、請求項2~5のいずれか1項に記載の洗浄浴槽。 The device according to any one of claims 2 to 5, wherein the second restraining portion includes a second restraining piece provided to face the bottom wall portion and to change a distance from the bottom wall portion. Wash tub as described.
  7.  前記筒状側壁部に対して回動機構を介して回動可能に装着された天面部を更に備え、
     前記第2の制止片は、前記天面部に設けられていて、前記天面部の前記回動機構を介した回動に伴って、前記底壁部との間隔が変化するように構成されている、請求項6に記載の洗浄浴槽。
    A top surface portion rotatably mounted to the cylindrical side wall portion via a rotation mechanism,
    The second stopping piece is provided on the top surface, and is configured such that a distance from the bottom wall changes with rotation of the top surface via the rotation mechanism. A washing tub according to claim 6.
  8.  前記筒状側壁部の筒軸方向に直交する断面において、前記筒状側壁部の内側面における曲線は、単数又は複数設けられていて、円弧状又は弓状の曲線である、請求項1~7のいずれか1項に記載の洗浄浴槽。 8. A cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion, wherein one or more curves on the inner side surface of the cylindrical side wall portion are provided and are arc-shaped or arcuate curves. The washing tub according to any one of the above.
  9.  少なくとも1つの前記円弧状又は弓状の曲線の曲率中心は、前記筒状側壁部の内側に位置する、請求項8に記載の洗浄浴槽。 The cleaning tub according to claim 8, wherein the center of curvature of the at least one arc-shaped or arc-shaped curve is located inside the cylindrical side wall.
  10.  少なくとも1つの前記円弧状又は弓状の曲線の曲率中心は、前記筒状側壁部の外側に位置する、請求項8に記載の洗浄浴槽。 The cleaning tub according to claim 8, wherein the center of curvature of the at least one arc-shaped or arc-shaped curve is located outside the cylindrical side wall.
  11.  前記円弧状又は弓状の曲線は複数設けられており、
     前記複数の円弧状又は弓状の曲線のうちの一部の曲線の曲率中心は、前記筒状側壁部の内側に位置し、
     残りの曲線の曲率中心は、前記筒状側壁部の外側に位置する、請求項8に記載の洗浄浴槽。
    A plurality of arc-shaped or arc-shaped curves are provided,
    The center of curvature of some of the plurality of arc-shaped or arcuate curves is located inside the cylindrical side wall portion,
    9. The washing tub according to claim 8, wherein the center of curvature of the remaining curve is located outside the cylindrical side wall.
  12.  前記筒状側壁部の筒軸方向に直交する断面において、前記筒状側壁部の内側面は、互いに平行な2つの直線と、前記2つの直線の一側端部同士及び他側端部同士を連結する、曲率中心が前記筒状側壁部の内側に位置する円弧状又は弓状の曲線とを含む形状、又は、略D字状に形成されている、請求項8又は9に記載の洗浄浴槽。 In a cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion, the inner side surface of the cylindrical side wall portion is formed by two straight lines parallel to each other, and one end portions of the two straight lines and other end portions. The washing tub according to claim 8 or 9, wherein the shape of the washing tub is such that the center of curvature is connected to an arc-shaped or arc-shaped curve positioned inside the cylindrical side wall portion, or substantially D-shaped. .
PCT/JP2019/027758 2018-08-02 2019-07-12 Cleaning bath WO2020026770A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2020533392A JP7053838B2 (en) 2018-08-02 2019-07-12 Wash tub
CN201980050101.0A CN112514033B (en) 2018-08-02 2019-07-12 Bath for cleaning

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-145634 2018-08-02
JP2018145634 2018-08-02

Publications (1)

Publication Number Publication Date
WO2020026770A1 true WO2020026770A1 (en) 2020-02-06

Family

ID=69231698

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/027758 WO2020026770A1 (en) 2018-08-02 2019-07-12 Cleaning bath

Country Status (3)

Country Link
JP (1) JP7053838B2 (en)
CN (1) CN112514033B (en)
WO (1) WO2020026770A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6332680U (en) * 1986-08-12 1988-03-02
JPS6421786U (en) * 1987-07-30 1989-02-03
JPH03222419A (en) * 1990-01-29 1991-10-01 Kokusai Denki Erutetsuku:Kk Supersonic cleaning device
JPH11347508A (en) * 1998-06-10 1999-12-21 Twinbird Corp Cleaning attachment of cleaning machine
JP2012104682A (en) * 2010-11-11 2012-05-31 Seiko Epson Corp Cleaning apparatus
WO2014038277A1 (en) * 2012-09-06 2014-03-13 三菱電機株式会社 Solar cell manufacturing apparatus and solar cell manufacturing method using same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2696017B2 (en) * 1991-10-09 1998-01-14 三菱電機株式会社 Cleaning device and cleaning method
US6523557B2 (en) * 2000-12-13 2003-02-25 Imtec Acculine, Inc. Megasonic bath
JP2003257918A (en) * 2002-02-27 2003-09-12 Seiko Epson Corp Washed-object holder and ultrasonic washing apparatus
JP2009039604A (en) * 2007-08-06 2009-02-26 Fujitsu Ltd Cleaning device, washing tank, cleaning method, and washing control program
CN206500403U (en) * 2017-01-19 2017-09-19 昆山国显光电有限公司 Ultrasonic cleaner
CN206689136U (en) * 2017-02-13 2017-12-01 深圳市佳洁农业投资发展有限公司 A kind of supersonic wave cleaning machine with cleaning basket

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6332680U (en) * 1986-08-12 1988-03-02
JPS6421786U (en) * 1987-07-30 1989-02-03
JPH03222419A (en) * 1990-01-29 1991-10-01 Kokusai Denki Erutetsuku:Kk Supersonic cleaning device
JPH11347508A (en) * 1998-06-10 1999-12-21 Twinbird Corp Cleaning attachment of cleaning machine
JP2012104682A (en) * 2010-11-11 2012-05-31 Seiko Epson Corp Cleaning apparatus
WO2014038277A1 (en) * 2012-09-06 2014-03-13 三菱電機株式会社 Solar cell manufacturing apparatus and solar cell manufacturing method using same

Also Published As

Publication number Publication date
JPWO2020026770A1 (en) 2021-08-02
CN112514033A (en) 2021-03-16
JP7053838B2 (en) 2022-04-12
CN112514033B (en) 2024-03-15

Similar Documents

Publication Publication Date Title
US7858427B2 (en) Crystalline silicon solar cells on low purity substrate
WO2012036146A1 (en) Crystalline solar cell and manufacturing method therefor
JP6254343B2 (en) Photoelectric conversion device
JP2013239694A (en) Back junction solar cell with tunnel oxide
CN112088436B (en) Method for manufacturing solar cell and carrying device used in method
US9397245B2 (en) Photoelectric conversion device and manufacturing method thereof
US8569098B2 (en) Method for manufacturing photoelectric conversion device
WO2014050304A1 (en) Photoelectric conversion element and method for manufacturing same
US20150162477A1 (en) Photoelectric conversion device
US20110308582A1 (en) Photoelectric conversion device and manufacturning method thereof
WO2019163647A1 (en) Method for producing solar cell
US20100224238A1 (en) Photovoltaic cell comprising an mis-type tunnel diode
US9076909B2 (en) Photoelectric conversion device and method for manufacturing the same
WO2020026770A1 (en) Cleaning bath
JP7281444B2 (en) Solar cell manufacturing method
US20110308600A1 (en) Photoelectric conversion device and method for manufacturing the same
WO2020026771A1 (en) Cassette and cleaning bath set
WO2019181834A1 (en) Method for producing solar cell, and solar cell
JP7183245B2 (en) Solar cell manufacturing method
US20110308585A1 (en) Dual transparent conductive material layer for improved performance of photovoltaic devices
KR20120047502A (en) Solar cell and manufacturing method thereof
CN111742416A (en) Method for manufacturing solar cell
JP7353865B2 (en) How to manufacture solar cells
KR101084650B1 (en) Solar cell crystallized using microcrystalline semiconductor layer and method for fabricating the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19845518

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020533392

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19845518

Country of ref document: EP

Kind code of ref document: A1