WO2020026770A1 - Bain de nettoyage - Google Patents

Bain de nettoyage Download PDF

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Publication number
WO2020026770A1
WO2020026770A1 PCT/JP2019/027758 JP2019027758W WO2020026770A1 WO 2020026770 A1 WO2020026770 A1 WO 2020026770A1 JP 2019027758 W JP2019027758 W JP 2019027758W WO 2020026770 A1 WO2020026770 A1 WO 2020026770A1
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WIPO (PCT)
Prior art keywords
side wall
wall portion
cylindrical side
cassette
semiconductor layer
Prior art date
Application number
PCT/JP2019/027758
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English (en)
Japanese (ja)
Inventor
真悟 渡邉
崇 口山
Original Assignee
株式会社カネカ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 株式会社カネカ filed Critical 株式会社カネカ
Priority to CN201980050101.0A priority Critical patent/CN112514033B/zh
Priority to JP2020533392A priority patent/JP7053838B2/ja
Publication of WO2020026770A1 publication Critical patent/WO2020026770A1/fr

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B08—CLEANING
    • B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B3/00—Cleaning by methods involving the use or presence of liquid or steam
    • B08B3/04—Cleaning involving contact with liquid
    • B08B3/10—Cleaning involving contact with liquid with additional treatment of the liquid or of the object being cleaned, e.g. by heat, by electricity or by vibration
    • B08B3/12—Cleaning involving contact with liquid with additional treatment of the liquid or of the object being cleaned, e.g. by heat, by electricity or by vibration by sonic or ultrasonic vibrations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting

Definitions

  • the technology disclosed in this specification relates to a cleaning bath for ultrasonically treating a semiconductor substrate.
  • Patent Literature 1 a substrate (in Patent Literature 1, a transparent substrate of a liquid crystal display element) is held in a cassette, and the substrate held in the cassette is immersed together with the cassette in a processing solution in a cleaning bath. The substrate is subjected to ultrasonic treatment.
  • the patterning step includes a thin film peeling step.
  • the yield of the step is dramatically improved.
  • the cassette immersed in the processing solution in the cleaning bath is usually only placed on the bottom wall of the cleaning bath. For this reason, the cassette may move by being vibrated by the ultrasonic waves in the cleaning bath, and the ultrasonic processing may not be performed properly.
  • a standing wave may be generated in the processing liquid in the cleaning bath depending on the shape of the cleaning bath and the cassette.
  • unevenness in the sound pressure due to the standing wave causes uneven cleaning, and particularly, a semiconductor substrate having a small thickness (for example, a semiconductor substrate for a solar cell) has an antinode portion (a high sound pressure) of the standing wave. Part) and is easily damaged.
  • the technology disclosed herein has been made in view of such a point, and an object thereof is to provide a cleaning bath that can favorably perform ultrasonic treatment of a semiconductor substrate regardless of the shape of a cassette. is there.
  • the cleaning bath is a cleaning bath for ultrasonically treating the semiconductor substrate in a state where the semiconductor substrate held in the cassette is immersed in the processing liquid to be stored together with the cassette.
  • a cylindrical side wall that rises from the wall and stores the processing liquid therein, and the cassette immersed in the processing liquid moves in the in-plane direction of the bottom wall and in the direction crossing the in-plane direction.
  • a stopping portion for stopping wherein in the cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion, a part of the inner side surface of the cylindrical side wall portion in the circumferential direction is curved and the remaining portion is straight. It is.
  • the ultrasonic treatment of the semiconductor substrate is favorably performed regardless of the shape and the installation position of the cassette, and the semiconductor substrate having a small thickness (for example, a semiconductor substrate for a solar cell) is ultrasonically treated. Also, the semiconductor substrate is not damaged.
  • FIG. 3 is a plan view showing a cleaning tub according to an exemplary embodiment together with a cassette. It is sectional drawing which cut
  • FIG. 3 is a cross-sectional view taken along the line III-III of FIG. 1.
  • FIG. 3 is a perspective view showing a cassette holding semiconductor substrates.
  • FIG. 2 is a schematic sectional view partially showing a solar cell.
  • FIG. 4 is a bottom view showing the back principal surface of the crystal substrate constituting the solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 6 is a diagram corresponding to FIG. 5, illustrating one step of a method for manufacturing a solar cell.
  • FIG. 3 is a view corresponding to FIG. 2, showing another shape of the inner side surface of the cylindrical side wall portion.
  • FIG. 7 is a view corresponding to FIG.
  • FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion.
  • FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion.
  • FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion.
  • FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion.
  • FIG. 7 is a view corresponding to FIG. 2, showing still another shape of the inner side surface of the cylindrical side wall portion.
  • FIGS. 1-3 show a cleaning tub 21 according to an exemplary embodiment.
  • the cleaning bath 21 is provided with at least one (in the present embodiment, a plurality of) semiconductor substrates 57 (see FIG. 4) held in the cassette 51 immersed in the processing liquid to be stored together with the cassette 51, at least. This is for subjecting one (plural) semiconductor substrates 57 to ultrasonic treatment.
  • the semiconductor substrate 57 is a semiconductor substrate for the solar cell 10.
  • FIG. 3 the illustration of the semiconductor substrate 57 is omitted.
  • the solar cell 10 uses a crystal substrate 11 made of silicon (Si).
  • Crystal substrate 11 has two main surfaces 11S (11SU, 11SB) facing each other.
  • the main surface on which light is incident is referred to as a front main surface 11SU
  • the main surface on the opposite side is referred to as a back main surface 11SB.
  • the front-side main surface 11SU is a light-receiving side that is a side that more actively receives light than the back-side main surface 11SB
  • the back-side main surface 11SB is a side that does not actively receive light and is a non-light-receiving side.
  • the solar cell 10 is a so-called heterojunction crystalline silicon solar cell, and is a back-contact type (backside electrode type) solar cell in which an electrode layer is disposed on the back main surface 11SB.
  • the solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12 (12U, 12p, 12n), a conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 ( Transparent electrode layer 17 and metal electrode layer 18).
  • members individually corresponding to the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be given “p” or “n” at the end of the reference numerals.
  • Crystal substrate 11 may be a semiconductor substrate formed of single-crystal silicon or a semiconductor substrate (single-crystal silicon substrate) formed of polycrystalline silicon.
  • a single crystal silicon substrate will be described as an example.
  • the conductivity type of the crystal substrate 11 may be an n-type single crystal silicon substrate into which impurities (for example, phosphorus (P) atoms) for introducing electrons into silicon atoms have been introduced, and holes may be used for silicon atoms.
  • impurities for example, phosphorus (P) atoms
  • holes may be used for silicon atoms.
  • an impurity for example, a boron (B) atom
  • the crystal substrate 11 has a texture structure TX (concave) formed of peaks (convex) and valleys (concave) on the surfaces of the two main surfaces 11S. (A first texture structure).
  • the texture structure TX is formed, for example, by anisotropic etching using the difference between the etching rate of the (100) plane and the etching rate of the (111) plane of the crystal substrate 11. Can be formed.
  • the size of the irregularities in the texture structure TX can be defined, for example, by the number of vertices (mountains).
  • the range is preferably 50,000 / mm 2 or more and 100,000 / mm 2 or less, and in particular, 70,000 / mm 2 or more and 85,000 / mm 2 or less. Is preferably within the range.
  • the thickness of the crystal substrate 11 may be 250 ⁇ m or less.
  • the measurement direction when measuring the thickness of the crystal substrate 11 is a direction perpendicular to the average plane of the crystal substrate 11 (the average plane means a plane of the entire substrate that does not depend on the texture structure TX). Therefore, hereinafter, this vertical direction, that is, the direction in which the thickness is measured is referred to as the thickness direction (also the thickness direction of the semiconductor substrate 57).
  • the thickness of the crystal substrate 11 is preferably at least 50 ⁇ m, more preferably at least 70 ⁇ m.
  • the thickness of the crystal substrate 11 is determined by the unevenness of the front main surface 11SU and the rear main surface 11SB. It is represented by the distance between straight lines connecting the convex vertices (vertices facing each other in the thickness direction) in the structure.
  • the intrinsic semiconductor layer 12 (12U, 12p, 12n) covers both main surfaces 11S (11SU, 11SB) of the crystal substrate 11, thereby performing surface passivation while suppressing diffusion of impurities into the crystal substrate 11.
  • intrinsic (i-type) is not limited to complete intrinsic without conductive impurities, but includes “weak” containing a small amount of n-type impurities or p-type impurities as long as the silicon-based layer can function as an intrinsic layer. Also encompasses "n-type” or "weak p-type” substantially intrinsic layers.
  • the intrinsic semiconductor layer 12 (12U, 12p, 12n) is not essential, and may be appropriately formed as needed.
  • the material of the intrinsic semiconductor layer 12 is not particularly limited, but may be an amorphous silicon-based material, and may be a hydrogenated amorphous silicon-based thin film containing silicon and hydrogen (a-Si: H thin film). There may be.
  • amorphous used herein refers to a long-period, non-ordered structure, that is, a structure that is not only completely disordered but also has a short-period order.
  • the thickness of the intrinsic semiconductor layer 12 is not particularly limited, but may be 2 nm or more and 20 nm or less. When the thickness is 2 nm or more, the effect as a passivation layer for the crystal substrate 11 is enhanced, and when the thickness is 20 nm or less, a decrease in conversion characteristics caused by an increase in resistance can be suppressed.
  • the method of forming the intrinsic semiconductor layer 12 is not particularly limited, but a plasma enhanced chemical vapor deposition (CVD) method is used. According to this method, passivation of the substrate surface can be effectively performed while suppressing diffusion of impurities into single crystal silicon. In addition, in the case of the plasma CVD method, by changing the hydrogen concentration in the layer of the intrinsic semiconductor layer 12 in the thickness direction, it is possible to form an energy gap profile that is effective for carrier recovery.
  • CVD plasma enhanced chemical vapor deposition
  • the conditions for forming a thin film by the plasma CVD method include, for example, a substrate temperature of 100 ° C. to 300 ° C., a pressure of 20 Pa to 2600 Pa, and a high-frequency power density of 0.003 W / cm 2 to 0.5 W / cm 2 or less.
  • a silicon-containing gas such as monosilane (SiH 4 ) and disilane (Si 2 H 6 ), or a mixture of these gases with hydrogen (H 2 ) May be mixed gas.
  • a gas containing a different kind of element such as methane (CH 4 ), ammonia (NH 3 ), or monogermane (GeH 4 ) is added to the above gas, and silicon carbide (SiC), silicon nitride (SiN)
  • SiC silicon carbide
  • SiN silicon nitride
  • the energy gap of the thin film may be appropriately changed.
  • Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13n. As shown in FIG. 5, the p-type semiconductor layer 13p is formed on a part of the back-side main surface 11SB of the crystal substrate 11 via the intrinsic semiconductor layer 12p. The n-type semiconductor layer 13n is formed on another part of the back-side main surface of the crystal substrate 11 via the intrinsic semiconductor layer 12n. That is, the intrinsic semiconductor layer 12 is interposed between the p-type semiconductor layer 13p and the crystal substrate 11 and between the n-type semiconductor layer 13n and the crystal substrate 11 as an intermediate layer that plays a role of passivation.
  • Each thickness of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n is not particularly limited, but may be 2 nm or more and 20 nm or less.
  • the thickness is 2 nm or more, the effect as a passivation layer for the crystal substrate 11 is enhanced, and when the thickness is 20 nm or less, a decrease in conversion characteristics caused by an increase in resistance can be suppressed.
  • the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are arranged such that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are electrically separated from each other on the back main surface 11SB of the crystal substrate 11.
  • the width of the conductive type semiconductor layer 13 may be 50 ⁇ m or more and 3000 ⁇ m or less, and may be 80 ⁇ m or more and 800 ⁇ m or less (note that the width of the semiconductor layer and the width of an electrode layer described later are the same unless otherwise specified.
  • the length of a portion of each of the layered layers is intended to be, for example, the length in a direction perpendicular to the extending direction of the linear portion by patterning).
  • the width of the p-type semiconductor layer 13p may be smaller than that of the n-type semiconductor layer 13n.
  • the width of the p-type semiconductor layer 13p may be 0.5 to 0.9 times the width of the n-type semiconductor layer 13n, or 0.6 to 0.8 times. Is also good.
  • the p-type semiconductor layer 13p is a silicon layer to which a p-type dopant (boron or the like) is added, and may be formed of amorphous silicon from the viewpoint of suppressing impurity diffusion or suppressing series resistance.
  • the n-type semiconductor layer 13n is a silicon layer to which an n-type dopant (such as phosphorus) is added, and may be formed of an amorphous silicon layer, similarly to the p-type semiconductor layer 13p.
  • a silicon-containing gas such as monosilane (SiH 4 ) or disilane (Si 2 H 6 ), or a mixed gas of a silicon-based gas and hydrogen (H 2 ) may be used.
  • a dopant gas diborane (B 2 H 6 ) or the like can be used for forming the p-type semiconductor layer 13p, and phosphine (PH 3 ) or the like can be used for forming the n-type semiconductor layer.
  • a mixed gas obtained by diluting a dopant gas with a source gas may be used.
  • the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be compounded.
  • the low reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10.
  • the material of the low reflective layer 14 is not particularly limited as long as it is a light-transmitting material that transmits light.
  • silicon oxide (SiO x ), silicon nitride (SiN x ), zinc oxide (ZnO), or oxide Titanium (TiO x ) is exemplified.
  • the low reflective layer 14 may be coated with a resin material in which nanoparticles of an oxide such as zinc oxide or titanium oxide are dispersed.
  • the electrode layer 15 is formed so as to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, respectively, and is electrically connected to each conductive semiconductor layer 13. Thereby, the electrode layer 15 functions as a transport layer for guiding carriers generated in the p-type semiconductor layer 13p or the n-type semiconductor layer 13n.
  • the electrode layer 15 may be formed only of a highly conductive metal. Further, from the viewpoint of electrical connection with the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or from the viewpoint of suppressing the diffusion of atoms of the metal as the electrode material into the two semiconductor layers 13p and 13n, the transparent material is used.
  • the electrode layer 15 made of a conductive oxide may be provided between the metal electrode layer and the p-type semiconductor layer 13p and between the metal electrode layer and the n-type semiconductor layer 13n.
  • the electrode layer 15 formed of a transparent conductive oxide is referred to as a transparent electrode layer 17, and the metal electrode layer 15 is referred to as a metal electrode layer 18.
  • an electrode layer formed on the back of the comb in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n each having a comb shape. May be referred to as a bus bar portion, and an electrode layer formed on the comb teeth portion may be referred to as a finger portion.
  • the material of the transparent electrode layer 17 is not particularly limited.
  • the thickness of the transparent electrode layer 17 may be 20 nm or more and 200 nm or less.
  • a method for forming a transparent electrode layer suitable for this thickness for example, a physical vapor deposition (PVD) method such as a sputtering method, or a metal organic compound utilizing a reaction between an organometallic compound and oxygen or water is used.
  • PVD physical vapor deposition
  • MOCVD Metal-Organic Chemical Vapor Deposition
  • the material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver (Ag), copper (Cu), aluminum (Al), and nickel (Ni).
  • the thickness of the metal electrode layer 18 may be 1 ⁇ m or more and 80 ⁇ m or less.
  • a method for forming the metal electrode layer 18 having a suitable thickness a printing method in which a material paste is printed by inkjet printing or screen printing, or a plating method is used.
  • the present invention is not limited to this, and when a vacuum process is employed, a vapor deposition or sputtering method may be employed.
  • the width of the comb-tooth portion of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be substantially equal to the width of the metal electrode layer 18 formed on the comb-tooth portion.
  • the width of the metal electrode layer 18 may be smaller than the width of the comb teeth.
  • the width of the metal electrode layer 18 may be wider than the width of the comb portion as long as the configuration prevents leakage current between the metal electrode layers 18.
  • the passivation and conduction of each junction surface are performed in a state where the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low reflection layer 14, and the electrode layer 15 are stacked on the back main surface 11SB of the crystal substrate 11.
  • a predetermined annealing process is performed for the purpose of suppressing generation of defect levels at the type semiconductor layer 13 and the interface thereof, and crystallization of the transparent conductive oxide in the transparent electrode layer 17.
  • the annealing process according to the present embodiment includes, for example, an annealing process in which the crystal substrate 11 on which the above-described layers are formed is placed in an oven heated to 150 ° C. or more and 200 ° C. or less.
  • the atmosphere in the oven may be air, and if hydrogen or nitrogen is used as the atmosphere, more effective annealing can be performed.
  • the annealing may be an RTA (Rapid Thermal Annealing) process in which the crystal substrate 11 on which each layer is formed is irradiated with infrared rays by an infrared heater.
  • a crystal substrate 11 having a texture structure TX on each of a front main surface 11SU and a back main surface 11SB is prepared.
  • an intrinsic semiconductor layer 12U is formed on the front main surface 11SU of the crystal substrate 11.
  • the antireflection layer 14 is formed on the formed intrinsic semiconductor layer 12U.
  • silicon nitride (SiN x ) or silicon oxide (SiO x ) having a suitable light absorption coefficient and refractive index is used from the viewpoint of a light confinement effect of confining incident light.
  • an intrinsic semiconductor layer 12p using, for example, i-type amorphous silicon is formed on the back-side main surface 11SB of the crystal substrate 11.
  • a p-type semiconductor layer 13p is formed on the formed intrinsic semiconductor layer 12p.
  • p-type semiconductor layer 13p with intrinsic semiconductor layer 12p interposed is formed on back main surface 11SB, which is one main surface of crystal substrate 11.
  • a plurality of lift-off layers LF (first lift-off layer LF1 and second lift-off layer LF2) are formed on the formed p-type semiconductor layer 13p.
  • a first lift-off layer LF1 and a second lift-off layer LF2 containing silicon-based thin film materials having different densities are sequentially laminated and formed.
  • the first lift-off layer LF1 is formed on the p-type semiconductor layer 13p
  • the second lift-off layer LF2 is formed on the first lift-off layer LF1.
  • the second lift-off layer LF2, the first lift-off layer LF1, and the p-type semiconductor layer 13p are patterned. Thereby, the p-type semiconductor layer 13p is selectively removed, and a non-formed region NA where the p-type semiconductor layer 13p is not formed is generated.
  • the second lift-off layer LF2, the first lift-off layer LF1, and the p-type semiconductor layer 13p remain in a region that is not etched on the back main surface 11SB of the crystal substrate 11.
  • Such a patterning step is realized by a photolithography method, for example, by forming a resist film (not shown) having a predetermined pattern on the second lift-off layer LF2 and etching a region masked by the formed resist film. I do.
  • a photolithography method for example, by forming a resist film (not shown) having a predetermined pattern on the second lift-off layer LF2 and etching a region masked by the formed resist film. I do.
  • a resist film not shown
  • etching solution used in the step shown in FIG. 10 for example, a mixed solution of hydrofluoric acid and an oxidizing solution (for example, hydrofluoric nitric acid) or a solution in which ozone is dissolved in hydrofluoric acid (hereinafter, ozone / hydrofluoric acid) Acid solution).
  • the etching agent that contributes to the etching of the lift-off layer LF is hydrogen fluoride.
  • the patterning here is not limited to wet etching using an etching solution.
  • the patterning may be, for example, dry etching or pattern printing using an etching paste or the like.
  • the intrinsic semiconductor layer including the second lift-off layer LF2, the first lift-off layer LF1, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p is formed on the back-side main surface 11SB of the crystal substrate 11.
  • 12n and the n-type semiconductor layer 13n are sequentially formed.
  • the stacked film of the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n is formed on the non-formation region NA, on the surface and side surface (end surface) of the second lift-off layer LF2, and on the first lift-off layer LF1 and the p-type semiconductor. It is formed on the side surface (end surface) of the layer 13p and the intrinsic semiconductor layer 12p.
  • the etching solution used in the lift-off step includes, for example, a solution containing hydrofluoric acid as a main component.
  • the etching solution attached to the crystal substrate 11 is removed by using a rinsing liquid (this step is called a rinsing step).
  • a rinsing liquid for example, a liquid obtained by adding a liquid property adjusting agent for adjusting the surface tension as described later is used based on pure water.
  • the surface tension of the etching solution and the rinsing solution used in the lift-off step and the rinsing step is preferably from 25 mN / m to 70 mN / m, and more preferably from 30 mN / m to 60 mN / m.
  • the lift-off step proceeds smoothly due to the high wettability to the p-type semiconductor layer 13p and the lift-off layer LF, and further, the n-type semiconductor layer 13n and the intrinsic The semiconductor layer 12n is easily aggregated in the etching solution and the rinsing liquid.
  • the particles are agglomerated and the particles become large, so that the re-adhesion of the n-type semiconductor layer 13n and the intrinsic semiconductor layer 12n to the crystal substrate 11 is suppressed. Further, when the etching solution or the rinsing liquid is circulated, the removal of the particles is facilitated by filtering. As described above, fine separation and suspended matter do not convect in the liquid for a long time, so that both productivity and yield are improved.
  • separation grooves are formed on the back main surface 11SB of the crystal substrate 11, that is, on each of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by, for example, a sputtering method using a mask.
  • the transparent electrode layer 17 (17p, 17n) is formed so as to give 25.
  • the transparent electrode layer 17 (17p, 17n) may be formed as follows instead of the sputtering method. For example, a transparent conductive oxide film is formed on the entire back surface 11SB without using a mask, and then the transparent conductive oxide film is formed on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by photolithography.
  • It may be formed by performing etching to leave a conductive oxide film.
  • a leak current is less likely to occur.
  • a linear metal electrode layer 18 (18p, 18n) is formed on the transparent electrode layer 17 using, for example, a mesh screen (not shown) having openings.
  • the back junction solar cell 10 is formed.
  • ultrasonic treatment is performed using the cleaning bath 21 in which the processing liquid is stored, whereby the n-type semiconductor layer 13 n and the intrinsic semiconductor layer 12 n are removed. Peeling becomes more reliable.
  • the processing liquid in the cleaning bath 21 is an etching solution used in the lift-off step in the lift-off step, and a rinsing liquid in the rinsing step.
  • the semiconductor substrate 57 held in the cassette 51 is the semiconductor substrate in the state shown in FIG. 11 or FIG.
  • the semiconductor substrate 57 has a substantially rectangular shape when viewed from the thickness direction.
  • the cassette 51 is formed of a resin-made tubular body 52, and the cleaning tub is placed such that the tubular axis direction of the tubular body 52 is the vertical direction. 21 is immersed in the processing solution.
  • the tubular body 52 is not limited to a resin, and may be, for example, a metal.
  • the cassette 51 (the tubular body 52) will be described as being in the posture (the posture immersed in the processing liquid) disposed in the cleaning bath 21.
  • the shape of the cross section of the cylindrical body 52 orthogonal to the cylindrical axis direction is substantially rectangular.
  • the direction in which the long side of the rectangle of the cross section extends is called the longitudinal direction
  • the direction in which the short side of the rectangle extends is the short direction.
  • the cross-sectional shape of the tubular body 52 is not limited to a substantially rectangular shape, and may be any shape.
  • the size of the cassette 51 may be such that the cassette 51 is disposed inside the cleaning bath 21 such that the cylindrical axis of the cylindrical body 52 is in the vertical direction, and is immersed in the processing liquid in the cleaning bath 21. Any size is possible if possible.
  • the cylindrical body 52 has an outer peripheral surface 52a exposed outside the cylindrical body 52 and an inner peripheral surface 52b forming a space inside the cylindrical body 52.
  • the inner peripheral surface 52b of the tubular body 52 extends straight in the tubular axis direction (vertical direction) of the tubular body 52 over the entirety of the tubular body 52 in the tubular axis direction.
  • the outer peripheral surface 52a of the cylindrical body 52 has a cylindrical axially extending portion 52c extending in the cylindrical axis direction of the cylindrical body 52 and the cylindrical body 52 so that the thickness of the cylindrical body 52 increases toward the upper side. And an inclined portion 52d inclined with respect to the cylinder axis direction.
  • the tubular axially extending portion 52c is provided only at the lower end of the outer peripheral surface 52a of the tubular body 52, and the inclined portion 52d is provided at a portion above the tubular axially extending portion 52c.
  • the inclined portion 52d By the inclined portion 52d, a large thickness of the upper end surface of the tubular body 52 is ensured, and the pushing of the tubular body 52 by the second blocking piece 42 described later is favorably performed.
  • the entirety of the outer peripheral surface 52a of the cylindrical body 52 in the cylinder axis direction may extend straight in the cylindrical axis direction (vertical direction) of the cylindrical body 52, similarly to the inner peripheral surface 52b.
  • a plurality of holding projections 52e for holding the semiconductor substrate 57 are provided on two portions of the inner peripheral surface 52b of the cylindrical body 52 facing each other in the short direction so as to be arranged in the longitudinal direction.
  • the distance between the holding projections 52e adjacent to each other in the longitudinal direction in each portion is substantially the same as the thickness of the semiconductor substrate 57 (in FIG. 4, exaggerated for simplicity), In the meantime, the semiconductor substrate 57 is held in an upright posture extending vertically.
  • a substrate supporting portion 52f (see FIG. 3) that supports the semiconductor substrate 57 by contacting the lower surface of the semiconductor substrate 57 is provided at a lower end portion between the adjacent holding projections 52e on each surface.
  • the configuration for holding the semiconductor substrate 57 is an example, and another configuration may be employed.
  • the posture of the semiconductor substrate 57 held by the cassette 51 may be any posture, for example, may be a posture inclined with respect to the vertical direction. Further, the surface of the semiconductor substrate 57 may be oriented in any direction.
  • the washing tub 21 includes a bottom wall portion 22 extending in the horizontal direction, and a cylindrical side wall portion 23 that rises upward from a peripheral portion of the bottom wall portion 22 and stores therein a processing liquid. It is formed in a bottomed cylindrical shape. That is, the cylindrical side wall 23 is formed so as to rise in a direction crossing the in-plane direction of the bottom wall 22.
  • the cylinder axis direction of the cylindrical side wall 23 coincides with the vertical direction (that is, in the present embodiment, the direction of intersection with the in-plane direction of the bottom wall 22 is the vertical direction).
  • the washing tub 21 is also made of resin like the tubular body 52.
  • the washing tub 21 is not limited to resin, but may be metal, for example.
  • the inner side surface of the cylindrical side wall portion 23 has two straight lines 23a parallel to each other and two straight lines 23a.
  • a shape including an arc-shaped curve 23b whose center of curvature is located inside the cylindrical side wall portion 23 and connects the one side end portions and the other side end portions hereinafter, referred to as a stadium shape.
  • the outer side surface of the cylindrical side wall portion 23 has the same shape as the inner side surface. Note that an arc-shaped curve may be used instead of the arc-shaped curve 23b.
  • the cleaning bath 21 is arranged in the vertical direction (intersecting direction with respect to the in-plane direction of the bottom wall portion 22) of the cassette 51 immersed in the processing liquid, and in the horizontal direction (the in-plane direction of the bottom wall portion 22) intersecting with the vertical direction. )
  • the restricting unit 30 includes a first restricting unit 31 that restricts the lateral movement of the cassette 51 and a second restricting unit 41 that restricts the vertical movement of the cassette 51. Note that, in the case where the movement of the cassette 51 in the vertical direction can also be stopped by the first stopping portion 31, the stopping portion 30 may have only the first stopping portion 31. Similarly, when the movement of the cassette 51 in the horizontal direction can be suppressed by the second restraining portion 41, the restraining portion 30 may include only the second restraining portion 41.
  • the plurality of first stoppers 31 are provided so as to be arranged in a circumferential direction around the outer periphery of the cassette 51 (tubular body 52) immersed in the processing liquid.
  • four) first stopping pieces 32 are included.
  • the four first stopping pieces 32 are provided on the bottom wall 22 of the washing tub 21, and are located at corners of a virtual rectangle 35 corresponding to the outer shape line of the lower end surface of the tubular body 52.
  • Each first stopping piece 32 has a mating surface 32a that matches each corner (the outer surface of the cassette 51) of the cylindrical axially extending portion 52c, and a receiving surface that receives the vicinity of the corner at the lower end surface of the cylindrical body 52. 32b.
  • the height position of the upper end surface of the cylindrical body 52 is lower than the height position of the processing liquid level.
  • the receiving surface 32b has a role of forming a gap between the lower end surface of the cylindrical body 52 and the bottom wall 22 of the cleaning bath 21 to promote the inflow and outflow of the processing liquid to the inside of the cylindrical body 52.
  • a slight gap is actually generated therebetween, and the inner wall of the cylindrical body 52 is Inflow and outflow of the processing liquid are performed.
  • the four first stopping pieces 32 are moved by a moving mechanism 36 (see FIG. 3) such as a motor that moves the first stopping pieces 32 so as to be detachable from and attached to the cassette 51 immersed in the processing liquid.
  • a moving mechanism 36 such as a motor that moves the first stopping pieces 32 so as to be detachable from and attached to the cassette 51 immersed in the processing liquid.
  • the moving mechanism 36 is provided on the lower surface of the bottom wall portion 22 and, for example, connects the two first stopping pieces 32 of each set located on each diagonal line of the virtual square 35 to each other. It is moved along the diagonal on the bottom wall portion 22 so as to be separated.
  • the detailed configuration of the moving mechanism 36 is omitted.
  • the four first stopping pieces 32 are brought close to the cassette 51 by the moving mechanism 36, and the matching surfaces 32a abut against the four corners of the cylindrical axially extending portion 52c to press the cylindrical body 52 inward. I do. As a result, the movement of the cassette 51 in the lateral direction is suppressed. Depending on the pressing force of the four first blocking pieces 32 against the cylindrical body 52, the movement of the cassette 51 in the vertical direction can be restrained by the four first blocking pieces 32.
  • the four first stopping pieces 32 are separated from the cassette 51 by the moving mechanism 36. At this time, each first stopping piece 32 moves by such an amount that the receiving surface 32b does not come off the lower end surface of the tubular body 52. Thereby, the cassette 51 can be easily taken in and out of the cleaning bath 21.
  • the first stopper 32 does not necessarily need to be configured to be movable, but may be fixed to the bottom wall 22.
  • the first stopping piece 32 is positioned such that the lower surface of the cylindrical body 52 is in contact with the receiving surface 32b and the mating surface 32a substantially abuts the corner of the cylindrical axially extending portion 52c. Is provided. Further, only a part of the plurality of first restraining pieces 32 may be configured to be movable.
  • the first blocking piece 32 may be provided on the cylindrical side wall 23 via a support member.
  • the first blocking piece 32 may be configured to be able to be separated from and connected to the cassette 51 immersed in the processing liquid via the support member.
  • the number of the first stoppers 32, the number of the first stoppers 32 configured to be detachable from the cassette 51, and the moving direction when the first stoppers 32 are configured to be movable It differs depending on the cross-sectional shape of the cylindrical body 52, and is appropriately set so that the lateral movement of the cassette 51 can be restrained.
  • the position of the cassette 51 with respect to the washing tub 21 as viewed from above (the position of the first blocking piece 32) is usually the center of the washing tub 21, but may be anywhere in the washing tub 21.
  • the washing tub 21 further includes a top surface portion 24 rotatably mounted on the cylindrical side wall portion 23 via a rotation mechanism 25.
  • the top surface portion 24 is divided into two divided portions 24a in a direction orthogonal to the two stadium-shaped straight lines 23a.
  • a hinge shaft 24b is provided at an end of the divided portion 24a on the side of the straight line 23a so as to penetrate in the direction in which the straight line 23a extends.
  • the hinge shaft 24b is fixed to the dividing portion 24a, and is rotatably supported by a hinge shaft support portion 23c provided at a portion corresponding to the straight line 23a at the upper end of the cylindrical side wall portion 23.
  • the two divided portions 24a are rotated by the rotation of respective hinge shafts 24b to open and close an opening at the upper end of the washing tub 21, like a double door.
  • the rotation mechanism 25 has, for example, one motor connected to the hinge shaft 24b of the two divided portions 24a via a speed reduction mechanism.
  • the hinge shafts 24b of the divided portions 24a rotate in opposite directions, and the two divided portions 24a rotate.
  • the two divided portions 24a do not cover all the portions of the opening at the upper end of the cleaning tub 21, but can also cover all the portions of the opening.
  • the second restraining portion 41 includes a second restraining piece 42 provided so as to face the bottom wall portion 22 and to change the distance from the bottom wall portion 22.
  • a second restraining piece 42 provided so as to face the bottom wall portion 22 and to change the distance from the bottom wall portion 22.
  • two second stopping pieces 42 are respectively provided at the distal ends (ends opposite to the hinge shaft 24 b) of the two divided portions 24 a on the top surface portion 24. (A total of four), and the interval between the two divided portions 24a and the bottom wall portion 22 is changed with the rotation of the two divided portions 24a via the rotation mechanism 25.
  • each second stopping piece 42 may be formed of an elastic member such as rubber.
  • the portion where the second stopper 41 presses the tubular body 52 may be anywhere on the upper end surface of the tubular body 52.
  • An ultrasonic transmitter 61 for transmitting ultrasonic waves to the treatment liquid stored in the cleaning bath 21 is attached to the outer surface of the cylindrical side wall 23 of the cleaning bath 21.
  • the mounting position of the ultrasonic transmitter 61 may be any position in the circumferential direction on the outer surface of the cylindrical side wall portion 23. However, in consideration of ease of mounting, a flat portion (stadium) on the outer surface of the cylindrical side wall portion 23 is taken into consideration. (Corresponding to the straight line 23a of the shape).
  • the axis direction of the ultrasonic waves transmitted from the ultrasonic transmitter 61 is the horizontal direction.
  • the ultrasonic wave transmitted from the ultrasonic wave transmitter 61 is reflected on the inner side surface of the cylindrical side wall portion 23 of the cleaning bath 21 and the outer peripheral surface 52 a of the cylindrical body 52. No matter how many times this reflection is repeated, the ultrasonic wave transmitted from the ultrasonic wave transmitter 61 will have the same transmission angle at the position where the transmission was started as at the time when the transmission was started due to the stadium shape of the washing tub 21. Will not return. That is, the trajectory of the ultrasonic wave is not a periodic trajectory, but a so-called chaotic trajectory. This is true regardless of the shape of the cassette 51. As a result, no standing wave is generated in the processing liquid, and a uniform sound field is formed in the processing liquid.
  • the semiconductor substrate 57 is ultrasonically treated with the treatment liquid in which such a uniform sound field is formed.
  • the movement of the cassette 51 in the vertical and horizontal directions is restricted by the first and second restricting pieces 32 and 42, and the inside of the cylindrical side wall 23 of the cleaning bath 21 is restricted. Since the side surface has a stadium shape such that a standing wave does not occur in the processing liquid, the ultrasonic processing of the semiconductor substrate 57 is performed favorably. Further, since no standing wave is generated in the processing liquid, even if the semiconductor substrate 57 for the solar cell 10 having a small thickness is subjected to ultrasonic treatment, the semiconductor substrate 57 is not damaged. This suppresses the performance degradation of the solar cell 10 due to the dangling bond of silicon.
  • the shape of the inner side surface of the cylindrical side wall 23 is not limited to the stadium shape. Irrespective of the shape of the cassette 51, in the cross section orthogonal to the cylinder axis direction of the cylindrical side wall 23, one of the circumferential directions of the inner side surface of the cylindrical side wall 23 is set so that the ultrasonic trajectory becomes a chaotic trajectory. What is necessary is just to make a part into a curve and to make the remainder straight. In this case, in the cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion 23, one or more curves on the inner side surface of the cylindrical side wall portion 23 are preferably provided, and are preferably arc-shaped or arc-shaped curves. .
  • the center of curvature of the at least one arc-shaped or arc-shaped curve may be located inside the cylindrical side wall 23 or may be located outside the cylindrical side wall 23.
  • the center of curvature of some of the plurality of arc-shaped or arc-shaped curves is located inside the cylindrical side wall portion 23, and the center of curvature of the remaining curves is outside the cylindrical side wall portion 23. It may be located.
  • the inner side surface of the cylindrical side wall portion 23 may be formed in a substantially D-shape in a cross section orthogonal to the cylinder axis direction of the cylindrical side wall portion 23.
  • the curve on the inner side surface of the cylindrical side wall portion 23 is an arc-shaped or arcuate curve whose center of curvature is located inside the cylindrical side wall portion 23.
  • the inner side surface of the cylindrical side wall portion 23 may be formed in any one of the shapes shown in FIGS.
  • the shape of FIG. 17 there are two curved surfaces on the inner surface of the cylindrical side wall portion 23, and the curved surface has an arc shape, and the center of curvature of the one curved line is located inside the cylindrical side wall portion 23.
  • the center of curvature of another arcuate curve is located outside the cylindrical side wall 23. 14 to 19, the illustration of the first stop piece 32 is omitted.
  • the semiconductor substrate 57 for the solar cell 10 is subjected to the ultrasonic treatment in the cleaning bath 21.
  • the present invention is not limited to this.
  • a bathtub 21 can be used.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)
  • Cleaning By Liquid Or Steam (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

L'invention concerne un bain de nettoyage (21) pour soumettre un substrat semi-conducteur (57) retenu dans une cassette (51) à un traitement par ultrasons comprenant : une partie de paroi inférieure (22) ; une partie de paroi latérale tubulaire (23) qui s'élève à partir de la partie de paroi inférieure (22) et à l'intérieur de laquelle un liquide de traitement est stocké ; et une partie d'inhibition (30) qui inhibe le mouvement de la cassette (51), immergée dans le liquide de traitement, dans une direction dans le plan de la partie de paroi inférieure (22) et dans une direction d'intersection par rapport à la direction dans le plan. Dans une section transversale perpendiculaire à la direction d'un axe tubulaire de la partie de paroi latérale tubulaire (23), une partie, dans une direction périphérique, d'une surface intérieure de la partie de paroi latérale tubulaire (23) est une courbe, et le reste de celle-ci est une ligne droite.
PCT/JP2019/027758 2018-08-02 2019-07-12 Bain de nettoyage WO2020026770A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201980050101.0A CN112514033B (zh) 2018-08-02 2019-07-12 清洗浴槽
JP2020533392A JP7053838B2 (ja) 2018-08-02 2019-07-12 洗浄浴槽

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-145634 2018-08-02
JP2018145634 2018-08-02

Publications (1)

Publication Number Publication Date
WO2020026770A1 true WO2020026770A1 (fr) 2020-02-06

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PCT/JP2019/027758 WO2020026770A1 (fr) 2018-08-02 2019-07-12 Bain de nettoyage

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JP (1) JP7053838B2 (fr)
CN (1) CN112514033B (fr)
WO (1) WO2020026770A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6332680U (fr) * 1986-08-12 1988-03-02
JPS6421786U (fr) * 1987-07-30 1989-02-03
JPH03222419A (ja) * 1990-01-29 1991-10-01 Kokusai Denki Erutetsuku:Kk 超音波洗浄装置
JPH11347508A (ja) * 1998-06-10 1999-12-21 Twinbird Corp 洗浄機の洗浄用アタッチメント
JP2012104682A (ja) * 2010-11-11 2012-05-31 Seiko Epson Corp 洗浄装置
WO2014038277A1 (fr) * 2012-09-06 2014-03-13 三菱電機株式会社 Appareil de fabrication de cellule solaire et procédé de fabrication de cellule solaire utilisant celui-ci

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2696017B2 (ja) * 1991-10-09 1998-01-14 三菱電機株式会社 洗浄装置及び洗浄方法
US6523557B2 (en) * 2000-12-13 2003-02-25 Imtec Acculine, Inc. Megasonic bath
JP2003257918A (ja) * 2002-02-27 2003-09-12 Seiko Epson Corp 被洗浄物ホルダおよび超音波洗浄装置
JP2009039604A (ja) * 2007-08-06 2009-02-26 Fujitsu Ltd 洗浄装置、洗浄槽、洗浄方法および洗浄制御プログラム
CN206500403U (zh) * 2017-01-19 2017-09-19 昆山国显光电有限公司 超声波清洗槽
CN206689136U (zh) * 2017-02-13 2017-12-01 深圳市佳洁农业投资发展有限公司 一种带有清洗篮的超声波清洗机

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6332680U (fr) * 1986-08-12 1988-03-02
JPS6421786U (fr) * 1987-07-30 1989-02-03
JPH03222419A (ja) * 1990-01-29 1991-10-01 Kokusai Denki Erutetsuku:Kk 超音波洗浄装置
JPH11347508A (ja) * 1998-06-10 1999-12-21 Twinbird Corp 洗浄機の洗浄用アタッチメント
JP2012104682A (ja) * 2010-11-11 2012-05-31 Seiko Epson Corp 洗浄装置
WO2014038277A1 (fr) * 2012-09-06 2014-03-13 三菱電機株式会社 Appareil de fabrication de cellule solaire et procédé de fabrication de cellule solaire utilisant celui-ci

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JP7053838B2 (ja) 2022-04-12
CN112514033A (zh) 2021-03-16
CN112514033B (zh) 2024-03-15
JPWO2020026770A1 (ja) 2021-08-02

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