WO2014050304A1 - Photoelectric conversion element and method for manufacturing same - Google Patents

Photoelectric conversion element and method for manufacturing same Download PDF

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Publication number
WO2014050304A1
WO2014050304A1 PCT/JP2013/070938 JP2013070938W WO2014050304A1 WO 2014050304 A1 WO2014050304 A1 WO 2014050304A1 JP 2013070938 W JP2013070938 W JP 2013070938W WO 2014050304 A1 WO2014050304 A1 WO 2014050304A1
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layer
semiconductor layer
amorphous semiconductor
concentration
photoelectric conversion
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PCT/JP2013/070938
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French (fr)
Japanese (ja)
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訓裕 川本
洋平 川上
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三洋電機株式会社
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Priority to JP2012-214089 priority
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Publication of WO2014050304A1 publication Critical patent/WO2014050304A1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Abstract

A photoelectric conversion element (10) comprising an i layer (43) that is an intrinsic amorphous semiconductor layer formed in the back surface side of a substrate (40), said substrate being a crystalline semiconductor layer, a p layer (44) that is a p-type amorphous semiconductor layer formed on the i layer (43), and a TCO (46) that is a transparent conductive film layer formed on the p layer (43), wherein the boron (B) concentration in the thickness direction of the p layer (43) has a peak position (X2) that is located closer to the i layer (43) than the interface position (X4) with the TCO (46). The B concentration may decrease from the peak position (X2) toward the interface position (X4) with the TCO (56) either step-by-step, gradually or stepwise. When the substrate (40) is in the n-type, it is preferred that, in the light receiving surface side thereof, the i layer that is an intrinsic amorphous semiconductor layer, an n layer that is an n-type amorphous semiconductor layer formed on the i layer, and the TCO that is a transparent conductive film layer formed on the n layer are arranged so that the peak position of the phosphorus (P) concentration of the n layer is located in the side of the n-type substrate (40) with the i layer interposed.

Description

Its manufacturing method and photoelectric conversion element

The present invention includes a photoelectric conversion element and its manufacturing method.

The intrinsic amorphous semiconductor film of the thin film is interposed photovoltaic devices are known for pn junction (Patent Document 1).

Further, when manufacturing a photovoltaic device as described above, in a state having a plurality of substrates on a tray, the method of forming the n-type amorphous semiconductor layer is known (Patent Document 2).

JP-4-199750 discloses JP 2008-135556 JP

When forming a photoelectric conversion element using the same equipment, it is possible to suppress the influence of boron mixed in the interface between the substrate and the intrinsic amorphous semiconductor layer. Specifically, when forming the photovoltaic element using repeated tray for mounting the substrate, boron attached to the tray (B) suppresses be incorporated at the interface between the substrate and the intrinsic amorphous semiconductor layer it is.

The photoelectric conversion element according to the present invention, an intrinsic amorphous semiconductor layer formed over the crystalline semiconductor layer, and a p-type amorphous semiconductor layer formed on the intrinsic amorphous semiconductor layer, p-type amorphous includes a transparent conductive film layer formed on the quality semiconductor layers, a, p-type amorphous semiconductor layer, and the acceptor concentration in the intrinsic amorphous semiconductor layer side than the position of the interface peaks of the transparent conductive film layer having a position.

The manufacturing method of a photoelectric conversion element according to the present invention is to place a crystalline semiconductor in the tray to form an intrinsic amorphous semiconductor layer on a crystalline semiconductor, p-type amorphous on the intrinsic amorphous semiconductor layer forming a quality semiconductor layer, carries the crystalline semiconductor on the intrinsic amorphous semiconductor layer and a p-type amorphous semiconductor layer formed laminate, the place the following crystalline semiconductor by using the same tray repeating the steps a method for manufacturing a photoelectric conversion element, the formation of p-type amorphous semiconductor layer is formed by forming at acceptor concentration of a predetermined peak concentration, formed by reducing the acceptor concentration from the peak concentration Te, the formation of p-type amorphous semiconductor layer is completed.

The photoelectric conversion element according to the present invention, an intrinsic amorphous semiconductor layer formed on the light-receiving surface side of the crystalline semiconductor layer, the intrinsic amorphous formed in the semiconductor layer on the same conductivity type as the crystalline semiconductor layer a conductive amorphous semiconductor layer containing an impurity, wherein the transparent conductive film layer formed on the conductive amorphous semiconductor layer, said conductive amorphous semiconductor layer, the intrinsic amorphous the concentration of the impurity at the position of the crystalline semiconductor layer side to sandwich the semiconductor layer becomes a peak, the concentration of the impurity at the position of the transparent conductive film layer side of the position is lower than the peak concentration.

With the above structure, since the acceptor concentration at the interface between the transparent conductive film layer of the p-type amorphous semiconductor layer lowers than the peak concentration, using the same manufacturing apparatus when forming the next photoelectric conversion device, the substrate and the intrinsic a- the effect of boron to be mixed at the interface of the amorphous semiconductor film can be suppressed.

Also, according to at least one of the foregoing structures, the light-receiving surface side, a crystalline semiconductor, the impurity concentration of the conductive type amorphous semiconductor layer of the same conductivity type as the crystalline semiconductor layer formed on the i-layer across the i-layer since such a peak concentration at a position of the layer side, it takes a large potential difference between the crystalline semiconductor layer and the conductive type amorphous semiconductor layer. Thus, it is possible to suppress light absorption loss as a photoelectric conversion element.

It is a diagram showing a structure of a photoelectric conversion device of the embodiment. In the photoelectric conversion device of the embodiment, a diagram showing the boron (B) concentration distribution of p-type amorphous semiconductor layer. In the prior art, it is a diagram showing the relationship between the B concentration and characteristics. In the photoelectric conversion device of the embodiment, a diagram showing the relationship between the peak concentration B PEAK and characteristics of boron of the p-type amorphous semiconductor layer (B). It is a diagram illustrating a procedure of a method for manufacturing a photoelectric conversion element in the embodiment. It is a diagram showing a structure of a photoelectric conversion element of the other embodiments. In the photoelectric conversion device of the embodiment of FIG. 6 is a diagram illustrating a phosphorus (P) concentration profile of the type amorphous semiconductor layer of the light-receiving surface side. In the photoelectric conversion device of another embodiment, the conductivity type of the crystalline semiconductor layer is a diagram illustrating the structure of a case of a p-type. It is a diagram showing a structure of a modification of FIG. It is a diagram showing a structure of a modification of FIG. It is a diagram showing a structure of a modified example of FIG. 10.

With reference to the accompanying drawings, exemplary embodiments will be described in detail. In the following, a structure of a photoelectric conversion element, across the substrate is a crystalline semiconductor layer, an intrinsic amorphous semiconductor layer and a p-type amorphous semiconductor layer is laminated on the light-receiving surface side, an intrinsic amorphous on the back side While it mentions a laminate of the semiconductor layer and the n-type amorphous semiconductor layer, which is an example for explanation, whether the light-receiving surface side or back side, is formed over the crystalline semiconductor layer intrinsic as long as the p-type amorphous semiconductor layer is formed on the amorphous semiconductor layer. In the following, describe what the amorphous semiconductor layer is formed on the entire surface of the substrate, which is one using as schematic description, to the substrate of each amorphous semiconductor layer using a selective mask such as it may alternatively selectively forming Te. For example, it may be as forming a selectively formed planarly pn junction one n-type amorphous semiconductor layer on the side and the p-type amorphous semiconductor layer of the substrate.

The thickness described below, concentration, etc. are merely examples for explanation, according to the specification of the photoelectric conversion element, it can be appropriately changed. Hereinafter, the same reference numerals are assigned to one or corresponding elements in all the drawings, without redundant description.

Figure 1 is a diagram showing a configuration of a photoelectric conversion element. The photoelectric conversion element 10 includes a substrate 40. The light-receiving surface side of the substrate 40 (upper side on the paper surface of FIG. 1), and the intrinsic amorphous semiconductor layer 41, an n-type amorphous semiconductor layer 42, is provided with a transparent conductive film layer 45. Further, on a rear surface of the substrate 40 (lower side on the plane of FIG. 1), and the intrinsic amorphous semiconductor layer 43, a p-type amorphous semiconductor layer 44, is provided with a transparent conductive film layer 46. p-type amorphous semiconductor layer 44 includes a first p-type amorphous semiconductor layer 44-1, and the second p-type amorphous semiconductor layer 44-2, a 3 p-type amorphous semiconductor layer and a 44-3.

Hereinafter, unless otherwise specified, it shows a substrate a crystalline semiconductor layer, an intrinsic amorphous semiconductor layer i layer, p-type amorphous semiconductor layer a p-layer, a transparent conductive film layer and the TCO. Further, an acceptor element is a p-type element, can be used other than boron (B), in the following, as using boron, shows the acceptor concentration and the B concentration. Below, i layer formed on the back surface side of the substrate, p layer, TCO will be described.

Substrate 40 is a semiconductor material of the crystal system. Substrate 40 may be an n-type or p-type conductivity of the crystalline semiconductor substrate. Substrate 40 may be used a single crystal silicon substrate, polycrystalline silicon substrate, gallium arsenide (GaAs) substrate, indium phosphide (InP) substrate. Substrate 40 is to absorb the incident light to generate electrons and holes of the carrier pairs by photoelectric conversion. In the following, an example of using the n-type single-crystal silicon as the substrate 40. In Figure 1, a substrate 40, it showed this as n-c-Si.

Substrate 40 is cleaned with hydrofluoric acid (HF) aqueous solution or RCA cleaning solution. Further, an alkaline etchant such as potassium hydroxide (KOH) aqueous solution may be formed textured structure (not shown) on the front and back surfaces of the substrate used.

i layer 41 is formed on the substrate 40 after cleaning. i layer 41, for example, an amorphous semiconductor layer including hydrogen. i layer 41, a plasma enhanced CVD (PECVD) method, catalyzed CVD (Cat-CVD) method, it can be formed by sputtering or the like. Plasma CVD, RF plasma CVD, the higher VHF plasma CVD frequency, it is possible to use a micro plasma CVD method. In the following, an example of using the RF plasma CVD method.

For example, i by supplying hydrogen as the silicon-containing gas and a dilution gas such as silane (SiH 4), and plasma by applying a RF high frequency power to parallel plate electrodes or the like, is supplied to the deposition surface of the heated substrate formation of layer 41 is performed. Temperature of the substrate during film formation was about 150 ~ 250 ℃, RF power density can be about 1 ~ 20mW / cm 2.

i layer 41 thinner absorption of light as much as possible be suppressed, while the thicker to the extent that the surface of the substrate is fully passivated. As an example of the thickness of the i layer, about 1 ~ 25 nm, it is possible to preferably about 5 ~ 10 nm. In Figure 1, the i-layer 41, showed this as i-a.

n layer 42 is formed on the i layer 41. n layer 42 includes a donor is an element of the n-type conductivity amorphous semiconductor layer including hydrogen. n layer 42 can be formed plasma CVD method, catalyzed CVD method, a sputtering method or the like. Plasma CVD method, it is possible to use a RF plasma CVD method. In the following, an example of using the RF plasma CVD method.

For example, the silicon-containing gas such as silane (SiH 4), was added a gas containing an n-type element such as phosphine (PH 3), and fed diluted with hydrogen, by applying a RF high frequency power to the parallel plate electrodes such as into plasma, the formation of the p layer is performed by supplying to the deposition surface of the heated substrate. Temperature of the substrate during film formation was about 150 ~ 250 ℃, RF power density can be about 1 ~ 20mW / cm 2. As an example of the thickness of the n layer, about 5 ~ 20 nm, it is possible to preferably about 10 ~ 15 nm. In Figure 1, the n layer 42, showed this as n-a.

i layer 43 is a substrate 40 on, i layer 41 is formed on the principal surface opposite to the surface to be formed. i layer 43 can be formed in the same manner as the i-layer 41. In Figure 1, the i-layer 43, showed this as i-a.

p layer 44 is formed on the i layer 43. p layer 44 comprises an acceptor is an element of p-type conductivity amorphous semiconductor layer including hydrogen. p layer 44 can be formed plasma CVD method, catalyzed CVD method, a sputtering method or the like. Plasma CVD method, it is possible to use a RF plasma CVD method. In the following, an example of using the RF plasma CVD method.

For example, applied to the silicon-containing gas such as silane (SiH 4), a gas containing a p-type element such as diborane (B 2 H 6) was added, and supplied diluted with hydrogen, the RF high frequency power to the parallel plate electrodes such as and into plasma, the formation of the p layer 44 is performed by supplying to the deposition surface of the heated substrate. Temperature of the substrate during film formation was about 150 ~ 250 ℃, RF power density can be about 1 ~ 20mW / cm 2. As an example of the thickness of the p layer 44, about 5 ~ 20 nm, it is possible to preferably about 10 ~ 15 nm. In Figure 1, the p layer 44, showed this as p-a.

p layer 44 includes a first p-type amorphous semiconductor layer (first p-layer) 44-1, a second p-type amorphous semiconductor layer (second p-layer) 44-2, first p-type amorphous semiconductor layer 3 includes a (second p-layer) 44-3. Boron (B) concentration of the second p-layer 44-2 is higher than the B concentration of the first p-layer 44-1. Further, the B concentration of the first p-layer 44-1 is lower than the B concentration of the third p-layer 44-3. For details of the p-layer 44 will be described later.

TCO45 is formed on the n layer 42. Moreover, TCO46 is formed on the p-layer 44. TCO45,46 the transparent conductive film layer, for example, indium oxide (In 2 O 3) having a polycrystalline structure, zinc oxide (ZnO), tin oxide (SnO 2), metal oxides such as titanium oxide (TiO 2) composed of at least one comprise a. Tin of these metal oxide (Sn), zinc (Zn), tungsten (W), antimony (Sb), titanium (Ti), cerium (Ce), an element such as gallium (Ga) may be added . TCO an evaporation method, a plasma CVD method, can be formed by a thin film forming method such as sputtering. The thickness of the TCO is can be appropriately adjusted by the refractive index, when an example is about 70 ~ 100 nm.

On the TCO45,46, for example a metal electrode (not shown) formed using a silver paste is formed. By connecting a wiring material to the metal electrodes, the power generated by the photoelectric conversion element 10 is output to the outside of the solar cell module.

Figure 2 is a diagram showing the configuration of the photoelectric conversion element 10, the distribution of the B concentration in the p-type amorphous semiconductor layer constituting the photoelectric conversion element 10.

2 (a) is a block diagram of the photoelectric conversion element 10. The photoelectric conversion element 10, a crystalline semiconductor layer as the substrate 40, an intrinsic amorphous semiconductor layer on the light-receiving surface side (i layer) 41 and the n-type amorphous semiconductor layer (n layer) 42 was laminated on the back side in which intrinsic amorphous semiconductor layer (i layer) 43 and a p-type amorphous semiconductor layer (p layer) 44 are laminated. The light-receiving surface side transparent conductive film layer on the n layer 42 (TCO) 45 is formed on the back surface side transparent conductive film layer on the p layer 44 (TCO) 46 is formed.

Figure 2 (b) is a B concentration distribution diagram of the p-layer. B concentration distribution diagram, the vertical axis B concentration, at a position in the thickness direction of the p layer 44 on the horizontal axis from the interface of the i-layer 43 to the interface TCO46, X 0 is the interface between the i layer 43 and the p layer 44 position, X 4 is the position of the interface between the p-layer 44 and TCO46. In forming the photoelectric conversion element 10, the i layer 43 is formed on the substrate 40, the next time to form the p layer 44 on the i layer 43, X 0 is at the beginning of the p layer 44 is formed, X 4 is an end position of the p layer 44 is formed.

B concentration distribution 11, from the X 0 is the position of the interface between the i-layer 43 along the thickness direction of the p layer 44 to X 1 is constant concentration. Among the p-layer 44, from X 0 to X 1 is a first p-layer 44-1. The thickness of from X 0 to X 1 may be about 1/3 of the total thickness of the p layer. Constant concentration in this region can be a 10 19 / cm 3 order.

Next, the B PEAK to further increase the B concentration in X 1, to maintain the B PEAK to X 2. Among the p-layer 44, from X 1 to X 2 is a second p-layer 44-2. B PEAK is set to the optimum concentration of the p layer of the pn junction in the photoelectric conversion element 10. For example, the B PEAK can with 10 22 / cm 3 order. The thickness of the X 1 to X 2 is approximately about 1/2 of the total thickness of the p layer.

Then, the B TCO to lower the B concentration in front of the X 3 of X 4, to maintain the B TCO to X 4. Among the p-layer 44, from X 2 to X 4 is a third p-layer 44-3. Reduce the B concentration over from X 2 to X 3 is either a stepwise or continuous. For example, the p layer formation process, when turned time corresponding to X 2, reducing the gas flow rate of diborane containing boron (B 2 H 6) to the target value. Thus, between the thickness of a few nm, it can be changed stepwise in B TCO the B concentration from the B PEAK. B TCO can and 10 20 / cm 3.

Reducing the B concentration may be other than stepwise. For example, it may be a decreasing shape gradually decreasing may be stepped to reduce in stages. In these cases, the position X 3 to be B TCO may be any until X 4, may be just a B TCO to the position of X 4.

Therefore, B concentration in the p layer 44, the low concentration in the first p-layer 44-1 from the interface X 0 of the i layer 43 to X 1, in the second p-layer 44-2 from X 1 to X 2 high density, medium density in the third p-layer 44-3 from X 3 to the interface TCO46, a 3 density structure. The position of the B PEAK the B concentration of peaks between the X 1 to X 2, with the position where the B concentration reaches a peak in the i layer side of the X 4 is the position of the interface between the TCO.

While the effect of the above configuration compared to the prior art will be described in detail below. FIG 2, B concentration distribution 12 is conventional for comparison are shown. B concentration is conventional distribution 12 in the thickness direction of the p layer, at a constant concentration from X 0 to X 1, and B TCO by increasing the B concentration at X 1, while X 4 to its high concentration maintained until. Thus, the peak concentration of B is between from X 1 to X 4, not lowering the particular B concentration X 4 of the TCO surface.

3, as in the prior art, is a schematic diagram showing the relationship between the properties of the B concentration and the photoelectric conversion element 10 when a constant concentration of B concentration in the p layer to TCO surface. The horizontal axis in B concentrations, the vertical axis, and V OC is an open circuit voltage of the photoelectric conversion element 10, the reciprocal of the contact resistance between the p layer and the TCO (1 / ρ C) is taken. Characteristic line 13 indicates the variation of V OC for B concentration, the characteristic line 14 shows for B concentration changes of (1 / ρ C). As shown in FIG. 3, if increasing the B concentration (1 / ρ C) is improved, the electrical connection performance of the p-layer and the TCO is improved.

If on the other hand increasing the B concentration, the amount of B to be mixed in the interface between the substrate 40 and the i-layer 43 in the photoelectric conversion element 10 produced using the same manufacturing apparatus is increased, resulting in V OC decreases. It uses the same manufacturing apparatus, subsequently when manufacturing the photoelectric conversion element 10, B adhering to the manufacturing equipment is considered to be because it is caused to be mixed into the interface of the substrate 40 and the i-layer 43. In particular, B attached to the tray and the mask for holding the substrate 40 is mixed at the time of the i layer 43 is formed, reduces the properties of the intrinsic amorphous semiconductor layer of the i layer 43. This problem is remarkably appears when used repeatedly the tray and masks to manufacture the photoelectric conversion element 10. Thus, when a constant concentration of B concentration in the p layer 44 to TCO46 interface, and improvement in electrical connection performance related to the p-layer 44, it is difficult achieve both the improvement in V OC. The electrical performance related to the p-layer 44, for example, electric conductivity and the p layer 44, and the electrical connection performance between the p layer 44 and TCO46.

As a method for solving the above problems, eliminating the boron adhering to the manufacturing equipment, for example, it is conceivable to wash the tray or mask. By performing the cleaning step, it can be avoided B contamination of the interface between the substrate 40 and the i-layer 43, but the productivity is lowered.

Therefore, in the prior art, with priority to ensure the V OC, setting a low B concentration. In the prior art of FIG. 2, a peak value 10 20 / cm 3 of B concentration from about 10 22 / cm 3 which is an optimum concentration of the p layer of the pn junction in the photoelectric conversion element 10 in the embodiment It is set quite low. Thus, the B concentration of the interface between the substrate 40 and the i-layer 43 is reduced, it can be secured V OC. Meanwhile, since the B concentration of the p layer 44 becomes lower, the fill factor (FF) is decreased electric conductivity and the p layer 44, a decrease of the electrical connection performance between the p layer 44 and TCO46, photoelectric conversion element 10 reduced reliability of. In the prior art, it is not easy to manufacture the photoelectric conversion element 10 that satisfy these two requirements at the same time.

Figure 4 is a diagram for explaining the action effect of using a B concentration distribution 11 of the embodiment. The horizontal axis of FIG. 4 is a B PEAK, the vertical axis represents the V OC. Characteristic line 15, each time for producing a photoelectric conversion element 10, always clean ideal state by washing the trays, showing the relationship between the B PEAK and V OC when forming the i layer on the substrate. Characteristic line 16, especially in a state in which no washing or the like trays in the same manufacturing apparatus, as B PEAK = B TCO, repeated, showing the relationship of B PEAK and V OC when forming the i layer on the substrate.

As shown in FIG. 4, in the characteristic curve 16 is also the characteristic lines 15, V OC increases the Yuku by increasing the B PEAK, a V OC of substantially constant saturated it exceeds a certain B PEAK . This range substantially constant value in the range of optimal concentrations of the p layer of the pn junction in the photoelectric conversion element 10. B PEAK = 10 22 / cm 3 in the B concentration distribution 11 of Figure 2 is set in this range. Incidentally, B PEAK is according to the specifications of the photoelectric conversion element 10 can be appropriately set in a range of, for example, 10 21 / cm 3 ~ 10 23 / cm 3.

Setting the B PEAK in the range of optimal concentration of the p layer 44, the characteristic line 16 otherwise cleaned trays of the same manufacturing apparatus, compared with the characteristic line 15 of an ideal state, a low V OC. Therefore, to reduce than the B TCO B PEAK. Characteristic line 17 at that time, falls short of the characteristic line 15, V OC is considerably improved as compared with the characteristic line 16. The reason for this is considered to be as follows. When using a tray or a mask for holding a substrate 40 to produce a photoelectric conversion element 10, B concentration adhering to the outermost surface of the tray and the mask density than B PEAK is lower B TCO. Therefore, the amount of B attached to the tray and the mask B is mixed be mixed during the i-layer 43 formed is reduced, the B influence of V OC decreases due to contamination is reduced, the characteristic line of the ideal state closer to 17.

In other words, the larger the (B PEAK -B TCO), or, (B PEAK / B TCO) is too large characteristic line 17, closer to the ideal state of the characteristic line 15 from the characteristic lines 16. Therefore, the B TCO set to optimum B concentration in terms of the electrical connection between the p layer and the TCO, if compared to the sufficiently high B PEAK its set B TCO, the characteristic line 17 approaches the characteristic line 15 of an ideal state, it is possible to improve the V OC. As shown in FIG. 4, the V OC is wide range of substantially constant value B PEAK, can be appropriately increased B PEAK in that range.

Thus, the range of optimum setting of B TCO, the range of optimum setting of B PEAK by using the difference, to set the B TCO according to the contact resistance between the p layer 44 and TCO46, also, depending on the V OC set (B pEAK -B TCO) or (B pEAK / B TCO), the B concentration distribution in the p-layer 44, peak B concentration in the i layer 43 side than the position of the interface between the TCO46 to have a a position. Thus, while maintaining the function of the p layer 44, to suppress the influence of the incorporation of B at the interface of the substrate 40 and the i-layer 43 of the photoelectric conversion element 10, to improve the fill factor (FF) and V OC can.

Figure 5 is a diagram illustrating a procedure of a method for manufacturing a photoelectric conversion element 10. Here, especially a procedure for forming the i layer 43 and the p layer 44 on the back side of the substrate 40. FIG. 5 (a) shows loading procedure, (b) the i layer forming procedure, (c) the p-layer forming procedure, the (d) are carried out procedure.

As an apparatus to be used, RF plasma CVD apparatus 20 having four chambers are shown. Four chambers, in each of FIGS. 5, in order from right to left, carry-in chamber 21, i layer forming chamber 22, p layer formation chamber 23, a carry-out chamber 24. Between the chambers, under the control of the control unit, not shown, are connected to each other by the opening and closing mechanism, or is blocked.

5 (a) is the most right side of the tray 25 to the carry-in chamber 21 is a chamber arrangement of the RF plasma CVD apparatus 20 is a diagram showing a state in which a plurality of substrates 40 are mounted on the tray 25. In Figure 5, one of the trays 25, the substrate 40 is shown, the number of trays 25, the number of substrates 40 may be other than this. When the substrate 40 is placed on the tray 25, the opening and closing mechanism between the carry-in chamber 21 and the i-layer formation chamber 22 is opened, the tray 25 on which the substrate 40 is placed is moved in the i layer forming chamber 22. When the movement of the tray 25 is completed, the opening and closing mechanism between the carry-in chamber 21 and the i-layer formation chamber 22 is closed, i layer forming chamber 22 is sealed space.

FIG. 5 (b), in the i layer forming chamber 22 is a diagram showing how the i layer 43 is formed on the substrate 40. Here, the tray 25 is disposed between the parallel plate electrodes, a predetermined substrate temperature, under formation conditions of RF power density, supplying hydrogen as a silane (SiH 4) and the diluent gas, RF high frequency parallel plate electrodes into plasma by applying a power, by supplying to the deposition surface of the heated substrate 40, formation of the i-layer 43 is performed on the substrate 40. At this time, the tray 25 also, the amorphous semiconductor thin film 28 is deposited.

When i layer forming process is completed move, opening and closing mechanism between the i layer forming chamber 22 and the p layer forming chamber 23 is opened, the tray 25 for mounting the substrate 40 on which the i-layer 43 is formed on the p layer forming chamber 23 to. When the movement of the tray 25 is completed, the opening and closing mechanism between the i layer forming chamber 22 and the p layer forming chamber 23 is closed, the p-layer formation chamber 23 becomes closed space.

FIG. 5 (c), the p layer forming chamber 23 is a diagram showing how the p layer 44 is formed on the i layer 43 on the substrate 40. Here, the tray 25 is disposed between the parallel plate electrodes, a predetermined substrate temperature, under formation conditions of RF power density, a silane (SiH 4), diborane (B 2 H 6) was added, diluted in hydrogen and by supplying, into plasma by applying a RF high frequency power to the parallel plate electrodes, by supplying to the deposition surface of the heated substrate 40, formation of the p layer 44 lines the i layer 43 on the substrate 40 divide.

When the p-layer formed, so that the B concentration distribution 11 described in FIG. 2, the amount of diborane (B 2 H 6) is controlled. That is, a predetermined optimal concentration as the peak concentration B PEAK as p layer 44 of the photoelectric conversion, formation of the p-layer 44 is performed while reducing the B concentration from the B PEAK to B TCO. At this time, the tray 25 also, a thin film 30 of amorphous semiconductor containing B is attached.

When p layer formation process is finished moving, the opening and closing mechanism between the carry-out chamber 24 and p layer forming chamber 23 is opened, the tray 25 for mounting the substrate 40 on which the i-layer 43 and the p layer 44 is formed on the carry-out chamber 24 to. When the movement of the tray 25 is completed, the opening and closing mechanism between the carry-out chamber 24 and p layer forming chamber 23 is closed.

5 (d) is in the carry-out chamber 24, the laminate 31 i layer 43 and the p layer 44 is formed on the substrate 40 is removed from the tray 25, is a view showing a state that is carried to the next step . The next step is the formation of the i-layer 41 and the n layer 42 of the light-receiving surface side process or inspection process. Tray 25 on which the thin film 30 of amorphous semiconductor containing B is attached is conveyed to the carry-in chamber 21 again, the next substrate 40 is mounted, the above described procedure is repeated.

Thus, although the tray 25 is attached is B, by forming a B concentration distribution 11 described in the p layer 44 in FIG. 2, when forming a photoelectric conversion element 10 with the same tray 25 , it is possible to suppress the influence of boron mixed at the interface of the substrate 40 and the i-layer 43.

Although there is shown a state that does not form a i layer 41 and the n layer 42 to the substrate 40 in FIG. 5, to form the i layer 43 and the p layer 44 above the substrate 40 as shown in FIG. 5 may be, the i layer 43 and the p layer 44 may be formed after forming the i layer 41 and the n layer 42 to the substrate 40.

Further, the present invention is equipped with a plurality of substrates 40 on the tray 25 is not limited to the method of forming the photoelectric conversion element 10 is transported through the four chambers. For example, without using the tray may be formed i layer 43 and the p layer 44 in one chamber. In this case, after forming the i layer 43 in one chamber to form a p layer 44 having a B concentration distribution 11 described in FIG. When forming the i layer 43 and the p layer 44 in the same chamber, the B adhered to the inner wall of the chamber, there is a risk of contamination during the formation of the next i-layer 43. The p layer 44 by a B concentration distribution as described in FIG. 2, it is possible to prevent the B adhering to the chamber are mixed during formation of the i layer 43, while retaining the function as the p-layer 44, photoelectric by suppressing the influence of the incorporation of B at the interface of the substrate 40 and the i-layer 43 of the conversion element 10, it is possible to improve the fill factor (FF) and VOC.

In the example of FIG. 1, the n-type substrate 40, it was to be arranged p layer 44 on the back side. In this case, the light-receiving surface side, i layer 41 on the n-type substrate 40, n layer 42 thereon, thereon TCO45 is laminated.

Here, when the photoelectric conversion element 10 is the light is incident, the substrate 40 is to absorb the incident light to generate electrons and holes of the carrier pairs by photoelectric conversion. Generated electrons and holes, the potential difference between the substrate 40 and the n layer 42, separated by a potential difference between the substrate 40 and the p layer 44, electrons are collector in TCO45, holes are collector with TCO46 that.

In the example of FIG. 1, the substrate 40 is n-type, the potential difference between the n-type substrate 40 and the p layer 44 is taken sufficiently large by p-type and n-type conductivity differences. In contrast, the potential difference between the n-type substrate 40 and n layer 42 is the same conductivity type, not get too large. To increase the potential difference between the n-type substrate 40 and n layer 42, phosphorus (P) concentration of the n layer 42 may be sufficiently higher concentration than the concentration of phosphorus in the substrate 40 of n-type. At this time, although the contact resistance is also improved between the n layer 42 and TCO45, when excessively high concentration phosphorus concentration throughout the n layer 42, tends electrons lost on n layer 42. Therefore, light absorption loss is increased in the n layer 42, short-circuit current I SC of the photoelectric conversion element 10 is lowered.

6 and 7, while maintaining the contact resistance between the n layer 42 and TCO45, is a diagram showing a configuration capable of increasing the I SC by suppressing the increase in light absorption loss of the photoelectric conversion element 10.

Figure 6 corresponds to Figure 1, showing the configuration of a photoelectric conversion element. The photoelectric conversion element 50 includes a substrate 40. The light-receiving surface side of the substrate 40, an i layer 41, the n layer 42, is provided with TCO45. Further, on a rear surface of the substrate 40, an i layer 43, the p layer 44, it is provided with TCO46. n layer 42 includes a first n-layer 42-1, the second n layer 44-2.

Figure 7 is a view corresponding to FIG. 2 is a diagram showing the configuration of the photoelectric conversion element 60, the distribution of phosphorus (P) concentration in the n layer constituting the photoelectric conversion element 60.

7 (a) is a diagram showing a configuration of a photoelectric conversion element 50. Since this is the same content as FIG. 2 (a), the detailed description thereof will be omitted.

7 (b) is a phosphorus (P) concentration distribution diagram of the i-layer 41 and n layer 42. P concentration distribution diagram, the P concentration and the vertical axis, from the interface between the horizontal axis and substrate 40 i layer 41, indicating the position in the thickness direction of the i layer 41 and the n layer 42 to the interface TCO45. Here, Y 0 is the position of the substrate interface is the interface of the substrate 40 and the i-layer 41, Y 3 is the position of the TCO surface. In forming the photoelectric conversion element 50, the i layer 41 is formed on the substrate 40, then when forming an n-layer 42 on the i-layer 41, at the start of the formation Y 0 is i layer 41 , at the start of the formation of the completion of forming the n layer 42 of Y 1 is i-layer 41, Y 3 is the position of the forming end of the n layer 41.

Among phosphorus (P) concentration profile 51, n-type substrate 40 is not shown in FIG. 7 (b), having a predetermined concentration determined in advance. As an example, it is 10 15 / cm 3 ~ 10 17 / cm 3. i layer 41 is formed from the position of the substrate interface, in the range up to the position Y 1 of the i layer interface is the interface of the i layer 41 and the n layer 42, without adding the raw material gas of impurities such as phosphorus (P) to. phosphorus (P) concentration of the n layer 42 highest peak concentration P PEAK next at the location Y 1 of the i layer interface in the thickness direction, to the position of Y 2 maintains its peak concentration P PEAK. Down to a concentration lower than the peak concentration P PEAK at the position of Y 2, maintains its low concentration to a position Y 3 of the TCO surface.

Ie, n layer 41 has a concentration distribution of the two phases. Of the n-layer 42, the Y 1 to Y 2 is a first n-layer 42-1. The thickness of the first n layer 42-1 may be about about half of the total thickness of the n layer. Peak concentration P PEAK in this area, to phosphorus (P) concentration of the substrate 40 may be given a possible density difference. Phosphorus (P) concentration in the first n-layer 42-1, be 1 × 10 20 ~ 1 × 10 22 / cm 3 is suitable, for example, a 5 × 10 21 / cm 3.

To the concentration of phosphorus (P) and the peak concentration P PEAK sandwiches the i layer 41 may be as close as possible to the position on the substrate 40 side. Thus, a potential difference based on phosphorus (P) concentration difference between the substrate 40 and the n layer 42 will be provided on the side of the substrate 40, can be increased I SC of photoelectric conversion element 10 prevents the electron loss.

Then, phosphorus (P) concentration as low density P TCO than the peak concentration P PEAK in Y 2, maintained to the position Y 3 of the TCO surface. Of the n-layer 42, a Y 2 to Y 3 is a second n-layer 42-2. The thickness of the second n layer 42-2 may be about about half of the total thickness of the n layer. Phosphorus (P) concentration P TCO of this region is the concentration required to contact with the TCO45. Phosphorus (P) concentration of the second n layer 42-2, 1 in the range of × 10 20 ~ 1 × 10 22 / cm 3, to be lower than the concentration of phosphorus (P) of the first n-layer 42-1 It is preferred, for example, to 1 × 10 21 / cm 3 order.

As in Y 2 phosphorus (P) FIG reduce the concentration 7 (b), or as one stage of step-like, or a few-step staircase-like. Alternatively, it may be continuously reduced the concentration of phosphorus (P). Sometimes, in order to further improve the contact with the TCO45, phosphorus (P) concentration may be increased again immediately before the Y 3.

The FIG. 7 (b), for comparison, the phosphorus (P) concentration profile 52, 53 of the i layer 41 and the n layer 42 in the prior art. Phosphorus (P) concentration profile 52 is a constant concentration throughout the thickness direction of the n layer 42. The size of the constant concentration, a contact resistance between the n layer 42 and TCO45, and the electrons disappear in the n-layer 42, the balance of being set in a range maintained. In this case, phosphorus (P) concentration difference between the substrate 40 and the n layer 42 can be secured, but can be secured even contact resistance between the n layer 42 and TCO45, not the best properties both characteristics. Another phosphorus (P) concentration profile 53 in the n layer 42, from the position Y 1 of the i layer interface toward a position Y 3 of the TCO surface is intended to increase phosphorus (P) concentration distribution in two stages . According to this structure, the contact resistance between the n layer 42 and TCO45 is improved, phosphorus (P) concentration of the low concentration in the position Y 1 of the i layer interface.

In contrast, phosphorus (P) concentration profile 51 of the embodiment shown in FIG. 7, the position of phosphorus (P) concentration peak density P PEAK next sandwiching the i layer 41 substrate 40 side, TCO45 side from that position phosphorus (P) concentration of P TCO was lower than the peak concentration P pEAK in position.

Phosphorus (P) concentration profile 51 of the embodiment shown in FIG. 7, as compared with phosphorus (P) concentration distribution 52 of the prior art, on the high phosphorus (P) concentration in the TCO surface, the position of the substrate 40 side peak concentration P pEAK is higher concentrations. Accordingly, in comparison with the phosphorus in the prior art (P) concentration profile 52, while maintaining the contact resistance between the n layer 42 and TCO45, phosphorus (P) concentration difference between the n layer 42 and the substrate 40 the can be larger.

Further, as compared with phosphorus prior art (P) concentration profile 52, the peak concentration P PEAK position of the substrate 40 side in the n layer 42 is more highly concentrated. Phosphorus (P) Phosphorus (P) the maximum value of the density of the density distribution 52 is a high concentration compared to the concentration of phosphorus (P) of the substrate 40, at its maximum density position, the substrate 40 side of the n layer 42 They are separated, the potential difference is reduced due to the density difference may suppress increase of electron collection rate.

In the embodiment shown in FIG. 7, the substrate 40 was a n-type, in the case of a p-type substrate can be the same structure in relation to the p layer. Figure 8 is a diagram showing a structure of a photoelectric conversion element in that case. Here includes a p-type substrate 60, shown as p-c-Si, the i layer 43 is formed on the substrate 60, is formed on top of the i layer 43 of the same conductivity type p-type impurity of the substrate 60 and p layer 61, and a TCO46 formed on the p-layer 61. Then, the p-layer 61, a first p-layer 61-1 in which the concentration of impurities becomes a peak at the position of the substrate 60 side sandwiching the i layer, than the concentration peak concentration of the impurity at the position of TCO46 side from that position also comprises a second p-layer 61-2 decreases. By doing so, even if the p-type substrate 60, while maintaining the contact resistance between the p layer 61 and TCO46, increase the I SC by suppressing the increase in light absorption loss of the photoelectric conversion element 10 it can.

FIGS. 9 11 is a diagram showing a modified example of the photoelectric conversion element using the structure described above. Figure 9 is a combination of the structure of FIG. 1 and FIG. 10, in the structure of FIG. 1, employs a p-type substrate 60, in which is arranged a p layer 62 having a constant density on the light-receiving surface side, and the n layer 63 having a concentration of three stages on the back side . n layer 63 having a concentration of three stages, as shown in FIG. 1, in the structure of the p-layer 44 of the three steps described in FIG. 2, was replaced with an impurity of p-type boron (B) to the n-type phosphorus (P) the first n-layer 63-1, second n-layer 63-2 is obtained by a third n-layer 63-3. Figure 11 is a combination of the structure of Structure and 8 in FIG. 10.

10,50 photoelectric conversion elements, 11, 12 B concentration distribution, 14, 15, 16, 17 characteristic lines, 20 RF plasma CVD apparatus, 21 loading chamber, 22 i layer forming chamber, 23 p layer forming chamber, 24 carry-out chamber, 25 trays, a thin film of 28 amorphous semiconductor, amorphous semiconductor thin film containing 30 boron, 31 laminate, 40 substrate, 41 and 43 intrinsic amorphous semiconductor layer (i layer), 42,42-1,42 -2,63,63-1,63-2,63-3 n-type amorphous semiconductor layer (n layer), 44,44-1,44-2,44-3,61,61-1,61- 2,62 p-type amorphous semiconductor layer (p layer), 45, 46 transparent conductive film layer (TCO), 51, 52, 53 phosphorus (P) concentration distribution.

Claims (10)

  1. And the intrinsic amorphous semiconductor layer formed on the light-receiving surface side of the crystalline semiconductor layer,
    A conductive amorphous semiconductor layer containing an impurity of the same conductivity type as formed in the intrinsic amorphous semiconductor layer a crystalline semiconductor layer,
    A transparent conductive film layer formed on the conductive amorphous semiconductor layer,
    It includes,
    The conductive amorphous semiconductor layer, the concentration of the impurity at the position of sandwiching the intrinsic amorphous semiconductor layer and the crystalline semiconductor layer side becomes the peak of the impurity at the position of the transparent conductive film layer side than the position concentration is lower than the peak concentration, a photoelectric conversion element.
  2. And the intrinsic amorphous semiconductor layer formed over the crystalline semiconductor layer,
    A p-type amorphous semiconductor layer formed on the intrinsic amorphous semiconductor layer,
    A transparent conductive film layer formed on the p-type amorphous semiconductor layer,
    It includes,
    The p-type amorphous semiconductor layer, wherein also the position of the interface between the transparent conductive film layer having a position in which the acceptor concentration reaches a peak in the intrinsic amorphous semiconductor layer side, the photoelectric conversion element.
  3. In the photoelectric conversion device according to claim 2,
    The acceptor concentration decreases stepwise towards the position of the interface between the transparent conductive layer from the position at which the peak, the photoelectric conversion element.
  4. In the photoelectric conversion element according to claim 2 or 3,
    The p-type amorphous semiconductor layer is provided and a second p-type amorphous semiconductor layer, on the opposite side of the side where the intrinsic amorphous semiconductor layer is provided in the second p-type amorphous semiconductor layer It includes a third p-type amorphous semiconductor layer to be a,
    The acceptor concentration reaches its peak in the second p-type amorphous semiconductor layer, the photoelectric conversion element.
  5. In the photoelectric conversion device according to claim 4,
    The first p-type amorphous semiconductor layer in which the intrinsic amorphous semiconductor layer of the second p-type amorphous semiconductor layer is provided on the side which is provided, further comprising,
    The acceptor concentration of the first p-type amorphous semiconductor layer is lower than the acceptor concentration of the third p-type amorphous semiconductor layer, the photoelectric conversion element.
  6. The crystalline semiconductor is disposed in the tray,
    The intrinsic amorphous semiconductor layer is formed on the crystalline semiconductor,
    The p-type amorphous semiconductor layer formed on the intrinsic amorphous semiconductor layer,
    And unloading the intrinsic amorphous semiconductor layer and the laminate to form the p-type amorphous semiconductor layer on the crystalline semiconductor,
    Repeating the above steps by placing the following of the crystalline semiconductor with the same said tray, a manufacturing method of a photoelectric conversion element,
    Formation of the p-type amorphous semiconductor layer is formed by forming at acceptor concentration of a predetermined peak concentration, formed by reducing the acceptor concentration from the peak concentration, formation of the p-type amorphous semiconductor layer is Exit to manufacturing method of a photoelectric conversion element.
  7. In the photoelectric conversion device according to claims 2 to any one of 5,
    The intrinsic amorphous semiconductor layer and the p-type semiconductor layer and the transparent conductive film layer is provided on the back side, the photoelectric conversion element.
  8. In the photoelectric conversion element as claimed in claim 1,
    The crystalline semiconductor layer, the conductivity type is n-type,
    The conductive amorphous semiconductor layer, the conductivity type is n-type photoelectric conversion element.
  9. In the photoelectric conversion element according to claim 1 or 8,
    The concentration of the impurity is reduced stepwise toward the position of the interface between the transparent conductive layer from the position at which the peak, the photoelectric conversion element.
  10. In the photoelectric conversion element according to claim 1 or 8,
    The conductive amorphous semiconductor layer is provided with a first conductive amorphous semiconductor layer, on the opposite side of the side where the intrinsic amorphous semiconductor layer is provided in the first conductive amorphous semiconductor layer comprising a second conductive amorphous semiconductor layer to be a,
    The concentration of the impurity has a peak in the first conductive amorphous semiconductor layer, the photoelectric conversion element.
PCT/JP2013/070938 2012-09-27 2013-08-01 Photoelectric conversion element and method for manufacturing same WO2014050304A1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015156233A1 (en) * 2014-04-11 2015-10-15 シャープ株式会社 Photoelectric conversion device
WO2018116782A1 (en) * 2016-12-21 2018-06-28 パナソニックIpマネジメント株式会社 Solar cell and method for producing solar cell
WO2019031029A1 (en) * 2017-08-09 2019-02-14 株式会社カネカ Photoelectric conversion element production method

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892218A (en) * 1981-11-28 1983-06-01 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device
JPH0260172A (en) * 1988-08-25 1990-02-28 Sharp Corp Manufacture of solar cell
JPH02119126A (en) * 1989-08-25 1990-05-07 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device
JP2003324209A (en) * 2001-11-29 2003-11-14 Sanyo Electric Co Ltd Photovoltaic device and its manufacturing method
JP2008135556A (en) * 2006-11-28 2008-06-12 Sanyo Electric Co Ltd P-type amorphous silicon thin film, photovoltaic device, and manufacturing method for them
JP2011009754A (en) * 2010-07-12 2011-01-13 Hitachi Ltd Method of manufacturing solar cell
JP2012009685A (en) * 2010-06-25 2012-01-12 Kaneka Corp Method of manufacturing laminated photoelectric converter
JP2012151506A (en) * 2005-10-03 2012-08-09 Sharp Corp Method for manufacturing silicon-based thin film photoelectric conversion device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3702240B2 (en) * 2002-03-26 2005-10-05 三洋電機株式会社 Semiconductor device and manufacturing method thereof
JP4169671B2 (en) * 2003-09-24 2008-10-22 三洋電機株式会社 Method of producing a photovoltaic element

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892218A (en) * 1981-11-28 1983-06-01 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device
JPH0260172A (en) * 1988-08-25 1990-02-28 Sharp Corp Manufacture of solar cell
JPH02119126A (en) * 1989-08-25 1990-05-07 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device
JP2003324209A (en) * 2001-11-29 2003-11-14 Sanyo Electric Co Ltd Photovoltaic device and its manufacturing method
JP2012151506A (en) * 2005-10-03 2012-08-09 Sharp Corp Method for manufacturing silicon-based thin film photoelectric conversion device
JP2008135556A (en) * 2006-11-28 2008-06-12 Sanyo Electric Co Ltd P-type amorphous silicon thin film, photovoltaic device, and manufacturing method for them
JP2012009685A (en) * 2010-06-25 2012-01-12 Kaneka Corp Method of manufacturing laminated photoelectric converter
JP2011009754A (en) * 2010-07-12 2011-01-13 Hitachi Ltd Method of manufacturing solar cell

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015156233A1 (en) * 2014-04-11 2015-10-15 シャープ株式会社 Photoelectric conversion device
CN106062973A (en) * 2014-04-11 2016-10-26 夏普株式会社 Photoelectric conversion means
JPWO2015156233A1 (en) * 2014-04-11 2017-04-13 シャープ株式会社 The photoelectric conversion device
WO2018116782A1 (en) * 2016-12-21 2018-06-28 パナソニックIpマネジメント株式会社 Solar cell and method for producing solar cell
WO2019031029A1 (en) * 2017-08-09 2019-02-14 株式会社カネカ Photoelectric conversion element production method

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