JP2019179860A - Solar cell and method for manufacturing solar cell - Google Patents

Abstract

To provide a solar cell capable of further suppressing characteristic deterioration.SOLUTION: A solar cell 10 comprises a semiconductor substrate 20 including a first principal surface and a second principal surface facing the first principal surface in a back-to-back manner and having a first conductivity type, a first semiconductor layer 23 provided on the first principal surface and having the first conductivity type, and a second semiconductor layer 21 provided on the second principal surface and having a second conductivity type different from the first conductivity type. In a plan view, the semiconductor substrate 20 comprises a first region 50 in which the second semiconductor layer 21 is not formed over one side constituting a peripheral part of the semiconductor substrate 20.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a solar battery cell and a method for manufacturing a solar battery cell.

  2. Description of the Related Art Conventionally, solar cells have been developed as photoelectric conversion devices that convert light energy into electrical energy. Solar cells are expected to be a new energy source because they can convert inexhaustible sunlight directly into electricity, and because they have less environmental impact and are cleaner than fossil fuel power generation.

  The solar battery cell can be manufactured, for example, by dividing a large-area semiconductor substrate into a small-area semiconductor substrate. Patent Document 1 discloses a solar cell in which a decrease in characteristics (a decrease in power generation efficiency) when a large-area semiconductor substrate is divided into a small-area semiconductor substrate to produce a solar cell is suppressed.

Japanese Patent No. 4036880

  In the solar battery cell, it is desired that the characteristic deterioration is further suppressed.

  Then, an object of this invention is to provide the manufacturing method of the photovoltaic cell which can suppress a characteristic fall more, and a photovoltaic cell.

  In order to achieve the above object, a photovoltaic cell according to an aspect of the present invention is a semiconductor substrate having a first main surface and a second main surface facing away from the first main surface, the first conductivity type A first semiconductor layer having the first conductivity type provided on the first main surface, and a second conductivity type different from the first conductivity type provided on the second main surface. The semiconductor substrate has a first region in which the second semiconductor layer is not formed over one side constituting the outer peripheral portion of the semiconductor substrate in plan view.

  In order to achieve the above object, a solar cell according to an aspect of the present invention is a semiconductor substrate having a first main surface and a second main surface facing away from the first main surface, A semiconductor substrate having a conductivity type, a first semiconductor layer provided on the first main surface and including a dopant of the first conductivity type, and provided on the second main surface, different from the first conductivity type. A second semiconductor layer containing a dopant of two conductivity types, and the semiconductor substrate is a first region extending over one side constituting the outer peripheral portion of the semiconductor substrate in plan view, and the second semiconductor layer A concentration of the second conductivity type dopant contained in the first region is lower than the concentration of the second conductivity type dopant contained in the second semiconductor layer disposed in a region other than the first region; Have.

  Moreover, in order to achieve the said objective, the manufacturing method of the photovoltaic cell which concerns on 1 aspect of this invention is a semiconductor substrate which has a 1st main surface and the 2nd main surface facing away from the said 1st main surface, A first film forming step of forming a second semiconductor layer having a second conductivity type different from the first conductivity type on the second main surface of the semiconductor substrate having the first conductivity type; and the semiconductor substrate. Forming a first semiconductor layer having the first conductivity type on the first main surface, and forming a separation groove for separating the semiconductor substrate in the semiconductor substrate, A separation step of separating the semiconductor substrate along the separation groove, and in the first film formation step, at least a groove formation region of the semiconductor substrate including a position where the separation groove is formed in a plan view An undeposited region where the second semiconductor layer is not formed in part To.

  Moreover, in order to achieve the said objective, the manufacturing method of the photovoltaic cell which concerns on 1 aspect of this invention is a semiconductor substrate which has a 1st main surface and the 2nd main surface facing away from the said 1st main surface, A first film forming step of forming a second semiconductor layer having a second conductivity type different from the first conductivity type on the second main surface of the semiconductor substrate having the first conductivity type; and Forming a second film forming step for forming the first semiconductor layer having the first conductivity type on the first main surface; and a separation groove for separating the semiconductor substrate in the semiconductor substrate; A separation step of separating the semiconductor substrate along the separation groove. In the first film formation step, at least one of the groove formation regions of the semiconductor substrate including a position where the separation groove is formed in a plan view. In the portion, the first portion disposed in the at least part of the groove forming region The concentration of the second conductivity type dopant contained in the second semiconductor layer is disposed in a region other than the at least part of the groove forming region. A lower first semiconductor layer is formed.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the photovoltaic cell which can suppress a characteristic fall more, and a photovoltaic cell can be provided.

3 is a plan view of the solar battery cell according to Embodiment 1. FIG. It is sectional drawing of the photovoltaic cell which concerns on Embodiment 1 in the II-II line | wire of FIG. 3 is a flowchart showing a method for manufacturing a solar battery cell according to Embodiment 1. 5 is a cross-sectional view for explaining the method for manufacturing the solar battery cell according to Embodiment 1. FIG. It is another example of sectional drawing of the photovoltaic cell which concerns on Embodiment 1 in the II-II line | wire of FIG. FIG. 10 is a cross-sectional view for illustrating the method for manufacturing the solar battery cell according to a modification of the first embodiment. It is sectional drawing of the photovoltaic cell which concerns on Embodiment 2 corresponding to the II-II line | wire of FIG. 5 is a flowchart showing a method for manufacturing a solar battery cell according to Embodiment 2. FIG. 10 is a cross-sectional view for explaining the method for manufacturing the solar battery cell according to the second embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Each of the embodiments described below shows a specific example of the present invention. Therefore, the numerical values, shapes, materials, components, component arrangement, connection modes, steps, and order of steps shown in the following embodiments are merely examples, and are not intended to limit the present invention. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims showing the highest concept of the present invention are described as optional constituent elements.

  Each figure is a schematic diagram and is not necessarily illustrated strictly. Moreover, in each figure, the same code | symbol is attached | subjected to the substantially same structure, The overlapping description may be abbreviate | omitted or simplified.

  In addition, the description of “substantially **” is intended to include what is substantially recognized as **. For example, when “substantially orthogonal” is described as an example, not only completely orthogonal but also substantially orthogonal It is the intention including what is recognized as. In this specification, “substantially” means that a manufacturing error and a dimensional tolerance are included.

  Moreover, in each figure, a Z-axis direction is a direction perpendicular | vertical to the light-receiving surface of a photovoltaic cell, for example. The X-axis direction and the Y-axis direction are orthogonal to each other, and both are directions orthogonal to the Z-axis direction. For example, in the following embodiments, “plan view” means viewing from the Z-axis direction. Further, in the following embodiments, “cross-sectional view” means a cut in which the solar battery cell is cut at a surface orthogonal to the light receiving surface of the solar battery cell (for example, a surface defined by the Z axis and the X axis). This means that the surface is viewed from a direction (for example, the Y-axis direction) substantially orthogonal to the cut surface.

(Embodiment 1)
Hereinafter, the solar cell according to the present embodiment will be described with reference to FIGS.

[1-1. Solar cell configuration]
First, the structure of the photovoltaic cell according to the present embodiment will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a plan view showing a solar battery cell 10 according to the present embodiment. FIG. 1 is a plan view of the solar battery cell 10 viewed from the front surface (light receiving surface) side. FIG. 2 is a cross-sectional view of solar cell 10 according to the present embodiment taken along line II-II in FIG.

  As shown in FIG. 1, the planar view shape of the photovoltaic cell 10 is a substantially rectangular shape. For example, the solar battery cell 10 has a shape in which a 125 mm square square is missing. In addition, the shape of the photovoltaic cell 10 is not limited to a substantially rectangular shape.

  As shown in FIG. 2, the solar battery cell 10 has a semiconductor pn junction as a basic structure. As an example, a silicon substrate 20 and an n-type semiconductor layer sequentially formed on one main surface side of the silicon substrate 20. 23, an n-side electrode 24 and an n-side current collecting electrode 40, and a p-type semiconductor layer 21, a p-side electrode 22 and a p-side current collecting electrode 30 which are sequentially formed on the other main surface side of the silicon substrate 20. . In the present embodiment, the one main surface of the silicon substrate 20 is a surface on the main light receiving surface side of the solar battery cell 10. The main light receiving surface is a surface on which more than 50% of light incident on the solar battery cell 10 is incident when a solar battery module is constructed using the solar battery cell 10. In the present embodiment, the other main surface of the silicon substrate 20 is a surface facing away from one main surface in the silicon substrate 20. The silicon substrate 20 is an example of a semiconductor substrate, and one main surface of the silicon substrate 20 (a surface on the light receiving surface 11 side, also referred to as a surface) is an example of a first main surface, and the silicon substrate 20 The other main surface (the surface on the back surface 12 side, also referred to as the back surface) is an example of the second main surface.

  The silicon substrate 20 is a crystalline silicon substrate, for example, an n-type single crystal silicon substrate. The silicon substrate 20 is not limited to a single crystal silicon substrate (n-type single crystal silicon substrate or p-type single crystal silicon substrate), and may be a crystalline silicon substrate such as a polycrystalline silicon substrate. In the following description, the case where the silicon substrate 20 is an n-type single crystal silicon substrate will be described. In this specification, the n-type is also referred to as the first conductivity type, and the p-type is also referred to as the second conductivity type. For example, the silicon substrate 20 is a silicon substrate having a first conductivity type. For example, the planar shape of the silicon substrate 20 is substantially rectangular, and the thickness is, for example, 30 to 300 μm, preferably 150 μm or less.

  An uneven shape (not shown) called a texture structure in which a plurality of pyramids are two-dimensionally arranged may be formed on at least one of the front and back surfaces of the silicon substrate 20. In the solar battery cell 10 whose both surfaces are light receiving surfaces, a texture structure may be formed on the front and back surfaces of the silicon substrate 20. Thereby, since the photovoltaic cell 10 according to the present embodiment can effectively increase the optical path length of light in the silicon substrate 20, the light that contributes to power generation without increasing the thickness of the silicon substrate 20. Can increase absorption. For example, the solar cell 10 can effectively contribute light having a wavelength with a small absorption coefficient in the silicon substrate 20 to power generation.

  The n-type semiconductor layer 23 includes an i-type amorphous silicon layer 23i (intrinsic amorphous silicon layer) and an n-type amorphous silicon layer 23n. The i-type amorphous silicon layer 23 i and the n-type amorphous silicon layer 23 n are stacked on the silicon substrate 20 in this order on the surface of the silicon substrate 20 on the light receiving surface 11 side. In addition, the lamination | stacking here means laminating | stacking in the Z-axis plus direction.

The i-type amorphous silicon layer 23i is a passivation layer disposed between the silicon substrate 20 and the n-type amorphous silicon layer 23n. The i-type amorphous silicon layer 23i can be made of amorphous silicon having a dopant content of less than 1 × 10 ¹⁹ cm ⁻³ . The n-type amorphous silicon layer 23 n is a semiconductor layer having the same conductivity type as that of the silicon substrate 20. The n-type amorphous silicon layer 23n can be made of, for example, amorphous silicon having a content of n-type dopants such as phosphorus (P) and arsenic (As) of 5 × 10 ¹⁹ cm ⁻³ or more. The n-type semiconductor layer 23 is an example of a first semiconductor layer. The n-type semiconductor layer 23 only needs to include at least the n-type amorphous silicon layer 23n.

  The p-type semiconductor layer 21 includes an i-type amorphous silicon layer 21i (intrinsic amorphous silicon layer) and a p-type amorphous silicon layer 21p. The i-type amorphous silicon layer 21 i and the p-type amorphous silicon layer 21 p are stacked on the silicon substrate 20 in this order on the surface on the back surface 12 side of the silicon substrate 20. In addition, the lamination | stacking here means laminating | stacking in a Z-axis minus direction. The i-type amorphous silicon layer 21i is an example of an i-type amorphous semiconductor layer, and the p-type amorphous silicon layer 21p is an example of a second conductivity type amorphous semiconductor layer.

The i-type amorphous silicon layer 21i is a passivation layer disposed between the silicon substrate 20 and the p-type amorphous silicon layer 21p. The p-type amorphous silicon layer 21 p is a semiconductor layer having a conductivity type different from that of the silicon substrate 20. In the p-type amorphous silicon layer 21p, for example, the content of a p-type dopant such as boron (B) is 5 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²² cm ⁻³ , and preferably 5 × 10 ²⁰ cm. ^{-3 to} 5 × 10 ²¹ cm ^-3 of amorphous silicon or the like can be used. The p-type semiconductor layer 21 is an example of a second semiconductor layer. In the present embodiment, the p-type semiconductor layer 21 only needs to include at least the p-type amorphous silicon layer 21p.

  This embodiment is characterized by the shape of the p-type semiconductor layer 21. The silicon substrate 20 has a region where the p-type semiconductor layer 21 is not formed in at least a part of the outer peripheral region of the silicon substrate 20. 1 and 2 show an example in which the p-type semiconductor layer 21 is not formed in the outer region 50 including the outer peripheral portion of the silicon substrate 20. The outer region 50 is a frame-like region in plan view. Note that the p-type semiconductor layer 21 is not formed means that at least the p-type amorphous silicon layer 21p among the i-type amorphous silicon layer 21i and the p-type amorphous silicon layer 21p included in the p-type semiconductor layer 21. Is not formed. In the present embodiment, the p-type amorphous silicon layer 21p of the i-type amorphous silicon layer 21i and the p-type amorphous silicon layer 21p is not formed in the outer region 50. That is, in plan view, the i-type amorphous silicon layer 21 i is equal in size to the silicon substrate 20, and the p-type amorphous silicon layer 21 p is smaller than the silicon substrate 20. The p-type amorphous silicon layer 21p is smaller than the n-type amorphous silicon layer 23n in plan view.

  The p-type amorphous silicon layer 21 p is disposed in a region other than the outer region 50 on the silicon substrate 20. Specifically, the p-type amorphous silicon layer 21 p is disposed in the inner region 60. In the present embodiment, the inner region 60 is a region surrounded by the outer region 50. The outer region 50 is an example of a first region where the p-type amorphous silicon layer 21p is not formed. The silicon substrate 20 has a first region where the p-type amorphous silicon layer 21p is not formed.

  In the above description, the example in which the outer region 50 is a region including the outer periphery of the silicon substrate 20 has been described. However, the present invention is not limited to this. The outer region 50 may be a region including at least a part of the outer peripheral portion of the silicon substrate 20. The outer region 50 may have, for example, a first region where the p-type amorphous silicon layer 21p is not formed over one side constituting the outer peripheral portion of the silicon substrate 20 in plan view. That is, the outer region 50 may be a linear region including the one side.

The n-side electrode 24 and the p-side electrode 22 are, for example, transparent conductive layers (TCO films) made of a transparent conductive material. The transparent conductive layer is, for example, at least one of metal oxides such as indium oxide (In ₂ O ₃ ), zinc oxide (ZnO), tin oxide (SnO ₂ ), and titanium oxide (TiO ₂ ) having a polycrystalline structure. It is preferable that it is comprised including seeds. These metal oxides include tin (Sn), zinc (Zn), tungsten (W), antimony (Sb), titanium (Ti), aluminum (Al), cerium (Ce), gallium (Ga), etc. For example, ITO in which In ₂ O ₃ is doped with Sn is particularly preferable. The density | concentration of dopa dough can be 0-20 mass%.

  In the present embodiment, at least a part of the p-side electrode 22 is disposed in contact with the i-type amorphous silicon layer 21i. Specifically, the p-side electrode 22 is disposed in contact with the i-type amorphous silicon layer 21i in the first region. The film thickness (thickness in the Z-axis direction) of the portion of the p-side electrode 22 disposed on the outer region 50 of the silicon substrate 20 is the portion of the p-side electrode disposed on the inner region 60 of the silicon substrate 20. Thicker than film thickness. The film thickness of the portion of the p-side electrode 22 disposed on the outer region 50 of the silicon substrate 20 is, for example, the film thickness of the portion of the p-side electrode disposed on the inner region 60 of the silicon substrate 20 and the p-type. The total thickness of the amorphous silicon layer 21p is approximately equal to the total thickness. The n-side electrode 24 is not in contact with the i-type amorphous silicon layer 21 i or the silicon substrate 20.

  The p-side collector electrode 30 is an electrode that is provided on the p-type semiconductor layer 21 and collects received light charges (holes) generated in the light receiving region on the silicon substrate 20. The p-side collector electrode 30 is connected to, for example, a plurality of finger electrodes 31 formed linearly in a direction orthogonal to the extending direction of a wiring member (not shown), and the finger electrodes 31 and fingers And a plurality of bus bar electrodes 32 formed linearly along a direction orthogonal to the electrode 31 (for example, a direction in which the wiring member extends).

  The n-side collector electrode 40 is an electrode that is provided on the n-type semiconductor layer 23 and collects received light charges (electrons) generated in the light receiving region on the silicon substrate 20. The n-side collector electrode 40 includes, for example, a plurality of finger electrodes 41 formed linearly in a direction orthogonal to the extending direction of a wiring member (not shown), and connected to these finger electrodes 41 and finger And a plurality of bus bar electrodes 42 formed in a straight line along a direction orthogonal to the electrode 41 (for example, a direction in which the wiring member extends).

  The number of finger electrodes 31 and 41 and bus bar electrodes 32 and 42 is not particularly limited. One or more finger electrodes 31 and 41 and bus bar electrodes 32 and 42 may be provided. For example, the number of bus bar electrodes 32 and 42 may be the same as the number of wiring members, for example. In the present embodiment, there are three. Moreover, a wiring member is a tab wiring which electrically connects two adjacent photovoltaic cells 10 when forming a solar cell module.

  The p-side collector electrode 30 and the n-side collector electrode 40 are made of a low resistance conductive material such as silver (Ag). For example, the p-side collector electrode 30 and the n-side collector electrode 40 are screen-printed in a predetermined pattern with a resin-type conductive paste (silver paste or the like) in which a conductive filler such as silver particles is dispersed in a binder resin. Can be formed.

  As described above, the solar battery cell 10 according to the present embodiment is, for example, a heterojunction solar battery cell. Thereby, defects at the interface between the silicon substrate 20 and the n-type semiconductor layer 23 and the interface between the silicon substrate 20 and the p-type semiconductor layer 21 (heterojunction interface) are reduced. Therefore, the photoelectric conversion efficiency of the solar battery cell 10 can be improved.

  Note that the passivation layer is not limited to the i-type amorphous silicon layers 21i and 23i, and may be a silicon oxide layer, a silicon nitride layer, or the like, or may not be provided.

[1-2. Manufacturing method of solar cell]
Next, the manufacturing method of the photovoltaic cell 10 according to the present embodiment will be described with reference to FIGS. Here, an example in which two solar cells are formed from a large silicon substrate will be described.

  FIG. 3 is a flowchart showing a method for manufacturing solar cell 10 according to the present embodiment. FIG. 4 is a cross-sectional view for explaining the method for manufacturing solar battery cell 10 according to the present embodiment.

  As shown in FIG. 3, first, a step (S10) of preparing a semiconductor substrate for preparing the silicon substrate 20a is performed. In the present embodiment, an n-type single crystal silicon substrate is prepared as the silicon substrate 20a. The silicon substrate 20a prepared here is larger than the silicon substrate 20 described above.

  FIG. 4A is a cross-sectional view of the silicon substrate 20a prepared in step S10. The silicon substrate 20a may have a texture structure formed on at least one main surface. The texture structure can be formed, for example, by anisotropically etching the (100) surface of the silicon substrate 20 using a potassium hydroxide (KOH) aqueous solution.

Referring again to FIG. 3, next, a step of forming an i-type amorphous semiconductor layer for forming i-type amorphous silicon layer 21i on the second main surface (Z-axis minus side surface) of silicon substrate 20a. (S11) is performed. For example, the i-type amorphous silicon layer 21i is formed by plasma enhanced chemical vapor deposition (PECVD), Cat-CVD (Catalytic Chemical Vapor Deposition), sputtering, or the like. PECVD may use any technique such as RF plasma CVD, high-frequency VHF plasma CVD, or microwave plasma CVD. In the present embodiment, for example, the i-type amorphous silicon layer 21i is formed using an RF plasma CVD method. Specifically, a gas obtained by diluting a silicon-containing gas such as silane (SiH ₄ ) with hydrogen is supplied to the film-forming chamber, and RF frequency power is applied to the parallel plate electrodes disposed in the film-forming chamber. Is turned into plasma. By supplying this plasma gas to the second main surface of the silicon substrate 20a heated to 150 ° C. or higher and 250 ° C. or lower, the i-type amorphous silicon layer 21i is formed.

  FIG. 4B is a cross-sectional view of the silicon substrate 20a on which the i-type amorphous silicon layer 21i is formed in step S11. As shown in FIG. 4B, an i-type amorphous silicon layer 21i is formed on the second main surface of the silicon substrate 20a. In the present embodiment, i-type amorphous silicon layer 21i is formed on the entire second main surface of silicon substrate 20a.

  Referring again to FIG. 3, next, a step (S12) of forming a p-type amorphous semiconductor layer for forming a p-type amorphous silicon layer 21p on the second main surface of the silicon substrate 20a is performed. Specifically, a p-type amorphous silicon layer 21p is stacked on the i-type amorphous silicon layer 21i. In step S12, a mask is used to form the first region of the solar battery cell 10 described above (that is, the region where the p-type amorphous silicon layer 21p is not formed). The mask has an opening in a region corresponding to a region where the p-type amorphous silicon layer 21p is formed. Thereby, the p-type amorphous silicon layer 21p is not formed in the region covered with the mask.

The p-type amorphous silicon layer 21p is formed by PECVD, Cat-CVD, sputtering, or the like. For PECVD, an RF plasma CVD method is applied. Specifically, a gas mixture obtained by diluting a silicon-containing gas such as silane (SiH ₄ ) and a p-type dopant containing gas such as diborane (B ₂ H ₆ ) with hydrogen is supplied to the film-forming chamber. An RF high frequency power is applied to the arranged parallel plate electrodes to turn the mixed gas into plasma. Note that the concentration of diborane (B ₂ H ₆ ) in the mixed gas is, for example, 1%. By supplying this plasma gas to the second main surface of the silicon substrate 20a heated to 150 ° C. or higher and 250 ° C. or lower, a p-type amorphous silicon layer is formed on the i-type amorphous silicon layer 21i. 21p is formed. Since the film formation is performed using the mask as described above, the p-type amorphous silicon layer 21p is not formed on the entire surface of the i-type amorphous silicon layer 21i. That is, an undeposited region where the p-type amorphous silicon layer 21p is not formed is formed on the second main surface of the silicon substrate 20a.

  As described above, in step S12, a semiconductor layer having a conductivity type (for example, the other of n-type and p-type) different from the conductivity type (for example, one of n-type and p-type) of the silicon substrate 20a is applied to the silicon substrate. A film is formed on 20a. Steps S11 and S12 are an example of a first film forming process.

  FIG. 4C is a cross-sectional view of the silicon substrate 20a on which the p-type amorphous silicon layer 21p is formed on the second main surface in step S12. As shown in FIG. 4C, a p-type amorphous silicon layer 21p is formed on the second main surface of the silicon substrate 20a. In the present embodiment, p-type amorphous silicon layer 21p is formed on a part of the second main surface of silicon substrate 20a. In other words, the silicon substrate 20a has an undeposited region 70 where the p-type amorphous silicon layer 21p is not formed. In the non-deposited region 70, the i-type amorphous silicon layer 21i is exposed.

  In step S12, the example in which the non-film formation region 70 is formed using a mask has been described. However, the present invention is not limited to this. For example, in step S12, the p-type amorphous silicon layer 21p is formed without using a mask, and the p-type amorphous silicon layer 21p is formed on the entire surface of the i-type amorphous silicon layer 21i. The non-film formation region 70 may be formed by removing a part of the amorphous silicon layer 21p by etching or the like.

  Referring again to FIG. 3, next, a step of forming an i-type amorphous semiconductor layer for forming i-type amorphous silicon layer 23i on the first main surface (Z-axis plus side surface) of silicon substrate 20a. (S13) is performed. Step S13 is the same as step S11, and a description thereof will be omitted. Then, a step (S14) of forming an n-type amorphous semiconductor layer for forming the n-type amorphous silicon layer 23n on the first main surface of the silicon substrate 20a is performed. Specifically, an n-type amorphous silicon layer 23n is stacked on the i-type amorphous silicon layer 23i.

The n-type amorphous silicon layer 23n is formed by PECVD, Cat-CVD, sputtering, or the like. For PECVD, an RF plasma CVD method is applied. Specifically, a mixed gas obtained by diluting a silicon-containing gas such as silane (SiH ₄ ) and an n-type dopant-containing gas such as phosphine (PH ₃ ) with hydrogen is supplied to the film forming chamber, and is disposed in the film forming chamber. RF high frequency power is applied to the parallel plate electrodes, and the mixed gas is turned into plasma. The plasma gas is supplied to the first main surface of the silicon substrate 20a heated to 150 ° C. or more and 250 ° C. or less, so that the n-type amorphous silicon is formed on the i-type amorphous silicon layer 23i. Layer 23n is formed.

  In step S14, the mask as in step S12 is not used. That is, the n-type amorphous silicon layer 23n is formed on the entire first main surface. Thereby, the n-type semiconductor layer 23 is formed on the first main surface of the silicon substrate 20a.

  FIG. 4D is a cross-sectional view of the silicon substrate 20a on which the n-type semiconductor layer 23 is formed on the first main surface in steps S13 and S14. As shown in FIG. 4D, the n-type semiconductor layer 23 is also formed in a region on the first main surface that overlaps with the non-deposition region 70 in plan view. That is, the n-type semiconductor layer 23 has a larger area than the p-type amorphous silicon layer 21p. Steps S13 and S14 are an example of a second film forming process.

  Referring to FIG. 3 again, next, a step (S15) of forming a transparent electrode film is performed. In step S15, the p-side electrode 22 and the n-side electrode 24 are formed. For example, first, the n-side electrode 24 is formed on the n-type amorphous silicon layer 23n, and the p-side electrode 22 is formed on the p-type amorphous silicon layer 21p. Specifically, a transparent conductive oxide such as indium tin oxide (ITO) is formed on the n-type amorphous silicon layer 23n and the p-type amorphous silicon layer 21p by vapor deposition or sputtering. Film.

  FIG. 4E is a cross-sectional view of the silicon substrate 20a on which the p-side electrode 22 and the n-side electrode 24 are formed in step S15. As shown in FIG. 4E, the p-side electrode 22 is formed so as to fill a space between adjacent p-type amorphous silicon layers 21p. In the p-side electrode 22, the thickness of the portion that overlaps the non-film formation region 70 in plan view is larger than the thickness of the other regions.

  Referring to FIG. 3 again, next, a separation step is performed for separating the silicon substrate 20a into a silicon substrate 20 of a predetermined size. In the separation step, for example, a separation groove for separating the silicon substrate 20a is formed in the silicon substrate 20a, and the silicon substrate 20a is separated along the separation groove. Thereby, a silicon substrate 20 smaller than the silicon substrate 20a is formed.

  The separation step includes a step of forming a separation groove by irradiating a laser from the second main surface side of the silicon substrate 20a (S16) and a step of separating the silicon substrate 20a (S17).

  In the step of forming the separation groove, the separation groove is formed by irradiating the surface (second main surface) on which the p-type semiconductor layer 21 of the silicon substrate 20a is formed with a laser. In the step of separating the silicon substrate 20a, the silicon substrate 20a is divided along the separation groove by applying stress to the silicon substrate 20a. Steps S16 and S17 are an example of a separation process.

  FIG. 4F is a cross-sectional view of the silicon substrate 20a on which the separation groove 80 is formed in step S16. As shown in FIG. 4F, the isolation trench 80 is formed in a region where the p-type amorphous silicon layer 21p is not formed (that is, an undeposited region 70). That is, the laser is irradiated to a region where the pn junction is not formed in the silicon substrate 20a. In other words, in the step of forming the p-type amorphous semiconductor layer (S12), the groove forming region of the silicon substrate 20a including the position where the isolation groove 80 is formed (that is, the region irradiated with the laser) in plan view. An undeposited region 70 in which the p-type amorphous silicon layer 21p is not formed is formed in at least a part of the region.

  The isolation groove 80 is formed with a depth that does not penetrate the silicon substrate 20a. The depth of the separation groove 80 (laser depth) is 25% or less, 50% or less, or 75% or less with respect to the thickness of the silicon substrate 20a. FIG. 4 (f) shows an example of about 25%. The depth here is the length in the Z-axis direction.

  The spot diameter of the laser is 10 μm or more and 1 cm or less, preferably 500 μm or more and 5 mm or less, and more preferably 1 mm or more and 2 mm or less. The laser conditions may be appropriately determined. For example, the wavelength of the laser light is 532 nm to 1090 nm, the power is 0.1 W to 5 W, and the irradiation time is 10 fsec to 100 nsec. Note that the width (length in the X-axis direction) of the undeposited region 70 in a sectional view is larger than the laser spot diameter. The carrier mobility is, for example, 1 mm.

  FIG. 4G is a cross-sectional view of the silicon substrate 20a cut along the separation groove 80 in step S17. As shown in FIG. 4G, two solar cells 10 are formed by cleaving along the separation groove 80.

  In the step of forming the electrode, the example in which the p-side electrode 22 is formed in a portion overlapping with the non-film formation region 70 in plan view is described, but the present invention is not limited to this. A solar battery cell in the case where the p-side electrode 22 is not formed in the undeposited region 70 in the step of forming the transparent conductive film will be described with reference to FIG.

  FIG. 5 is another example of a cross-sectional view of solar cell 10a according to the present embodiment, taken along line II-II in FIG.

  As shown in FIG. 5, the p-side electrode 22 a may not be formed in the outer region 50. In other words, the p-side electrode 22a may not be formed in at least a part of the region irradiated with the laser. The p-side electrode 22a may be formed, for example, in a region overlapping with the p-type amorphous silicon layer 21p in plan view (that is, a region where a pn junction is formed). In this case, at least a part of the i-type amorphous silicon layer 21i may be exposed.

  Although not shown, the i-type amorphous silicon layer 21 i may not be formed in the outer region 50. In other words, the i-type amorphous silicon layer 21i may not be formed in at least a part of the region irradiated with the laser. The i-type amorphous silicon layer 21i may be formed, for example, in a region overlapping with the p-type amorphous silicon layer 21p in plan view.

[1-3. Effect etc.]
As described above, the solar cells 10 and 10a according to the present embodiment are the silicon substrate 20 having the first main surface and the second main surface facing away from the first main surface, and silicon having n-type. The substrate 20 includes an n-type semiconductor layer 23 provided on the first main surface and having n-type, and a p-type semiconductor layer 21 provided on the second main surface and having p-type. And the silicon substrate 20 has the outer area | region 50 in which the p-type semiconductor layer 21 is not formed over the one side which comprises the outer peripheral part of the said silicon substrate 20 in planar view.

  Thus, when the solar cells 10 and 10a are formed by cleaving the large silicon substrate 20a, there is a region where a pn junction is not formed in at least a part of the portion to be cleaved. By producing the solar cell 10 by cleaving the region, it is possible to suppress a decrease in output caused by the p-type semiconductor layer 21 peeling off at the time of cleaving and the silicon substrate 20 and the p-type semiconductor layer 21 leaking. can do. Therefore, the photovoltaic cell 10 and 10a which concerns on this Embodiment can suppress a characteristic fall more. Hereinafter, the solar battery cells 10 and 10a are also referred to as the solar battery cell 10 or the like.

  The p-type semiconductor layer 21 has an i-type amorphous silicon layer 21i laminated on the first main surface and a p-type amorphous silicon layer 21p laminated on the i-type amorphous silicon layer 21i. Of the i-type amorphous silicon layer 21 i and the p-type amorphous silicon layer 21 p, at least the p-type amorphous silicon layer 21 p is disposed in a region on the silicon substrate 20 excluding the outer region 50.

  Thus, when the p-type semiconductor layer 21 is formed of a plurality of layers, the p-type amorphous silicon layer 21p that causes a leak is not formed in the outer region 50, so that the silicon substrate 20 and the p-type amorphous layer 21 are formed. It is possible to effectively suppress a decrease in output due to leakage of the silicon layer 21p.

  The silicon substrate 20 has a substantially rectangular shape, and the outer region 50 includes the outer peripheral portion of the silicon substrate.

  Thereby, the p-type amorphous silicon layer 21p is peeled off at the time of cleaving, and the output reduction due to leakage of the silicon substrate 20 and the p-type amorphous silicon layer 21p can be further suppressed. Therefore, the photovoltaic cell 10 grade | etc., Which concerns on this Embodiment can further suppress a characteristic fall.

  Further, as described above, the method for manufacturing the solar battery cell 10 or the like according to the present embodiment is a silicon substrate 20a having a first main surface and a second main surface facing away from the first main surface, A first film forming step (S11 and S12) for forming a p-type semiconductor layer 21 having a p-type on a second main surface of a silicon substrate 20a having an n-type, and a first main surface of the silicon substrate 20a, A second film formation step (S13 and S14) for forming the n-type semiconductor layer 23 having n-type, a separation groove 80 for separating the silicon substrate 20a in the silicon substrate 20a, and the separation groove 80 And a separation step (S16 and S17) for separating the silicon substrate 20a. In the second film formation step, the non-film formation region 70 in which the p-type semiconductor layer 21 is not formed in at least a part of the groove formation region of the silicon substrate 20a including the position where the separation groove 80 is formed in plan view. Form.

  Thereby, there exists an effect similar to the photovoltaic cell 10 grade | etc.,. Since the silicon substrate 20a is separated in the region including the undeposited region 70, the output decrease caused by the p-type semiconductor layer 21 peeling off at the time of cleaving and the silicon substrate 20 and the p-type semiconductor layer 21 leaking is suppressed. can do.

  Further, the separation groove 80 is formed by irradiating the second main surface of the silicon substrate 20a with a laser.

  Thereby, compared with the case where a laser is irradiated from the 1st main surface (light-receiving surface) side, more electric power generation areas of the 1st semiconductor layer arrange | positioned at the light-receiving surface side can be ensured. For example, when the laser is irradiated from the first main surface side, the effective power generation area is reduced by the deterioration of the first semiconductor layer due to the heat generated by the laser irradiation. By irradiating the laser from the second main surface side, the reduction in the power generation area can be suppressed. Therefore, according to the method for manufacturing solar battery cell 10 and the like according to the present embodiment, it is possible to further suppress deterioration in characteristics caused by dividing silicon substrate 20a.

(Modification of Embodiment 1)
Hereinafter, a solar battery cell according to a modification of the first embodiment will be described with reference to FIG. In this modification, differences from the first embodiment will be mainly described.

  FIG. 6 is a cross-sectional view for explaining the method for manufacturing solar battery cell 100 according to the modification of the first embodiment. In addition, the manufacturing method of the photovoltaic cell 100 is the same as that of FIG. 6 (a) to 6 (c) are the same as FIGS. 4 (a) to 4 (c) of the first embodiment, and a description thereof is omitted.

  FIG. 6D is a cross-sectional view of the silicon substrate 20a in which the n-type semiconductor layer 123 is formed on the first main surface (the surface on the positive side of the Z axis of the silicon substrate 20a) in steps S13 and S14. As shown in FIG. 6D, the n-type semiconductor layer 123 includes an i-type amorphous silicon layer 23i and an n-type amorphous silicon layer 123n stacked on the i-type amorphous silicon layer 23i. And have. In this modification, an n-type amorphous silicon layer 123n is formed on a part of the first main surface of the silicon substrate 20a. In other words, the silicon substrate 20a has an undeposited region 170 where the n-type amorphous silicon layer 123n is not formed. In the undeposited region 170, the i-type amorphous silicon layer 23i is exposed.

  As described above, in step S14, the non-film formation region 170 in which the n-type amorphous silicon layer 123n is not formed is formed on the silicon substrate 20a. The non-film formation region 170 may be a region overlapping the non-film formation region 70 in plan view. Note that the non-film-forming region 170 forms a second region (the outer region 150 shown in FIG. 6G) where the n-type amorphous silicon layer 123n is not formed in the solar battery cell 100.

  In step S14, a mask for forming the second region of solar cell 100 described above (that is, a region where n-type amorphous silicon layer 123n is not formed) is used. The mask has an opening in a region corresponding to a region where the n-type amorphous silicon layer 123n is formed. Thus, the n-type amorphous silicon layer 123n is not formed in the region covered with the mask.

  Note that although an example in which the non-film formation region 170 is formed using a mask has been described in step S14, the present invention is not limited to this. For example, after forming the n-type amorphous silicon layer 123n without using a mask in step S14 and forming the n-type amorphous silicon layer 123n on the entire surface of the i-type amorphous silicon layer 23i, the n-type amorphous silicon layer 123n is formed. The non-film formation region 170 may be formed by removing a part of the amorphous silicon layer 123n by etching or the like.

  FIG. 6E is a cross-sectional view of the silicon substrate 20a on which the p-side electrode 22 and the n-side electrode 24 are formed in step S15. As shown in FIG. 6E, the n-side electrode 24 is formed so as to fill a space between adjacent n-type amorphous silicon layers 123n. In the n-side electrode 24, the portion of the n-side electrode 24 that overlaps the non-deposited region 170 in plan view is thicker than the other portions.

  FIG. 6F is a cross-sectional view of the silicon substrate 20a on which the separation groove 180 is formed in step S16. As shown in FIG. 6F, the separation groove 180 is formed on the first main surface (the surface on the Z-axis plus side) of the silicon substrate 20a. The isolation trench 180 is formed in a region where the p-type amorphous silicon layer 21p and the n-type amorphous silicon layer 123n are not formed (that is, a region where the non-film-formed regions 70 and 170 overlap in plan view). The That is, the laser is irradiated from the first main surface side to a region where the pn junction of the silicon substrate 20a is not formed. In other words, in the step of forming the n-type amorphous semiconductor layer (S14), the groove forming region of the silicon substrate 20a including the position where the isolation groove 180 is formed (that is, the region irradiated with the laser) in plan view. An undeposited region 170 in which the n-type amorphous silicon layer 123n is not formed is formed in at least a part of the region.

  FIG. 6G is a cross-sectional view of the silicon substrate 20a cut along the separation groove 180 in step S17. As shown in (g) of FIG. 6, two solar cells 100 are formed by cleaving along the separation groove 180. A pn junction is not formed in at least a part of the portion to be cut of the silicon substrate 20a. The solar cell 10 has an outer region 50 in which the p-type amorphous silicon layer 21p is not formed on the second main surface (Z-axis negative side surface) of the silicon substrate 20, and the first main surface of the silicon substrate 20 It has an outer region 150 where the n-type amorphous silicon layer 123n is not formed. The outer area 150 is an example of a second area.

  In the step of forming the transparent electrode film, the example in which the n-side electrode 24 is formed in a portion overlapping with the non-film formation region 170 in plan view is described, but the present invention is not limited to this. In the step of forming the transparent electrode film, the n-side electrode 24 may not be formed in the non-deposition region 170. For example, the n-side electrode 24 may be formed in a region overlapping the n-type amorphous silicon layer 123n in plan view. In this case, at least a part of the i-type amorphous silicon layer 23i may be exposed.

  Although not shown, the i-type amorphous silicon layer 23 i may not be formed in the non-film formation region 170. In other words, the i-type amorphous silicon layer 23i may not be formed in at least a part of the region irradiated with the laser.

  As described above, solar cell 100 according to the present embodiment further includes outer region 150 in which n-type semiconductor layer 23 is not formed over one side constituting the outer peripheral portion of silicon substrate 20 in plan view.

  Thereby, even when the laser is irradiated from the first semiconductor layer side, the output decrease due to the p-type semiconductor layer 21 being peeled off and the silicon substrate 20 and the p-type semiconductor layer 21 leaking is suppressed. can do. Therefore, the solar cell 100 according to the present embodiment can further suppress the characteristic deterioration. Further, the portion of the n-type amorphous silicon layer 123n that is deteriorated by laser irradiation can be removed in advance.

(Embodiment 2)
Hereinafter, the solar battery cell according to the present embodiment will be described with reference to FIGS. In the present embodiment, differences from the first embodiment will be mainly described.

[2-1. Solar cell configuration]
First, the configuration of the solar battery cell according to the present embodiment will be described with reference to FIG.

  FIG. 7 is a cross-sectional view of solar cell 200 according to the present embodiment, corresponding to line II-II in FIG. Solar cell 200 according to the present embodiment is different from solar cell 10 according to Embodiment 1 in the configuration of the p-type semiconductor layer.

  As shown in FIG. 7, the p-type semiconductor layer 221 of the solar cell 200 according to the present embodiment includes an i-type amorphous silicon layer 21i, a p-type amorphous silicon layer 221p, and a p-type non-layer. A crystalline silicon layer 222p is provided. The p-type amorphous silicon layers 221p and 222p are stacked in different regions on the i-type amorphous silicon layer 21i. When the solar battery cell 200 is viewed in plan, the p-type amorphous silicon layers 221p and 222p are arranged at positions that do not overlap each other. Specifically, the p-type amorphous silicon layer 221p is disposed in the inner region 60, and the p-type amorphous silicon layer 222p is disposed in the outer region 50. The outer region 50 is an example of a first region.

The p-type amorphous silicon layers 221p and 222p can be made of, for example, amorphous silicon having a p-type dopant concentration (content) of 5 × 10 ¹⁹ cm ⁻³ or more, such as boron (B). The concentration of the p-type dopant is different. The concentration of the p-type dopant in the p-type amorphous silicon layer 222p is lower than the concentration of the p-type dopant in the p-type amorphous silicon layer 221p. For example, the concentration of the p-type dopant in the p-type amorphous silicon layer 222p is 5 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ , and the concentration of the p-type dopant in the p-type amorphous silicon layer 221p Is 5 × 10 ²⁰ cm ^{−3 to} 5 × 10 ²¹ cm ⁻³ .

[2-2. Manufacturing method of solar cell]
Next, a method for manufacturing solar battery cell 200 according to the present embodiment will be described with reference to FIGS.

  FIG. 8 is a flowchart showing a method for manufacturing solar cell 200 according to the present embodiment. FIG. 9 is a cross-sectional view for explaining the method for manufacturing solar cell 200 according to the present embodiment.

  Steps S20 and S21 in FIG. 8 are the same as steps S10 and S11 shown in FIG. Moreover, (a) in FIG. 9 and (b) in FIG. 9 are the same as (a) in FIG. 4 and (b) in FIG.

  As shown in FIG. 8, after step S21, p-type amorphous semiconductor layers for forming p-type amorphous silicon layers 221p and 222p on the other main surface (an example of the second main surface) of the silicon substrate 20a are formed. A forming step (S22) is performed. In step S22, p-type amorphous silicon layers 221p and 222p are stacked on the i-type amorphous silicon layer 21i so as not to overlap each other. That is, regions having different p-type dopant concentrations are formed on the i-type amorphous silicon layer 21i.

  In step S22, a mask is used to form the first region of the solar battery cell 200 described above (that is, the region where the p-type dopant concentration is low in the p-type semiconductor layer 221). For example, the mask has an opening in a region corresponding to a region where the p-type amorphous silicon layer 221p having a high p-type dopant concentration is formed. By performing film formation using the mask, a film containing a p-type dopant is formed only in a region corresponding to the opening. Thereafter, the mask is removed, and film formation is performed again. Thereby, the region where the film is formed twice has a high p-type dopant concentration, and the region where the film is formed once has a lower p-type dopant concentration than the region where the film is formed twice. That is, the p-type amorphous silicon layers 221p and 222p are formed by film formation using a mask. Note that the method of forming the p-type amorphous silicon layers 221p and 222p (for example, PECVD) is the same as that of the p-type amorphous silicon layer 21p, and the description thereof is omitted.

  As described above, in step S22, two types of semiconductor layers different in conductivity type (for example, one of n-type and p-type) from the conductivity type (for example, one of n-type and p-type) of the silicon substrate 20a are formed. A film is formed on the silicon substrate 20a at a dopant concentration. Note that the step of forming the p-type amorphous semiconductor layer (S22) is an example of a first film formation step.

  FIG. 9C is a cross-sectional view of the silicon substrate 20a in which the p-type amorphous silicon layers 221p and 222p are formed on the second main surface (the surface on the negative side of the Z axis of the silicon substrate 20a) in step S22. . As shown in FIG. 9C, p-type amorphous silicon layers 221p and 222p are formed on the second main surface of the silicon substrate 20a. In the present embodiment, p-type amorphous silicon layers 221p and 222p are formed on a part of the second main surface of the silicon substrate 20a. The p-type amorphous silicon layers 221p and 222p are arranged in contact with each other at least partially. At the time of step S22, for example, the p-type amorphous silicon layer 222p is disposed between the p-type amorphous silicon layer 221p.

  Referring to FIG. 8 again, next, Steps S23 to S25 are performed, which are the same as Steps S13 to S15 of FIG. Further, (d) in FIG. 9 and (e) in FIG. 9 are the same as (d) in FIG. 4 and (e) in FIG. Steps S23 and S24 are an example of a second film forming process.

  Next, a separation process for separating the silicon substrate 20a into silicon substrates 20 of a predetermined size is performed. In the separation step, for example, a separation groove for separating the silicon substrate 20a is formed in the silicon substrate 20a, and the silicon substrate 20a is separated along the separation groove. Thereby, a silicon substrate 20 smaller than the silicon substrate 20a is formed.

  The separation step includes a step of forming a separation groove by irradiating a laser from the second main surface side of the silicon substrate 20a (S26) and a step of separating the silicon substrate 20a (S27).

  In the step of forming the separation groove, the separation groove is formed by irradiating the surface (second main surface) on which the p-type amorphous silicon layers 221p and 222p of the silicon substrate 20a are formed with a laser. In the step of separating the silicon substrate 20a, the silicon substrate 20a is divided along the separation groove by applying stress to the silicon substrate 20a. Steps S26 and S27 are an example of a separation process.

  FIG. 9F is a cross-sectional view of the silicon substrate 20a on which the separation groove 280 is formed in step S26. As shown in FIG. 9F, the separation groove 280 is a region where the p-type amorphous silicon layer 222p is formed (that is, a region having a low dopant concentration) among the p-type amorphous silicon layers 221p and 222p. ). That is, the laser is irradiated to the region where the p-type dopant concentration is low in the silicon substrate 20a. In other words, in the step of forming the p-type amorphous semiconductor layer (S22), the groove forming region (that is, the region irradiated with the laser) of the silicon substrate 20a including the position where the separation groove 280 is formed in plan view. The concentration of the p dopant contained in the p-type amorphous silicon layer 222p disposed in at least a part of the p-type amorphous silicon layer 221p is included in the p-type amorphous silicon layer 221p disposed in a region other than at least a part of the trench formation region. A p-type semiconductor layer 221 having a lower p-type dopant concentration is formed.

  FIG. 9G is a cross-sectional view of the silicon substrate 20a cut along the separation groove 280 in step S27. As shown in (g) of FIG. 9, two solar cells 200 are formed by cleaving along the separation groove 280. At least a portion of the cleaved portion of the silicon substrate 20a includes a region where the p-type dopant concentration is low.

[2-3. Effect etc.]
As described above, solar cell 200 according to the present embodiment is provided on the first main surface, n-type semiconductor layer 23 including an n-type dopant, and provided on the second main surface, and a p-type dopant. A p-type semiconductor layer 221 including The silicon substrate 20 is an outer region 50 extending over one side constituting the outer peripheral portion of the silicon substrate 20 in a plan view, and the concentration of the p-type dopant contained in the p-type semiconductor layer 221 is a region other than the outer region 50. The outer region 50 is lower than the p-type dopant concentration contained in the p-type semiconductor layer 221 disposed in the region.

  Thereby, when the solar cell 200 is formed by cleaving the large silicon substrate 20a, a region where the p-type dopant concentration is lower than other regions is present in at least a part of the portion to be cleaved. Since the solar cell 200 is produced by cleaving the region, even if the p-type amorphous silicon layer 222p peels off at the time of cleaving and the silicon substrate 20 and the p-type semiconductor layer 221 leak, It is possible to suppress the influence on the output reduction due to the leak. Therefore, the photovoltaic cell 200 according to the present embodiment can further suppress the characteristic deterioration.

  In addition, as described above, the method for manufacturing the photovoltaic cell 200 according to the present embodiment is the silicon substrate 20a having the first main surface and the second main surface facing away from the first main surface, and is n-type. A first film forming step (S21 and S22) for forming a p-type semiconductor layer 221 having a p-type on the second main surface of the silicon substrate 20a, and an n-type on the first main surface of the silicon substrate 20a. A second film forming step (S23 and S24) for forming the n-type semiconductor layer 23, and a separation groove 280 for separating the silicon substrate 20a is formed in the silicon substrate 20a, along the separation groove 280. And a separation step (S26 and S27) for separating the silicon substrate 20a. In the second film formation step, the p-type disposed in at least a part of the groove forming region in at least a part of the groove forming region of the silicon substrate 20a including the position where the separation groove 280 is formed in a plan view. The p-type semiconductor layer 221 (for example, p-type) in which the concentration of the p-type dopant contained in the semiconductor layer 221 (for example, the p-type amorphous silicon layer 222p) is disposed in a region other than at least a part of the trench formation region. A p-type semiconductor layer 221 having a lower p-type dopant concentration contained in the amorphous silicon layer 221p) is formed.

  Thereby, there exists an effect similar to the photovoltaic cell 200.

(Other embodiments)
As mentioned above, although the photovoltaic cell etc. which concern on this invention were demonstrated based on embodiment, this invention is not limited to the said embodiment.

  For example, in the above-described embodiment, the example in which the p-side electrode and the n-side electrode are formed in the step of forming the electrode has been described. However, the p-side collector electrode and the n-side collector electrode may also be formed. Good.

  Moreover, although the said embodiment demonstrated the example in which an n-type semiconductor layer was formed in the surface at the side of the main light-receiving surface of a photovoltaic cell, it is not limited to this. A p-type semiconductor layer may be formed on the surface on the main light receiving surface side of the solar battery cell.

  Moreover, although the n side current collection electrode demonstrated the example which has a finger electrode and a bus-bar electrode in the said embodiment, it is not limited to this. The n-side current collecting electrode only needs to have at least finger electrodes. Moreover, although the p side current collection electrode demonstrated the example which has a finger electrode and a bus-bar electrode, it is not limited to this. The p side current collection electrode should just have a finger electrode at least.

  Moreover, the order of each process in the manufacturing method of the photovoltaic cell demonstrated by the said embodiment is an example, and is not limited to this. The order of each process may be changed, and a part of each process may not be performed.

  Moreover, each process in the manufacturing method of the photovoltaic cell demonstrated by the said embodiment may be implemented by one process, and may be implemented by a separate process. Note that the term “performed in one step” is intended to include that each step is performed using one apparatus, that each step is performed continuously, or that each step is performed in the same place. It is. In addition, a separate process means that each process is performed using different devices, each process is performed at a different time (for example, different days), or each process is performed at a different place. It is an intention to include.

  In addition, the embodiment can be realized by arbitrarily combining the components and functions in each embodiment without departing from the scope of the present invention, or a form obtained by subjecting each embodiment to various modifications conceived by those skilled in the art. Forms are also included in the present invention.

10, 10a, 100, 200 Solar cell 20, 20a Silicon substrate (semiconductor substrate)
21, 221 p-type semiconductor layer (second semiconductor layer)
21i i-type amorphous silicon layer (i-type amorphous semiconductor layer)
21p, 221p, 222p p-type amorphous silicon layer (second conductivity type amorphous semiconductor layer)
23, 123 n-type semiconductor layer (first semiconductor layer)
23n, 123n n-type amorphous silicon layer 30 p-side collector electrode 31, 41 finger electrode 32, 42 bus bar electrode 40 n-side collector electrode 50 outer region (first region)
70, 170 Undeposited region 80, 180, 280 Separation groove 150 Outer region (second region)

Claims (8)

A semiconductor substrate having a first main surface and a second main surface facing away from the first main surface, the semiconductor substrate having a first conductivity type;
A first semiconductor layer provided on the first main surface and having the first conductivity type;
A second semiconductor layer provided on the second main surface and having a second conductivity type different from the first conductivity type;
The said semiconductor substrate has a 1st area | region where said 2nd semiconductor layer is not formed over one side which comprises the outer peripheral part of the said semiconductor substrate in planar view. The second semiconductor layer has an i-type amorphous semiconductor layer stacked on the second main surface, and a second conductive amorphous semiconductor layer stacked on the i-type amorphous semiconductor layer,
Of the i-type amorphous semiconductor layer and the second conductivity type amorphous semiconductor layer, at least the second conductivity type amorphous semiconductor layer is in a region on the semiconductor substrate excluding the first region. The solar cell according to claim 1, which is arranged. A semiconductor substrate having a first main surface and a second main surface facing away from the first main surface, the semiconductor substrate having a first conductivity type;
A first semiconductor layer provided on the first main surface and containing the dopant of the first conductivity type;
A second semiconductor layer provided on the second main surface and including a dopant of a second conductivity type different from the first conductivity type;
The semiconductor substrate is a first region over one side constituting an outer peripheral portion of the semiconductor substrate in a plan view, and a concentration of the second conductivity type dopant contained in the second semiconductor layer is the first region. A solar cell having a first region lower than a dopant concentration of the second conductivity type included in the second semiconductor layer disposed in a region other than one region. The semiconductor substrate is substantially rectangular,
The solar cell according to claim 1, wherein the first region includes an outer peripheral portion of the semiconductor substrate. The semiconductor substrate further includes a second region in which the second semiconductor layer is not formed over the one side constituting the outer peripheral portion of the semiconductor substrate in a plan view. The solar battery cell according to 1. A semiconductor substrate having a first main surface and a second main surface facing away from the first main surface, wherein the second main surface of the semiconductor substrate having the first conductivity type is different from the first conductivity type. A first film forming step of forming a second semiconductor layer having a two-conductivity type;
A second film forming step of forming a first semiconductor layer having the first conductivity type on the first main surface of the semiconductor substrate;
Forming a separation groove for separating the semiconductor substrate in the semiconductor substrate, and separating the semiconductor substrate along the separation groove,
In the first film formation step, an undeposited region in which the second semiconductor layer is not formed in at least a part of the groove formation region of the semiconductor substrate including a position where the separation groove is formed in a plan view. The manufacturing method of the photovoltaic cell to form. A semiconductor substrate having a first main surface and a second main surface facing away from the first main surface, wherein the second main surface of the semiconductor substrate having the first conductivity type is different from the first conductivity type. A first film forming step of forming a second semiconductor layer having a conductivity type;
A second film forming step of forming a first semiconductor layer having the first conductivity type on the first main surface of the semiconductor substrate;
Forming a separation groove for separating the semiconductor substrate in the semiconductor substrate, and separating the semiconductor substrate along the separation groove,
In the first film forming step, the planar arrangement includes at least a part of the groove forming region of the semiconductor substrate including a position where the separation groove is formed in a plan view. The second conductivity type dopant contained in the second semiconductor layer has a concentration of the second conductivity type contained in the second semiconductor layer disposed in a region other than the at least part of the groove forming region. The manufacturing method of the photovoltaic cell which forms the 1st semiconductor layer lower than dopant concentration. The method for manufacturing a solar cell according to claim 6 or 7, wherein, in the separation step, the separation groove is formed by irradiating the second main surface of the semiconductor substrate with a laser.

Images