JPS5892218A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5892218A
JPS5892218A JP56191268A JP19126881A JPS5892218A JP S5892218 A JPS5892218 A JP S5892218A JP 56191268 A JP56191268 A JP 56191268A JP 19126881 A JP19126881 A JP 19126881A JP S5892218 A JPS5892218 A JP S5892218A
Authority
JP
Japan
Prior art keywords
semiconductor device
type
semiconductor layer
reaction
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56191268A
Other languages
Japanese (ja)
Other versions
JPH0512850B2 (en
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP56191268A priority Critical patent/JPS5892218A/en
Publication of JPS5892218A publication Critical patent/JPS5892218A/en
Publication of JPH0512850B2 publication Critical patent/JPH0512850B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02529Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To form a practically instrinsic coating film on a semiconductor layer made at the previous process in order to prevent an N or P type impurity in a semiconductor device made at the previous process from discharging again from the inner wall of a reaction device or the holder of a substrate and from mixing in a P or N type semiconductor made at the next process when the first semiconductor devices having P type and N type semiconductor layers are continuously made by a plasma vapor method by using the same reaction tank. CONSTITUTION:Evacuation is applied to a reaction furnace in process 49. Silicon or silicon carbide is coated to a reaction cylinder and a holder in process 40. Next, evacuation 41 to a system, furthermore, the manufacture 42 of a P or an N type semiconductor device, the manufacture 43 of an I type semiconductor layer, the manufacture 44 of an N type semiconductor layer are done to make 48 the first semiconductor device. Furthermore, after that, the possibility of alternately mixing a P or an N type impurity between the final process 44 for the manufacture 48 of the first semiconductor device and the first process 42 at the next process 48 can be removed by coating an I type semiconductor layer shown as 46 to above system and a reaction system inserted and installed the reaction furnace and the holder.

Description

【発明の詳細な説明】 本発明はプラズマ気相法によシ、再現性、特性のよい半
導体装置を作製する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device with good reproducibility and characteristics by a plasma vapor phase method.

本発明はプラズマ気相法によシ反応炉内に設けられた基
板上にP型およびN型の半導体層を有する第1の半導体
装置を形成した後、この半導体装置のNまたはP型不純
物が次に作られるPまたはN型の半導体層中に反応装置
の内壁まため、この各工程の間に前回作られた半導体層
上に真性または実質的に真性(以下1層という)のコー
ティング用の被膜を形成する工程(この場合は次の工程
の最初に作られる被膜歳irシコーティングしてもよい
)Kよシ実質的に過去の履歴を除去してしまうことを目
的としている〇さらKまたは前回作られた半導体層のう
ち、反応装置の内壁、基板のホルダー等の表面に付着し
たものをay等の反応性気体をプラズマ化するととKよ
シ除去してしまう工程を設けることを目的とする。
In the present invention, after a first semiconductor device having P-type and N-type semiconductor layers is formed on a substrate provided in a reactor by a plasma vapor phase method, N or P-type impurities of this semiconductor device are removed. The internal walls of the reactor are then coated onto the P- or N-type semiconductor layer produced, and during each step an intrinsic or substantially intrinsic (hereinafter referred to as one layer) coating is applied to the previously produced semiconductor layer. The process of forming a film (in this case, the film formed at the beginning of the next step may also be irradiated) is intended to substantially remove past history. The purpose is to provide a process in which the previously produced semiconductor layer that adheres to the inner wall of the reaction device, the surface of the substrate holder, etc. is removed by turning reactive gas such as ay into plasma. do.

もきわめてすぐれたものとすることがで話るという特徴
を有する。
It also has the characteristic of being able to speak very well.

また本発明は反応炉内に設けられた基板上に少くともひ
とつの接合特にP工層、P工、N工またはPN接合を有
する半導体装置において、反応炉の内壁特にプラズマ原
子または反応性気体が衝突する内壁よシネ細物特に酸素
、アルカリ金属原子が放出されることを防ぐため、これ
らの表面にあらかじめ真性または実質的に真性の半導体
層例えば非単結晶珪素を形成することを目的としている
The present invention also provides a semiconductor device having at least one junction, particularly a P layer, a P layer, an N layer, or a PN junction on a substrate provided in a reactor, in which the inner wall of the reactor, particularly plasma atoms or reactive gases, is In order to prevent the emission of cine particles, particularly oxygen and alkali metal atoms, from the colliding inner walls, the purpose is to form an intrinsic or substantially intrinsic semiconductor layer, such as non-single crystal silicon, on these surfaces in advance.

本発明はこれらの実質的に除去するためのコーティング
によシ再放出を防ぐため、半導体層を半導体装置の作製
に必要な電磁エネルギの出力Po例えば5〜100W、
i度To例えば200〜320°Cに対し、PO−10
W(但し最低5wとする)〜P。
In order to prevent re-emission by coating to substantially remove these, the present invention coats the semiconductor layer with an electromagnetic energy output Po, e.g., 5 to 100 W, necessary for manufacturing a semiconductor device.
For example, 200-320°C, PO-10
W (however, the minimum is 5W) to P.

+30Wの範囲、またTo−50’0−To+50@O
特に好ましくけPo、 Toと同じまたは概略同じ条件
にて作製し、0.2〜1μの厚さに形成せしめることを
特徴としている。
+30W range, also To-50'0-To+50@O
Particularly preferably, it is produced under the same or approximately the same conditions as Po and To, and is characterized by being formed to a thickness of 0.2 to 1 μm.

従来プラズマCVD法に関しては、ひとつの反応炉にて
PIN接合等を有する半導体装置の作製が行なわれてい
た0しかしこの接合を〈シがえし行なうと、全くわけの
わからない劣化、バラツキに悩まされてしまい、半導体
装置としての信頼性に不適当なものしかできなかった。
Conventionally, with the plasma CVD method, semiconductor devices with PIN junctions, etc., were manufactured in a single reactor; however, when this junction was replaced, it was plagued by completely unexplained deterioration and variations. As a result, the reliability of the semiconductor device was inadequate.

この原因を調べた結果、仁の最大の原因は、反応炉内に
付着している酸素、アルカリ金属が半導体層中に混入し
て、電気伝導度の低下をもたらすものであり、酸素にあ
ってはlPPMの混入であっても、暗示導度IC1’ 
(、i c m)を1M (rLc m5’と1/10
0Kまで下げてしまってに走。
As a result of investigating the cause of this, we found that the biggest cause of this is that oxygen and alkali metals adhering to the reactor mix into the semiconductor layer, causing a decrease in electrical conductivity. Even if lPPM is mixed in, the implied conductivity IC1'
(, i c m) to 1M (rLc m5' and 1/10
I dropped it to 0K and ran.

またアルカリ金属にあっても、5PPMの混入において
、P型、I型の伝導度の低下また透明導電膜の伝導度の
低下をもたらしてしまった。
Furthermore, in the case of alkali metals, when 5PPM is mixed, the conductivity of P-type and I-type and the conductivity of the transparent conductive film are lowered.

これらの混入を防ぐため、反応炉の内壁また基板のホル
ダー(ボートともいう)の特にプラズマによる反応性気
体にスパッタされる部分に対して、あらかじめ半導体層
を0.2〜2μの厚さに形成させ、コーティングしてし
まうことがきわめて重要であった。さらに再現性特性劣
化に対しては、ひとつの半導体装置の作製に対し、その
最後の工程がKまたはP型半導体層を作シまた次の最初
の工程にPまたはN型の半導体層を作ろうとした時、1
0〜10 c m’の濃度に最初の不純物例えばリンが
P型半導体層中に混入してしまう。このためP型半導体
層は例えば10〜10amの濃度にホウ素を添加してP
型層としてもその電気伝導度はリンの混入によシ再結合
中心が増加するためきわめて特性が悪く、混入がない場
合1d〜16′(ACm)Iに対し、10−xl O”
 (AOm)’と1/100〜1/10001.か得ら
れなかつ友。
In order to prevent these contamination, a semiconductor layer is formed in advance to a thickness of 0.2 to 2μ on the inner wall of the reactor and on the parts of the substrate holder (also called boat) that will be sputtered by the reactive gas generated by plasma. It was extremely important that the material be completely coated. Furthermore, regarding the deterioration of reproducibility characteristics, when manufacturing one semiconductor device, if the last step is to create a K or P type semiconductor layer, and then the next first step is to create a P or N type semiconductor layer. When I did, 1
Initial impurities such as phosphorus are mixed into the P-type semiconductor layer at a concentration of 0 to 10 cm'. For this reason, the P-type semiconductor layer is made by adding boron to a concentration of 10 to 10 am, for example.
Even as a mold layer, its electrical conductivity is extremely poor because the number of recombination centers increases due to the incorporation of phosphorus, and when there is no incorporation, the electrical conductivity is 1d~16'(ACm)I, whereas it is 10-xl O''
(AOm)' and 1/100 to 1/10001. An unforgettable friend.

このためPIN型光電変換装置においては2〜4%の効
率を各ランごとのバラツキを±200チも有して得られ
たにすぎず好ましくなかっ九〇しかし本発明方法にあっ
ては、8〜10%の約3〜5倍の高い変換効率を得るこ
とができるようになった。
For this reason, in the PIN type photoelectric conversion device, an efficiency of 2 to 4% was obtained with a variation of ±200 degrees from run to run, which is undesirable. It has become possible to obtain a conversion efficiency about 3 to 5 times higher than 10%.

またこの不純物酸素ドーピングの効果を少くするため、
本発明人の出願になる特許願 半導体装置作製方法 5
6−55608(態表示53−15288’/昭和53
年12月10日出願)が知られている。これは例えばP
工N半導体装置を作ろうとする時、各P層、1層、N層
をそれぞれ独立の反応炉を作シ、基板をその層間を移動
せしめることによシ行わんとするものである。この方法
にあっては、本発明と同じ対策を持つことができ、きわ
めて好ましい電気的特性を得ることができる。しかしそ
の場合、装置はひとつの室の方式の3倍であシ、製造コ
ストが2.5〜3倍も高価になってしまう。さらに多量
生産向きでない等の欠点を有していた。
In addition, in order to reduce the effect of this impurity oxygen doping,
Patent application filed by the inventor: Semiconductor device manufacturing method 5
6-55608 (status display 53-15288'/Showa 53
(filed on December 10, 2013) is known. For example, this is P
When attempting to fabricate an engineered N semiconductor device, the process is carried out by creating independent reactors for each of the P, 1, and N layers, and moving the substrate between the layers. This method can take the same measures as the present invention and can provide extremely favorable electrical characteristics. However, in that case, the equipment would be three times as large as the one-chamber system, and the manufacturing cost would be 2.5 to 3 times more expensive. Furthermore, it had drawbacks such as not being suitable for mass production.

本発明けかかる反応デルτおいて、特に横型の反応炉に
おいて特に有効である。また多量に基板上に半導体装置
を特徴とする特に有効であり、半導体装置ひとつあたシ
の装置の減価償却を含めて、製造コストをたて型反応炉
の1/100にできるという大きな特徴を有している。
The reaction delta according to the present invention is particularly effective in a horizontal reactor. It is also particularly effective when a large amount of semiconductor devices are mounted on a substrate, and has the great feature that the manufacturing cost can be reduced to 1/100 of that of a vertical reactor, including the depreciation of the equipment for each semiconductor device. have.

すなわち本発明はかかる多量生産用に横型に配置された
反応炉または反応筒(10〜30 c us、長さ1〜
5m)を用いる方法を中心として記す。
That is, the present invention provides a horizontally arranged reactor or reaction tube (10 to 30 cuus, length 1 to 30 cm) for mass production.
The method using 5m) will be mainly described.

かかる反応筒の外側に一対の反応性気体をプラズマ化す
る電磁エネルギ供給用の電極と該電極の外側にこの反応
筒および電極を囲んで加熱装置とを具備し、この反応炉
内を炉方向に反応性気体を流し、この気体の流れにそっ
て基板を配置せしめ九ものである。
A pair of electrodes for supplying electromagnetic energy for turning a reactive gas into plasma are provided on the outside of the reaction tube, and a heating device is provided outside of the electrodes to surround the reaction tube and the electrodes, and the inside of the reactor is heated in the direction of the furnace. This method involves flowing a reactive gas and arranging the substrate along the flow of the gas.

さらにかかる装置内に一対の電極によ多発生する電磁界
に垂直または平行に基板を配置し、これを複数段または
樋数列配置して2〜20c♂の基板例、えば10 c 
m’の基板を20段20列計400まいの被形成面上に
一度に被膜特に珪素、炭素炭化珪素または珪化ゲルマニ
ューム、ゲルマニューム鼓膜すなわち4価の元素を中心
とした半導体膜を形成せしめることを中心として記す。
Further, in such a device, a substrate is arranged perpendicularly or parallel to the electromagnetic field generated by a pair of electrodes, and these are arranged in multiple stages or in several rows to form a substrate of 2 to 20 c♂, for example, 10 c
The method mainly focuses on forming a film, particularly a semiconductor film mainly made of silicon, silicon carbide, germanium silicide, germanium tympanum, or a tetravalent element, on a total of 400 surfaces of 20 rows and 20 rows of 400 m' substrates at once. It is written as

本発明は炭素−珪素結合を有する水素化物またはハロゲ
ン化物(炭化珪化物気体)よりなる反応性気体、シラン
(stnu  n 1)の如き珪化物気体またはアセチ
レン等の炭化水素を用いて被形成面上に非単結晶の炭化
珪素、珪素または炭素を主成分とする被膜を0.05〜
1tOrrの反応炉圧力で100〜400°Cの温度で
形成せしめるプラズマ気相法にj′、1する。
The present invention uses a reactive gas consisting of a hydride or halide (carbohydrate silicide gas) having a carbon-silicon bond, a silicide gas such as silane (stnun 1), or a hydrocarbon such as acetylene to form a surface on the surface to be formed. A film containing non-single crystal silicon carbide, silicon or carbon as a main component is applied to the coating from 0.05 to
A plasma vapor phase process is performed at a reactor pressure of 1 tOrr and a temperature of 100 to 400°C.

本発明はさらにかかる反応性気体に膳価の不純物である
B、 AI、 Ga、Inを含む不純物気体例えばジボ
ラン(B局、V価の不純物を含む不純物気体例えばフオ
スヒン(pa)またはアルシン(A s H,)を漸次
添加して被形成面を有する基板上に密接してP型層、さ
らに工型層およびN型層をP工Nの順序に−C積層形成
せしめ、これをくシかえし、安定して作製することを目
的としている。さらに本発明はプラズマ化する電磁エネ
ルギのパワーによシ、アモルファス構造の半導体(ム8
という)、5〜100ムの大きさの微結晶性を有するセ
ミアモルファス(半非晶質、以]8A8という)を九は
5〜200Aの大きさのマイクロポリクリスタル(微多
結晶、以下PCという)の構造を有する半導体の如き非
単結晶半導体層を作製せんとするものである。さらrc
強い電磁エネルギを与える場合、基板表面ではスパッタ
ーされた電気的に欠陥だらけのアモルファス構造tζな
シやすい0かかる欠陥構造をなくすため、基板は互いに
10w40mm代表的には20〜25mm離間し、プラ
ズマ反応に200〜500Wという高いエネルギが必要
な場合であっても、被形成面上にはこのスビーシスの実
質的なプラズマエネルギを得る距離を基板間の距離で制
御し、実質的に2〜aOWという弱いパワーで被膜化せ
しめると同等の特性を有せしめたことを特徴とする。
The present invention further provides such reactive gases with impurity gases containing impurities such as B, AI, Ga, and In, such as diborane (B), and impurity gases containing V-valent impurities such as phoscine (pa) or arsine (As). H,) is gradually added to form a P-type layer closely on the substrate having the surface to be formed, and then a -C layer is formed in the order of P-type layer and N-type layer, and this is repeated. The purpose of the present invention is to stably produce semiconductors with an amorphous structure (mu 8
), semi-amorphous (semi-amorphous, hereafter referred to as 8A8) with a size of 5 to 100 μm, and micro polycrystal (micropolycrystal, hereinafter referred to as PC) with a size of 5 to 200 μm. ) The purpose is to fabricate a non-single crystal semiconductor layer such as a semiconductor having the structure shown in FIG. Sara rc
When applying strong electromagnetic energy, the substrate surface tends to have a sputtered amorphous structure full of electrical defects.In order to eliminate such defective structures, the substrates are spaced apart from each other by 10w40mm, typically 20 to 25mm, to prevent plasma reaction. Even if a high energy of 200 to 500 W is required, the distance to obtain the substantial plasma energy of this subisis on the surface to be formed is controlled by the distance between the substrates, and a weak power of 2 to aOW is effectively applied. It is characterized in that it has the same properties when coated with.

このため本発明においては、その出発物質である反応性
気体に炭化珪素(8iXO/−X Oα〈1)を作ろう
とした場合、炭素−珪素結合を有する材料を用い友。す
なわち炭素−珪素結合を有する水素化物またはノ・ロゲ
ン化物例えばテトラエチルシラン(al(c砧)弾K 
TMEIという)、テトラエチルシラン(s 1(a、
Q) 、 s 1(oQ xo1*t(Is x= 3
)Si(CQX111tχ1’−xε3)等の反応性気
体を用いて反応生成物中に81−0結合を得やすくして
いる。
Therefore, in the present invention, when silicon carbide (8iXO/-XOα<1) is to be made from the reactive gas that is the starting material, a material having a carbon-silicon bond is used. That is, a hydride or a halogenide having a carbon-silicon bond, such as tetraethylsilane (al(c))
TMEI), tetraethylsilane (s 1 (a,
Q), s 1(oQ xo1*t(Is x= 3
) A reactive gas such as Si (CQX111tχ1'-xε3) is used to facilitate obtaining the 81-0 bond in the reaction product.

また珪素を主成分とする被膜を得ようとする時は81n
Ht−、Cn2N)のシラン、81F9またはこれらの
混合気体を用いた。炭素を得ようとする時は、アセチレ
ン(0、幻またはエチレン(0鳥を主として用いた。こ
うすることによシ、珪素(S 1> 、炭【珪素(El
 i x 07−、 O<x< 1)または炭素(0)
(これらを合わせるとs 1x 0r−r (o≦X≦
1)と示すことができるため、以下炭化珪素という時は
81XC,、(OtX41)を意味するものとする)を
作製する。
Also, when trying to obtain a film whose main component is silicon, 81n
Ht-, Cn2N) silane, 81F9, or a mixed gas thereof was used. When trying to obtain carbon, acetylene (0, phantom or ethylene (0) was mainly used. By doing this, silicon (S 1>, carbon [silicon (El
i x 07-, O<x<1) or carbon (0)
(If you put these together, s 1x 0r-r (o≦X≦
1), hence the term silicon carbide hereinafter refers to 81XC, (OtX41)).

さらにここに璽価または7価の不純物を添加して被形成
面よりP型、1型(真性またはオートドーピング等を含
む人為的に不純物を添加しない実質的に真性)さらKN
型の半導体または半絶縁体を作製した。
Furthermore, a valent or heptavalent impurity is added to form a P-type, 1-type (intrinsic or substantially intrinsic without artificially adding impurities including autodoping, etc.) from the surface to be formed, and further KN.
A type of semiconductor or semi-insulator was fabricated.

さらにかかる反応性気体を用いると、反応炉を1気圧以
下特に0.01〜10tOrr、代表的には0.3〜O
,5torrの圧力下にて50W以下の電磁エネルギに
おいても、例えば0.01〜100MHz特K !SO
OICHg tたは13.56MHzにおいて被膜を形
成することが可能である。即ち低エネルギプラズマ、O
VD装置とすることができた。
Furthermore, when such a reactive gas is used, the reactor can be heated to 1 atm or less, particularly 0.01 to 10 tOrr, typically 0.3 to 0.0
, even with electromagnetic energy of 50 W or less under a pressure of 5 torr, for example, 0.01 to 100 MHz special K! S.O.
It is possible to form a coating at OICHg t or 13.56 MHz. That is, low energy plasma, O
It was possible to use it as a VD device.

サラWc5o〜600Wという高エネルギプラズマ雰囲
気とすると、形成された炭化珪素は微結晶化し、その結
果P型またはN型において、ホウ素またはリンを0.1
〜5%(ここでは(BHまたはPIE) / (炭化物
気体または炭化珪化物気体+珪化物気体)の比をパーセ
ントで示す)添加した場合、低エネルギでは電気伝導度
は10〜1o←cm)′であったものが10〜10(、
nam)’と約千倍にまで高めることができた。
When a high-energy plasma atmosphere of 50 to 600 W is used, the formed silicon carbide becomes microcrystalline, and as a result, in P type or N type, boron or phosphorus is added to 0.1
When added ~5% (here the ratio of (BH or PIE) / (carbide gas or carbide silicide gas + silicide gas) is expressed as a percentage), at low energy the electrical conductivity is 10~1o←cm)' 10 to 10 (,
nam)' and was able to increase it approximately 1,000 times.

さらKこの高エネルギ法を用いて得られた炭化珪素は5
〜200Aの大きさの微結晶構造を有するいわゆる日ム
B構造を有せしめることができた。
Moreover, the silicon carbide obtained using this high-energy method is 5
It was possible to have a so-called Himu B structure having a microcrystalline structure with a size of ~200A.

かかるBARにおいて、そのPまたはN型の不純物のア
クセプタまたはドナーとなるイオン化率を91〜100
チを有し、添加した不純物のすべてを活性化することが
できた。
In such a BAR, the ionization rate of the P or N type impurity as an acceptor or donor is set to 91 to 100.
was able to activate all of the added impurities.

以下に図面に従って本発明のプラズマ気相法を説明する
The plasma vapor phase method of the present invention will be explained below with reference to the drawings.

第1図は本発明を用いたプラズマ0VD装置の概要を示
す。
FIG. 1 shows an outline of a plasma 0VD apparatus using the present invention.

第1図において被形成面を有する基板(1)は角型の石
英ホルダーにて保持され、図面では1段2列計14まい
の構成をさせている。基板およびホルダーは反応炉の前
方の別室−に入口(3o)よシ予め設置され、パルプ(
32)ロータリーポンプ(33)によシ真空びきがなさ
れる。さらに開閉とびら(3荀を開けて、反応炉内に自
動送シ装置によシ導入され、さらにミキサー用混合板(
3ツも同時配置される。これらは反応炉、別室ともに真
空状態においてなされ、反応炉内に酸素(空気)が少し
でも混入しないように務めた。
In FIG. 1, a substrate (1) having a surface to be formed is held in a square quartz holder, and the drawing shows a total of 14 holders in one stage and two rows. The substrate and holder were installed in advance in a separate room at the front of the reactor, near the entrance (3o), and the pulp (
32) Vacuuming is performed by the rotary pump (33). Furthermore, the opening/closing doors (3 doors) are opened, and the automatic feeder is introduced into the reactor, and the mixing plate for the mixer (
All three will be placed at the same time. These were carried out in a vacuum state in both the reactor and a separate room to prevent even the slightest amount of oxygen (air) from entering the reactor.

さらに開閉とびら(34)を閉じたことによシ、図面の
如く電極(9)、Cl0)の間に基板が配置された0各
基板はNo〜40mm代表的には20〜25mmの間か
くをおいて配列されておシ、このホルダーによる反応性
気体は反応炉(ハ)の前方にミキサ(8)を設は層流と
し、さらにこれらの反応性気体が基板の間の空隙に均一
に注入するように設けである。被形成面は基板の下面ま
たは互いに裏面を重ね合わせて垂直に配置された側面で
ある。
Furthermore, by closing the opening/closing door (34), each substrate is placed between the electrode (9) and Cl0) as shown in the drawing. A mixer (8) is installed in front of the reactor (c) to create a laminar flow of reactive gases from this holder, and these reactive gases are evenly distributed in the gap between the substrates. It is equipped to be injected. The surface to be formed is the lower surface of the substrate or side surfaces arranged vertically with their back surfaces stacked on top of each other.

また図面は反応系を上方よシながめた構造を示したもの
であシ、基板(1)は互いに裏面を合わせて垂直に配置
させている0かくの如く重力を利用してフレイクを下部
に除去することは、量産歩留りを考慮する時きわめて重
要である。さらにこの基板(荀を折入させた反応炉(2
)には、この基板に垂直または平行(特に平行にすると
被膜の均一性が得やすい)に電磁エネルギの電界が第2
図■または(B)特K CB)の如くに加わるように一
対の電極(9)ρO)を上下または左右に配置して設け
た0との電極の外側に電気炉(6)が設けられておシ、
基板(1)が100−400°C代表的には300°C
に加熱されている。
The drawing also shows the structure of the reaction system viewed from above. The substrates (1) are arranged vertically with their back sides facing each other. As shown, flakes are removed to the bottom using gravity. This is extremely important when considering mass production yield. In addition, this substrate (a reaction furnace (2
), a second electric field of electromagnetic energy is applied perpendicularly or parallel to this substrate (parallel makes it easier to obtain a uniform coating).
A pair of electrodes (9) ρO) are arranged vertically or horizontally as shown in Figure ■ or (B) Special K CB), and an electric furnace (6) is installed outside the electrodes. Oshi,
Substrate (1) is 100-400°C typically 300°C
is heated to.

反応性気体は水素またはへリュームのキャリアガス例え
ばヘリュームを(至)よシ、璽価の不純物である。&≦
にセ一/◇◆より、7価の不純物であるフオスヒンを(
l→よシ、■価の添加物である珪化物気体のシランを0
時より導入した。
The reactive gas is a hydrogen or helium carrier gas, such as helium, and is an impurity. &≦
From Niseichi/◇◆, the heptavalent impurity phosuhin (
l→Yoshi, silane, a silicide gas, which is an additive with a ■ value, is reduced to 0.
It was introduced at the time.

また炭素−珪素結合を有する反応性気体TM8(至)を
用いると、初期状態で液体であるためステンレス容器Q
υに保存される。この容器は電子恒温層(イ)により所
定の温度に制御されている。
In addition, when reactive gas TM8 (to) having a carbon-silicon bond is used, since it is liquid in the initial state, the stainless steel container Q
stored in υ. This container is controlled at a predetermined temperature by an electronic constant temperature layer (a).

このTM8は沸点が2660であり、p−タリーポンプ
0′4をパルプ(1カをへて排気させ、反応炉内を0.
01〜1OtOrr特に0.02〜0.4torrに保
持させた。こうすることによシ、1気圧よシ低い圧力に
よシ結果として特に加熱しなくても7M8を気化させる
ことができる。この気化した7M8を1oo−の濃度で
流量計を介して反応炉に導入することは、従来の如く容
器学力をバブルして反応性気体を放出するやυ方に比較
して、その流量制御が精度よく可能でちゃ、技術上重要
であるO 実用上流量計がつまった場合、図面において(ハ)よシ
ヘリエームを導入した。
This TM8 has a boiling point of 2660, and the p-tally pump 0'4 is evacuated through pulp (1), and the inside of the reactor is 0.
It was maintained at 0.01 to 1 OtOrr, particularly 0.02 to 0.4 torr. By doing this, 7M8 can be vaporized at a pressure as low as 1 atm, and as a result, without special heating. Introducing this vaporized 7M8 into the reactor through a flowmeter at a concentration of 100-10-10 - is easier to control the flow rate than the conventional method of bubbling the container and releasing the reactive gas. It is technically important to be able to do this with high precision.O If the flowmeter becomes clogged in practice, we have introduced (c) a siheliame in the drawing.

また反応筒01またはホルダー(2)の内壁または表面
に付着した反応生成物を除去する場合は卯よル01.ま
たはOF、+ O,(2〜6チ)を導入し、電磁エネル
ギを加えてフッ素ラジカルを発生させて気相エツチング
をして除去した。
In addition, when removing reaction products attached to the inner wall or surface of the reaction tube 01 or holder (2), use Uyoyoru 01. Alternatively, OF, +O, (2 to 6 channels) was introduced and electromagnetic energy was applied to generate fluorine radicals, which were removed by gas phase etching.

さらにこのプラズマ放電においては、反応性気体が混合
室(8)をへて混合された後、励起室(ハ)において分
解または反応をおこさしめ、反応生成物を基板上に形成
する空間反応を主として用い九。電磁エネルギは電源(
4)よシ直流または高周波を主として用いた。
Furthermore, in this plasma discharge, after the reactive gas passes through the mixing chamber (8) and is mixed, it decomposes or reacts in the excitation chamber (c), and mainly involves a spatial reaction in which reaction products are formed on the substrate. Use 9. Electromagnetic energy is a power source (
4) Direct current or high frequency was mainly used.

このようにして被形成面上に炭化珪素被膜を形成した。In this way, a silicon carbide film was formed on the surface to be formed.

例えば基板温度300”O,高周波エネルギの出力26
W1 シランまたはテM850cc、イ分キャリアガス
としてのHe 250ecZ分とした。
For example, the substrate temperature is 300”O, the high frequency energy output is 26”
W1: 850 cc of silane or Te M, 250 cc of He as a carrier gas.

(反応性気体/He)5において160ム/分の被膜成
長速度を得ることができた。
(Reactive gas/He) A film growth rate of 160 μm/min could be obtained.

さらにこの被膜形成には、FIN接合、pH接合、P工
、Nx接合、P工NP111接合等をその必要な厚さに
必要な反応生成物を基板上に漸次積層して形成させた。
Further, to form this film, a FIN junction, a pH junction, a P-type junction, an Nx junction, a P-type NP111 junction, etc. were formed by gradually laminating the necessary reaction products to the required thickness on the substrate.

このようにして被形成面上に被膜を形成させ倫 てしまった後、反応   を反応筒よシ十分にパージし
た後、開閉とびら(34)を開け、ミキサ用混合板(3
5) 、ジグ(3)上の基板を別室−に自動引出し管に
よシ反応筒および別室をともに真空(0,(ltorr
以下)Kして移動させた。さらに開閉とびら(34)を
閉じた後、別室に(31)よりパルプを開けて空気を充
填し大気圧とした後、外部にジグおよび被膜の形成され
た基板をとル出したO 以上の実施例よシ明らかな如く、本発明は反応性気体を
ミキサ(8)にて混合した後、排気口(6)1層状(き
りpにはプラズマ化された状態ではランダム運動をして
いた)K流し1この流れに平行に基板を配置して被形成
面上にその膜厚が±5%以内のパラツキで0.1〜3μ
の厚さに被膜を形成せしめたことを特徴としているOさ
らにこの際プラズマをグロー放軍法を利用しておこさせ
るが、その電極を反応筒の外側に配置せしめ、多量の基
板に均一にプラズマがおこるようにしたことを特徴とし
ている01+被膜の形成に際し、図面の如く1段2列で
はなく、20段20列の如く反応筒を長くする場合、0
.4’tOrrではなくさらKO02,0,1,0、0
5torrとよシ低圧にすることが、その膜質の均−性
特に最前列と最後列との均一性を得しめる上に重要であ
る0 またこの反応筒内に酸素等の制御できない酸化物気体の
混入を防ぐため、別室を設け、この別室を介して大気中
での作業と結合せしめたことけ、得られた被膜の特性の
再現性を得るのにきわめて重要であった。
After forming a film on the surface to be formed in this manner and thoroughly purging the reaction tube, open the opening/closing door (34) and open the mixer mixing plate (34).
5) Transfer the substrate on the jig (3) to a separate chamber using an automatic extraction tube, and place both the reaction tube and the separate chamber under vacuum (0, (ltorr).
(below) K and moved. Furthermore, after closing the opening/closing door (34), the pulp was opened from (31) in a separate room and air was filled to bring it to atmospheric pressure. As is clear from the examples, in the present invention, after the reactive gases are mixed in the mixer (8), the exhaust port (6) is formed in a single layer (the gas was in random motion when it was turned into plasma). K sink 1 Place the substrate parallel to this flow, and deposit the film thickness on the surface to be formed with a variation of 0.1 to 3μ within ±5%.
The film is characterized by forming a film with a thickness of When forming a 01+ film, when the reaction tubes are made long, such as 20 stages and 20 rows, instead of 1 stage and 2 rows as shown in the drawing, 0
.. Not 4'tOrr but Sara KO02,0,1,0,0
It is important to maintain a pressure as low as 5 torr in order to obtain uniformity of the film quality, especially between the front and rear rows.Also, it is important to maintain a pressure as low as 5 torr. In order to prevent contamination, a separate room was provided, and the operation was connected to the atmosphere via this separate room, which was extremely important for obtaining reproducibility of the properties of the resulting coatings.

第2図は第1図の図面における排気口(6)方向よシみ
た基板(1)の配置と電極<9)、(1のとの関係を示
す。図面において体)は基板を水平、電極(9号(10
)による電磁界を水平方向に配置したもので、この場合
一度に導入できる基板の枚数をふやすことができる。
Figure 2 shows the relationship between the arrangement of the substrate (1) and the electrodes (1) when viewed from the direction of the exhaust port (6) in the drawing of Figure 1. (No. 9 (10
) in which the electromagnetic field is arranged horizontally.In this case, the number of substrates that can be introduced at once can be increased.

第2図CB)は電極(鴨(10)による電磁界、基板側
)ともに垂直にしたもので、基板の配置数が(4)の2
倍になる。
In Figure 2 CB), both electrodes (electromagnetic field by duck (10), substrate side) are vertical, and the number of substrates arranged is 2 (4).
Double.

第3図は本発明の半導体装置作製方法の操作手順チャー
トを示したものである。
FIG. 3 shows an operational procedure chart of the semiconductor device manufacturing method of the present invention.

図面において0″である0りは反応炉の真空引によるO
、 oxtorr以下の保持を示す。さらにa1″の0
0)は本発明による反応炉または反応筒およびホルダー
に珪素または炭化珪素のコーテイングを示す。
In the drawing, 0" is O due to vacuuming of the reactor.
, indicating retention below oxtorr. Furthermore, 0 of a1″
0) shows a coating of silicon or silicon carbide on the reactor or reaction tube and holder according to the invention.

このコーティングはその詳細を示すと第3図(B)、(
0)である。第3図(9)は真空引(49)により0.
01torr以下KL、10〜30分保持した後、水素
を電磁エネルギによ#)0〜30分30〜50Wの出力
によりプラズマクリーニングを行ない、吸着、水分、酸
素を除去した。さらにその水素を除去した後、←)によ
りヘリュームを同時に30〜50Wの出力によシュ0〜
30分プラズマ化し、さらに表面の水素を除去した。こ
の水素プラズマ発生(5o)に対しては、水素中に1〜
5%の濃度でHoe、または01を添加して行なうと、
塩素ラジカルが同時に発生し、このラジカルが石英等ホ
ルダーの内側に存在しているナトリュームの如きアルカ
リ金騙をすい出す効果を有する。このためパックグラウ
ンドレベルでのナトリューム、水分、酸素の濃度を形成
された被膜中にて1ocm以下にすることができ、きわ
めて重要な前処理工程であった〇 この塩素を添加した場合、さらにこの壁面に残留吸着し
た塩素を除去するため(51)の不活性気体によるスパ
ッタリングによる除去も有効であった。
The details of this coating are shown in Figure 3 (B), (
0). Figure 3 (9) shows that the vacuum is 0.0 by evacuation (49).
After maintaining the temperature at 0.01 torr or less for 10 to 30 minutes, plasma cleaning was performed using electromagnetic energy to remove hydrogen adsorption, moisture, and oxygen at an output of 30 to 50 W for 0 to 30 minutes. After further removing the hydrogen, the helium is simultaneously applied with an output of 30 to 50W using ←).
Plasma was generated for 30 minutes, and hydrogen on the surface was further removed. For this hydrogen plasma generation (5o), 1~
When Hoe or 01 is added at a concentration of 5%,
Chlorine radicals are generated at the same time, and these radicals have the effect of scooping out alkali metals such as sodium present inside the holder, such as quartz. For this reason, it was possible to reduce the concentration of sodium, moisture, and oxygen at pack ground level to 1 ocm or less in the formed film, which was an extremely important pretreatment step. In order to remove residual adsorbed chlorine, sputtering with an inert gas as described in (51) was also effective.

この後これらの系を真空引した後、珪化物気体であるシ
ランまたは炭化珪素化物であるτMBを導入し、プラズ
マエネルギによシ分解して、0.1〜2μ代表的には0
.2〜0.5pの厚さに形成させた。これらの被膜形成
をさせる際、高い電磁エネルギが力ねわる領域すなわち
不純物が再放出されやすい領域に特に厚くつきゃすく、
二重に好ましい結果をもたらせた。
After evacuating these systems, silane, which is a silicide gas, or τMB, which is a silicon carbide compound, is introduced and decomposed by plasma energy, typically 0.1 to 2μ.
.. It was formed to a thickness of 2 to 0.5p. When forming these films, they are particularly thick in areas where high electromagnetic energy is applied, that is, areas where impurities are likely to be re-released.
This yielded double positive results.

かかる本発明の複雑な前処理工程を行わない場合であっ
ても、第3図(0) K示す如く真空引の後、珪素また
は炭化珪素を(52)において同様に0.1〜2μ形成
し、反応炉壁がらの酸素、アルカリ金稿の再放出を防ぐ
ことが有効でめった。
Even when such a complicated pretreatment process of the present invention is not performed, silicon or silicon carbide is similarly formed in the range of 0.1 to 2 μm at (52) after evacuation as shown in FIG. 3(0)K. It was rarely effective to prevent the re-release of oxygen and alkali metal from the reactor walls.

また第3図(A) t、cおいては半導体装置の作製の
ため、基板のコーティング、系の真空引(4])さらに
PまたはN型半導体0作m(42)、工型半導体層の作
製(ai、y型半導体層の作製04)を行い、第1の半
導体装置を作製α8)シた。この半導体装置は前記した
p工、NX、 P工層、PN等の接合を少くとも1つ有
するディバイス設計仕kKよって作られなければならな
いことはいうまでもない。
In addition, in t and c of FIG. 3(A), for the fabrication of the semiconductor device, the substrate is coated, the system is evacuated (4)), the P or N type semiconductor is fabricated (42), and the molded semiconductor layer is formed. Fabrication (ai, fabrication of y-type semiconductor layer 04) was performed, and a first semiconductor device was fabricated α8). It goes without saying that this semiconductor device must be manufactured by a device design method having at least one junction of the above-described p-layer, NX, p-layer, PN, etc.

さらKこの後、この系に対し、反応炉のみまたけこの反
応炉とホルダーを挿入設置された反応系に対しく46)
K示す工型半導体層またはC2)に示す半導体層と同じ
半導体層のコーティングにワ にした。その詳細は第3図鴨(O入%(6)に示す。
After that, insert the reactor and the holder into this system.46)
The semiconductor layer shown in K or the same semiconductor layer as the semiconductor layer shown in C2) was coated. The details are shown in Figure 3 (O content % (6)).

すなわち第3図φ)は前記しfCill h ILと同
じく真空引(49)水素プラズマ放電(5o)ヘリュー
ムプラズi処理(51)、)4f4ryのランの最初の
工程の半導体層を形成する工程(52)を有する。しか
しこの(50) (5])がすでに■での06)で行わ
れているため、一般には(0)の(52)での0.1〜
2μの厚さの半導体層の作製で十分であった。
That is, Fig. 3 φ) is the same as the above-mentioned fCill h IL, evacuation (49), hydrogen plasma discharge (5o), helium plasma i treatment (51), and the step of forming a semiconductor layer in the first step of the run of )4f4ry ( 52). However, since this (50) (5]) has already been done in 06) in ■, generally 0.1 to (52) in (0)
It was sufficient to produce a semiconductor layer with a thickness of 2μ.

t7’?この前の半導体装置の作製(4o)すなわち前
のランでの履歴をなくす九め、鮪(IOK示すプラズマ
エツチング工程を行ってもよい0すなわち第3図(B)
は真空引(49)OIFま九は01P+OQl’J5%
)を第1図でのα力より導入し、20分〜1時間プラズ
マエツチング(5■を行なった。さらに真空引をしてそ
の後C1アの残留物を除去するため水素プラズマ処理(
50)を10〜30分、さらにとの1層に0.05〜0
.5μの1型または次の工程の最初のランの半導体層(
42)と同様の導電型、成分簡単な方法としては(6)
に示す(4G)の真空引、プラズマエツチング(5段残
部吸着ガスの除去(6o)C程を行なった。
t7'? In the fabrication of the previous semiconductor device (4o), that is, to eliminate the history of the previous run, a plasma etching step (IOK) may be performed (see FIG. 3(B)).
Vacuuming (49) OIF maku is 01P+OQl'J5%
) was introduced using the α force shown in Figure 1, and plasma etching (Step 5) was performed for 20 minutes to 1 hour. Further, vacuuming was performed, and then hydrogen plasma treatment (
50) for 10 to 30 minutes, and then 0.05 to 0.
.. 5μ type 1 or semiconductor layer of the first run of the next process (
A simple method using the same conductivity type and components as 42) is (6)
Vacuum evacuation and plasma etching (removal of remaining adsorbed gas in the 5th stage (6o) C) as shown in (4G) were carried out.

かくすることにより第1の半導体装置の作製(4B)の
最後工程c4)と次の工程(48)の最初の工程(42
)との間でPまたはN型の不純物が互いK(42)にて
混入する可能性を除去することができた。
By doing this, the last step c4) of the first semiconductor device fabrication (4B) and the first step (42) of the next step (48) are completed.
) could eliminate the possibility that P or N type impurities would be mixed in at K(42).

また0荀での炭素、ゲル!二予−ム等の添加物を02)
Kて混入することも防ぐことができた。
Carbon and gel at 0 xuan again! Additives such as pre-me 02)
It was also possible to prevent contamination with K.

かかる本発明の方法によりその効果を評価した結果を第
4図に示す0 第4図は本発明方法を用いて作られた光電変換装置の結
果である0この場合基板として金属例えばステンレス基
板または透光性基板であるガラス上にエテOを500〜
2000ム、さらにこの上に酸化スズまたは酸化アンチ
モンを100〜500ムの厚さに形成させた多重膜の電
極を有する基板を用いたOこの上KP型型化化珪素st
xc、、 O(X’−1)(例えばx* 0.3〜0.
5)を100〜300ムの厚さにまたこの1藺に真性ま
たは実質的に真性のムSまたは8ム8の珪素を0.4〜
0.′7μの厚さに、さらにこの上面KM型型化化珪素
sixo、−、oごXCX例えば!、0.3〜0.5)
を100〜300ムの厚さに形成さ、(1,(44)、
 (42i)・・・に対応させた。
The results of evaluating the effects of the method of the present invention are shown in FIG. 4. FIG. 4 shows the results of a photoelectric conversion device manufactured using the method of the present invention. 500 ~
2,000 μm, and a multilayer electrode on which tin oxide or antimony oxide is formed to a thickness of 100 to 500 μm.
xc,, O(X'-1) (for example, x* 0.3 to 0.
5) to a thickness of 100 to 300 μm, and to this layer, silicon of 0.4 μm to 0.4 μm to 0.4 μm to 8 μm of intrinsic or substantially intrinsic silicon is added.
0. '7μ thick, and further this upper surface KM type silicon sixo, -, o XCX for example! , 0.3-0.5)
(1, (44),
(42i)... has been made compatible.

さらにこの後この工程にITOを600〜800ムの厚
さKまたはアルミニューム金属膜を真空蒸着法で形成し
て光電変換装置を作った。その変換効率を第4図(A)
に示す。
Further, after this step, a photoelectric conversion device was fabricated by forming an ITO or aluminum metal film with a thickness of 600 to 800 μm by vacuum evaporation. Figure 4 (A) shows the conversion efficiency.
Shown below.

xcmのセルの大きさでムM 1(l OOmW/c 
j)の条件にて前処理00)をいれない場合Qυの3−
が、また前処理を行なうと00)の値が得られた。さら
に中間の06)の工程を加えることによるランL( (製造1〕鼻)のA14−の奪合(60)になシ全く加
えないと(6])が得られた。
With a cell size of x cm, M 1 (l OOmW/c
If pretreatment 00) is not included under the conditions of j), Qυ is 3-
However, when pretreatment was performed again, a value of 00) was obtained. Furthermore, by adding the intermediate step 06), (6) was obtained when no addition was made to the A14- capture (60) of run L ((Production 1) nose).

(60)はその効率が11〜9チを得ることができるの
に対し、本発明方法を用いない場合1〜4チしがなかっ
た。
(60) can obtain an efficiency of 11 to 9 inches, whereas when the method of the present invention is not used, there is no efficiency of 1 to 4 inches.

さらにこのセル面積をxooem”にすると、本発明方
法を用いると7〜9チの効率を得ることができるのに際
し、本発明方法を用いないと0〜391+であった。特
にダイオード特性がないものが30チ以上を有し、製造
不可能であり九。
Furthermore, if this cell area is xooem'', the efficiency of 7 to 9 cm can be obtained using the method of the present invention, whereas it was 0 to 391 + without using the method of the present invention.Especially for cells without diode characteristics. 9. has a diameter of 30 inches or more and is impossible to manufacture.

第4図φ)は特に表面程にてP型の半導体を作る工程で
1型の珪素半導体を作った場合の電気伝導度の値を示す
FIG. 4 φ) shows the value of electrical conductivity when a type 1 silicon semiconductor is made in the process of making a P type semiconductor especially at the surface.

前工程でP型半導体を作シ、本発明方法の中間処理法の
前処理を行なわない時、ムM1の光照射による電気伝導
度が(65)である。暗伝導度(64)漣の場合セ1卜
ゐ一′またその値も10〜10で大きにパラツキがあっ
た0他方本発明の前処理を行なった場合、光示”導度Q
O)、暗伝導度(1d)力監得られた。まえ中間処理を
行なった時す伝導度(6つ、暗伝導度(63)が得られ
た0これらは本発明におけるドーピング効果防止がいか
に重要であるかを明確に示したものであるO 以上の説明より明らかな如く、本発明は同一反応筒を用
いて光電変換装置または発光素子のみならず、電界効果
半導体装置、フォトセンサアレー等の各種の半導体装置
を作製する上にきわめて重要な製造装置および製造方法
を提供したものであり、これにより従来たて型のプラズ
マ0マD装fllftcc1ocm′を4まい作ると同
じ時間で、100〜500まいの基板上に非単結晶半導
体膜を作ることができ、きわめて多量生産向きである。
When a P-type semiconductor is produced in the pre-process and no pre-treatment is performed in the intermediate treatment method of the method of the present invention, the electrical conductivity of the beam M1 when irradiated with light is (65). In the case of dark conductivity (64), the value also varied greatly between 10 and 10.0 On the other hand, when the pretreatment of the present invention was performed, the light conductivity Q
O), dark conductivity (1d) force monitoring was obtained. When the intermediate treatment was performed, the conductivity (6) and the dark conductivity (63) were obtained. These clearly show how important it is to prevent doping effects in the present invention. As is clear from the description, the present invention is an extremely important manufacturing apparatus and device for manufacturing not only photoelectric conversion devices or light emitting devices, but also various semiconductor devices such as field effect semiconductor devices and photosensor arrays using the same reaction tube. This method provides a manufacturing method that enables the production of non-single-crystal semiconductor films on 100 to 500 substrates in the same amount of time as it would take to produce 4 layers of conventional vertical plasma 0M D device fllftcc1ocm. , is extremely suitable for mass production.

さらに本発明の如き電極構造または基板の配置をするこ
とによfi、PIN構造を有する光電変換装置において
10チ以上の変換効率をくシかえし安定して得ることが
でき、その膜質においてもきわめてすぐれたものであっ
た。
Furthermore, by arranging the electrode structure or substrate as in the present invention, it is possible to repeatedly and stably obtain a conversion efficiency of 10 or more in a photoelectric conversion device having a fi or PIN structure, and its film quality is also extremely excellent. It was something like that.

本発明においては、炭化珪素φiXO+−KO(x41
)を中心として記した。しかし反応性気体をゲルマンを
用いると、5ixGe、−(0!−x(−りを得ること
力文でき、第1のP工N構造を珪素と炭化珪素によシさ
らに第2のP工N構造を珪素と珪化ゲルマニュームによ
りP工NPIN構造いわゆるタンデム構造を得ることも
可能である。
In the present invention, silicon carbide φiXO+-KO (x41
). However, if germane is used as a reactive gas, it is possible to obtain 5ixGe, -(0! It is also possible to obtain a P-NPIN structure, a so-called tandem structure, by using silicon and germanium silicide.

本発明は第1図に示す横型のグラズマOVD装置を中心
として示した。しかしその電極の作シ方を誘電型とした
り、またアーク放電を利用するプラズマ0VD装置であ
っても本発明は有効である。またたて型、れ1偵型のペ
ルジャー型のプラズマ0VD装置であっても同様に本発
明方法を適用することができる。
The present invention has been mainly described with reference to a horizontal glasma OVD apparatus shown in FIG. However, the present invention is also effective in plasma 0VD devices in which the electrodes are made of a dielectric type or utilize arc discharge. Furthermore, the method of the present invention can be similarly applied to vertical and rectangular Pelger type plasma 0VD apparatuses.

【図面の簡単な説明】 第1図は本発明のプラズマ気相装置である。 第2図は第1図の一部を示す。 第S図は第1図の装置を用い、本発明方法のプラズマ気
相法を用いるチャートである。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a plasma vapor phase apparatus of the present invention. FIG. 2 shows a part of FIG. FIG. S is a chart using the plasma vapor phase method of the present invention using the apparatus shown in FIG.

Claims (1)

【特許請求の範囲】 1、 プラズマ気相法により反応炉内に設けられた基板
上に少くともひとつの接合を有する半導体装置を形成す
るに際し、前記反応炉の内壁または半導体層が形成され
る領域にあらかじめ真性または実質的に真性の半導体層
を形成することを特徴とする半導体装置作製方法。 2、特許請求の範囲第1項において、真性または実質的
に真性の半導体層は接合を有する半導体装置の作製に用
いられる電磁エネルギPoに対し、PO−10WA−P
O+30Wの範囲の電磁エネルギを加えて形成せしめる
ことを特徴とする半導体装置作製方法。 3、特許請求の範囲第1項において、真性または実質的
に真性の半導体層は接合を有す □る半導体装置を作製
することを特徴とする半導体装置作製方法。
[Claims] 1. When a semiconductor device having at least one junction is formed on a substrate provided in a reactor by a plasma vapor phase method, an inner wall of the reactor or a region where a semiconductor layer is formed. 1. A method for manufacturing a semiconductor device, comprising forming an intrinsic or substantially intrinsic semiconductor layer in advance. 2. In claim 1, the intrinsic or substantially intrinsic semiconductor layer is PO-10WA-P with respect to electromagnetic energy Po used for manufacturing a semiconductor device having a junction.
A method for manufacturing a semiconductor device, characterized in that the semiconductor device is formed by applying electromagnetic energy in the range of O+30W. 3. A method for manufacturing a semiconductor device according to claim 1, characterized in that the semiconductor device is manufactured in which the intrinsic or substantially intrinsic semiconductor layer has a junction.
JP56191268A 1981-11-28 1981-11-28 Manufacture of semiconductor device Granted JPS5892218A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56191268A JPS5892218A (en) 1981-11-28 1981-11-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56191268A JPS5892218A (en) 1981-11-28 1981-11-28 Manufacture of semiconductor device

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP1219302A Division JPH02119126A (en) 1989-08-25 1989-08-25 Manufacture of semiconductor device
JP3169305A Division JP2573108B2 (en) 1991-06-14 1991-06-14 Plasma processing method

Publications (2)

Publication Number Publication Date
JPS5892218A true JPS5892218A (en) 1983-06-01
JPH0512850B2 JPH0512850B2 (en) 1993-02-19

Family

ID=16271712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56191268A Granted JPS5892218A (en) 1981-11-28 1981-11-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5892218A (en)

Cited By (21)

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Publication number Priority date Publication date Assignee Title
JPS61256625A (en) * 1985-05-08 1986-11-14 Nippon Denso Co Ltd Manufacture of thin film semiconductor element
JPS63215037A (en) * 1987-03-04 1988-09-07 Toshiba Corp Manufacture of silicon thin film
JPH056877A (en) * 1991-06-14 1993-01-14 Semiconductor Energy Lab Co Ltd Etching method of carbon film
JPH0620975A (en) * 1992-09-11 1994-01-28 Semiconductor Energy Lab Co Ltd Carbon film manufacturing method
US5521400A (en) * 1982-08-24 1996-05-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor photoelectrically sensitive device with low sodium concentration
US5599732A (en) * 1995-08-21 1997-02-04 Northwestern University Method for growing III-V semiconductor films using a coated reaction chamber
US5632821A (en) * 1995-03-03 1997-05-27 Anelva Corporation Post treatment method for in-situ cleaning
US6020035A (en) * 1996-10-29 2000-02-01 Applied Materials, Inc. Film to tie up loose fluorine in the chamber after a clean process
US6028264A (en) * 1982-08-24 2000-02-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor having low concentration of carbon
US6121161A (en) * 1997-06-11 2000-09-19 Applied Materials, Inc. Reduction of mobile ion and metal contamination in HDP-CVD chambers using chamber seasoning film depositions
US6180991B1 (en) 1982-12-23 2001-01-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor having low concentration of phosphorous
US6221701B1 (en) 1984-05-18 2001-04-24 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor and its manufacturing method
USRE37441E1 (en) 1982-08-24 2001-11-13 Semiconductor Energy Laboratory Co., Ltd. Photoelectric conversion device
US6346716B1 (en) 1982-12-23 2002-02-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor material having particular oxygen concentration and semiconductor device comprising the same
US6589868B2 (en) 2001-02-08 2003-07-08 Applied Materials, Inc. Si seasoning to reduce particles, extend clean frequency, block mobile ions and increase chamber throughput
US6664566B1 (en) 1982-08-24 2003-12-16 Semiconductor Energy Laboratory Co., Ltd. Photoelectric conversion device and method of making the same
USRE38727E1 (en) 1982-08-24 2005-04-19 Semiconductor Energy Laboratory Co., Ltd. Photoelectric conversion device and method of making the same
US7038238B1 (en) 1985-05-07 2006-05-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a non-single crystalline semiconductor layer
US7109114B2 (en) 2004-05-07 2006-09-19 Applied Materials, Inc. HDP-CVD seasoning process for high power HDP-CVD gapfil to improve particle performance
US7465966B2 (en) 2003-03-19 2008-12-16 Semiconductor Energy Laboratory Co., Ltd. Film formation method and manufacturing method of semiconductor device
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Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6028264A (en) * 1982-08-24 2000-02-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor having low concentration of carbon
US6664566B1 (en) 1982-08-24 2003-12-16 Semiconductor Energy Laboratory Co., Ltd. Photoelectric conversion device and method of making the same
USRE37441E1 (en) 1982-08-24 2001-11-13 Semiconductor Energy Laboratory Co., Ltd. Photoelectric conversion device
USRE38727E1 (en) 1982-08-24 2005-04-19 Semiconductor Energy Laboratory Co., Ltd. Photoelectric conversion device and method of making the same
US5521400A (en) * 1982-08-24 1996-05-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor photoelectrically sensitive device with low sodium concentration
US6180991B1 (en) 1982-12-23 2001-01-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor having low concentration of phosphorous
US6346716B1 (en) 1982-12-23 2002-02-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor material having particular oxygen concentration and semiconductor device comprising the same
US6503771B1 (en) 1983-08-22 2003-01-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor photoelectrically sensitive device
US6660574B1 (en) 1984-05-18 2003-12-09 Semiconductor Energy Laboratory Co., Ltd. Method of forming a semiconductor device including recombination center neutralizer
US6221701B1 (en) 1984-05-18 2001-04-24 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor and its manufacturing method
US5556794A (en) * 1985-05-07 1996-09-17 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device having low sodium concentration
US6043105A (en) * 1985-05-07 2000-03-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor sensitive devices
US7038238B1 (en) 1985-05-07 2006-05-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a non-single crystalline semiconductor layer
JPS61256625A (en) * 1985-05-08 1986-11-14 Nippon Denso Co Ltd Manufacture of thin film semiconductor element
JPS63215037A (en) * 1987-03-04 1988-09-07 Toshiba Corp Manufacture of silicon thin film
JPH056877A (en) * 1991-06-14 1993-01-14 Semiconductor Energy Lab Co Ltd Etching method of carbon film
JPH0620975A (en) * 1992-09-11 1994-01-28 Semiconductor Energy Lab Co Ltd Carbon film manufacturing method
US5632821A (en) * 1995-03-03 1997-05-27 Anelva Corporation Post treatment method for in-situ cleaning
US5599732A (en) * 1995-08-21 1997-02-04 Northwestern University Method for growing III-V semiconductor films using a coated reaction chamber
US6223685B1 (en) 1996-10-29 2001-05-01 Applied Materials, Inc. Film to tie up loose fluorine in the chamber after a clean process
US6020035A (en) * 1996-10-29 2000-02-01 Applied Materials, Inc. Film to tie up loose fluorine in the chamber after a clean process
US6121161A (en) * 1997-06-11 2000-09-19 Applied Materials, Inc. Reduction of mobile ion and metal contamination in HDP-CVD chambers using chamber seasoning film depositions
US6589868B2 (en) 2001-02-08 2003-07-08 Applied Materials, Inc. Si seasoning to reduce particles, extend clean frequency, block mobile ions and increase chamber throughput
US6846742B2 (en) 2001-02-08 2005-01-25 Applied Materials, Inc. Si seasoning to reduce particles, extend clean frequency, block mobile ions and increase chamber throughput
US7465966B2 (en) 2003-03-19 2008-12-16 Semiconductor Energy Laboratory Co., Ltd. Film formation method and manufacturing method of semiconductor device
US7109114B2 (en) 2004-05-07 2006-09-19 Applied Materials, Inc. HDP-CVD seasoning process for high power HDP-CVD gapfil to improve particle performance
WO2014050304A1 (en) * 2012-09-27 2014-04-03 三洋電機株式会社 Photoelectric conversion element and method for manufacturing same
JPWO2014050304A1 (en) * 2012-09-27 2016-08-22 パナソニックIpマネジメント株式会社 Photoelectric conversion element and manufacturing method thereof

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