WO2020026516A1 - 半導体装置、焼結金属シートおよび焼結金属シートの製造方法 - Google Patents

半導体装置、焼結金属シートおよび焼結金属シートの製造方法 Download PDF

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WO2020026516A1
WO2020026516A1 PCT/JP2019/011935 JP2019011935W WO2020026516A1 WO 2020026516 A1 WO2020026516 A1 WO 2020026516A1 JP 2019011935 W JP2019011935 W JP 2019011935W WO 2020026516 A1 WO2020026516 A1 WO 2020026516A1
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Prior art keywords
sintered metal
low porosity
metal layer
region
semiconductor device
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English (en)
French (fr)
Japanese (ja)
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鈴木　智久
守谷　浩志
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Hitachi Ltd
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Hitachi Ltd
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Priority to US17/261,715 priority Critical patent/US11437338B2/en
Publication of WO2020026516A1 publication Critical patent/WO2020026516A1/ja
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Definitions

  • the present invention relates to a semiconductor device, a sintered metal sheet, and a method for manufacturing a sintered metal sheet that are suitably used for power conversion equipment and the like.
  • a power module using a SiC semiconductor can operate at a high temperature of 200 ° C. or higher, and can not only increase the efficiency of power conversion but also significantly reduce the size and weight.
  • a lead-free solder conventionally used as a chip bonding material cannot be used due to a remelting problem.
  • High-melting-point solders with a lead content of 85% or more, which are currently excluded from the RoHS (Restriction of Hazardous Substances) directive will inevitably be subject to the RoHS directive in the future. Therefore, there is an urgent need to develop a substitute material for lead-free solder.
  • the bonding layer made of a sintered metal material has a porous structure including pores inside as shown in Patent Document 1, for example.
  • a semiconductor element is bonded to a substrate via a sintered metal material as disclosed in Patent Document 2, for example.
  • Patent Document 1 a sintered metal sheet prepared by preliminarily heating and temporarily sintering a metal paste material mixed with metal fine particles and an organic solvent was placed on a substrate, and a semiconductor element was mounted thereon. Thereafter, a method of heating and sintering again to join the semiconductor element to the substrate is shown. Further, in Patent Document 2, a metal paste material in which metal fine particles and an organic solvent are mixed is applied on a substrate, a semiconductor element is mounted thereon, and then the metal paste material is sintered by heating. A method for bonding to a substrate is shown.
  • the pressure during sintering may be increased to lower the porosity of the sintered metal layer.
  • the pressure during sintering is too high, the rigidity of the sintered metal layer becomes too high, which causes another problem that peripheral members such as semiconductor elements are easily damaged.
  • Patent Document 2 discloses that the porosity is low in a portion near the side of the semiconductor element and the porosity is low in a portion near the center by making a difference in the thickness of the metal paste when applying the metal paste.
  • a technique for forming a sintered metal layer having an increased surface roughness In such a sintered metal layer, the outer edge is formed hard, so that the growth of a crack from the outer edge can be suppressed.
  • Patent Document 3 discloses a technique of forming a sintered metal layer having a region with a lower porosity at a peripheral portion or a corner portion of a semiconductor element than at a central portion by using two types of metal pastes. ing.
  • Patent Document 4 discloses a sintered metal layer having a region with low porosity at its outer edge and corners by disposing a metal foam after applying a metal paste and densifying the metal foam by a sintering process. Are disclosed.
  • the porosity of the sintered metal layer is high, that is, since the gap is large, the sintered metal layer There is a problem that cracks are likely to occur from the sides and corners. Further, if the porosity of the sintered metal layer is simply reduced, stress is concentrated on the interface between the sintered metal layer and the semiconductor element, and there is a problem that separation is likely to occur at the interface.
  • Patent Document 4 also mentions a sintered metal layer having a region with a low porosity inside the outer edge portion, but the region with a low porosity is printed after printing a metal paste of a material. It is formed by a method of mounting another member (metal foam) from the upper part of the surface. For this reason, the size of the metal foam to be arranged needs to be large enough to be self-sustaining, due to the workability of the mount. That is, it is difficult to form a low porosity region with a fine pattern.
  • an object of the present invention is to provide a highly reliable semiconductor device, a sintered metal sheet, and a sintered metal capable of suppressing risks such as peeling, crack propagation, and semiconductor element destruction.
  • An object of the present invention is to provide a sheet manufacturing method.
  • the present invention is a semiconductor device in which a semiconductor element is bonded onto a support substrate via a sintered metal layer, and the sintered metal layer has an outer peripheral portion of the semiconductor element when bonded.
  • a low porosity region having a lower porosity than other regions is formed in a region corresponding to the inside.
  • a highly reliable semiconductor device a sintered metal sheet, and a method for manufacturing a sintered metal sheet that can suppress risks such as occurrence of peeling, crack propagation, and semiconductor element destruction.
  • FIG. 2 is a view showing an example of a cross-sectional structure of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a diagram illustrating an example of a top view of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a diagram showing a difference in structure between the semiconductor device according to the first embodiment of the present invention and a semiconductor device according to the related art.
  • FIG. 6 is a view showing a difference between the effects of the semiconductor device according to the first embodiment of the present invention and the semiconductor device according to the related art.
  • FIG. 1 is a view showing an example of a cross-sectional structure of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a diagram illustrating an example of a top view of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a diagram showing a difference in structure between the semiconductor device according to the first embodiment of the present invention and a semiconductor device according to the related art.
  • FIG. 6 is
  • FIG. 4 schematically shows a state in which a crack generated from an end of the sintered metal layer of the semiconductor device according to the first embodiment of the present invention propagates inside the sintered metal layer and is stopped and stopped in a low porosity region.
  • FIG. FIG. 7 is a view showing an example of a cross-sectional structure of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 6 is a diagram illustrating an example of a top view of a semiconductor device according to a second embodiment of the present invention.
  • FIG. 9 is a view showing an example of a cross-sectional structure of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 11 is a diagram illustrating an example of a top view of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 14 is a view showing an example of a cross-sectional structure of a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 14 is a diagram showing an example of a top view of a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 14 is a view showing an example of a cross-sectional structure of a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 14 is a diagram showing an example of a top view of a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 4 is a view showing an example of a process of manufacturing a sheet of a sintered metal layer in a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a diagram showing an example of a process of forming a low porosity region in a sintered metal layer and manufacturing a sintered metal sheet in a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a diagram illustrating an example of a process of manufacturing a semiconductor device using a sintered metal sheet in a process of manufacturing the semiconductor device according to the first embodiment of the present invention. It is the figure which showed the example of the result which computed the temperature distribution inside the sintered metal layer at the time of the heating by energization by thermal analysis simulation.
  • FIG. 1A is a diagram showing an example of a cross-sectional structure of a semiconductor device 100 according to the first embodiment of the present invention
  • FIG. 1B is an example of a top view of the semiconductor device 100 according to the second embodiment of the present invention.
  • a semiconductor device 100 is configured by joining a semiconductor element 1 to a support substrate 10 via a sintered metal layer 2.
  • the top view of the semiconductor device 100 in FIG. 1B shows a top view in a state where the semiconductor element 1 is removed
  • the cross-sectional view in FIG. 1 shows a cross-sectional view including an element 1.
  • FIG. 1A is a diagram showing an example of a cross-sectional structure of a semiconductor device 100 according to the first embodiment of the present invention
  • FIG. 1B is an example of a top view of the semiconductor device 100 according to the second embodiment of the present invention.
  • FIG. 1A and 1B a semiconductor device 100 is configured by joining a semiconductor element 1 to a support substrate 10 via a sintered metal layer 2.
  • the semiconductor element 1 is an IGBT (Insulated Gate Bipolar Transistor) or a diode for current control, and is made of a semiconductor material such as silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • a semiconductor material such as silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • the semiconductor material it is preferable to use a wide band gap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) with low power loss.
  • the support substrate 10 has a three-layer structure including the conductive member 4, the insulating member 5, and the cooling member 6.
  • each of the conductive member 4 and the cooling member 6 is made of a conductive material having high electric conductivity or heat conductivity such as copper (Cu) or aluminum (Al).
  • the insulating member 5 is made of an insulating material such as aluminum nitride (AlN), silicon nitride (Si3N4), aluminum oxide (Al2O3), a resin sheet, and grease.
  • the cross-sectional structure of the semiconductor device 100 is not limited to this, and may be a structure in which the periphery of the semiconductor element 1 is covered with a sealing material.
  • a sealing material an insulating material including a thermosetting resin such as an epoxy resin and a silica filler, a silicone gel, or the like is used.
  • the support substrate 10 may be configured entirely of the conductive member 4.
  • FIG. 1A shows only a semiconductor device 100 in which one semiconductor element 1 is bonded on a support substrate 10, the semiconductor device 100 has a plurality of semiconductor elements 1 on one support substrate 10. 1 may be joined.
  • the sintered metal layer 2 is made of a sintered metal bonding material obtained by firing a paste material in which fine particles of metal such as Ag, Cu, Au, Ni, and Pt on the order of nm to ⁇ m and an organic solvent are mixed. In this case, it is preferable to use Ag or Cu as the metal fine particles of the paste.
  • the sintered metal joining material thus obtained is a porous body having a large number of pores inside.
  • a low porosity region 3 having a lower porosity than other regions is provided in the sintered metal layer 2.
  • the low porosity region 3 is made of a sintered metal bonding material obtained by sintering a paste material having the same composition as that of the sintered metal layer 2, and is characterized in that the porosity is higher than other regions.
  • the low porosity region 3 is formed along the outer edge of the semiconductor element 1 in the sintered metal layer 2 inside the outer edge of the semiconductor element 1 when joined. It is formed so as to make one round of the part.
  • the low porosity region 3 is formed so as to penetrate the sintered metal layer 2 from the upper surface to the lower surface of the sintered metal layer 2 as shown in FIG. 1A.
  • the low porosity region 3 divides the sintered metal layer 2 in plane into a high porosity region on the outside and a high vacancy region on the inside, and has a planar shape in the form of an elongated cord. It can be called a structure.
  • a low porosity region 3 does not necessarily need to be formed linearly in plan view, but may be formed in a wavy curved shape.
  • the planar shape is preferably a symmetrical pattern in order to avoid biased deformation due to stress.
  • the porosity of the low porosity region 3 is preferably higher by at least 10% than the porosity of the region of the sintered metal layer 2 other than the low porosity region 3.
  • the porosity of the region 3 is preferably less than 10%.
  • the structure in the vertical direction (z-axis direction) of the low porosity region 3 is not limited to a single layer having a constant porosity. It may be composed of layers.
  • FIG. 2A is a diagram illustrating a difference in structure between the semiconductor device 100 according to the first embodiment of the present invention and the semiconductor device 101 according to the related art
  • FIG. 2B is a diagram illustrating a semiconductor according to the first embodiment of the present invention
  • FIG. 11 is a diagram showing a difference in effect between the device 100 and a semiconductor device 101 according to the related art
  • 2A are a cross-sectional structure and a top view of the semiconductor device 100 according to the first embodiment, and are substantially the same as FIG. 1. However, the cross-sectional structure is shown as the structure of the outer edge of the semiconductor device 100.
  • 2A are a cross-sectional structure and a top view of the semiconductor device 101 according to the related art, and the cross-sectional structure is shown as a structure of an outer edge portion of the semiconductor device 101.
  • FIG. 2B shows the results of calculating and comparing the stress applied to the semiconductor element 1 in each of the semiconductor device 100 according to the first embodiment and the conventional semiconductor device 101.
  • the following conditions were set for each of the semiconductor device 100 according to the present embodiment and the semiconductor device 101 according to the related art.
  • the chip size of the semiconductor element 1 was 5 mm ⁇ 5 mm.
  • the low porosity region 3 in the sintered metal layer 2 is provided with a width of 0.2 mm just below the outer edge of the semiconductor element 1 by 1 mm inside. did.
  • the low porosity region 3 is provided at a position immediately below the outer edge of the semiconductor device 101, that is, at the outer edge of the sintered metal layer 2 with a width of 0.2 mm.
  • the sintered metal layer 2 was a sintered copper (Cu) layer having a thickness of 50 ⁇ m in each case.
  • the semiconductor element 1 is made of Si
  • the insulating member 5 is made of AlN
  • the conductive member and the cooling member are made of Cu
  • the stress distribution when a temperature change from 200 ° C. to ⁇ 40 ° C. is applied to the entire semiconductor devices 100 and 101 is finite. Calculated by element analysis.
  • the stress applied to the semiconductor element 1 is reduced to about 1 / 1.3 at the position A in the first embodiment and 1 at the position B in the first embodiment as compared with the related art. /2.1.
  • position A represents the upper and lower center position of the outer peripheral end of semiconductor element 1
  • position B is the outer peripheral end of the interface between semiconductor element 1 and sintered metal layer 2. Indicates the position.
  • the stress applied to the semiconductor element 1 is smaller than that in the related art, the damage to the semiconductor element 1 is reduced, and the risk of the semiconductor element 1 being broken is also reduced. . In addition, the risk of separation between the semiconductor element 1 and the sintered metal layer 2 is reduced.
  • FIG. 3 shows that the crack 8 generated from the end of the sintered metal layer 2 of the semiconductor device 100 according to the first embodiment propagates into the sintered metal layer 2 and is stopped and stopped in the low porosity region 3.
  • FIG. 3 is a diagram schematically showing the state of the operation.
  • the outer edge of the sintered metal layer 2 is a high porosity region, a crack is easily generated from the outer peripheral end.
  • the wall-shaped low porosity region 3 is provided at the inner position, the crack progresses. Is stopped in the low porosity region 3 and stopped.
  • FIG. 4A is a diagram showing an example of a cross-sectional structure of a semiconductor device 100a according to the second embodiment of the present invention
  • FIG. 4B is an example of a top view of the semiconductor device 100a according to the second embodiment of the present invention.
  • the semiconductor device 100a is configured by joining a semiconductor element 1 to a support substrate 10 via a sintered metal layer 2.
  • the top view of the semiconductor device 100a in FIG. 4B shows a top view in a state where the semiconductor element 1 is removed
  • the cross-sectional view in FIG. 4A shows the semiconductor in the Ya-Ya portion in the plan view in FIG. 4B. 1 shows a cross-sectional view including an element 1.
  • FIG. 4A shows a diagram showing an example of a cross-sectional structure of a semiconductor device 100a according to the second embodiment of the present invention
  • FIG. 4B is an example of a top view of the semiconductor device 100a according to the second embodiment of the present invention.
  • FIG. 4A shows a top view in a
  • the difference between the semiconductor device 100a according to the present embodiment and the semiconductor device 100 according to the first embodiment is that a sintered metal layer 2 has a low porosity region 3 provided therein. Except for this, the structures of the two are almost the same. Therefore, the following mainly describes the points different from the first embodiment.
  • the low porosity region 3 is preferably formed so as to have no corners (a circle, an ellipse, or the like) when viewed from above. This is for the purpose of avoiding stress that tends to concentrate on the corners.
  • the low porosity region 3 looks like a column when viewed from the side, the column does not need to be a straight columnar column, and may be a column having a curved surface such as a barrel type or a constricted type.
  • the pillar may be a pillar that is inclined obliquely.
  • the diameter of these columns is preferably at least larger than the diameter of the pores in the sintered metal layer 2 and smaller than the thickness of the sintered metal layer 2, for example, about 5 ⁇ m to 100 ⁇ m.
  • a plurality of columnar low porosity regions 3 are continuously formed, and the semiconductor element 1 is included in the sintered metal layer 2 which is located inside the outer edge of the semiconductor element 1 to be joined. Is formed so as to surround the region immediately below the central portion of the semiconductor element 1 along the outer edge of the semiconductor device 1.
  • the columnar low porosity regions 3 need not be formed in a line as shown in FIG. 4B, but may be formed in a plurality of lines as long as they are formed along the outer edge of the semiconductor element 1.
  • the arrangement may be a staggered arrangement or a random arrangement. However, in order to avoid bias of deformation due to stress, the planar shape of the arrangement is preferably a symmetric pattern.
  • the low porosity region 3 is made of a sintered metal bonding material obtained by sintering a paste material having the same composition as the sintered metal layer 2, and has a higher porosity than other regions.
  • the porosity of the low porosity region 3 is preferably at least 10% or more higher than the porosity of the region of the sintered metal layer 2 other than the low porosity region 3.
  • the porosity of the rate region 3 is preferably less than 10%.
  • the crack that occurs at the outer peripheral end of the sintered metal layer 2 and propagates to the inside easily hits the low porosity region 3, so that the effect of suppressing the crack growth is expected. be able to.
  • the low porosity region 3 is formed of minute columns, it has flexibility against shear deformation. Therefore, peeling at the interface with the semiconductor element 1 and damage to peripheral members including the semiconductor element 1 can be reduced.
  • the low porosity region 3 is formed of minute columns, cracks in the thickness direction are more likely to occur than cracks in the direction along the surface of the sintered metal layer 2. The thermal conductivity and electrical conductivity of the binding metal layer 2 are not impaired. Conversely, as the crack propagates in the thickness direction, the stress in the sintered metal layer 2 is alleviated, so that the effect of suppressing the generation and propagation of the subsequent crack can be expected.
  • FIG. 5A is a diagram showing an example of a cross-sectional structure of a semiconductor device 100b according to the third embodiment of the present invention
  • FIG. 5B is an example of a top view of the semiconductor device 100b according to the third embodiment of the present invention.
  • the semiconductor device 100b is configured by joining a semiconductor element 1 to a support substrate 10 via a sintered metal layer 2.
  • the top view of the semiconductor device 100b in FIG. 5B shows a top view in a state where the semiconductor element 1 is removed
  • the cross-sectional view in FIG. 5A shows the semiconductor in the Yb-Yb portion in the plan view in FIG. 5B
  • 1 shows a cross-sectional view including an element 1.
  • FIG. 5A shows a cross-sectional view including an element 1.
  • the difference between the semiconductor device 100b according to the present embodiment and the semiconductor device 100a according to the second embodiment is that the sintered metal layer 2 is a method of arranging the columnar low porosity region 3 provided in the inside 2. Except for this, the structures of the two are almost the same. Therefore, the following mainly describes the points different from the second embodiment.
  • the columnar low porosity region 3 is provided in the sintered metal layer 2.
  • the columnar low porosity region 3 is formed in the sintered metal layer 2 corresponding to immediately below four corners inside the outer edge of the semiconductor element 1 as shown in FIG. 5B. Provided.
  • the columnar low porosity region 3 is provided near the four corners of the sintered metal layer 2, thereby efficiently suppressing the growth of cracks generated at the end of the sintered metal layer 2. be able to. Further, in the present embodiment, since the number of the columnar low porosity regions 3 formed in the sintered metal layer 2 can be reduced, the steps of the manufacturing process for forming the low porosity regions 3 are simplified. The effect can be expected.
  • the number is not limited to three.
  • the low porosity region 3 may be arranged in any manner as long as it is arranged near each corner of the sintered metal layer 2.
  • the planar shape of the arrangement is preferably a symmetric pattern.
  • FIG. 6A is a diagram showing an example of a cross-sectional structure of a semiconductor device 100c according to the fourth embodiment of the present invention
  • FIG. 6B is an example of a top view of the semiconductor device 100c according to the fourth embodiment of the present invention.
  • the semiconductor device 100c is configured by joining a semiconductor element 1 to a support substrate 10 via a sintered metal layer 2.
  • the top view of the semiconductor device 100c in FIG. 6B shows a top view in a state where the semiconductor element 1 is removed
  • the cross-sectional view in FIG. 6A shows the semiconductor in the Yc-Yc portion in the plan view in FIG. 6B
  • 1 shows a cross-sectional view including an element 1.
  • the difference between the semiconductor device 100c according to the present embodiment and the semiconductor device 100a according to the second embodiment is that the sintered metal layer 2 is a method of arranging the columnar low porosity region 3 provided in the inside 2. Except for this, the structures of the two are almost the same, and therefore, the points that are different from the second embodiment will be mainly described.
  • the columnar low porosity region 3 is provided in the sintered metal layer 2.
  • the low porosity regions 3 are spread at predetermined intervals over the entire region of the sintered metal layer 2 immediately below the inner region from the outer edge of the semiconductor element 1. It is provided in such a manner. Therefore, also in the present embodiment, it is possible to expect an effect of suppressing a crack generated at an end portion of the sintered metal layer 2 from extending to the center along the surface of the sintered metal layer 2.
  • cracks generated in the sintered metal layer 2 are easily induced in the thickness direction, but the cracks in the thickness direction do not impair the thermal conductivity and the electrical conductivity of the sintered metal layer 2. .
  • the stress in the sintered metal layer 2 is alleviated, so that the effect of suppressing the subsequent generation and propagation of the crack can be expected.
  • a large number of columnar low porosity regions 3 having excellent thermal conductivity and electrical conductivity are provided over the entire region between the semiconductor element 1 and the conductive member 4 of the support substrate 10. The effect of improving the heat dissipation and electrical conductivity of the sintered metal layer 2 can be expected.
  • the columnar low porosity regions 3 need not be regularly arranged at regular intervals in the sintered metal layer 2 as shown in FIG. Whatever is done is good. However, in order to avoid bias of deformation due to stress, it is preferable that the entire arrangement be a pattern symmetrical in a plane.
  • FIG. 7A is a diagram showing an example of a cross-sectional structure of a semiconductor device 100d according to the fifth embodiment of the present invention
  • FIG. 7B is an example of a top view of the semiconductor device 100d according to the fifth embodiment of the present invention.
  • the semiconductor device 100d is configured by joining a semiconductor element 1 to a support substrate 10 via a sintered metal layer 2.
  • the top view of the semiconductor device 100d in FIG. 7B shows a top view in a state where the semiconductor element 1 is removed
  • the cross-sectional view in FIG. 7A shows the semiconductor in the Yd-Yd portion in the plan view in FIG. 7B
  • 1 shows a cross-sectional view including an element 1.
  • FIG. 7A shows a cross-sectional view including an element 1.
  • the semiconductor device 100d according to the present embodiment is different from the semiconductor device 100 according to the first embodiment.
  • a semiconductor device 100c according to the fourth embodiment That is, in the present embodiment, in the sintered metal layer 2, the wall-shaped low porosity region 3a and the columnar low porosity region 3b are provided.
  • the wall-shaped low porosity region 3a is formed in the sintered metal layer 2 which is located inside the outer edge of the semiconductor element 1 to be joined, as in the first embodiment. It is formed so as to surround a region just below the center of the semiconductor element 1 along the outer edge. Further, the columnar low porosity region 3b is formed in the sintered metal layer 2 at a position closer to the center than the wall-like low porosity region 3a.
  • FIG. 8A is a diagram showing an example of a process of manufacturing a sheet of the sintered metal layer 2 in the manufacturing process of the semiconductor device 100 according to the first embodiment of the present invention
  • FIG. FIG. 8C shows an example of a process of forming the low porosity region 3 therein and manufacturing the sintered metal sheet 20
  • FIG. 8C shows an example of a process of manufacturing the semiconductor device 100 using the sintered metal sheet 20.
  • FIG. Here, for convenience of explanation, a sintered metal sheet 20 in which a low porosity region 3 is formed in a sintered metal layer 2 is referred to as a sintered metal sheet 20, and a sintered metal sheet before the low porosity region 3 is formed is a sintered metal sheet.
  • a sheet of layer 2 in general, both should be called sintered metal sheets.
  • a paste material 21 prepared by mixing fine metal particles of several tens nm to several hundreds nm and an organic solvent is applied on the plate 11 in a sheet shape by a screen printing method, a dispensing method, or the like. Subsequently, the applied paste material 21 is baked at about 70 ° C. to 400 ° C. and removed from the plate 11 to obtain a sheet of the sintered metal layer 2.
  • a portion of the sheet of the sintered metal layer 2 where the low porosity region 3 is to be formed is locally heated. Heating in this case can be realized by local heating by a heater, local energization, local pressurization, and the like.
  • the heating, energizing, and pressing jigs corresponding to the planar shape of the low porosity region 3 shown in the first to fifth embodiments are used, so that the desired metal is formed in the sintered metal layer 2.
  • the low porosity region 3 can be formed.
  • FIG. 8B a method of heating by local energization is shown. That is, the electrodes 9 are arranged on the upper and lower surfaces of the sintered metal layer 2 at positions corresponding to the planar shape in which the low porosity region 3 is to be formed, and the sintered metal layers 2 located between the upper and lower electrodes 9 are arranged. Is energized to the region 31 in the inside. By this energization, the region 31 of the sintered metal layer 2 sandwiched between the upper and lower electrodes 9 is heated at a temperature higher than the sintering temperature of the sintered metal layer 2. As a result, sintering locally proceeds in the region 31 of the sintered metal layer 2 sandwiched between the upper and lower electrodes 9, and the sintered metal sheet 20 having the low porosity region 3 is manufactured.
  • the electrodes 9 are applied to the upper and lower electrodes 9 one by one for each of the plurality of columnar low porosity regions 3. You may energize while.
  • a plurality of electrodes 9 corresponding to the plurality of low porosity regions 3 are provided above and below the plurality of columnar low porosity regions 3, and the plurality of upper and lower electrodes 9 are energized at once. Is also good.
  • the wall-shaped low porosity region 3 for example, the wall-shaped electrode 9 as shown in FIG. May be formed.
  • the region 31 in the sintered metal layer 2 is heated by energization using the upper and lower electrodes 9 to form the low porosity region 3 has been described. Instead, heat generated by a local heater or heat generated by a local pressurization may be used.
  • the temperature for forming the low porosity region 3 is preferably 200 ° C. or more when the sintered metal layer 2 is sintered silver and 350 ° C. or more when the sintered metal layer 2 is sintered copper.
  • a major feature of the process for manufacturing the sintered metal sheet 20 described above is that the entire sintered metal sheet 20 having the low porosity region 3 can be formed of the same material. That is, since the low porosity region 3 is made of the same material as that of the sintered metal layer 2, problems such as poor joining and peeling due to different materials do not occur. Further, advantages such as simplification of the process of manufacturing the sintered metal sheet 20 can be expected.
  • the sintered metal sheet 20 is disposed on the conductive member 4 of the support substrate 10, and the semiconductor element 1 is further disposed thereon, in a high-temperature atmosphere of about 200 ° C. to 400 ° C. Then, the sintered metal sheet 20 is sintered and bonded to the semiconductor element 1 and the supporting substrate 10. At this time, in order to obtain good sinter bonding, it is preferable to apply a pressure of 0.01 MPa or more simultaneously with the heating. Further, it is preferable to select an appropriate atmosphere, such as in the air, N2, or H2, according to the metal fine particles used at that time.
  • FIGS. 8A to 8C illustrate the manufacturing process of the semiconductor device 100 according to the first embodiment, the description is based on the manufacturing processes of the semiconductor devices 100a to 100d according to the second to fifth embodiments. The same can be applied to the process.
  • FIG. 9 is a diagram showing a result of calculating a temperature distribution inside the sintered metal layer 2 at the time of heating by energization by a thermal analysis simulation.
  • the thermal analysis simulation in this case is based on a two-dimensional axisymmetric model. Therefore, the calculation result corresponds to a temperature distribution when the columnar low porosity region 3 is formed.
  • the thickness of the sheet of the sintered metal layer 2 was set to 50 ⁇ m, and the diameter of the energized region of the electrode 9 was set to 6 ⁇ m, and the temperature distribution inside the sintered metal layer 2 due to heat generation during energization was calculated.
  • FIG. 9 shows the calculated temperature distribution in the form of an isotherm. In this case, the horizontal axis represents the distance from the center of the circular electrode 9 and the vertical axis represents the position of the sintered metal layer 2 in the thickness direction.
  • the region where the temperature is 200 ° C. or higher is a columnar region having a diameter of about 40 ⁇ m, and that a neck is formed at the center in the thickness direction. Therefore, for example, in the case of a material whose sintering starts at 200 ° C. or higher, the low porosity region 3 is formed in such a columnar region.
  • the low porosity region 3 is formed as a fine structure or pattern which has been conventionally difficult. It can be formed in the sintered metal layer 2. Therefore, in the semiconductor device 100 manufactured using the sintered metal layer 2 (sintered metal sheet 20) in which the low porosity region 3 is formed, it is easy to disperse the stress in the sintered metal layer 2, A structure capable of preventing the occurrence and progress of cracks and peeling is realized.
  • the present invention is not limited to the embodiment and the modified examples described above, and includes various modified examples.
  • the above-described embodiments and modified examples have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described above.
  • a part of the configuration of an embodiment or a modified example can be replaced with the configuration of another embodiment or a modified example. Can be added.
  • the configuration included in another embodiment or modification can be added, deleted, or replaced.

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