WO2020024547A1 - 一种选择性背金芯片封装结构及其工艺方法 - Google Patents

一种选择性背金芯片封装结构及其工艺方法 Download PDF

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WO2020024547A1
WO2020024547A1 PCT/CN2018/124572 CN2018124572W WO2020024547A1 WO 2020024547 A1 WO2020024547 A1 WO 2020024547A1 CN 2018124572 W CN2018124572 W CN 2018124572W WO 2020024547 A1 WO2020024547 A1 WO 2020024547A1
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chip
trench
pad
substrate
gold
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PCT/CN2018/124572
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English (en)
French (fr)
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王杰
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江苏长电科技股份有限公司
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Publication of WO2020024547A1 publication Critical patent/WO2020024547A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings

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  • the invention relates to a selective gold back chip packaging structure and a process method thereof, and belongs to the technical field of semiconductor packaging.
  • GaAs chips in order to meet the requirements of electrical performance, will be designed with selective gold backing design, as shown in Figure 1, where A and C areas are gold-plated areas, B area is an isolation area, left and right gold-plated areas C is a signal pad, and the large gold-plated area A is a ground pad.
  • the signal pad must not be bridged with any other gold-plated area, otherwise it will short-circuit and affect performance.
  • the chip is getting smaller and smaller, the distance between the signal pad and the ground pad is small, and the substrate design problem, if using the traditional dispensing process, not only the bridging risk is very large, but the left and right signal pads may not be covered Silver glue, which can't connect with the chip.
  • the technical problem to be solved by the present invention is to provide a selective gold backed chip packaging structure and a process method for the above-mentioned prior art.
  • a laser slot is provided on the surface of the chip. The channel, by means of laser passing through the plastic material layer and the chip layer and filling the insulating material after the normal chip encapsulation, isolates and blocks the ground pads and signal pads, and solves the bridge or The problem that the signal pad cannot be connected to the chip.
  • a selective back gold chip packaging structure which includes a substrate, and the chip is provided with a chip through silver glue, and the chip includes a signal pad and a ground pad.
  • a plastic sealing material is encapsulated above the chip, and a groove is formed on the plastic sealing material in an isolation region corresponding to the signal pad and the ground pad, and the groove extends downward to the surface of the substrate, in the groove. Fill with insulating material.
  • the groove size of the molding compound area is larger than the groove size of the chip area.
  • a process method for selectively backing a gold chip packaging structure includes the following steps:
  • Step one perform glueing operation on the back of the chip in a normal manner to ensure the coverage of the silver glue on the back of the chip;
  • Step 2 Load the film and wire to normal encapsulation during normal operation
  • Step 3 Laser grooving. After encapsulation, the groove is formed by laser on the surface of the plastic packaging material corresponding to the isolation area between the chip ground pad and the signal pad. The laser passes through the plastic sealing layer and the chip layer in sequence to the substrate surface;
  • Step 4 Fill the trench with insulating material to block the ground pads and signal pads.
  • Step five curing the insulation material in the trench
  • Step 6 Follow-up processes, such as cutting, complete the packaging.
  • the laser groove range of the plastic sealing material layer in step 3 is larger than the laser groove range of the chip layer.
  • a selective gold backed chip packaging structure and a method for the same are provided.
  • the chip is designed to be selectively gold backed
  • a channel for laser slotting is set on the surface of the chip.
  • the method of laser plastic sealing material and chip and filling the insulating material isolates and blocks the ground pad and the signal pad, and solves the problem of bridging or signal pads that cannot be connected to the chip encountered in the selective back gold chip mounting.
  • FIG. 1 is a schematic structural diagram of a selective back gold chip.
  • FIG. 2 is a schematic diagram of a selective gold chip package structure according to the present invention.
  • FIG. 3 to FIG. 6 are schematic diagrams of each process flow of a process method for selectively backing a gold chip packaging structure according to the present invention.
  • a selective back-gold chip packaging structure in this embodiment includes a substrate 1, and the substrate 1 is provided with a chip 3 through a silver glue 2.
  • the chip 3 includes signal pads 31 and A ground bonding pad 32 is encapsulated above the chip 3 with a molding compound 7, and the molding compound 7 is provided with a trench 5 in an isolation region corresponding to the signal bonding pad 31 and the ground bonding pad 32.
  • the trench 5 extends downward to the surface of the substrate 1, and the trench 5 is filled with an insulating material 6;
  • the size of the groove 5 in the area of the plastic packaging material 7 is larger than the size of the groove 5 in the area of the chip 3.
  • Step 1 Referring to FIG. 3, perform a scribe operation on the back of the chip in a normal manner to ensure the coverage of the silver glue on the back of the chip;
  • Step 2 Refer to Figure 4, the normal operation of loading film, wire to encapsulation is completed;
  • Step 3 Participate in Figure 5.
  • Laser grooving After encapsulation, grooves are formed on the surface of the plastic packaging material corresponding to the isolation area between the chip ground pads and signal pads by laser. surface;
  • the laser range of the plastic packaging layer is larger than the laser range of the chip layer
  • the chip is not provided with a line in the longitudinal region of the trench;
  • Step 4 Referring to FIG. 6, the trench is filled with an insulating material, which has the effect of blocking the ground pad and the signal pad;
  • Step five curing the insulation material in the trench
  • Step 6 Finish the package after cutting and other processes.
  • the present invention also includes other embodiments. Any technical solution formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the claims of the present invention.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种选择性背金芯片封装结构，所述封装结构包括基板（1），所述基板（1）上通过银胶（2）设置有芯片（3），所述芯片（3）包括信号焊垫（31）和接地焊垫（32），所述芯片（3）上方包封有塑封料（7），所述塑封料（7）上在对应于信号焊垫（31）和接地焊垫（32）之间的隔离区域开设有沟槽（5），所述沟槽（5）向下延伸到基板（1）表面，所述沟槽（5）内填充绝缘材料（6）。上述结构能够解决选择性背金芯片装片遇到的信号焊垫（31）无法与芯片（3）连接的问题。还提供了一种制造选择性背金芯片封装结构的工艺方法。

Description

一种选择性背金芯片封装结构及其工艺方法 技术领域
本发明涉及一种选择性背金芯片封装结构及其工艺方法，属于半导体封装技术领域。
背景技术
现在一些GaAs芯片，为满足电性能的要求，会将芯片设计成选择性背金的设计，如图1所示，其中A和C区域为镀金区域，B区域为隔离区域，左右两边的镀金区域C为信号焊垫，中间大块镀金区域A为接地焊垫，信号焊垫不得与其他任何镀金区域桥接，否则会短路影响性能。
然而，由于芯片越做越小，信号焊垫与接地焊垫间距小，加上基板设计问题，如果使用传统点胶工艺，不仅桥接风险非常大，同时左右两个信号焊垫也有可能未覆盖到银胶，造成无法与芯片连接的问题。
发明内容
本发明所要解决的技术问题是针对上述现有技术提供一种选择性背金芯片封装结构及其工艺方法，它在芯片设计为选择性背金的情况下，在芯片表面设置一镭射开槽的沟道，通过在正常装片包封后镭射通过塑封料层和芯片层并填充绝缘材料的方式，隔离阻断接地焊垫和信号焊垫，解决选择性背金芯片装片遇到的桥接或信号焊垫无法与芯片连接的问题。
本发明解决上述问题所采用的技术方案为：一种选择性背金芯片封装结构，它包括基板，所述基板上通过银胶设置有芯片，所述芯片包括信号焊垫和接地焊垫，所述芯片上方包封有塑封料，所述塑封料上在对应于信号焊垫和接地焊垫之间的隔离区域开设有沟槽，所述沟槽向下延伸到基板表面，所述沟槽内填充绝缘材料。
所述塑封料区域的沟槽尺寸大于芯片区域的沟槽尺寸。
一种选择性背金芯片封装结构的工艺方法，所述方法包括以下步骤：
步骤一、以正常方式在芯片背面进行划胶作业，保证芯片背面银胶的覆盖率；
步骤二、正常作业装片、打线至包封完成；
步骤三、镭射开沟槽，包封后在塑封料表面对应于芯片接地焊垫和信号焊垫间隔离 区域的位置通过镭射形成沟槽，镭射依次通过塑封层和芯片层直至基板表面；
步骤四、在沟槽内填充绝缘材料，起到阻断接地焊垫和信号焊垫的效果；
步骤五、固化沟槽内的绝缘材料；
步骤六、切割等后续制程，完成封装。
优选的，步骤三中塑封料层的镭射沟槽范围大于芯片层的镭射沟槽范围。
与现有技术相比，本发明的优点在于：
本发明一种选择性背金芯片封装结构及其工艺方法，它在芯片设计为选择性背金的情况下，在芯片表面设置一供镭射开槽的沟道，通过在正常装片包封后镭射塑封料和芯片并填充绝缘材料的方式，隔离阻断接地焊垫和信号焊垫，解决选择性背金芯片装片遇到的桥接或信号焊垫无法与芯片连接的问题。
附图说明
图1为选择性背金芯片的结构示意图。
图2为本发明一种选择性背金芯片封装结构的示意图。
图3～图6为本发明一种选择性背金芯片封装结构的工艺方法各工序流程示意图。
其中：
基板1
银胶2
芯片3
信号焊垫31
接地焊垫32
保护膜4
沟槽5
绝缘材料6
塑封料7。
具体实施方式
以下结合附图实施例对本发明作进一步详细描述。
如图2所示，本实施例中的一种选择性背金芯片封装结构，它包括基板1，所述基板1上通过银胶2设置有芯片3，所述芯片3包括信号焊垫31和接地焊垫32，所述芯片3上方包封有塑封料7，所述塑封料7上在对应于信号焊垫31和接地焊垫32之间的隔离区域开设有沟槽5，所述沟槽5向下延伸到基板1表面，所述沟槽5内填充绝缘材料6；
所述塑封料7区域的沟槽5尺寸大于芯片3区域的沟槽5尺寸。
其工艺方法如下：
步骤一、参见图3，以正常方式在芯片背面进行划胶作业，保证芯片背面银胶的覆盖率；
步骤二、参见图4，正常作业装片、打线至包封完成；
步骤三、参加图5，镭射开沟槽，包封后在塑封料表面对应于芯片接地焊垫和信号焊垫间隔离区域的位置通过镭射形成沟槽，镭射依次通过塑封层和芯片层直至基板表面；
塑封料层的镭射范围大于芯片层的镭射范围；
芯片在开沟槽的纵向区域内不设置线路；
步骤四、参见图6，在沟槽内填充绝缘材料，起到阻断接地焊垫和信号焊垫的效果；
步骤五、固化沟槽内的绝缘材料；
步骤六、切割等后制程，完成封装。
除上述实施例外，本发明还包括有其他实施方式，凡采用等同变换或者等效替换方式形成的技术方案，均应落入本发明权利要求的保护范围之内。

Claims (4)

  1. 一种选择性背金芯片封装结构，其特征在于：它包括基板(1)，所述基板(1)上通过银胶(2)设置有芯片(3)，所述芯片(3)包括信号焊垫(31)和接地焊垫(32)，所述芯片(3)上方包封有塑封料(7)，所述塑封料(7)上在对应于信号焊垫(31)和接地焊垫(32)之间的隔离区域开设有沟槽(5)，所述沟槽(5)向下延伸到基板(1)表面，所述沟槽(5)内填充绝缘材料(6)。
  2. 根据权利要求1所述的一种选择性背金芯片封装结构，其特征在于：所述塑封料(7)区域的沟槽(5)尺寸大于芯片(3)区域的沟槽(5)尺寸。
  3. 一种选择性背金芯片封装结构的工艺方法，其特征在于所述方法包括以下步骤：
    步骤一、以正常方式在芯片背面进行划胶作业，保证芯片背面银胶的覆盖率；
    步骤二、正常作业装片、打线至包封完成；
    步骤三、镭射开沟槽，包封后在塑封料表面对应于芯片接地焊垫和信号焊垫间隔离区域的位置通过镭射形成沟槽，镭射依次通过塑封层和芯片层直至基板表面；
    步骤四、在沟槽内填充绝缘材料，起到阻断接地焊垫和信号焊垫的效果；
    步骤五、固化沟槽内的绝缘材料；
    步骤六、切割等后续制程，完成封装。
  4. 根据权利要求3所述的一种选择性背金芯片封装结构的工艺方法，其特征在于：步骤三中塑封料层的镭射范围大于芯片层的镭射范围。
PCT/CN2018/124572 2018-08-02 2018-12-28 一种选择性背金芯片封装结构及其工艺方法 WO2020024547A1 (zh)

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