WO2020019633A1 - 一种加入随机扰动的多相时钟生成电路 - Google Patents

一种加入随机扰动的多相时钟生成电路 Download PDF

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WO2020019633A1
WO2020019633A1 PCT/CN2018/120792 CN2018120792W WO2020019633A1 WO 2020019633 A1 WO2020019633 A1 WO 2020019633A1 CN 2018120792 W CN2018120792 W CN 2018120792W WO 2020019633 A1 WO2020019633 A1 WO 2020019633A1
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matrix
switch
unit
column
row
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English (en)
French (fr)
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蒲杰
胡刚毅
付东兵
张正平
李梁
李婷
徐代果
徐鸣远
沈晓峰
万贤杰
王友华
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中国电子科技集团公司第二十四研究所
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Priority to US17/257,315 priority Critical patent/US11323129B2/en
Publication of WO2020019633A1 publication Critical patent/WO2020019633A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing

Definitions

  • the invention belongs to the field of integrated circuits, and relates to clock generation circuits, and more particularly, to a multi-phase clock generation circuit incorporating random disturbances.
  • TI ADC time-interleaved structure data converter
  • the phase accuracy of a polyphase clock directly affects system performance, and a polyphase clock generation circuit is often affected by factors such as process deviation and circuit mismatch. It is inevitable that there is a phase error.
  • the clock phase error will cause the dynamic performance SFDR to drop significantly.
  • f s is the TI ADC sampling frequency
  • f in is the input signal frequency
  • L is the number of TI ADC integrated channels.
  • K 1,2, ..., L-1) error stray components appear, which needs to be corrected.
  • the conventional method of eliminating the clock phase error is usually a method of foreground adjustment or background real-time correction.
  • the method of foreground adjustment is simple to implement and has high stability. It is difficult to adjust the clock phase directly after estimating the error, but it is difficult Avoid clock phase error performance degradation caused by fluctuations in the working environment; the background real-time correction method requires real-time operation, estimate the amount of error and then correct, the circuit design has high complexity and limited reliability.
  • an object of the present invention is to provide a polyphase clock generation circuit with random disturbances, which is used to solve the current existing TI ADC ADC clock phase error elimination technology, which has high design and implementation complexity, The problems of limited reliability or inability to track and eliminate the amount of clock phase error in real time with changes in the working environment.
  • the present invention provides a polyphase clock generation circuit with random disturbances, which includes a main clock module, a random signal generation module, and a buffer matrix switch module;
  • the master clock module is configured to generate N polyphase clock signals
  • the buffer matrix switch module is used for
  • the input transmission paths of the N polyphase clock signals are randomly switched, and N polyphase clock signals with random disturbance are output.
  • the clock generation circuit further includes a delay line module for pre-adjusting the phases of the N polyphase clock signals generated by the main clock module; a buffer matrix switch module is used for the random signal generation module Under the control of the output random control signal, the transmission paths of the N polyphase clock signals after pre-adjustment of the delay line module are randomly switched, and N polyphase clock signals with random disturbance are output.
  • a delay line module for pre-adjusting the phases of the N polyphase clock signals generated by the main clock module
  • a buffer matrix switch module is used for the random signal generation module Under the control of the output random control signal, the transmission paths of the N polyphase clock signals after pre-adjustment of the delay line module are randomly switched, and N polyphase clock signals with random disturbance are output.
  • the buffer matrix switch module includes an input switch matrix, an output switch matrix, and N + ⁇ N buffer circuits of the same structure; wherein,
  • the input switch matrix includes N columns of switch matrix units I, and each column of switch matrix units I includes N + ⁇ N switch units I having an input terminal and an output terminal;
  • the output switch matrix includes N columns of switch matrix units II, and each column of switch matrix units II includes N + ⁇ N switch units II having an input terminal and an output terminal;
  • each switch unit I is connected to form the input terminal of the switch matrix unit I, and the k-th polyphase clock signal is connected to the input terminal of the k-th switch matrix unit I of the input switch matrix.
  • the output end of the switch unit I in the m-th row of the switch matrix unit I is connected to the input end of the m-th buffer circuit, where k is an integer of [1, N], m is an integer of [1, N + ⁇ N], and ⁇ N is An integer greater than zero;
  • the output terminals of the m-th buffer circuit are respectively connected to the input terminals of the m-th row switching unit II in each column of the switching moment unit II, and the output terminals of each switching unit II are connected to form the output of the switching matrix unit II. end.
  • the random signal generating module generates a (N + ⁇ N) ⁇ N control signal matrix, and the control signal belonging to the mth row and the kth column in the control signal matrix controls the input matrix unit I of the kth column in the switch matrix.
  • control signals belonging to the m-th row and the k-th column in the control signal matrix control the on-off of the m-th row switch unit II in the k-th column matrix unit II in the output switch matrix.
  • control signals in the control signal matrix are represented by '1' and '0', '1' represents a switch-on control, and '0' represents a switch-off control; the control signals in the control signal matrix satisfy the following conditions: The sum of the column vector of each column in the control signal matrix is 1, where the sum of the row vector of N rows is equal to 1, and the sum of the row vector of ⁇ N rows is equal to 0.
  • the buffer matrix switch module includes an input switch matrix, an output switch matrix, and N + ⁇ N buffer circuits of the same structure; wherein,
  • the input switch matrix includes N + ⁇ N columns of switch matrix units I, and each column of switch matrix units I includes N + ⁇ N switch units I having an input end and an output end;
  • the output switch matrix includes N columns of switch matrix units II, and each column of switch matrix units II includes N + ⁇ N switch units II having an input terminal and an output terminal;
  • each switch unit I is connected to form the input terminal of the switch matrix unit I, and the k-th polyphase clock signal is connected to the input terminal of the k-th switch matrix unit I of the input switch matrix.
  • the output end of the switch unit I in the m-th row of the switch matrix unit I is connected to the input end of the m-th buffer circuit, where k is an integer of [1, N], m is an integer of [1, N + ⁇ N], and ⁇ N is An integer greater than zero;
  • the input terminal of each of the N + 1th to N + ⁇ Nth switching matrix units I is connected to a 0 level, and the N + 1th to N + ⁇ Nth switching matrix units I
  • the output terminal of the switch unit I in the m-th row is connected to the input terminal of the m-th buffer circuit;
  • the output terminals of the m-th buffer circuit are respectively connected to the input terminals of the m-th row switching unit II in each column of the switching moment unit II, and the output terminals of each switching unit II are connected to form the output of the switching matrix unit II. end.
  • the random signal generating module generates a (N + ⁇ N) ⁇ (N + ⁇ N) control signal matrix, and the control signal belonging to the mth row and the kth column in the control signal matrix controls the kth column in the input switch matrix.
  • the on / off of the m-th row of the switch matrix unit I in the switch matrix unit I; the control signal belonging to the m-th row and the k 'column of the control signal matrix controls the m-th row of the switch matrix unit I in the k'-th column of the input switch matrix
  • k ' is an integer of [N + 1, N + ⁇ N];
  • control signals belonging to the m-th row and the k-th column in the control signal matrix control the on-off of the m-th row switch unit II in the k-th column matrix unit II in the output switch matrix.
  • control signals in the control signal matrix are represented by '1' and '0', '1' represents a switch-on control, and '0' represents a switch-off control; the control signals in the control signal matrix satisfy the following conditions: The column vector sum result of each column of the control signal matrix is 1, and the row vector sum result of each row is 1.
  • a polyphase clock generating circuit with random disturbance of the present invention has the following beneficial effects:
  • the present invention whitens the clock phase error by pre-trimming and adding random perturbations, and only loses a small amount of signal-to-noise ratio, can in real time eliminate the impact of multi-phase clock phase errors on the performance of high-precision TI ADCs, and can track and eliminate clock phase errors.
  • the error stray component at a fixed frequency is whitened into the noise floor, without interrupting the normal operation of the TI ADC, the design is simple to implement, and the stability is high.
  • FIG. 1 is a schematic circuit diagram of an embodiment of a multi-phase clock generating circuit with random disturbance added according to the present invention
  • FIG. 2 is a schematic diagram of an implementation structure of a buffer matrix switch module according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of an implementation structure of a control signal matrix according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of another implementation structure of a buffer matrix switch module according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of another implementation structure of a control signal matrix according to an embodiment of the present invention.
  • the multi-phase clock generating circuit with random disturbance includes a main clock module 110, a delay line module 120, and a random signal.
  • the transmission paths of the phase clocks are randomly switched, and N polyphase clocks with random disturbances are output, so that the fixed clock phase error between the polyphase clock signals is converted into approximately irregular clock jitter.
  • the present invention breaks the inherent mode of the polyphase clock output state by adding a random perturbation, and whitens the phase error of the polyphase clock into a clock jitter, so that the phase error affects the stray error component at a specific frequency caused by the TI ADC After being eliminated, only a small amount of signal-to-noise ratio is lost, and the purpose of improving dynamic performance SFDR can be achieved.
  • the multi-phase clock generating circuit further includes a delay line module 120, and the delay line module 120 can pre-adjust the generated multi-phase clock phase.
  • pre-trimming refers to measuring the phase error amount between multi-phase clocks under a certain working environment condition through mature front-end trimming technology, and then controlling the delay line module 120 to implement trimming to minimize as much as possible.
  • the phase error between the phase clocks is conducive to whitening the residual phase error after the clock transmission path is randomly switched, and it is also beneficial to reduce the effect of the clock phase error whitening operation on the noise floor.
  • the buffer matrix switch module 130 includes an input switch matrix 131 and an output switch matrix 132, and N + ⁇ N buffer circuits 133 having the same structure.
  • the input switch matrix 131 and the output switch matrix 132 have the same structure and include (N + ⁇ N) ⁇ N switches.
  • the input switch matrix includes N columns of switch matrix units I, and each column of switch matrix units I includes N + ⁇ N switch units I having one input end and one output end; the output switch matrix includes N columns of switch matrix units II, each column
  • the switch matrix unit II includes N + ⁇ N switch units II having an input terminal and an output terminal; the input terminal of each switch unit I is connected to form the input terminal of the switch matrix unit I, and also serves as the input of the entire buffer matrix switch module 130.
  • the k-th polyphase clock signal is connected to the input of the k-th switch matrix unit I of the input switch matrix, and the output of the m-th switch unit I of each switch matrix unit I is connected to the input of the m-th buffer circuit.
  • k is an integer of [1, N]
  • m is an integer of [1, N + ⁇ N]
  • ⁇ N is an integer greater than zero
  • the output of the m-th buffer circuit is respectively the m-th of the switching moment cell II in each column
  • the input terminals of the row switch unit II are connected, and the output terminal of each switch unit II is connected to form the output terminal of the switch matrix unit II, and also serves as the output terminal CLK_out ⁇ k> of the entire buffer matrix switch module 130.
  • the control signals of the input switch matrix and the output switch matrix are provided by a random signal generation module.
  • the random signal generating module 140 generates a control signal matrix of (N + ⁇ N) ⁇ N, where the element values (ie, control signals) in the control signal matrix are represented by '1' and '0', ' 1 'stands for switch-on control, and' 0 'stands for switch-off control.
  • the control signals belonging to the mth row and the kth column in the control signal matrix control the on / off of the mth row of the switch matrix unit I in the kth column of the switch matrix unit in the input switch matrix; and the mth row of the control signal matrix
  • the control signal in the k-th column controls the on-off of the m-th row switching unit II in the k-th column matrix unit II in the output switch matrix.
  • the element values in the control signal matrix satisfy the following conditions: the column vector of each column of the control signal matrix is summed to 1, and among the rows of the control signal matrix (N + ⁇ N), the row vectors of N rows are summed The result is 1, and the sum of the row vectors with ⁇ N rows is 0; a schematic diagram of a control signal matrix structure in this embodiment is shown in FIG. 3.
  • the random signal generating module also generates a random level SV [1: 1 + ⁇ N] of 1 + ⁇ N, where the value of SV [1] is '0' or '1', and SV [2: 1+ Only one of the ⁇ N bits of ⁇ N] is 1 and the remaining bits are 0; the random level SV is used to control the change of element values in the control signal matrix.
  • the element values in the control signal matrix are switched in the following manner.
  • the input terminals of the buffer switch matrix module with ⁇ N buffer units will be in a floating state, and switch between the floating state and the determined state, which may cause a decrease in reliability to a certain extent.
  • the buffer switch matrix module 130 of this embodiment may also adopt another implementation manner.
  • the input switch matrix 131 includes (N + ⁇ N) ⁇ (N + ⁇ N) switches
  • the output switch matrix 132 includes (N + ⁇ N) ⁇ N switches.
  • the input terminal of the ⁇ N column switch added to the input switch matrix 131 is connected to the 0 level. That is, the input switch matrix includes N + ⁇ N columns of switch matrix units I, and each column of switch matrix units I includes N + ⁇ N switch units I having an input terminal and an output terminal;
  • the output switch matrix includes N columns of switch matrix units II, and each column of switch matrix units II includes N + ⁇ N switch units II having an input terminal and an output terminal;
  • each switch unit I is connected to form the input terminal of the switch matrix unit I, and the k-th polyphase clock signal is connected to the input terminal of the k-th switch matrix unit I of the input switch matrix.
  • the output end of the switch unit I in the m-th row of the switch matrix unit I is connected to the input end of the m-th buffer circuit, where k is an integer of [1, N], m is an integer of [1, N + ⁇ N], and ⁇ N is An integer greater than zero;
  • An input terminal of each of the switch matrix units I in the N + 1th to N + ⁇ N columns of the switch matrix unit I is connected to a 0 level, and the N + 1th to N + ⁇ Nth of the switch matrix units I
  • the output terminal of the switch unit I in the m-th row is connected to the input terminal of the m-th buffer circuit;
  • the output terminals of the m-th buffer circuit are respectively connected to the input terminals of the m-th row switching unit II in each column of the switching moment unit II, and the output terminals of each switching unit II are connected to form the output of the switching matrix unit II. end.
  • the element values in the control signal matrix satisfy the following conditions: the column vector sum result of each column of the control signal matrix is 1, and the row vector sum result of each row is 1.
  • a schematic diagram of a control signal matrix structure in another implementation manner of this embodiment is shown in FIG. 5.
  • the random signal generation module 140 generates a control signal matrix of (N + ⁇ N) ⁇ (N + ⁇ N), and the set and functions of the elements in the control signal matrix are the same as described above.
  • the control signals belonging to the m-th row and the k-th column in the control signal matrix control the on-off of the m-th row switch unit I in the k-th column switch matrix unit I in the input switch matrix, where k is [1, N ];
  • the control signal belonging to the mth row and k 'column in the control signal matrix controls the on / off of the mth row switch unit I in the k'th column switch matrix unit I in the input switch matrix, where k' is [N + 1, N + ⁇ N] Integer;
  • control signals belonging to the mth row and kth column in the control signal matrix control the on / off of the mth row switch unit II in the kth column matrix unit II in the output switch matrix .
  • the element values in the control signal matrix are switched and changed in the following manner.
  • the method is the same as that described in the previous implementation.
  • each buffer circuit in the buffer matrix switch module is connected to the 0 level when no clock signal is connected; when the clock signal source connected changes, it is also always 0. Level, without introducing uncertainty.
  • the present invention Compared with the traditional background correction method, the present invention has no complicated arithmetic unit, the circuit implementation is simpler, the effect is more stable, and the implementation complexity is low.
  • the invention adds random disturbance to the clock, which can track and eliminate the influence of the clock phase error with the fluctuation of the working environment.
  • the invention can reduce the clock phase error through pre-trimming, and disturb the inherent clock phase error by randomly switching the clock path.
  • the residual clock phase error and its stray components due to fluctuations in the working environment are whitened into the noise floor, so as to achieve the purpose of correcting the clock phase error in real time and improving the dynamic performance of the TI ADC.

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Abstract

本发明公开了一种加入随机扰动的多相时钟生成电路，该时钟生成电路包括主时钟模块、随机信号生成模块和buffer矩阵开关模块；所述主时钟模块用于生成N条多相时钟信号；所述buffer矩阵开关模块用于在所述随机信号生成模块输出的随机控制信号控制下，对输入的所述N条多相时钟信号的传输路径进行随机切换，输出N条加入随机扰动的多相时钟信号。本发明通过加入随机扰动的方式，将时钟相位误差白化，仅仅损失少量信噪比，就能够实时消除多相时钟相位误差对高精度TI ADC性能的影响，且能够跟踪消除时钟相位误差随工作环境变化波动的影响，将固定频率处的误差杂散分量白化到噪底中，不打断TI ADC正常工作，设计实现简单，稳定度高。

Description

一种加入随机扰动的多相时钟生成电路 技术领域
本发明属于集成电路领域，涉及时钟生成电路，更具体地，特别涉及一种加入随机扰动的多相时钟生成电路。
背景技术
在时间交织结构数据转换器(TI ADC)中，多相时钟相位精度直接影响系统性能，而多相时钟生成电路往往受工艺偏差、电路失配等因素的影响，不可避免的具有相位误差，对于高精度TI ADC中，时钟相位误差会导致动态性能SFDR大幅下降，在k·f s/L±f in(f s为TI ADC采样频率，f in为输入信号频率,L为TI ADC集成通道数，k＝1,2,…,L-1)处出现误差杂散分量，需要进行校正。目前常规的消除时钟相位误差的方法通常是采用前台修调或者后台实时校正的方法；前台修调的方法，实现简单，稳定性高，估计出误差后直接对时钟相位进行修调，但很难避免时钟相位误差随工作环境变化波动而导致的性能恶化；而后台实时校正的方法需要实时进行运算，估计出误差量然后进行校正，电路设计实现复杂度高，且稳定可靠性受限。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种加入随机扰动的多相时钟生成电路，用于解决目前现有的TI ADC消除时钟相位误差技术中，设计实现复杂度高、稳定可靠性受限或者无法对时钟相位误差量随工作环境变化进行实时跟踪消除的问题。
为实现上述目的及其他相关目的，本发明提供一种加入随机扰动的多相时钟生成电路，该时钟生成电路包括主时钟模块、随机信号生成模块和buffer矩阵开关模块；
所述主时钟模块用于生成N条多相时钟信号；
所述buffer矩阵开关模块用于在所述
随机信号生成模块输出的随机控制信号控制下，对输入的所述N条多相时钟信号的传输路径进行随机切换，输出N条加入随机扰动的多相时钟信号。
优选地，该时钟生成电路还包括延时线模块，用于对主时钟模块生成的所述N条多相时钟信号的相位进行预修调；buffer矩阵开关模块用于在所述随机信号生成模块输出的随机控制信号控制下，对经过延时线模块预修调后的N条多相时钟信号的传输路径进行随机切换，输 出N条加入随机扰动的多相时钟信号。
优选地，所述buffer矩阵开关模块包括输入开关矩阵、输出开关矩阵和N+ΔN个相同结构的buffer电路；其中，
所述输入开关矩阵包括N列开关矩阵单元I，每列开关矩阵单元I包括N+ΔN个具有一输入端和一输出端的开关单元I；
所述输出开关矩阵包括N列开关矩阵单元II，每列开关矩阵单元II包括N+ΔN个具有一输入端和一输出端的开关单元II；
每个所述开关单元I的输入端连接构成开关矩阵单元I的输入端，第k条多相时钟信号与所述输入开关矩阵的第k列开关矩阵单元I的输入端相连，每列所述开关矩阵单元I的第m行开关单元I的输出端与第m个buffer电路的输入端相连，其中k为[1,N]的整数，m为[1,N+ΔN]的整数，ΔN为大于零的整数；
所述第m个buffer电路的输出端分别与每列所述开关矩单元II的第m行开关单元II的输入端相连，每个所述开关单元II的输出端连接构成开关矩阵单元II的输出端。
优选地，所述随机信号生成模块生成(N+ΔN)×N的控制信号矩阵，同时属于控制信号矩阵中的第m行第k列的控制信号控制输入开关矩阵中第k列开关矩阵单元I中的第m行开关单元I的通断；
同时属于控制信号矩阵中的第m行第k列的控制信号控制输出开关矩阵中第k列矩阵单元II中的第m行开关单元II的通断。
优选地，所述控制信号矩阵中的控制信号由‘1’和‘0’表示，‘1’代表开关闭合控制，‘0’代表开关断开控制；控制信号矩阵中的控制信号满足如下条件：控制信号矩阵中的每一列的列向量求和结果均为1，其中,N行的行向量求和结果等于1，有ΔN行的行向量求和结果等于0。
优选地，所述buffer矩阵开关模块包括输入开关矩阵、输出开关矩阵和N+ΔN个相同结构的buffer电路；其中，
所述输入开关矩阵包括N+ΔN列开关矩阵单元I，每列开关矩阵单元I包括N+ΔN个具有一输入端和一输出端的开关单元I；
所述输出开关矩阵包括N列开关矩阵单元II，每列开关矩阵单元II包括N+ΔN个具有一输入端和一输出端的开关单元II；
每个所述开关单元I的输入端连接构成开关矩阵单元I的输入端，第k条多相时钟信号与所述输入开关矩阵的第k列开关矩阵单元I的输入端相连，每列所述开关矩阵单元I的第m行 开关单元I的输出端与第m个buffer电路的输入端相连，其中k为[1,N]的整数，m为[1,N+ΔN]的整数，ΔN为大于零的整数；
第N+1到第N+ΔN个所述开关矩阵单元I中的每个所述开关单元I的输入端接0电平，第N+1到第N+ΔN个所述开关矩阵单元I的第m行开关单元I的输出端与第m个buffer电路的输入端相连；
所述第m个buffer电路的输出端分别与每列所述开关矩单元II的第m行开关单元II的输入端相连，每个所述开关单元II的输出端连接构成开关矩阵单元II的输出端。
优选地，所述随机信号生成模块生成(N+ΔN)×(N+ΔN)的控制信号矩阵，同时属于控制信号矩阵中的第m行第k列的控制信号控制输入开关矩阵中第k列开关矩阵单元I中的第m行开关单元I的通断；同时属于控制信号矩阵中的第m行第k'列的控制信号控制输入开关矩阵中第k'列开关矩阵单元I中的第m行开关单元I的通断，其中k'为[N+1,N+ΔN]的整数；
同时属于控制信号矩阵中的第m行第k列的控制信号控制输出开关矩阵中第k列矩阵单元II中的第m行开关单元II的通断。
优选地，所述控制信号矩阵中的控制信号由‘1’和‘0’表示，‘1’代表开关闭合控制，‘0’代表开关断开控制；控制信号矩阵中的控制信号满足如下条件：控制信号矩阵每一列的列向量求和结果均为1，每一行的行向量求和结果均为1。
如上所述，本发明的一种加入随机扰动的多相时钟生成电路，具有以下有益效果：
本发明通过预修调和加入随机扰动的方式，将时钟相位误差白化，仅仅损失少量信噪比，就能够实时消除多相时钟相位误差对高精度TI ADC性能的影响，且能够跟踪消除时钟相位误差随工作环境变化波动的影响，将固定频率处的误差杂散分量白化到噪底中，不打断TI ADC正常工作，设计实现简单，稳定度高。
附图说明
图1为本发明一种加入随机扰动的多相时钟生成电路的一个实施例电路示意图；
图2为本发明实施例中buffer矩阵开关模块的一种实现结构示意图；
图3为本发明实施例中控制信号矩阵的一种实现结构示意图；
图4为本发明实施例中buffer矩阵开关模块的另一种实现结构示意图；
图5为本发明实施例中控制信号矩阵的另一种实现结构示意图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
参见图1，为本发明一种加入随机扰动的多相时钟生成电路的一个实施例电路示意图，该加入随机扰动的多相时钟生成电路，包括主时钟模块110、延时线模块120和随机信号生成模块140；其中，主时钟模块110生成N条多相时钟信号CLK<1:N>；buffer矩阵开关模块130可以在随机信号生成模块140输出的随机控制信号的控制下，实现对N条多相时钟的传输路径进行随机切换，输出N条加入随机扰动的多相时钟，以此将多相时钟信号之间固定的时钟相位误差转变为近似无规律的时钟jitter。
本发明通过加入随机扰动的方式，打破了多相时钟输出状态的固有模式，将多相时钟的相位误差白化为时钟jitter，这样相位误差对TI ADC造成的特定频率处的误差杂散分量的影响被消除，仅仅损失少量信噪比，就可以达到提升动态性能SFDR的目的。
作为对本实施例的改进，该多相时钟生成电路还包括延时线模块120，延时线模块120可以对生成的多相时钟相位进行预修调。具体地，预修调指通过成熟的前台修调技术在某一工作环境条件下，测量出多相时钟之间的相位误差量，然后控制延时线模块120实现修调，以尽量减小多相时钟之间的相位误差，利于在时钟传输路径随机切换操作后将残留的相位误差白化，同时利于减小时钟相位误差白化操作后对噪底的影响。
参见图2，本实施例中buffer矩阵开关模块130包括输入开关矩阵131和输出开关矩阵132，以及N+ΔN个相同结构的buffer电路133。本实施例中输入开关矩阵131和输出开关矩阵132为相同结构，包括(N+ΔN)×N个开关。
具体地，输入开关矩阵包括N列开关矩阵单元I，每列开关矩阵单元I包括N+ΔN个具有一输入端和一输出端的开关单元I；输出开关矩阵包括N列开关矩阵单元II，每列开关矩阵单元II包括N+ΔN个具有一输入端和一输出端的开关单元II；每个开关单元I的输入端连接构成开关矩阵单元I的输入端，同时也作为整个buffer矩阵开关模块130的输入端CLK_in<k>。
第k条多相时钟信号与输入开关矩阵的第k列开关矩阵单元I的输入端相连，每列开关矩阵单元I的第m行开关单元I的输出端与第m个buffer电路的输入端相连，其中k为[1,N]的整数，m为[1,N+ΔN]的整数，ΔN为大于零的整数；第m个buffer电路的输出端分别与每列开关矩单元II的第m行开关单元II的输入端相连，每个开关单元II的输出端连接构成开关矩阵单元II的输出端，同时也作为整个buffer矩阵开关模块130的输出端CLK_out<k>。
输入开关矩阵和输出开关矩阵的控制信号均由随机信号生成模块提供。
于本本实施例中，随机信号生成模块140，产生(N+ΔN)×N的控制信号矩阵，其中，控制信号矩阵中的元素值(即控制信号)由‘1’和‘0’表示，‘1’代表开关闭合控制，‘0’代表开关断开控制。
同时属于控制信号矩阵中的第m行第k列的控制信号控制输入开关矩阵中第k列开关矩阵单元I中的第m行开关单元I的通断；同时属于控制信号矩阵中的第m行第k列的控制信号控制输出开关矩阵中第k列矩阵单元II中的第m行开关单元II的通断。那么由图2可知，第k个多相时钟输入信号的传输路径由控制信号矩阵中第k列的元素值决定。
本实施例中，控制信号矩阵中的元素值满足如下条件：控制信号矩阵每一列的列向量求和结果均为1，控制信号矩阵(N+ΔN)行中，有N行的行向量求和结果为1，有ΔN行的行向量求和结果为0；本实施例中的一种控制信号矩阵结构示意图参见图3所示。
本实施例中，随机信号生成模块还产生1+ΔN bit的随机电平SV[1:1+ΔN]，其中SV[1]的值为‘0’或者‘1’，SV[2:1+ΔN]的ΔN bit中只有1bit为1，其余bit均为0；随机电平SV用于控制所述控制信号矩阵中的元素值的切换变化。
本实施例中，控制信号矩阵中的元素值按下列方式进行切换变化，设置寄存器CLK_reg[k]存储当前控制信号矩阵第k列中元素值等于1的行编号，其中k＝1,2,3,…,N；设置寄存器idle_reg[1:ΔN]存储当前控制信号矩阵中行向量求和结果等于0的ΔN个行编号。在第k条多相时钟输入信号下降沿到来或者处于0电平时，根据随机信号生成模块产生的随机电平SV，决定是否将控制信号矩阵中，寄存器CLK_reg[k]存储的行编号与寄存器idle_reg存储的某一个行编号所对应的行向量值互换，同时将寄存器CLK_reg[k]存储的行编号值与寄存器idle_reg存储的对应的某一个行编号值也互换；例如，在第k条多相时钟输入信号下降沿到来或者处于0电平时，当随机信号电平SV[1]为‘1’时，将控制信号矩阵中CLK_reg[k]存储的行编号对应的行 向量值与idle_reg[x-1]存储的行编号对应的行向量值互换，同时将CLK_reg[k]与idle_reg[x-1]中存储的行编号值也进行互换，其中x为SV[2:1+ΔN]中元素等于1的数列编号，x＝2,3,…1+ΔN；当随机信号SV[1]为‘0’时，则控制信号矩阵中的元素值不做改变；通过上述方式可改变控制信号矩阵中第k列的元素值，达到随机切换第k条多相时钟传输路径的目的。
通过上述方式实现了对时钟传输路径的随机切换，虽然各条时钟传输路径上的电路结构完全一致，但是器件和走线在版图设计上的区别以及工艺实现上的偏差，仍然会导致不同路径的延时有微小差异，且随环境变化也有一定波动，由此在进行时钟路径的随机切换后，时钟相位误差会被白化，从而消除了时钟相位误差对TI ADC动态性能的影响。
上述实现方式，由于在工作过程中，buffer开关矩阵模块有ΔN个buffer单元的输入端会处于悬空状态，且在悬空态和确定态之间切换，这一定程度上可能会造成可靠性下降。
为避免上述问题，本实施例的buffer开关矩阵模块130还可以采用另一种实现方式，参见图4，输入开关矩阵131包括(N+ΔN)×(N+ΔN)个开关，而输出开关矩阵132包括(N+ΔN)×N个开关。其中输入开关矩阵131中增加的ΔN列开关的输入端与0电平相连。即，所述输入开关矩阵包括N+ΔN列开关矩阵单元I，每列开关矩阵单元I包括N+ΔN个具有一输入端和一输出端的开关单元I；
所述输出开关矩阵包括N列开关矩阵单元II，每列开关矩阵单元II包括N+ΔN个具有一输入端和一输出端的开关单元II；
每个所述开关单元I的输入端连接构成开关矩阵单元I的输入端，第k条多相时钟信号与所述输入开关矩阵的第k列开关矩阵单元I的输入端相连，每列所述开关矩阵单元I的第m行开关单元I的输出端与第m个buffer电路的输入端相连，其中k为[1,N]的整数，m为[1,N+ΔN]的整数，ΔN为大于零的整数；
第N+1到第N+ΔN列所述开关矩阵单元I中的每个所述开关单元I的输入端接0电平，第N+1到第N+ΔN个所述开关矩阵单元I的第m行开关单元I的输出端与第m个buffer电路的输入端相连；
所述第m个buffer电路的输出端分别与每列所述开关矩单元II的第m行开关单元II的输入端相连，每个所述开关单元II的输出端连接构成开关矩阵单元II的输出端。
在本实施例的另一种实现方式中，控制信号矩阵中的元素值满足如下条件：控制信号矩阵每一列的列向量求和结果均为1，每一行的行向量求和结果均为1。本实施例的另一种实现方式中的一种控制信号矩阵结构示意图参见图5所示。
在另一种实现方式中，如图5所示，随机信号发生模块140产生(N+ΔN)×(N+ΔN)的控制信号矩阵，控制信号矩阵中元素的集合和功能与前面描述相同。具体地，同时属于控制信号矩阵中的第m行第k列的控制信号控制输入开关矩阵中第k列开关矩阵单元I中的第m行开关单元I的通断，其中k为[1,N]的整数；同时属于控制信号矩阵中的第m行第k'列的控制信号控制输入开关矩阵中第k'列开关矩阵单元I中的第m行开关单元I的通断，其中k'为[N+1,N+ΔN]的整数；同时属于控制信号矩阵中的第m行第k列的控制信号控制输出开关矩阵中第k列矩阵单元II中的第m行开关单元II的通断。
在另一种实现方式中，控制信号矩阵中的元素值按下列方式进行切换变化，设置寄存器CLK_reg[k]存储当前控制信号矩阵第k列中元素值等于1的行编号，其中k＝1,2,3,…,N；设置寄存器idle_reg[1:ΔN]存储当前控制信号矩阵第N+1到N+ΔN列中元素值等于1的ΔN个行编号，控制信号矩阵中的元素值的更新方式与前一种实现方式描述相同。
在另一种实现方式中，buffer矩阵开关模块中的每一个buffer电路，在未接入时钟信号时，均与0电平相连；在接入的时钟信号源发生改变时刻，也恒定为0电平，不会引入不确定态。
由上述实施例可见，相比于传统的后台校正方式，本发明无复杂的运算单元，电路实现更为简单，效果更为稳定，实现复杂度低；相比于传统的前台修调的方式，本发明对时钟加入随机扰动，可以跟踪消除时钟相位误差随工作环境变化波动的影响；本发明可通过预修调减小时钟相位误差，通过对时钟路径的随机切换，扰动固有的时钟相位误差，将残留的时钟相位误差以及其受工作环境变化波动产生的误差杂散分量白化到噪底中，从而达到实时校正时钟相位误差，提升TI ADC动态性能的目的。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (8)

  1. 一种加入随机扰动的多相时钟生成电路，其特征在于，该时钟生成电路包括主时钟模块、随机信号生成模块和buffer矩阵开关模块；
    所述主时钟模块用于生成N条多相时钟信号；
    所述buffer矩阵开关模块用于在所述随机信号生成模块输出的随机控制信号控制下，对输入的所述N条多相时钟信号的传输路径进行随机切换，输出N条加入随机扰动的多相时钟信号。
  2. 根据权利要求1所述的一种加入随机扰动的多相时钟生成电路，其特征在于，该时钟生成电路还包括延时线模块，用于对主时钟模块生成的所述N条多相时钟信号的相位进行预修调；buffer矩阵开关模块用于在所述随机信号生成模块输出的随机控制信号控制下，对经过延时线模块预修调后的N条多相时钟信号的传输路径进行随机切换，输出N条加入随机扰动的多相时钟信号。
  3. 根据权利要求1所述的一种加入随机扰动的多相时钟生成电路，其特征在于，所述buffer矩阵开关模块包括输入开关矩阵、输出开关矩阵和N+ΔN个相同结构的buffer电路；其中，所述输入开关矩阵包括N列开关矩阵单元I，每列开关矩阵单元I包括N+ΔN个具有一输入端和一输出端的开关单元I；
    所述输出开关矩阵包括N列开关矩阵单元II，每列开关矩阵单元II包括N+ΔN个具有一输入端和一输出端的开关单元II；
    每个所述开关单元I的输入端连接构成开关矩阵单元I的输入端，第k条多相时钟信号与所述输入开关矩阵的第k列开关矩阵单元I的输入端相连，每列所述开关矩阵单元I的第m行开关单元I的输出端与第m个buffer电路的输入端相连，其中k为[1,N]的整数，m为[1,N+ΔN]的整数，ΔN为大于零的整数；
    所述第m个buffer电路的输出端分别与每列所述开关矩单元II的第m行开关单元II的输入端相连，每个所述开关单元II的输出端连接构成开关矩阵单元II的输出端。
  4. 根据权利要求3所述的一种加入随机扰动的多相时钟生成电路，其特征在于，所述随机信号生成模块生成(N+ΔN)×N的控制信号矩阵，同时属于控制信号矩阵中的第m行第k列的控制信号控制输入开关矩阵中第k列开关矩阵单元I中的第m行开关单元I的通断；
    同时属于控制信号矩阵中的第m行第k列的控制信号控制输出开关矩阵中第k列矩阵单元II中的第m行开关单元II的通断。
  5. 根据权利要求4所述的一种加入随机扰动的多相时钟生成电路，其特征在于，所述控制信号矩阵中的控制信号由‘1’和‘0’表示，‘1’代表开关闭合控制，‘0’代表开关断开控制；控制信号矩阵中的控制信号满足如下条件：控制信号矩阵中的每一列的列向量求和结果均为1，其中,N 行的行向量求和结果等于1，ΔN行的行向量求和结果等于0。
  6. 根据权利要求1所述的一种加入随机扰动的多相时钟生成电路，其特征在于，所述buffer矩阵开关模块包括输入开关矩阵、输出开关矩阵和N+ΔN个相同结构的buffer电路；其中，所述输入开关矩阵包括N+ΔN列开关矩阵单元I，每列开关矩阵单元I包括N+ΔN个具有一输入端和一输出端的开关单元I；
    所述输出开关矩阵包括N列开关矩阵单元II，每列开关矩阵单元II包括N+ΔN个具有一输入端和一输出端的开关单元II；
    每个所述开关单元I的输入端连接构成开关矩阵单元I的输入端，第k条多相时钟信号与所述输入开关矩阵的第k列开关矩阵单元I的输入端相连，每列所述开关矩阵单元I的第m行开关单元I的输出端与第m个buffer电路的输入端相连，其中k为[1,N]的整数，m为[1,N+ΔN]的整数，ΔN为大于零的整数；
    第N+1到第N+ΔN列所述开关矩阵单元I中的每个所述开关单元I的输入端接0电平，第N+1到第N+ΔN列所述开关矩阵单元I的第m行开关单元I的输出端与第m个buffer电路的输入端相连；
    所述第m个buffer电路的输出端分别与每列所述开关矩单元II的第m行开关单元II的输入端相连，每个所述开关单元II的输出端连接构成开关矩阵单元II的输出端。
  7. 根据权利要求6所述的一种加入随机扰动的多相时钟生成电路，其特征在于，所述随机信号生成模块生成(N+ΔN)×(N+ΔN)的控制信号矩阵，同时属于控制信号矩阵中的第m行第k列的控制信号控制输入开关矩阵中第k列开关矩阵单元I中的第m行开关单元I的通断；同时属于控制信号矩阵中的第m行第k'列的控制信号控制输入开关矩阵中第k'列开关矩阵单元I中的第m行开关单元I的通断，其中k'为[N+1,N+ΔN]的整数；
    同时属于控制信号矩阵中的第m行第k列的控制信号控制输出开关矩阵中第k列矩阵单元II中的第m行开关单元II的通断。
  8. 根据权利要求6所述的一种加入随机扰动的多相时钟生成电路，其特征在于，所述控制信号矩阵中的控制信号由‘1’和‘0’表示，‘1’代表开关闭合控制，‘0’代表开关断开控制；控制信号矩阵中的控制信号满足如下条件：控制信号矩阵每一列的列向量求和结果均为1，每一行的行向量求和结果均为1。
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