WO2020015095A1 - 移位暂存器、显示面板、以及移位暂存器的驱动方法 - Google Patents

移位暂存器、显示面板、以及移位暂存器的驱动方法 Download PDF

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Publication number
WO2020015095A1
WO2020015095A1 PCT/CN2018/105075 CN2018105075W WO2020015095A1 WO 2020015095 A1 WO2020015095 A1 WO 2020015095A1 CN 2018105075 W CN2018105075 W CN 2018105075W WO 2020015095 A1 WO2020015095 A1 WO 2020015095A1
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Prior art keywords
switch
signal
shift register
electrically coupled
point voltage
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English (en)
French (fr)
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单剑锋
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HKC Co Ltd
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HKC Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to a display panel, and in particular, to a shift register in the display panel and a driving method for eliminating ripples in a high-frequency signal combination circuit in the shift register.
  • the display panel industry such as liquid crystal display panels
  • the array substrate type drive technology (Gate, Driver, Array, GOA).
  • the traditional LCD display panel technology relies on the source driver IC (gate IC) and the gate driver IC (gate IC) to drive.
  • the former controls the voltage to transmit the signal, and the latter uses the transistor as a switch to control and determine the amount of light transmission. .
  • the array substrate type driving technology is to abandon the traditional gate driving chip and replace the gate driving circuit structure directly on the glass substrate of the liquid crystal display panel. Because the gate driving circuit structure uses the exposure and development method, the glass substrate Related logic circuits of multiple shift registers are generated at the edges, so whether it is in materials or manufacturing processes, it can achieve the purpose of reducing costs, and can also achieve the effect of reducing the LCD display frame.
  • the principle of the array substrate type driving technology is developed based on the Tompson circuit. In order to achieve a smooth driving effect, it is usually precharged at the Quiescent point to achieve a higher voltage level. This enables subsequent coupling with the clock signal into an ideal signal waveform, whereby when the transistor switch is turned on, the gate scanning signal required by the gate line can be smoothly transmitted.
  • the clock signal is a periodic signal.
  • the ripple signal is generated due to the operating point voltage signal coupled to the operating point, and the gate line is extremely short-lived. Malfunction.
  • the present disclosure provides a shift register, a display panel, and a method for driving the shift register, which can effectively remove the ripple signal generated by the clock signal, thereby preventing the gate circuit from malfunctioning.
  • An embodiment of the present disclosure proposes a shift register, which is a gate driving circuit structure for a display panel of an array substrate type driving technology (Gate Driver On Array; GOA).
  • the display panel is, for example, A liquid crystal display panel having a plurality of cascaded shift registers such as n, where n is a positive integer greater than 2, and the nth shift register receives the nth shift register of the previous stage.
  • the -1 level gate signal is used to transmit the gate scanning signal Gn of this stage to the gate line, wherein the shift register has the operating point voltage signal Qn of this stage.
  • the shift register includes a pull-down maintaining module and a control module.
  • the control module is electrically coupled to the pull-down maintenance module, and is configured to generate correct timing to control the pull-down maintenance module.
  • the pull-down maintenance module is electrically coupled to a low preset potential for eliminating noise of a working point voltage in the shift register.
  • the pull-down maintenance module further includes a high-frequency signal combination circuit.
  • the high-frequency signal combination circuit includes a first switch, a second switch, and a third switch.
  • the control terminal of the first switch is electrically coupled to one of the clock signal CKn-1 of the previous stage and the clock signal CKn of this stage, and the first terminal of the first switch is electrically coupled to the clock signal. CKn-1 and the other signal of the clock signal CKn.
  • the control terminal of the second switch is electrically coupled to the operating point voltage signal Qn, and the first terminal of the second switch is electrically coupled to the second terminal of the first switch.
  • the control terminal of the third switch is electrically coupled to the second terminal of the second switch, and the first terminal of the third switch is electrically coupled to the operating point voltage signal Qn.
  • the two terminals are electrically coupled to a low preset potential Vss.
  • the control terminal of the first switch may be electrically coupled to the clock signal CKn, and the first terminal of the first switch may be electrically coupled to the clock signal CKn-1. Therefore, a high-frequency signal combination circuit is added in the shift register, thereby effectively removing the ripple signal generated by the clock signal CKn, and preventing the gate circuit from malfunctioning.
  • the first switch may be a first transistor
  • the second switch may be a second transistor
  • the third switch may be a third transistor
  • the shift register may further include an input module, an output module, and a feedback module.
  • the input module is configured to receive a gate signal of the n-1th stage and generate a working point voltage of the shift register according to the gate signal of the n-1th stage.
  • the output module is configured to receive a clock signal CKn and precharge the operating point voltage of the shift temporary storage circuit into a precharge bit, and couple the precharge bit into the operating point voltage signal according to the clock signal CKn. Qn, and output a gate scan signal Gn according to the coupled operating point voltage signal Qn and the clock signal CKn.
  • the feedback module is configured to receive a feedback signal and pull the potential of the gate scan signal Gn to a low preset potential according to the feedback signal.
  • the present disclosure provides a display panel and a high-frequency signal combining circuit used in the display panel.
  • the high-frequency signal combining circuit is used for a liquid crystal display panel of an array substrate type driving technology.
  • the liquid crystal display panel has n
  • the cascaded shift register, n is a positive integer greater than 2, the nth shift register receives the gate signal of the n-1th stage to transmit the gate scanning signal Gn through the gate line,
  • the shift register has an operating point voltage signal Qn.
  • the pull-down maintenance module in the shift register has the high-frequency signal combination circuit, and the pull-down maintenance module is used to eliminate noise of the operating point voltage of the shift register.
  • the high-frequency signal combination circuit includes a first switch, a second switch, and a third switch.
  • the control terminal of the first switch is electrically coupled to one of the clock signal CKn-1 and the clock signal CKn, and the first terminal of the first switch is electrically coupled to the clock signal CKn-1 and the clock signal CKn. Another signal.
  • the control terminal of the second switch is electrically coupled to the operating point voltage signal Qn, and the first terminal of the second switch is electrically coupled to the second terminal of the first switch.
  • the control terminal of the third switch is electrically coupled to the second terminal of the second switch, and the first terminal of the third switch is electrically coupled to the operating point voltage signal Qn.
  • the two terminals are electrically coupled to a low preset potential Vss.
  • control terminal of the first switch may be an electrically coupled clock signal CKn
  • first terminal of the first switch may be an electrically coupled clock signal CKn-1. Therefore, a high-frequency signal combination circuit is added in the shift register, thereby effectively removing the ripple signal generated by the clock signal CKn, and preventing the gate circuit from malfunctioning.
  • the first switch is a first transistor
  • the second switch is a second transistor
  • the third switch is a third transistor
  • the shift register may further include a control module, an input module, an output module, and a feedback module.
  • the control module is electrically coupled to the pull-down maintenance module, and is configured to generate correct timing to control the pull-down maintenance module.
  • the input module is configured to receive a gate signal of the n-1th stage and generate a working point voltage of the shift register according to the gate signal of the n-1th stage.
  • the output module is configured to receive a clock signal CKn and precharge the operating point voltage of the shift temporary storage circuit into a precharge bit, and couple the precharge bit into the operating point voltage signal according to the clock signal CKn. Qn, and output a gate scan signal Gn according to the coupled operating point voltage signal Qn and the clock signal CKn.
  • the feedback module is configured to receive a feedback signal and pull the potential of the gate scan signal Gn to a low preset potential according to the feedback signal.
  • the driving method is for a liquid crystal display panel of an array substrate type driving technology, and the liquid crystal display panel has n cascaded shift registers. , N is a positive integer greater than 2.
  • the driving method includes the following steps: the n-th shift register receives a gate signal of the n-1th stage to transmit a gate-scan signal Gn through a gate line, and the shift register has a function of Point voltage signal Qn.
  • the pull-down maintenance module in the shift register has the high-frequency signal combination circuit, and the high-frequency signal combination circuit includes a first switch, a second switch, and a third switch; and transmits a clock signal CKn-1 to all The first terminal of the first switch; transmitting a clock signal CKn to the control terminal of the first switch, wherein the first terminal of the second switch is electrically coupled to the second terminal of the first switch; transmitting the An operating point voltage signal Qn is provided to the control terminal of the second switch, wherein the control terminal of the third switch is electrically coupled to the second terminal of the second switch; and the operating point voltage signal Qn is transmitted to the second switch.
  • the first terminal of the third switch and the second terminal of the third switch are electrically coupled to a low preset potential Vss, where the low preset potential Vss will pull down the operating point voltage signal Qn.
  • the driving method further includes the steps of: receiving a gate signal of the n-1th stage, and generating an operating point voltage of the shift register according to the gate signal of the n-1th stage; The operating point voltage of the shift register is maintained at a low preset potential; used to receive a clock signal CKn and precharge the operating point voltage of the shift register into a precharge bit, and according to the clock signal CKn Coupling the precharge bit into the operating point voltage signal Qn; outputting the gate scan signal Gn according to the coupled operating point voltage signal Qn and the clock signal CKn; and receiving a feedback signal, and according to the feedback The signal pulls the potential of the gate scan signal Gn to a low preset potential.
  • a shift register, a display panel, and a method for driving the shift register utilize a high-frequency signal combination circuit in the shift register to effectively remove the shift register.
  • the ripple signal generated by the clock signal CKn can prevent malfunction of the gate line.
  • FIG. 1 is a schematic diagram of a liquid crystal display panel where a shift register of the present disclosure is located.
  • FIG. 2A is a functional correlation diagram of a shift register of the present disclosure.
  • FIG. 2B is a schematic diagram of an embodiment of a shift register according to the present disclosure.
  • FIG. 3 is a schematic circuit diagram of a high-frequency signal combining circuit of the present disclosure.
  • FIG. 4 is a waveform diagram of levels of various signals of the present disclosure.
  • FIG. 5 is a flowchart of a driving method performed by the high-frequency signal combining circuit of the present disclosure.
  • FIG. 6 is a flowchart of a driving method performed by a shift register of the present disclosure.
  • FIG. 1 is a schematic diagram of a liquid crystal display panel 10 in which the shift register 30 of the present disclosure is located.
  • An embodiment of the present disclosure proposes a shift register 30 for a display panel of an array substrate type driver technology (GOA).
  • the display panel is, for example, a liquid crystal display panel 10, and is subsequently displayed in liquid crystal.
  • the panel 10 is described as an example.
  • the liquid crystal display panel 10 has multiple cascaded shift registers 30, where n is a positive integer greater than 2, and the n-th shift register 30 receives the n-th
  • the gate signal of level 1 transmits the gate scanning signal Gn of this level to the gate line 32, wherein the operating point of the shift register 30 has the operating point voltage signal Qn of this level.
  • the liquid crystal display panel 10 still has a source driving chip 12, and the array substrate type driving technology abandons the gate driving chip. Instead, as shown in the figure, a plurality of shift registers 30 are directly disposed on a glass substrate as a driver. Circuit of the gate line 32. Each shift register 30 receives the gate signal of the previous stage to transmit the gate scan signal through the gate line 32.
  • FIG. 2A is a functional correlation diagram of the shift register 30 of the present disclosure.
  • FIG. 2B is a schematic diagram of an embodiment of a shift register 30 according to the present disclosure.
  • the n-th shift register 30 is described in this embodiment.
  • the n-th shift register 30 includes a pull-down maintaining module 58, a control module 56, an input module 50, an output module 52, and a feedback module 54. .
  • the shift register 30 receives the gate signal and the clock signal CKn of the previous stage to generate a desired operating point voltage signal Qn and a gate scanning signal Gn.
  • the clock signal CKn is a periodic signal.
  • the voltage signal of the operating point is also coupled, and there is a chance to cause a ripple signal and cause the gate line 32 to malfunction.
  • a high-frequency signal combination circuit 5802 is added to the pull-down maintaining module 58 to solve this problem.
  • the pull-down maintaining module 58 is electrically coupled to a low preset potential Vss, and is used to eliminate noise at the operating point voltage of the shift register 30.
  • the high-frequency signal combination circuit 5802 can effectively remove the ripple signal generated by the clock signal CKn, thereby preventing the gate line 32 from malfunctioning.
  • the control module 56 is electrically coupled to the low preset potential Vss, and is electrically coupled to the pull-down maintenance module 58 for generating a correct timing to control the pull-down maintenance module 58.
  • the input module 50 is configured to receive the gate signal of the n-1th stage and generate the operating point voltage of the shift register 30 according to the gate signal of the n-1th stage.
  • the output module 52 is configured to receive a clock signal CKn and precharge the operating point voltage of the shift temporary storage circuit into a precharge bit, and couple the precharge bit to the operating point voltage according to the clock signal CKn.
  • a signal Qn, and a gate scan signal Gn is output according to the coupled operating point voltage signal Qn and the clock signal CKn.
  • the feedback module 54 is configured to receive a feedback signal Gn + and pull down the potentials of the operating point voltage signal Qn and the gate scan signal Gn to a low preset potential according to the feedback signal Gn +.
  • the input module 50 has a transistor switch to receive the gate signal. After F2, the operating point voltage required by the shift register 30 is generated for the operating point of the shift register 30.
  • the output module 52 includes two transistor switches.
  • the control terminal of the transistor switch on the left will first precharge the operating point voltage of the operating point of the shift register 30 into a precharge bit, and charge the precharge according to the clock signal CK3.
  • the bit coupling becomes the operating point voltage signal Q3.
  • the first terminal of the transistor switch receives the clock signal CK3, and the second terminal of the transistor switch generates the gates required for the post-start stage shift register 30 and the gate line 32.
  • the control terminal of the right transistor switch receives the operating point voltage signal Q3.
  • the control terminal of the transistor switch receives the clock signal CK3 according to the operating point voltage signal Q3, and the first terminal of the transistor switch receives the clock signal CK3 from the second terminal.
  • a gate scan signal G3 is output to the gate line 32.
  • the feedback module 54 also includes two transistor switches, and the control terminals of the two transistor switches are coupled to the gate scan signal G7 of the subsequent stage.
  • the gate scan signal G7 is used as a feedback signal G7 for the purpose of ending the gate scan signal.
  • the second ends of the two transistor switches are both coupled to a low preset potential Vss.
  • FIG. 3 is a circuit diagram of a high-frequency signal combining circuit 5802 according to the present disclosure.
  • the high-frequency signal combination circuit 5802 includes a first switch 40, a second switch 42, and a third switch 44.
  • the control terminal 40G of the first switch 40 is electrically coupled to one of the clock signal CKn-1 of the previous stage and the clock signal CKn of this stage.
  • the first terminal 40D of the first switch 40 is electrically The clock signal CKn-1 and the other signal of the clock signal CKn are coupled.
  • the illustration still uses the foregoing embodiment of the 6CK clock signal to describe the high-frequency signal combination circuit 5802 in the third shift register 30.
  • the control end 40G of the first switch 40 in the figure is electrically coupled to the clock.
  • the signal CK3 and the first terminal 40D of the first switch 40 are electrically coupled to the clock signal CK2.
  • the pull-down signal PQ3 at the intersection of the clock signal CK3 and the clock signal CK2 is transmitted to the second terminal 40S of the first switch 40.
  • the control terminal 42G of the second switch 42 is electrically coupled to the operating point voltage signal Q3, and the first terminal 42D of the second switch 42 is electrically coupled to the second terminal of the first switch 40. Therefore, when the operating point voltage signal Q3 turns on the second switch 42 through the control terminal 42G, the pull-down signal PQ3 is transmitted to the second terminal 42S of the second switch 42.
  • the control terminal 44G of the third switch 44 is electrically coupled to the second terminal 42S of the second switch 42, and the first terminal 44D of the third switch 44 is electrically coupled to the operating point voltage signal Q3.
  • the second terminal 44S of the third switch 44 is electrically coupled to a low preset potential Vss.
  • the first switch 40 is a first transistor
  • the second switch 42 is a second transistor
  • the third switch 44 is a third transistor.
  • FIG. 4 is a schematic waveform diagram of levels of various signals of the present disclosure. Each signal has a different level, that is, a high voltage value can represent a valid signal. The illustration is still described with the embodiment of the 6CK clock signal.
  • the clock signals are CK1, CK2, CK3, CK4, CK5, and CK6, respectively.
  • the operating point voltage signal Q3 is a relatively ideal waveform that has been pre-coupled to the clock signal CK3, in order to smoothly pull up to a high voltage level, efficiently turn on the transistor switch, and the gate scan signal G3 is smoothly transmitted to the gate line. 32.
  • the ripple signal Ri In order for the ripple signal Ri to occur at the operating point voltage signal Q3, the ripple signal Ri is effectively pulled down.
  • another embodiment of the present disclosure provides a display panel and a high-frequency signal combining circuit 5802 in the display panel.
  • the display panel is, for example, a liquid crystal display panel 10, and the high-frequency signal combining circuit 5802 is for an array substrate type.
  • the liquid crystal display panel 10 has n cascaded shift registers 30 and gate lines 32 electrically coupled to the shift registers 30. n is a positive integer greater than 2.
  • the nth shift register receives the gate signal of the n-1th stage to transmit the gate scan signal Gn through the gate line 32, wherein the shift register 30 has an operating point voltage signal Qn.
  • the pull-down maintaining module 58 in the shift register 30 has the high-frequency signal combining circuit 5802, and the pull-down maintaining module 58 is used to eliminate noise of the operating point voltage of the shift register 30.
  • the high-frequency signal combination circuit 5802 further includes a first switch 40, a second switch 42, and a third switch 44.
  • the control terminal of the first switch 40 is electrically coupled to one of the clock signal CKn-1 and the clock signal CKn.
  • the first terminal of the first switch 40 is electrically coupled to the clock signal CKn-1 and the clock signal. Another signal in CKn.
  • a control terminal of the second switch 42 is electrically coupled to the operating point voltage signal Qn, and a first terminal of the second switch 42 is electrically coupled to a second terminal of the first switch 40.
  • the control terminal of the third switch 44 is electrically coupled to the second terminal of the second switch 42.
  • the first terminal of the third switch 44 is electrically coupled to the operating point voltage signal Qn.
  • the second terminal of the switch 44 is electrically coupled to the low preset potential Vss.
  • the high-frequency signal combination circuit 5802 is provided in the pull-down maintaining module 58 and can generate a pull-down signal PQ3 which is an intersection of the clock signal CK2 and the clock signal CK3.
  • the pull-down signal PQ3 can effectively remove the clock signal CK3 from the operating point voltage signal Qn.
  • the generated ripple signal Ri can prevent the gate line 32 from malfunctioning.
  • control terminal of the first switch 40 may be electrically coupled to the clock signal CKn, and the first terminal of the first switch 40 may be electrically coupled to the clock signal CKn-1 .
  • the first switch 40 is a first transistor
  • the second switch 42 is a second transistor
  • the third switch 44 is a third transistor.
  • the shift register 30 may further include a control module 56, an input module 50, an output module 52, and a feedback module 54.
  • the control module 56 is electrically coupled to the pull-down maintenance module 58 for generating a timing to control the pull-down maintenance module 58.
  • the input module 50 is configured to receive the gate signal of the n-1th stage and generate the operating point voltage of the shift register 30 according to the gate signal of the n-1th stage.
  • the output module 52 is configured to receive a clock signal CKn and precharge the operating point voltage of the shift temporary storage circuit into a precharge bit, and couple the precharge bit to the operating point voltage according to the clock signal CKn.
  • a signal Qn, and a gate scan signal Gn is output according to the coupled operating point voltage signal Qn and the clock signal CKn.
  • the feedback module 54 is configured to receive a feedback signal and pull the potential of the gate scan signal Gn to a low preset potential according to the feedback signal.
  • FIG. 5 is a flowchart of a driving method performed by the high-frequency signal combining circuit 5802 according to the present disclosure.
  • Another embodiment of the present disclosure provides a driving method of a shift register.
  • the driving method is used for a liquid crystal display panel 10 of an array substrate type driving technology.
  • the liquid crystal display panel 10 has n cascaded shifts.
  • the register 30, n is a positive integer greater than two.
  • the driving method includes the following steps:
  • the shift register 30 has Operating point voltage signal Qn.
  • the pull-down maintaining module 58 in the shift register 30 includes the high-frequency signal combining circuit 5802.
  • the high-frequency signal combining circuit 5802 includes a first switch 40, a second switch 42, and a third switch 44.
  • the second terminal 42S and the second terminal 44S of the third switch 44 are electrically coupled to a low preset potential Vss.
  • FIG. 6 is a flowchart of a driving method performed by the shift register 30 of the present disclosure.
  • the n-1th stage gate signal is received to transmit the gate scanning signal Gn through the gate line 32, wherein the shift stage The memory 30 has an operating point voltage signal Qn.
  • the driving method further includes the following steps:
  • step one (S11), step one (S12), step one (S13), and step one (S14) describe in detail how to perform step one (S01) of FIG. 5.
  • step 2 (S02), step 3 (S03), step 4 (S04), step 5 (S05), and step 6 (S06) of the example shown in FIG. 5 are performed.
  • step 1 (S15) in FIG. 6 is performed: receiving a feedback signal, and pulling the potential of the operating point voltage signal Qn or the gate scan signal Gn to a low preset potential according to the feedback signal.
  • the shift register 30 further includes a pull-down maintaining module 58, a control module 56, an input module 50, an output module 52, and a feedback module 54.
  • the first switch 40 is a first transistor
  • the second switch 42 is a second transistor
  • the third switch 44 is a third transistor.
  • the shift register 30, the display panel, and the driving method of the shift register utilize a high-frequency signal combination circuit 5802 in the shift register 30, thereby enabling The ripple signal generated by the operating point voltage signal Qn is effectively removed, and the malfunction of the gate line 32 can be avoided.

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Abstract

一种移位暂存器（30）、显示面板（10）、以及移位暂存器（30）的驱动方法，显示面板（10）中的移位暂存器（30）包括控制模块（56）及下拉维持模块（58），下拉维持模块（58）进一步包括高频信号组合电路（5802），高频信号组合电路（5802）包括第一开关（40）、第二开关（42）、以及第三开关（44），第一开关（40）的控制端（40G）电性耦接本级时钟信号（CKn），第一开关（40）的第一端（40D）电性耦接前一级的时钟信号（CKn-1），第二开关（42）的控制端（42G）电性耦接工作点电压信号（Q3），第二开关（42）的第一端（42D）电性耦接第一开关（40）的第二端（40S），第三开关（44）的控制端（44G）电性耦接第二开关（42）的第二端（42S），第三开关（44）的第一端（44D）电性耦接工作点电压信号（Q3），第三开关（44）的第二端（44S）电性耦接低预设电位（Vss）。

Description

移位暂存器、显示面板、以及移位暂存器的驱动方法 技术领域
本公开涉及一种显示面板，尤其涉及一种显示面板中的移位暂存器以及移位暂存器中高频信号组合电路消除涟波的驱动方法。
背景技术
为节省成本，如液晶显示面板的显示面板产业已经广泛采用阵列基板型驱动技术(Gate Driver on Array；GOA)。传统液晶显示面板的技术需仰赖源极驱动芯片(Source IC)及栅极驱动芯片(Gate IC)来进行驱动，前者控制电压来传输信号，后者以晶体管当作开关来控制及决定透光量。
阵列基板型驱动技术就是舍弃传统的栅极驱动芯片，取而代之的是将栅极驱动电路结构直接制做在液晶显示面板的玻璃基板上，由于栅极驱动电路结构是利用曝光显影方式，在玻璃基板边缘产生多个移位暂存器的相关逻辑电路，所以无论是材料或是制造流程上，皆能藉此达到降低成本的目的，并且还能达到缩减液晶显示器边框的效果。
阵列基板型驱动技术的原理是从汤普森(Tompson)电路基础上所发展出来的，为求驱动效果顺畅，通常会在工作点(Quiescent point)进行预充，以达到较高电平的电压准位，使得后续能跟时钟信号耦合成理想的信号波型，藉此，当晶体管的开关打开时，栅极线路所需的栅级扫描信号得以顺利传递。
但是，时钟信号是一种周期性信号,在不需要产生栅级扫描信号时，也会因耦合到工作点的工作点电压信号，而产生涟波(ripple)信号而对栅极线路产生极短暂的误动作。
因此，如何去除时钟信号所产生的涟波信号，避免栅极线路产生误动作，已成为本领域技术人员欲解决的问题之一。
发明内容
本公开提出一种移位暂存器、显示面板、以及移位暂存器的驱动方法，能够有效的去除时钟信号所产生的涟波信号，藉此可以避免栅极线路产生误动作。
本公开的一实施例提出一种移位暂存器，为一种栅极驱动电路结构，用于阵列基板型驱动技术(Gate Driver on Array；GOA)的显示面板，所述的显示面板例如是液晶显示面板，所述液晶显示面板具有多个如n个级联的移位暂存器，n为大于2的正整数，所述第n个移位暂存器接收如前一级的第n-1级栅级信号，以传送这一级的栅级扫描信号Gn至栅极线路，其中所述移位暂存器具有这一级的工作点电压信号Qn。所述移位暂存器包括下拉维持模块、及控制模块。
所述控制模块电性耦接所述下拉维持模块，用于产生正确的时序来控制所述下拉维持模块。所述下拉维持模块电性耦接低预设电位，用于消除所述移位暂存器中工作点电压的杂讯，所述下拉维持模块进一步包括高频信号组合电路。所述高频信号组合电路包括第一开关、第二开关、以及第三开关。
所述第一开关的控制端电性耦接前一级的时钟信号CKn-1以及这一级的时钟信号CKn中的其中一个信号，所述第一开关的第一端电性耦接时钟信号CKn-1以及时钟信号CKn中的另外一个信号。
所述第二开关的控制端电性耦接所述工作点电压信号Qn，所述第二开关的第一端电性耦接所述第一开关的第二端。
所述第三开关的控制端电性耦接所述第二开关的第二端，所述第三开关的第一端电性耦接所述工作点电压信号Qn，所述第三开关的第二端电性耦接低预设电位Vss。
其中，所述第一开关的控制端可以电性耦接时钟信号CKn，所述第一开关的第一端可以电性耦接时钟信号CKn-1。藉此，利用移位暂存器中增设一个高频信号组合电路，藉此能够有效的去除时钟信号CKn所产生的涟波信号，并且可以避免栅极线路产生误动作。
补充说明的是，所述第一开关可以为第一晶体管，所述第二开关可以为第二晶体管，所述第三开关可以为第三晶体管。
在本实施例中，所述移位暂存器还可进一步包括输入模块、输出模块、以及反馈模块。
所述输入模块用于接收第n-1级的栅级信号，并根据第n-1级的栅级信号，生成所述移位暂存器的工作点电压。
所述输出模块用于接收时钟信号CKn以及预充所述移位暂存电路的工作点电压成为预充电位，并根据所述时钟信号CKn将所述预充电位耦合成为所述工作点电压信号Qn，且根据耦合后的工作点电压信号Qn与所述时钟信号CKn输出栅极扫描信号Gn。
所述反馈模块用于接收反馈信号，并根据所述反馈信号将所述栅极扫描信号Gn电位拉低至低预设电位。
本公开的另一实施例提出一种显示面板以及利用在显示面板中的高频信号组合电路，高频信号组合电路用于阵列基板型驱动技术的液晶显示面板，所述液晶显示面板具有n个级联的移位暂存器，n为大于2的正整数，所述第n个移位暂存器接收第n-1级的栅级信号，以通过栅极线路传送栅级扫描信号Gn，其中所述移位暂存器具有工作点电压信号Qn。
所述移位暂存器中的下拉维持模块具有所述高频信号组合电路，所述下拉维持模块用于消除所述移位暂存器的工作点电压的杂讯。所述高频信号组合电路包括第一开关、第二开关、以及第三开关。
所述第一开关的控制端电性耦接时钟信号CKn-1以及时钟信号CKn中的其中一个信号，所述第一开关的第一端电性耦接时钟信号CKn-1以及时钟信号CKn中的另外一个信号。
所述第二开关的控制端电性耦接所述工作点电压信号Qn，所述第二开关的第一端电性耦接所述第一开关的第二端。
所述第三开关的控制端电性耦接所述第二开关的第二端，所述第三开关的第一端电性耦接所述工作点电压信号Qn，所述第三开关的第二端电性耦接低预设电位Vss。
进一步，所述第一开关的控制端可以为电性耦接时钟信号CKn，所述第一开关的第一端可以为电性耦接时钟信号CKn-1。藉此，利用移位暂存器中增设一个高频信号组合电路，藉此能够有效的去除时钟信号CKn所产生的涟波信号，并且可以避免栅极线路产生误动作。
补充说明的是，所述第一开关为第一晶体管，所述第二开关为第二晶体管，所述第三开关为第三晶体管。
在本实施例中，所述移位暂存器还可进一步包括控制模块、输入模块、输出模块、以及反馈模块。
所述控制模块电性耦接所述下拉维持模块，用于产生正确的时序来控制所述下拉维持模块。
所述输入模块用于接收第n-1级的栅级信号，并根据第n-1级的栅级信号，生成所述移位暂存器的工作点电压。
所述输出模块用于接收时钟信号CKn以及预充所述移位暂存电路的工作点电压成为预充电位，并根据所述时钟信号CKn将所述预充电位耦合成为所述工作点电压信号Qn，且根据耦合后的工作点电压信号Qn与所述时钟信号CKn输出栅极扫描信号Gn。
所述反馈模块用于接收反馈信号，并根据所述反馈信号将所述栅极扫描信号Gn电位拉低至低预设电位。
此外，本公开的另一实施例提出一种消除涟波的驱动方法，所述驱动方法用于阵列基板型驱动技术的液晶显示面板，所述液晶显示面板具有n个级联的移位暂存器，n为大于2的正整数。所述驱动方法包括下列步骤：所述第n个移位暂存器接收第n-1级的栅级信号，以通过栅极线路传送栅级扫描信号Gn，所述移位暂存器具有工作点电压信号Qn。其中，移位暂存器中的下拉维持模块具有所述高频信号组合电路，所述高频信号组合电路包括第一开关、第二开关、以及第三开关；传送时钟信号CKn-1予所述第一开关的第一端；传送时钟信号CKn予所述第一开关的控制端，其中所述第二开关的第一端电性耦接所述第一开关的第二端；传送所述工作点电压信号Qn予所述第二开关的控制端，其中所述第三开关的控制端电性耦接所述第二开关的第二端；以及传送所述工作点电压信号Qn予所述第三开关的第一端，所述第三开关的第二端电性耦接低预设电位Vss，其中所述低预设电位Vss会拉低工作点电压信号Qn。
进一步，如前述的驱动方法，针对所述第n个移位暂存器接收第n-1级的栅级信号，以通过栅极线路传送栅级扫描信号Gn，其中所述移位暂存器具有工作点电压信号Qn。根据上述步骤，所述驱动方法进一步包括下列步骤：接收第n-1级的栅级信号，并根据第n-1级的栅级信号，生成所述移位暂存器的工作点电压；使所述移位暂存器的工作点电压维持为低预设电位；用于 接收时钟信号CKn以及预充所述移位暂存器的工作点电压成为预充电位，并根据所述时钟信号CKn将所述预充电位耦合成为所述工作点电压信号Qn；根据耦合后的工作点电压信号Qn与所述时钟信号CKn输出所述栅极扫描信号Gn；以及接收反馈信号，并根据所述反馈信号将所述栅极扫描信号Gn电位拉低至低预设电位。
藉此，本公开实施例的一种移位暂存器、显示面板、以及移位暂存器的驱动方法，利用移位暂存器中增设一个高频信号组合电路，藉此能够有效的去除时钟信号CKn所产生的涟波信号，并且可以避免栅极线路产生误动作。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其他目的、特征和优点能够更明显易懂，以下特举具体实施例，并配合附图,详细说明如下。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本公开移位暂存器所在液晶显示面板的示意图。
图2A是本公开移位暂存器的功能关联图。
图2B是本公开移位暂存器实施例的示意图。
图3是本公开高频信号组合电路的电路示意图。
图4是本公开各种信号的准位的波形示意图。
图5是本公开高频信号组合电路所进行驱动方法的流程图。
图6是本公开移位暂存器所进行驱动方法的流程图。
具体实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本公开的示例性实施例的目的。但是本公开可以通过许多替换形式来具体实 现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本公开的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或组件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本公开的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个组件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
请参照图1，图1是本公开移位暂存器30所在液晶显示面板10的示意图。本公开的一实施例提出一种移位暂存器30，用于阵列基板型驱动技术(Gate Driver on Array；GOA)的显示面板，所述显示面板例如是液晶显示面板10，后续以液晶显示面板10为例来说明。所述液晶显示面板10具有多个如n个级联的移位暂存器30，n为大于2的正整数，所述第n个移位暂存器30接收如前一级的第n-1级栅级信号，以传送这一级的栅级扫描信号Gn至栅极线路32，其中所述移位暂存器30的工作点具有这一级的工作点电压 信号Qn。
图中液晶显示面板10仍具有源极驱动芯片12，阵列基板型驱动技术舍弃了栅极驱动芯片，取而代之的是如图将多个移位暂存器30直接设置在玻璃基板上，来作为驱动栅极线路32的电路。每一个移位暂存器30会接收前级的栅级信号，以通过栅极线路32传送栅级扫描信号。
请参照图2A以及图2B，图2A是本公开移位暂存器30的功能关联图。图2B是本公开移位暂存器30实施例的示意图。在本实施例中针对第n个移位暂存器30说明，其中，第n个移位暂存器30包括下拉维持模块58、控制模块56、输入模块50、输出模块52、以及反馈模块54。
移位暂存器30会接收前级的栅级信号以及时钟信号CKn来产生所要的工作点电压信号Qn以及栅级扫描信号Gn。但是时钟信号CKn是一个周期性信号,在非需要栅级扫描信号Gn输出时，也会耦合工作点电压信号,而有机会造成涟波信号，使栅极线路32产生误动作。
因此，所述下拉维持模块58中增设一个高频信号组合电路5802来解决这个问题。所述下拉维持模块58电性耦接低预设电位Vss，用于消除所述移位暂存器30的工作点电压的杂讯。所述高频信号组合电路5802能够有效的去除时钟信号CKn所产生的涟波信号，藉此可以避免栅极线路32产生误动作。
所述控制模块56电性耦接所述低预设电位Vss，并电性耦接所述下拉维持模块58，用于产生正确的时序来控制所述下拉维持模块58。
所述输入模块50用于接收第n-1级的栅级信号，并根据第n-1级的栅级信号，生成所述移位暂存器30的工作点电压。
所述输出模块52用于接收时钟信号CKn以及预充所述移位暂存电路的工作点电压成为预充电位，并根据所述时钟信号CKn将所述预充电位耦合成为所述工作点电压信号Qn，且根据耦合后的工作点电压信号Qn与所述时钟信号CKn输出栅极扫描信号Gn。
所述反馈模块54用于接收反馈信号Gn+，并根据所述反馈信号Gn+将所述工作点电压信号Qn与所述栅极扫描信号Gn的电位拉低至低预设电位。
进一步以图2B的实施例来做说明，如图是一个6CK时钟信号的实施例，为了对第3条栅极线路32产生栅极扫描信号G3，输入模块50具有一个晶体 管开关，接收栅级信号F2后，对所述移位暂存器30的工作点生成移位暂存器30所需的工作点电压。
输出模块52包括二个晶体管开关，左边晶体管开关的控制端会先预充所述移位暂存器30工作点的工作点电压成为预充电位，并根据所述时钟信号CK3将所述预充电位耦合成为所述工作点电压信号Q3，此晶体管开关的第一端接收时钟信号CK3，此晶体管开关的第二端则产生启动后级移位暂存器30以及栅极线路32所需要的栅级信号F3。
右边晶体管开关的控制端接收所述工作点电压信号Q3，此晶体管开关的控制端根据所术工作点电压信号Q3，与此晶体管开关的第一端接收所述时钟信号CK3，以自第二端对栅极线路32输出栅极扫描信号G3。
反馈模块54也包括二个晶体管开关，两个晶体管开关的控制端皆耦接后级的栅极扫描信号G7，此栅极扫描信号G7是用于作为反馈信号G7，目的来结束栅极扫描信号G3。两个晶体管开关的第二端皆耦接低预设电位Vss，当左边的晶体管开关收到所述后级的栅极扫描信号G7后，根据此反馈信号G7，分别将工作点电压信号Q3以及所述栅极扫描信号G3的电位拉低至低预设电位Vss，因此使栅极线路32结束信号。
图3是本公开高频信号组合电路5802的电路示意图。所述高频信号组合电路5802包括第一开关40、第二开关42、以及第三开关44。
所述第一开关40的控制端40G电性耦接前一级的时钟信号CKn-1以及这一级的时钟信号CKn中的其中一个信号，所述第一开关40的第一端40D电性耦接时钟信号CKn-1以及时钟信号CKn中的另外一个信号。
图例依旧以前述6CK时钟信号的实施例，针对第3个移位暂存器30中的高频信号组合电路5802来说明，图示中所述第一开关40的控制端40G电性耦接时钟信号CK3，所述第一开关40的第一端40D电性耦接时钟信号CK2。当时钟信号CK3通过控制端40G打开第一开关40后，时钟信号CK3与时钟信号CK2交集的下拉信号PQ3，就会传输至第一开关40的第二端40S。
所述第二开关42的控制端42G电性耦接所述工作点电压信号Q3，所述第二开关42的第一端42D电性耦接所述第一开关40的第二端。所以，当工作点电压信号Q3通过控制端42G打开第二开关42后，下拉信号PQ3就会传输至第二开关42的第二端42S。
所述第三开关44的控制端44G电性耦接所述第二开关42的第二端42S，所述第三开关44的第一端44D电性耦接所述工作点电压信号Q3，所述第三开关44的第二端44S电性耦接低预设电位Vss。
所以，当下拉信号PQ3通过控制端44G打开第三开关44后，第二端44S的低预设电位Vss就会拉低第一端44D的工作点电压信号Q3。
因此，当工作点电压信号Q3发生所述涟波信号时，会打开第二开关42，进而使下拉信号PQ3打开第三开关44，也因此将工作点电压信号Q3拉低至低预设电位Vss，因而消除涟波信号。
补充说明的是，所述第一开关40为第一晶体管，所述第二开关42为第二晶体管，所述第三开关44为第三晶体管。
针对信号所产生的波形请参照图4，图4是本公开各种信号的准位的波形示意图。每个信号会有高低不同的电平，也就是高电平的电压值可以代表有效的信号。图示依旧是以6CK时钟信号的实施例来说明，时钟信号分别为CK1、CK2、CK3、CK4、CK5、CK6，波形依时序分别如图所示。
工作点电压信号Q3是已经对时钟信号CK3预充所耦合成较理想的波形，以便顺利拉高至高电压准位，有效率的打开晶体管开关，而使栅极扫描信号G3顺利传递至栅极线路32。
为了使工作点电压信号Q3发生涟波信号Ri时，将涟波信号Ri有效的被拉下，高频信号组合电路5802所产生由时钟信号CK2与时钟信号CK3交集而成的下拉信号PQ3，则可以有效且快速的拉低工作点电压信号Q3的涟波信号Ri至低预设电位Vss，能减少杂讯。
此外，根据前述图例，本公开的另一实施例提出一种显示面板以及显示面板中的高频信号组合电路5802，显示面板例如是液晶显示面板10，高频信号组合电路5802用于阵列基板型驱动技术的液晶显示面板10。所述液晶显示面板10具有n个级联的移位暂存器30以及移位暂存器30所电性耦接的栅极线路32，n为大于2的正整数，所述第n个移位暂存器30接收第n-1级的栅级信号，以通过栅极线路32传送栅级扫描信号Gn，其中所述移位暂存器30具有工作点电压信号Qn。所述移位暂存器30中的下拉维持模块58具有所述高频信号组合电路5802，所述下拉维持模块58用于消除所述移位暂存器30的工作点电压的杂讯。
所述高频信号组合电路5802进一步包括第一开关40、第二开关42、以及第三开关44。
所述第一开关40的控制端电性耦接时钟信号CKn-1以及时钟信号CKn中的其中一个信号，所述第一开关40的第一端电性耦接时钟信号CKn-1以及时钟信号CKn中的另外一个信号。
所述第二开关42的控制端电性耦接所述工作点电压信号Qn，所述第二开关42的第一端电性耦接所述第一开关40的第二端。
所述第三开关44的控制端电性耦接所述第二开关42的第二端，所述第三开关44的第一端电性耦接所述工作点电压信号Qn，所述第三开关44的第二端电性耦接低预设电位Vss。
而高频信号组合电路5802设置在下拉维持模块58中，能够产生由时钟信号CK2与时钟信号CK3交集而成的下拉信号PQ3，下拉信号PQ3能够有效的去除时钟信号CK3于工作点电压信号Qn中所产生的涟波信号Ri，藉此可以避免栅极线路32产生误动作。
如前述的高频信号组合电路5802，所述第一开关40的控制端可以为电性耦接时钟信号CKn，所述第一开关40的第一端可以为电性耦接时钟信号CKn-1。
补充说明的是，所述第一开关40为第一晶体管，所述第二开关42为第二晶体管，所述第三开关44为第三晶体管。
进一步，所述移位暂存器30还可包括控制模块56、输入模块50、输出模块52、以及反馈模块54。
所述控制模块56电性耦接所述下拉维持模块58，用于产生时序来控制所述下拉维持模块58。
所述输入模块50用于接收第n-1级的栅级信号，并根据第n-1级的栅级信号，生成所述移位暂存器30的工作点电压。
所述输出模块52用于接收时钟信号CKn以及预充所述移位暂存电路的工作点电压成为预充电位，并根据所述时钟信号CKn将所述预充电位耦合成为所述工作点电压信号Qn，且根据耦合后的工作点电压信号Qn与所述时钟信号CKn输出栅极扫描信号Gn。
所述反馈模块54用于接收反馈信号，并根据所述反馈信号将所述栅极 扫描信号Gn电位拉低至低预设电位。
请参阅图5，图5是本公开高频信号组合电路5802所进行驱动方法的流程图。本公开的另一实施例提出一种移位暂存器的驱动方法，所述驱动方法用于阵列基板型驱动技术的液晶显示面板10，所述液晶显示面板10具有n个级联的移位暂存器30，n为大于2的正整数。所述驱动方法包括下列步骤：
步骤一(S01)：所述第n个移位暂存器30接收第n-1级的栅级信号，以通过栅极线路32传送栅级扫描信号Gn，所述移位暂存器30具有工作点电压信号Qn。其中，移位暂存器30中的下拉维持模块58具有所述高频信号组合电路5802，所述高频信号组合电路5802包括第一开关40、第二开关42、以及第三开关44。
步骤二(S02)：传送时钟信号CKn-1予所述第一开关40的第一端40D。
步骤三(S03)：判断所述第一开关40的控制端40G是否接收到时钟信号CKn。其中，所述第二开关42的第一端42D电性耦接所述第一开关40的第二端40S，当步骤三(S03)为是，则时钟信号CK2与时钟信号CK3交集而成的下拉信号PQ3会传送至第二开关42的第一端42D，并进行步骤五(S05)。
步骤四(S04)：传送所述工作点电压信号Qn予所述第三开关44的第一端44D，其中，所述第三开关44的控制端44G电性耦接所述第二开关42的第二端42S，所述第三开关44的第二端44S电性耦接低预设电位Vss。
步骤五(S05)：判断所述第二开关42的控制端42G是否接收到所述工作点电压信号Qn。当步骤五(S05)为是，则下拉信号PQ3会传送至第二开关42的第二端42S，并配合步骤四(S04)进行步骤六(S06)。
步骤六(S06):下拉信号PQ3会打开第三开关44的控制端44G，并将第一端44D的工作点电压信号Qn拉低至所述低预设电位Vss。藉此，所述低预设电位Vss会拉低工作点电压信号Qn的涟波信号Ri，因而去除栅级扫描信号Gn的杂讯。
请参阅图6，图6是本公开移位暂存器30所进行驱动方法的流程图。如前述的驱动方法，针对图5所述第n个移位暂存器30接收第n-1级的栅级信号，以通过栅极线路32传送栅级扫描信号Gn，其中所述移位暂存器30具有工作点电压信号Qn。根据前述，所述驱动方法进一步包括下列步骤：
步骤一(S11):接收第n-1级的栅级信号，并根据第n-1级的栅级信号， 生成所述移位暂存器30的工作点电压。
步骤二(S12):使所述移位暂存器30的工作点电压维持为低预设电位。
步骤三(S13):用于接收时钟信号CKn以及预充所述移位暂存器30的工作点电压成为预充电位，并根据所述时钟信号CKn将所述预充电位耦合成为所述工作点电压信号Qn。
步骤四(S14):根据耦合后的工作点电压信号Qn与所述时钟信号CKn输出所述栅极扫描信号Gn。
上述步骤一(S11)、步骤一(S12)、步骤一(S13)、以及步骤一(S14)，细述了如何执行了图5例的步骤一(S01)。
接着，进行图5例的步骤二(S02)、步骤三(S03)、步骤四(S04)、步骤五(S05)、以及步骤六(S06)。后续，再进行图6步骤一(S15)：接收反馈信号，并根据所述反馈信号将工作点电压信号Qn或所述栅极扫描信号Gn电位拉低至低预设电位。
所述本公开移位暂存器30所进行驱动方法的实施例中，移位暂存器30进一步包括下拉维持模块58、控制模块56、输入模块50、输出模块52、以及反馈模块54。所述第一开关40为第一晶体管，所述第二开关42为第二晶体管，所述第三开关44为第三晶体管。以上相关组件于驱动方法中之相对运作关系，已在前实施利中所述及，因此于此不再冗述。
综上所述，本公开实施例的移位暂存器30、显示面板、以及移位暂存器的驱动方法，利用移位暂存器30中增设一个高频信号组合电路5802，藉此能够有效的去除工作点电压信号Qn所产生的涟波信号，并且可以避免栅极线路32产生误动作。
以上所述，仅是本公开的具体实施例而已，并非对本公开作任何形式上的限制，虽然本公开已以具体实施例揭露如上，然而并非用以限定本公开,任何熟悉本专业的技术人员,在不脱离本公开技术方案范围内，当可利用上述揭示的方法及技术内容作出些许的更动或修饰为等同变化的等效实施例，但凡是未脱离本公开技术方案的内容，依据本公开的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本公开技术方案的范围内。

Claims (20)

  1. 一种移位暂存器，用于阵列基板型驱动技术的显示面板，所述显示面板具有多个级联的移位暂存器，所述移位暂存器接收前一级的栅级信号，以传送栅级扫描信号至栅极线路，其中所述移位暂存器具有工作点电压信号，其中，所述移位暂存器包括：
    下拉维持模块，电性耦接低预设电位，用于消除所述移位暂存器的工作点电压的杂讯，所述下拉维持模块进一步包括：
    高频信号组合电路，包括第一开关、第二开关、以及第三开关，所述第一开关的控制端电性耦接前一级的时钟信号以及这一级的时钟信号中的其中一个信号，所述第一开关的第一端电性耦接前一级的时钟信号以及这一级的时钟信号中的另外一个信号，所述第二开关的控制端电性耦接所述工作点电压信号，所述第二开关的第一端电性耦接所述第一开关的第二端，所述第三开关的控制端电性耦接所述第二开关的第二端，所述第三开关的第一端电性耦接所述工作点电压信号，所述第三开关的第二端电性耦接低预设电位；以及
    控制模块，电性耦接所述下拉维持模块，用于产生时序来控制所述下拉维持模块。
  2. 如权利要求1所述的移位暂存器，其中，所述第一开关的控制端电性耦接这一级的时钟信号，所述第一开关的第一端电性耦接前一级的时钟信号。
  3. 如权利要求1所述的移位暂存器，其中，所述移位暂存器进一步包括：
    输入模块，用于接收前一级的栅级信号，并根据前一级的栅级信号，生成所述移位暂存器的工作点电压；以及
    输出模块，用于接收时钟信号以及预充所述移位暂存电路的工作点电压成为预充电位，并根据所述时钟信号将所述预充电位耦合成为所述工作点电压信号，且根据耦合后的工作点电压信号与所述时钟信号输出栅极扫描信号。
  4. 如权利要求3所述的移位暂存器，其中，所述移位暂存器进一步包括：
    反馈模块，用于接收反馈信号，并根据所述反馈信号将所述栅极扫描信号电位拉低至低预设电位。
  5. 如权利要求1所述的移位暂存器，其中，所述第一开关为第一晶体管，所述第二开关为第二晶体管，所述第三开关为第三晶体管。
  6. 一种显示面板，用于阵列基板型驱动技术，其中，所述显示面板包括：
    多个栅极线路；以及
    多个级联的移位暂存器，所述移位暂存器电性耦接所述栅极线路，所述移位暂存器接收前一级的栅级信号，以传送栅级扫描信号至栅极线路，其中所述移位暂存器具有工作点电压信号，所述移位暂存器包括下拉维持模块，所述下拉维持模块用于消除所述移位暂存器的工作点电压的杂讯，所述下拉维持模块包括
    高频信号组合电路，所述高频信号组合电路包括
    第一开关，所述第一开关的控制端电性耦接前一级的时钟信号以及这一级的时钟信号中的其中一个信号，所述第一开关的第一端电性耦接前一级的时钟信号以及这一级的时钟信号中的另外一个信号，
    第二开关，所述第二开关的控制端电性耦接所述工作点电压信号，所述第二开关的第一端电性耦接所述第一开关的第二端，及
    第三开关，所述第三开关的控制端电性耦接所述第二开关的第二端，所述第三开关的第一端电性耦接所述工作点电压信号，所述第三开关的第二端电性耦接低预设电位。
  7. 如权利要求6所述的显示面板，其中，所述第一开关的控制端电性耦接这一级的时钟信号，所述第一开关的第一端电性耦接前一级的时钟信号。
  8. 如权利要求6所述的显示面板，其中，所述移位暂存器进一步包括：
    控制模块，电性耦接所述下拉维持模块，用于产生时序来控制所述下拉维持模块。
  9. 如权利要求8所述的显示面板，其中，所述移位暂存器进一步包括：
    输入模块，用于接收前一级的栅级信号，并根据前一级的栅级信号，生成所述移位暂存器的工作点电压。
  10. 如权利要求9所述的显示面板，其中，所述移位暂存器进一步包括：
    输出模块，用于接收时钟信号以及预充所述移位暂存电路的工作点电压成为预充电位，并根据所述时钟信号将所述预充电位耦合成为所述工作点电压信号，且根据耦合后的工作点电压信号与所述时钟信号输出栅极扫描信号。
  11. 如权利要求10所述的显示面板，其中，所述移位暂存器进一步包括：
    反馈模块，用于接收反馈信号，并根据所述反馈信号将所述栅极扫描信号电位拉低至低预设电位。
  12. 如权利要求6所述的显示面板，其中，所述第一开关为第一晶体管，所述第二开关为第二晶体管，所述第三开关为第三晶体管。
  13. 一种移位暂存器的驱动方法，所述驱动方法用于阵列基板型驱动技术的显示面板，所述显示面板具有多个级联的移位暂存器，其中，所述驱动方法包括下列步骤：
    所述移位暂存器接收前一级的栅级信号，以通过栅极线路传送栅级扫描信号，所述移位暂存器具有工作点电压信号，其中移位暂存器中的下拉维持模块具有所述高频信号组合电路，所述高频信号组合电路包括第一开关、第二开关、以及第三开关；
    传送前一级的时钟信号予所述第一开关的第一端；
    传送这一级的时钟信号予所述第一开关的控制端，其中所述第二开关的第一端电性耦接所述第一开关的第二端；
    传送所述工作点电压信号予所述第二开关的控制端，其中所述第三开关的控制端电性耦接所述第二开关的第二端；以及
    传送所述工作点电压信号予所述第三开关的第一端，所述第三开关的第二端电性耦接低预设电位，其中所述低预设电位会拉低工作点电压信号。
  14. 如权利要求13所述的驱动方法，针对所述移位暂存器接收前一级的栅级信号，以通过栅极线路传送栅级扫描信号，其中所述移位暂存器具有工作点电压信号，其中，所述驱动方法进一步包括下列步骤：
    接收前一级的栅级信号，并根据前一级的栅级信号，生成所述移位暂存器的工作点电压；
    使所述移位暂存器的工作点电压维持为低预设电位；
    用于接收时钟信号以及预充所述移位暂存器的工作点电压成为预充电位，并根据所述时钟信号将所述预充电位耦合成为所述工作点电压信号；
    根据耦合后的工作点电压信号与所述时钟信号输出所述栅极扫描信号；以及
    接收反馈信号，并根据所述反馈信号将所述栅极扫描信号电位拉低至低预设电位。
  15. 如权利要求14所述的驱动方法，其中，所述第一开关的控制端电性耦接这一级的时钟信号，所述第一开关的第一端电性耦接前一级的时钟信号。
  16. 如权利要求14所述的驱动方法，其中，所述移位暂存器进一步包括：
    控制模块，电性耦接所述下拉维持模块，用于产生时序来控制所述下拉维持模块。
  17. 如权利要求16所述的驱动方法，其中，所述移位暂存器进一步包括：
    输入模块，用于接收前一级的栅级信号，并根据前一级的栅级信号，生成所述移位暂存器的工作点电压。
  18. 如权利要求17所述的驱动方法，其中，所述移位暂存器进一步包括：
    输出模块，用于接收时钟信号以及预充所述移位暂存电路的工作点电压成为预充电位，并根据所述时钟信号将所述预充电位耦合成为所述工作点电压信号，且根据耦合后的工作点电压信号与所述时钟信号输出栅极扫描信号。
  19. 如权利要求16所述的驱动方法，其中，所述移位暂存器进一步包括：
    反馈模块，用于接收反馈信号，并根据所述反馈信号将所述栅极扫描信号电位拉低至低预设电位。
  20. 如权利要求13所述的驱动方法，其中，所述第一开关为第一晶体管，所述第二开关为第二晶体管，所述第三开关为第三晶体管。
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