WO2020010804A1 - 薄膜晶体管结构及其制作方法与显示面板 - Google Patents

薄膜晶体管结构及其制作方法与显示面板 Download PDF

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Publication number
WO2020010804A1
WO2020010804A1 PCT/CN2018/122696 CN2018122696W WO2020010804A1 WO 2020010804 A1 WO2020010804 A1 WO 2020010804A1 CN 2018122696 W CN2018122696 W CN 2018122696W WO 2020010804 A1 WO2020010804 A1 WO 2020010804A1
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Prior art keywords
layer
heavily doped
active layer
doped silicon
silicon layer
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PCT/CN2018/122696
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English (en)
French (fr)
Inventor
张伟彬
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武汉华星光电半导体显示技术有限公司
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Priority to US16/492,946 priority Critical patent/US11063153B2/en
Publication of WO2020010804A1 publication Critical patent/WO2020010804A1/zh

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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
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    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/30—Doping active layers, e.g. electron transporting layers
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/40—Thermal treatment, e.g. annealing in the presence of a solvent vapour
    • H10K71/421—Thermal treatment, e.g. annealing in the presence of a solvent vapour using coherent electromagnetic radiation, e.g. laser annealing
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    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates

Definitions

  • the invention relates to a thin film transistor structure, in particular to a thin film transistor structure of a flexible organic light emitting display, a manufacturing method thereof and a display panel.
  • Flexible organic light-emitting display structures eg, active-matrix organic light-emitting diodes) diode, AMOLED
  • AMOLED active-matrix organic light-emitting diodes
  • the flexible organic light-emitting display structure can use a very thin organic material coating and a glass substrate, so the display structure can be thinner than a conventional display.
  • an amorphous silicon is recrystallized to form polysilicon by excimer laser annealing (ELA), and then doped, and a metal electrode is formed thereon.
  • ELA excimer laser annealing
  • the contact barrier between metal and semiconductor is very high and the contact resistance is very large.
  • increasing the contact area between semiconductor and metal is the simplest and most effective way to reduce resistance.
  • other reductions in on-resistance must be developed to reduce energy consumption.
  • the surface of the amorphous silicon is irradiated with an instantaneous pulse of the laser to melt it and recrystallize it.
  • pinholes are formed on the structure due to impurities and defects.
  • the flexible organic light emitting display still has the following problems in practical use.
  • the on-resistance of the flexible organic light emitting display is a key factor for reducing energy consumption.
  • the resistance often comes from the contact resistance at the metal-semiconductor contact interface.
  • the metal-semiconductor contact barrier is very high, which makes the contact resistance very large.
  • the invention provides a thin film transistor structure, a manufacturing method thereof and a display panel to solve the problem of energy consumption caused by too high contact resistance in the prior art. It can also solve the damage of the flexible substrate under the excimer laser annealing.
  • the main purpose of the present invention is to provide a thin film transistor structure, which can reduce the contact resistance of the source and the drain by using the active layer as the semiconductor material with the source and the drain thereon.
  • a secondary object of the present invention is to provide a thin film transistor structure, which can solve the damage of the flexible substrate under the excimer laser annealing existing in the prior art.
  • an embodiment of the present invention provides a method for manufacturing a thin film transistor.
  • the manufacturing method includes the steps of: providing a flexible substrate, forming an active layer on the flexible substrate; providing a dielectric. A layer disposed above the active layer, the dielectric layer having a plurality of openings; a heavily doped silicon layer is provided in the plurality of openings, and is connected to the active layer, the heavily doped A silicon layer extends upward along a sidewall of the plurality of openings and covers an upper surface of the dielectric layer, the heavily doped silicon layer forms at least one source electrode and at least one drain electrode; and a metal layer is provided on the substrate. Within the plurality of openings, above the at least one source electrode and the at least one drain electrode, and connected to the at least one source electrode and the at least one drain electrode.
  • another embodiment of the present invention provides another thin film transistor structure, including: a flexible substrate, an active layer disposed on the flexible substrate; and a dielectric layer disposed above the active layer,
  • the dielectric layer has a plurality of openings; a heavily doped silicon layer is disposed in the plurality of openings and is connected to the active layer; and the heavily doped silicon layer is along a sidewall of the plurality of openings.
  • the heavily doped silicon layer is configured as at least one source electrode and at least one drain electrode; and a metal layer is disposed in the plurality of openings and is at least one source Above the at least one drain electrode and connected to the at least one source electrode and the at least one drain electrode.
  • a display panel including: a thin film transistor structure including: a flexible substrate, an active layer disposed on the flexible substrate; and a dielectric layer disposed on the active layer.
  • the dielectric layer has a plurality of openings; a heavily doped silicon layer is disposed in the plurality of openings and is connected to the active layer, and the heavily doped silicon layer is along the plurality of openings.
  • a side wall extends upward and covers an upper surface of the dielectric layer, the heavily doped silicon layer is configured as at least one source electrode and at least one drain electrode; and a metal layer is disposed in the plurality of openings and is disposed in the Above the at least one source and the at least one drain are connected to the at least one source and the at least one drain.
  • the manufacturing method further includes: forming a gate on the flexible substrate; forming a first amorphous silicon layer over the gate, and using the gate as a mask The film performs an excimer laser annealing on the first amorphous silicon layer to modify the first amorphous silicon layer to form the active layer, and the active layer is stacked above the gate.
  • the manufacturing method further includes a step of etching the active layer so that the active layer and the gate have the same width and a pattern.
  • the manufacturing method further includes a step before forming a first amorphous silicon layer: providing a gate insulating layer disposed above the gate and the flexible substrate.
  • the gate insulating layer has a flat surface; and the step of providing the heavily doped silicon layer in the plurality of openings by the manufacturing method further includes: disposing the heavily doped silicon layer in the plurality of openings; Above the flat surface and in contact with the flat surface.
  • the heavily doped silicon layer and the active layer are connected as follows: the heavily doped silicon layer is in contact with the plurality of openings through a sidewall contacting the plurality of openings.
  • the active layers are connected.
  • a projection area of the active layer is larger than a projection area of the gate.
  • the active layer has an upper surface, and the heavily doped silicon layer is in contact with the upper surface of the active layer.
  • the step of forming the active layer further includes a step: performing a first heavily doping process on a part of the active layer; and a step of providing the heavily doped silicon layer.
  • the method further includes a step of performing a second heavily doping process on the heavily doped silicon layer.
  • the thin film transistor structure of the present invention can not only use the gate as a mask to avoid the damage of the flexible substrate under the excimer laser annealing.
  • the active layer and the source and drain electrodes thereon can also be made of semiconductor material, so that the contact resistance of the source and drain electrodes can be reduced.
  • FIG. 1 is a schematic diagram of a method for manufacturing a thin film transistor according to a first embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of a thin film transistor structure according to a first embodiment of the present invention.
  • FIG 3 is a schematic cross-sectional view of a thin film transistor structure according to a second embodiment of the present invention.
  • a gate or “at least one gate” may include a plurality of gates.
  • a method for manufacturing a thin film transistor according to a first embodiment of the present invention mainly includes the following steps:
  • Step S11 providing a flexible substrate 120, and forming an active layer 151 on the flexible substrate 120;
  • Step S12 providing a dielectric layer 150 disposed above the active layer 151, the dielectric layer 150 having a plurality of openings 154;
  • Step S13 A heavily doped silicon layer is provided in the plurality of openings 154 and is connected to the active layer 151.
  • the heavily doped silicon layer extends upward along a sidewall of the plurality of openings 154 and Covering an upper surface of the dielectric layer 150, the heavily doped silicon layer forming at least one source electrode 152 and at least one drain electrode 153; and
  • Step S14 providing a metal layer in the plurality of openings 154 and above the at least one source electrode 152 and the at least one drain electrode 153 and with the at least one source electrode 152 and the at least one drain electrode 153 phase connection.
  • a first embodiment of the present invention provides a substrate 110.
  • the substrate 110 may be a glass substrate, and a flexible substrate 120 is provided on the substrate.
  • the material of the flexible substrate 120 may be, but is not limited to, polyimide (PI), polyethylene terephthalate (PET), polyetheretherketone (PEEK), polyethersulfone (PES), and the like.
  • a buffer layer 130 is provided on the flexible substrate 120.
  • the material of the buffer layer 130 may be silicon oxide, silicon nitride, or a combination of the two.
  • a gate 141 is formed on the flexible substrate and the buffer layer 130.
  • the gate 141 can be formed by deposition and patterning, for example, by a physical vapor deposition method, a chemical vapor deposition method, or a plasma-assisted chemistry. Vapor deposition.
  • a gate insulating layer 140 is formed on the gate 141.
  • the gate insulating layer 140 is an inorganic insulating layer or an organic insulating layer, and the inorganic insulating layer is silicon dioxide, silicon nitride, or the like.
  • the organic insulating layer is polyvinylpyrrolidone, polyimide, acrylic, or the like.
  • PECVD plasma-assisted chemical vapor deposition
  • a first amorphous silicon layer is formed above the gate electrode 141, and excimer laser annealing is performed on the first amorphous silicon layer to change the first amorphous silicon layer.
  • a first polysilicon layer is formed above the gate electrode 141, and excimer laser annealing is performed on the first amorphous silicon layer to change the first amorphous silicon layer.
  • a first polysilicon layer is formed above the gate electrode 141, and excimer laser annealing is performed on the first amorphous silicon layer to change the first amorphous silicon layer.
  • performing a channel doping and a first heavily doping process on the first polysilicon layer to form a channel doped region 151c, a source portion 152a of the first heavily doped silicon layer, and A drain electrode 153 a of the first heavily doped silicon layer, and a portion of the first polysilicon layer is etched to perform a patterning process to form an active layer 151
  • the gate 141 can be used as a mask to protect the flexible substrate 120 to prevent damage to the flexible substrate 120 below.
  • the active layer 151 has an upper surface, and a second heavily doped silicon layer is in contact with the upper surface of the active layer 151.
  • the source portion 152a of the first heavily doped silicon layer and the drain electrode 153a of the first heavily doped silicon layer are doped with an n-type dopant (for example, containing phosphorus or arsenic). So that the source portion 152a of the first heavily doped silicon layer and the drain electrode 153a of the first heavily doped silicon layer form an n-type semiconductor.
  • the active layer 151 is stacked on the gate 141.
  • the gate electrode 141 is stacked on the active layer 151.
  • a dielectric layer 150 is provided above the active layer 151.
  • the dielectric layer 150 has a plurality of openings 154.
  • a second heavily doped silicon layer is provided in the plurality of openings 154 and is connected to the active layer 151.
  • the second The heavily doped silicon layer extends upward along a side wall 155 of the plurality of openings 154 and covers an upper surface 156 of the dielectric layer 150.
  • the first and second heavily doped silicon layers form at least one source electrode 152 And at least one drain 153.
  • a source portion 152b and a drain portion 153b of the second heavily doped silicon layer are provided in the plurality of openings 154 and connected to the active layer 151.
  • the step of providing a second heavily doped silicon layer in the plurality of openings 154 includes: providing a second amorphous silicon layer or a second polysilicon layer, and then applying a second amorphous silicon layer or The second polysilicon layer is subjected to a second heavy doping process, so that the second amorphous silicon layer or the second polysilicon layer forms a second heavily doped silicon layer.
  • a patterning process is performed on the second heavily doped silicon layer, so that the second heavily doped silicon layer forms the source portion 152b and the drain portion of the second heavily doped silicon layer. 153b.
  • the source portion 152b and the drain portion 153b of the second heavily doped silicon layer are doped with an n-type dopant (for example, containing phosphorus or arsenic) so that the source The electrode portion 152b and the drain portion 153b form an n-type semiconductor.
  • the source portion 152a of the first heavily doped silicon layer and the source portion 152b of the second heavily doped silicon layer together constitute the source electrode 152, and the first heavily doped silicon layer
  • the drain portion 153a and the drain portion 153b of the second heavily doped silicon layer together form the drain 153.
  • a metal layer is provided, and the metal layer is subjected to a patterning process so that the metal layer forms a source portion 152 c and a source portion of the metal layer.
  • a drain portion 153c is within the plurality of openings 154 and above the source portion 152b and the drain portion 153b of the second heavily doped silicon layer.
  • the source portion 152c and the drain portion 153c of the metal layer, and the source portions 152a, 152b and the drain of the first and second heavily doped silicon layers The electrode portions 153a and 153b together form a source electrode 152 and a drain electrode 153.
  • a flat layer 160 is formed over the source electrode 152 and the drain electrode 153, and an electrode layer 161 is formed over the flat layer 160.
  • the electrode layer 161 is an anode metal layer.
  • a pixel definition layer 170 is formed on the electrode layer 161, and a photoresist spacer 171, 172 is formed on the pixel definition layer 170.
  • the semiconductor-to-semiconductor contact barrier is lower than the metal-to-semiconductor contact barrier, which makes the contact resistance smaller, and the source portion 152b and the drain portion 153b of the second heavily doped silicon layer
  • the plurality of openings 154 are connected to the active layer 151, and the source portion 152b and the drain portion 153b of the second heavily doped silicon layer are arranged along the plurality of openings 154;
  • the side wall 155 extends upward and covers the upper surface 156 of the dielectric layer, so that the contact area can be increased to reduce the contact resistance.
  • the manufacturing method of the thin film transistor according to the second embodiment of the present invention is similar to that of the first embodiment of the present invention, and the same component names and drawing numbers are generally used, but the difference of the second embodiment lies in:
  • the method further includes a step before the step of forming a first amorphous silicon layer: a gate insulating layer 140 is provided above the gate 141 and the flexible substrate 120, and the gate insulating layer 140 has A flat surface 142; and the manufacturing method, in the step of providing the heavily doped silicon layer in the plurality of openings 154, further comprising: removing the source portion 152b and the source portion of the heavily doped silicon layer;
  • the drain portion 153 b is disposed above the flat surface 142 and is in contact with the flat surface 142.
  • a portion of the first polysilicon layer is etched to perform a patterning process to form an active layer 151.
  • the manufacturing method further includes a step of etching the active layer 151 so that the channel doped region 151c of the active layer 151 and the gate electrode 141 have the same width and a pattern.
  • the heavily doped silicon layer and the active layer 151 are connected as follows: the heavily doped silicon layer is in contact with all of the layers through a side wall 157 in contact with the plurality of openings 154.
  • the active layer 151 is connected.
  • the thin film transistor structure of the second embodiment reduces the first heavy doping processing step.
  • the advantage of the above features is that the manufacturing process is relatively simplified. Therefore, not only the production cost can be reduced, but also the manufacturing time can be saved, thereby further increasing the manufacturing efficiency.
  • another embodiment of the present invention provides another thin film transistor structure, including: a substrate 110, the substrate 110 may be a glass substrate, and a flexible substrate 120 is provided on the substrate.
  • the material of the flexible substrate 120 may be, but is not limited to, polyimide (PI), polyethylene terephthalate (PET), polyetheretherketone (PEEK), polyethersulfone (PES), and the like.
  • a buffer layer 130 is provided on the flexible substrate 120.
  • the material of the buffer layer 130 may be silicon oxide, silicon nitride, or a combination of the two.
  • a gate 141 is provided on the flexible substrate and the buffer layer 130. There is a gate insulating layer 140 on the gate 141.
  • the gate insulating layer 140 is an inorganic insulating layer or an organic insulating layer.
  • the inorganic insulating layer is silicon dioxide, silicon nitride, or the like.
  • the organic insulating layer is polyvinylpyrrolidone, polyimide, acrylic, or the like.
  • An active layer 151 is stacked over the gate 141, and has a channel doped region 151c, a source portion 152a of a first heavily doped silicon layer, and a drain of the first heavily doped silicon layer. Section 153a. In this embodiment, a projection area of the active layer 151 is larger than a projection area of the gate electrode 141.
  • the active layer 151 has an upper surface, and a second heavily doped silicon layer is in contact with the upper surface of the active layer.
  • the source portion 152a of the first heavily doped silicon layer and the drain portion 153a of the first heavily doped silicon layer are n-type semiconductors.
  • a dielectric layer 150 is disposed above the active layer 151.
  • the dielectric layer 150 has a plurality of openings 154.
  • the second heavily doped silicon layer has a source portion 152b and a drain portion 153b in the plurality of openings 154 and is connected to the active layer 151.
  • the second heavily doped silicon layer A side wall 155 along the plurality of openings 154 extends upward and covers an upper surface 156 of the dielectric layer.
  • the source portion 152b and the drain portion 153b are n-type semiconductors.
  • a source portion 152c and a drain portion 153c of a metal layer are in the plurality of openings 154 and above the source portion 152b and the drain portion 153b of the second heavily doped silicon layer.
  • the source portion 152c and the drain portion 153c of the metal layer together with the source portion 152b and the drain portion 153b of the heavily doped silicon layer form a source electrode 152 and a drain Pole 153.
  • a planarization layer 160 is disposed above the source electrode 152 and the drain electrode 153, and an electrode layer 161 is disposed above the planarization layer 160.
  • the electrode layer 161 is an anode metal layer.
  • a pixel definition layer 170 is disposed on the electrode layer 161, and a photoresist spacer 171, 172 is disposed on the pixel definition layer 170.
  • yet another embodiment of the present invention provides another thin film transistor structure, but the difference is that the gate insulating layer 140 has a flat surface 142; The source portion 152b and the drain portion 153b are directly disposed above the flat surface 142 and are in contact with the flat surface 142.
  • only one channel doped region 151c is provided without the source portion 152a of the first heavily doped silicon layer and the drain portion 153a of the first heavily doped silicon layer.
  • the channel doped region 151c of the active layer 151 and the gate electrode 141 have the same width and a pattern.
  • the source portion 152b and the drain portion 153b of the heavily doped silicon layer are connected to the active layer 151 through a sidewall 157 in contact with the plurality of openings 154.
  • the semiconductor-to-metal contact area can be increased, it also often has a strong Fermi level pinning effect at the contact interface between the semiconductor polysilicon and the metal, making the metal-semiconductor contact potential
  • the barrier is very high, which makes it impossible to contact.
  • the thin film transistor structure of the present invention uses the same source and drain electrodes as the semiconductor material on the active layer and the source and drain electrodes. The contact resistance of the electrode is reduced, which can effectively reduce the contact resistance, thereby increasing the energy consumption, and solves the damage to the flexible substrate below when the excimer laser annealing in the prior art exists.

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Abstract

本发明公开一种薄膜晶体管的制作方法，其包含步骤：提供一有源层；提供一介质层，所述介质层具有多个开口；提供一重掺杂硅层于所述多个开口内，并与所述有源层相连接，所述重掺杂硅层沿所述多个开口的一侧壁向上延伸并覆盖所述介质层的一上表面；以及提供一金属层于所述多个开口内且于所述重掺杂硅层的至少一源极及至少一漏极的上方并与所述至少一源极及所述至少一漏极的相连接。本发明通过有源层与其上的源极及漏极同为半导体材质，以降低源漏极的接触电阻。

Description

薄膜晶体管结构及其制作方法与显示面板 技术领域
本发明是有关于一种薄膜晶体管结构，特别是有关于一种柔性有机发光显示器的薄膜晶体管结构及其制作方法与显示面板。
 背景技术
柔性有机发光显示器结构（例如，有源矩阵有机发光二极体（Active-matrix organic light-emitting diode, AMOLED））具有自发光性、视角广、色饱和度高、高对比、驱动电压低、功耗低、反应快、重量轻、构造简单、成本低等优点，因此不需要设置背光模组。再者，柔性有机发光显示器结构可以采用非常薄的有机材料涂层及玻璃基板，因此显示器结构可以较传统显示器的厚度薄。
但现有技术通过准分子激光退火(ELA)使非晶硅再结晶形成多晶硅后，再进行掺杂后，并于其上形成金属电极。
因为半导体多晶硅与金属的接触界面存在强烈的费米能级钉扎效应，使得金属与半导体接触势垒很高，使得接触电阻很大。目前增大半导体与金属接触面积是最简便有效的降低电阻的方法。但仍须发展其他降低导通电阻，以降低能耗。再者，在对非晶硅(a-Si)进行准分子激光退火时，利用激光的瞬间脉冲照射到非晶硅表面，使其溶化并重新结晶。而非晶硅在制备过程中由于杂质及缺陷等问题，而在结构上形成针孔。因此在进行准分子激光退火时，高能量的激光会透过针孔照射基底。对玻璃基底而言，可以耐受高能量的激光照射。但当使用聚合物作为柔性基底时，由于聚合物柔性基底具有较低的玻璃化温度及对紫外光的高吸收率，因而难以承受准分子激光退火的激光能量密度，可能造成下方的柔性基底破空或硬化。
然而，所述柔性有机发光显示器在实际使用上仍具有下述问题，例如：柔性有机发光显示器的导通电阻是降低能耗的关键因素。电阻往往来自于在金属与半导体接触界面的接触电阻，金属与半导体接触势垒很高，使得接触电阻很大。
故，有必要提供一种薄膜晶体管结构，以解决现有技术所存在的问题。
 技术问题
本发明提供一种薄膜晶体管结构及其制作方法与显示面板，以解决现有技术所存在的接触电阻太高而造成能耗的问题。还可以解决进行准分子激光退火时，造成下方的柔性基底的破坏。
 技术解决方案
本发明的主要目的在于提供一种薄膜晶体管结构，其可以通过有源层与其上的源极及漏极同为半导体材质，使得源漏极的接触电阻降低。
本发明的次要目的在于提供一种薄膜晶体管结构，其可以解决现有技术所存在的进行准分子激光退火时，造成下方的柔性基底的破坏。
为达成本发明的前述目的，本发明的一个实施例提供一种薄膜晶体管的制作方法，所述制作方法包含步骤：提供一柔性基底，在所述柔性基底上形成一有源层；提供一介质层，设置于所述有源层的上方，所述介质层具有多个开口；提供一重掺杂硅层于所述多个开口内，并与所述有源层相连接，所述重掺杂硅层沿所述多个开口的一侧壁向上延伸并覆盖所述介质层的一上表面，所述重掺杂硅层形成至少一源极及至少一漏极；以及提供一金属层于所述多个开口内且于所述至少一源极及所述至少一漏极的上方并与所述至少一源极及所述至少一漏极的相连接。
再者，本发明的另一个实施例提供另一种薄膜晶体管结构，包含：一柔性基底，一有源层设置于所述柔性基底上；一介质层，设置于所述有源层的上方，所述介质层具有多个开口；一重掺杂硅层设置于所述多个开口内，并与所述有源层相连接，所述重掺杂硅层沿所述多个开口的一侧壁向上延伸并覆盖所述介质层的一上表面，所述重掺杂硅层配置为至少一源极及至少一漏极；以及一金属层设置所述多个开口内且于所述至少一源极及所述至少一漏极的上方并与所述至少一源极及所述至少一漏极的相连接。
另外，本发明的又一个实施例提供一种显示面板，包含：一薄膜晶体管结构包含：一柔性基底，一有源层设置于所述柔性基底上；一介质层，设置于所述有源层的上方，所述介质层具有多个开口；一重掺杂硅层设置于所述多个开口内，并与所述有源层相连接，所述重掺杂硅层沿所述多个开口的一侧壁向上延伸并覆盖所述介质层的一上表面，所述重掺杂硅层配置为至少一源极及至少一漏极；以及一金属层设置所述多个开口内且于所述至少一源极及所述至少一漏极的上方并与所述至少一源极及所述至少一漏极的相连接。
在本发明的一实施例中，所述制造方法更包含：形成一栅极在所述柔性基底上；形成一第一非晶硅层于所述栅极的上方，并以所述栅极为掩膜对所述第一非晶硅层进行准分子激光退火，使所述第一非晶硅层改质以形成所述有源层，所述有源层堆叠于所述栅极的上方。
在本发明的一实施例中，所述制作方法更包含一步骤：对所述有源层进行蚀刻，使得所述有源层与所述栅极具有相同的一宽度及一图形。
在本发明的一实施例中，所述制作方法于形成一第一非晶硅层的步骤之前更包含一步骤：提供一栅极绝缘层，设置于所述栅极及所述柔性基底的上方，所述栅极绝缘层具有一平坦表面；以及所述制作方法于提供所述重掺杂硅层于所述多个开口内的步骤中更包含：将所述重掺杂硅层设置于所述平坦表面的上方，并与所述平坦表面相接触。
在本发明的一实施例中，所述重掺杂硅层与所述有源层相连接为：所述重掺杂硅层通过与所述多个开口相接触的一侧壁而与所述有源层相连接。
在本发明的一实施例中，所述有源层的一投影面积大于所述栅极的一投影面积。
在本发明的一实施例中，所述有源层具有一上表面，所述重掺杂硅层与所述有源层的所述上表面相接触。
在本发明的一实施例中，形成所述有源层的步骤更包含一步骤：对所述有源层的一部分进行一第一重掺杂处理；以及提供所述重掺杂硅层的步骤更包含一步骤：对所述重掺杂硅层进行一第二重掺杂处理。
 有益效果
与现有技术相比较，本发明的薄膜晶体管结构，不但可通过以栅极为掩膜，避免进行准分子激光退火时，造成下方的柔性基底的破坏。还可以通过有源层与其上的源极及漏极同为半导体材质，使得源漏极的接触电阻降低。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，除非另有明确说明，不然在附图中为相同或至少具有相同功能的元件、特征及信号皆提供相同的参考标号，详细说明如下：
图1是本发明第一实施例薄膜晶体管的制作方法示意图。
图2是本发明第一实施例薄膜晶体管结构的剖视示意图。
图3是本发明第二实施例薄膜晶体管结构的剖视示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
本文所使用的单数型式“一”、“一个”及“至少一”包括复数形式，除非上下文另有明确规定。例如，术语“一栅极”或“至少一栅极”可以包括多个栅极。
请参照图1所示，本发明第一实施例的薄膜晶体管的制作方法，主要包含以下步骤：
步骤S11：提供一柔性基底120，在所述柔性基底120上形成一有源层151；
步骤S12：提供一介质层150，设置于所述有源层151的上方，所述介质层150具有多个开口154；
步骤S13：提供一重掺杂硅层于所述多个开口154内，并与所述有源层151相连接，所述重掺杂硅层沿所述多个开口154的一侧壁向上延伸并覆盖所述介质层150的一上表面，所述重掺杂硅层形成至少一源极152及至少一漏极153；以及
步骤S14：提供一金属层于所述多个开口154内且于所述至少一源极152及所述至少一漏极153的上方并与所述至少一源极152及所述至少一漏极153的相连接。
本发明将于下文利用图1至图2逐一详细说明第一实施例上述各元件的细部构造、组装关系及其运作原理。
请参照图2所示，并参照图1的步骤S11所示，本发明第一实施例的提供一基板110，所述基板110可以为一玻璃基板，在所述基板上提供有一柔性基底120，所述柔性基底120的材料可以为但不限于聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚醚醚酮(PEEK)、聚醚砜(PES)等。在所述柔性基底120上提供有一缓冲层130，所述缓冲层130的材料可以为氧化硅、氮化硅或二者的组合。接着，在所述柔性基底及所述缓冲层130上形成一栅极141，所述栅极141可以通过沉积并图案化形成，例如通过物理气相沉积法、化学气相沉积法或是电浆辅助化学气相沉积法。接着，在所述栅极141上形成一栅极绝缘层140，所述栅极绝缘层140为一无机绝缘层或者一有机绝缘层，所述无机绝缘层为二氧化硅、氮化硅等，所述有机绝缘层为聚乙烯吡咯烷酮、聚酰亚胺、丙烯等。所述栅极绝缘层140为一无机绝缘层时，采用电浆辅助化学气相沉积法(PECVD)形成。
请参照图2所示，形成一第一非晶硅层于所述栅极141的上方，并对所述第一非晶硅层进行准分子激光退火，使所述第一非晶硅层改质以形成一第一多晶硅层。接着，对所述第一多晶硅层进行一沟道掺杂及一第一重掺杂处理，以形成一沟道掺杂区151c、一第一重掺杂硅层的源极部分152a及一第一重掺杂硅层的漏极153a，并通过蚀刻部分所述第一多晶硅层以进行一图案化工艺，以形成一有源层151。在本实施例中，所述有源层151的一投影面积大于所述栅极141的一投影面积。因此，在对所述第一非晶硅层进行准分子激光退火的步骤时，可以使用所述栅极141为一掩膜保护所述柔性基底120，避免造成下方的所述柔性基底120的破坏。在本实施例中，所述有源层151具有一上表面，一第二重掺杂硅层与所述有源层151的所述上表面相接触。在本实施例中，所述第一重掺杂硅层的源极部分152a及所述第一重掺杂硅层的漏极153a使用n型掺杂剂（例如含有磷或砷）进行掺杂，使得所述第一重掺杂硅层的源极部分152a及所述第一重掺杂硅层的漏极153a形成n型半导体。于本实施例中，所述有源层151堆叠于所述栅极141的上方。在一个非限制性的实施例中，所述栅极141堆叠于所述有源层151的上方。
请参照图2所示，并参照图1的步骤S12所示，提供一介质层150，设置于所述有源层151的上方，所述介质层150具有多个开口154。
请参照图2所示，并参照图1的步骤S13所示，提供一第二重掺杂硅层于所述多个开口154内，并与所述有源层151相连接，所述第二重掺杂硅层沿所述多个开口154的一侧壁155向上延伸并覆盖所述介质层150的一上表面156，所述第一及第二重掺杂硅层形成至少一源极152及至少一漏极153。在一个实施例中，提供所述第二重掺杂硅层的一源极部分152b及一漏极部分153b于所述多个开口154内，并与所述有源层151相连接，所述提供一第二重掺杂硅层于所述多个开口154内的步骤系包含：提供一第二非晶硅层或一第二多晶硅层，接着对所述第二非晶硅层或所述第二多晶硅层进行一第二重掺杂处理，使得所述第二非晶硅层或所述第二多晶硅层形成一第二重掺杂硅层。接着，对所述第二重掺杂硅层进行图案化工艺，使得所述第二重掺杂硅层形成所述第二重掺杂硅层的所述源极部分152b及所述漏极部分153b。在本实施例中，所述第二重掺杂硅层的所述源极部分152b及所述漏极部分153b使用n型掺杂剂（例如含有磷或砷）进行掺杂，使得所述源极部分152b及漏极部分153b形成n型半导体。所述第一重掺杂硅层的所述源极部分152a及所述第二重掺杂硅层的所述源极部分152b共同构成所述源极152，所述第一重掺杂硅层的漏极部分153a及所述第二重掺杂硅层的所述漏极部分153b共同构成所述漏极153。
请参照图2所示，并参照图1的步骤S14所示，提供一金属层，对所述金属层进行图案化工艺，使得所述金属层形成所述金属层的一源极部分152c及一漏极部分153c于所述多个开口154内且于所述第二重掺杂硅层的所述源极部分152b及所述漏极部分153b的上方。在一个实施例中，所述金属层的所述源极部分152c及所述漏极部分153c与所述第一及第二重掺杂硅层的所述源极部分152a、152b及所述漏极部分153a、153b共同形成一源极152及一漏极153。接着，于所述源极152及所述漏极153上方形成一平坦层160，及于所述平坦层160上方形成一电极层161。在本实施例中，所述电极层161为一阳极金属层。于所述电极层161上形成一像素定义层170，并于所述像素定义层170上形成一光阻间隙物171、172。
如此，半导体与半导体接触势垒相对于金属与半导体接触势垒低，使得接触电阻变小，且所述第二重掺杂硅层的所述源极部分152b及所述漏极部分153b于所述多个开口154内，并与所述有源层151相连接，所述第二重掺杂硅层的所述源极部分152b及所述漏极部分153b沿所述多个开口154的所述侧壁155向上延伸并覆盖所述介质层的所述上表面156，如此可以加大接触面积，以降低接触电阻。
请参照图3所示，本发明第二实施例的薄膜晶体管的制作方法相似于本发明第一实施例，并大致沿用相同元件名称及图号，但第二实施例的差异在于：所述制作方法于形成一第一非晶硅层的步骤之前更包含一步骤：提供一栅极绝缘层140，设置于所述栅极141及所述柔性基底120的上方，所述栅极绝缘层140具有一平坦表面142；以及所述制作方法于提供所述重掺杂硅层于所述多个开口154内的步骤中更包含：将所述重掺杂硅层的所述源极部分152b及所述漏极部分153b设置于所述平坦表面142的上方，并与所述平坦表面142相接触。通过蚀刻部分所述第一多晶硅层以进行一图案化工艺，以形成一有源层151。所述制作方法更包含一步骤：对所述有源层151进行蚀刻，使得所述有源层151的所述沟道掺杂区151c与所述栅极141具有相同的一宽度及一图形。在本发实施例中，所述重掺杂硅层与所述有源层151相连接为：所述重掺杂硅层通过与所述多个开口154相接触的一侧壁157而与所述有源层151相连接。
所述第二实施例的薄膜晶体管结构减少了第一重掺杂处理步骤。上述特征的优点在于：相对地简化制造工艺。因此，不但可降低生产成本，并可节省制造时间，因而进一步相对增加制造效率。
请参照图2所示，本发明的另一个实施例提供另一种薄膜晶体管结构，包含：一基板110，所述基板110可以为一玻璃基板，在所述基板上具有一柔性基底120，所述柔性基底120的材料可以为但不限于聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚醚醚酮(PEEK)、聚醚砜(PES)等。在所述柔性基底120上具有一缓冲层130，所述缓冲层130的材料可以为氧化硅、氮化硅或二者的组合。所述柔性基底及所述缓冲层130上具有一栅极141。在所述栅极141上具有一栅极绝缘层140，所述栅极绝缘层140为一无机绝缘层或者一有机绝缘层，所述无机绝缘层为二氧化硅、氮化硅等，所述有机绝缘层为聚乙烯吡咯烷酮、聚酰亚胺、丙烯等。一有源层151，堆叠于所述栅极141的上方，具有一沟道掺杂区151c、一第一重掺杂硅层的源极部分152a及一第一重掺杂硅层的漏极部分153a。在本实施例中，所述有源层151的一投影面积大于所述栅极141的一投影面积。在本实施例中，所述有源层151具有一上表面，一第二重掺杂硅层与所述有源层的所述上表面相接触。在本实施例中，所述第一重掺杂硅层的源极部分152a及所述第一重掺杂硅层的漏极部分153a是n型半导体。一介质层150，设置于所述有源层151的上方，所述介质层150具有多个开口154。所述第二重掺杂硅层具有一源极部分152b及一漏极部分153b于所述多个开口154内，并与所述有源层151相连接，所述第二重掺杂硅层沿所述多个开口154的一侧壁155向上延伸并覆盖所述介质层的一上表面156。在本实施例中，所述源极部分152b及漏极部分153b为n型半导体。一金属层的一源极部分152c及一漏极部分153c于所述多个开口154内且于所述第二重掺杂硅层的所述源极部分152b及所述漏极部分153b的上方，所述金属层的所述源极部分152c及所述漏极部分153c与所述重掺杂硅层的所述源极部分152b及所述漏极部分153b共同形成一源极152及一漏极153。所述源极152及所述漏极153上方具有一平坦层160，及于所述平坦层160上方具有一电极层161。在本实施例中，所述电极层161为一阳极金属层。于所述电极层161上具有一像素定义层170，并于所述像素定义层170上设置一光阻间隙物171、172。
请参照图3所示，本发明的又一个实施例提供又一种薄膜晶体管结构，但差异在于：所述栅极绝缘层140具有一平坦表面142；将所述重掺杂硅层的所述源极部分152b及所述漏极部分153b直接设置于所述平坦表面142的上方，并与所述平坦表面142相接触。在本实施例中，仅设置一沟道掺杂区151c，而不具有所述第一重掺杂硅层的源极部分152a及所述第一重掺杂硅层的漏极部分153a。所述有源层151的所述沟道掺杂区151c与所述栅极141具有相同的一宽度及一图形。所述重掺杂硅层的所述源极部分152b及所述漏极部分153b通过与所述多个开口154相接触的一侧壁157而与所述有源层151相连接。
如上所述，相较于现有薄膜晶体管结构虽能增大半导体与金属接触面积，却也常于半导体多晶硅与金属的接触界面存在强烈的费米能级钉扎效应，使得金属与半导体接触势垒很高，使得，而导致无法接触电阻很大等缺点，本发明薄膜晶体管结构通过在所述有源层与其上的所述源极及所述漏极同为半导体材质，使得所述源漏极的接触电阻降低，其确实可以有效降低接触电阻，进而提高减少能耗，且解决现有技术所存在的进行准分子激光退火时，造成下方的柔性基底的破坏。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。
虽然本发明的具体实施例在本文中已经有说明及描述，但应理解的是，通过本技术领域的技术人员可利用存在的各种替代和/或等效的方式实现。应当认识到，所述示例性实施例或示例性实施例仅作为示例，并不会限制其范围、适用性或配置。相反地，前面的概述及详细描述在至少一个示例性实施例中实施而为本领域的技术人员提供方便的指示，可理解的是，在不脱离所附属的权利要求及其合法规定的范围下，一个示例性实施例中描述的元件的功能及设置可以作出各种改变，在一般情况下，本申请案涵盖本文所讨论的具体实施例的任何修改或变更。

Claims (20)

  1. 一种薄膜晶体管的制作方法，其包含步骤：
    提供一柔性基底，在所述柔性基底上形成一有源层；
    提供一介质层，设置于所述有源层的上方，所述介质层具有多个开口；
    提供一重掺杂硅层于所述多个开口内，并与所述有源层相连接，所述重掺杂硅层沿所述多个开口的一侧壁向上延伸并覆盖所述介质层的一上表面，所述重掺杂硅层形成至少一源极及至少一漏极；以及
    提供一金属层于所述多个开口内且于所述至少一源极及所述至少一漏极的上方并与所述至少一源极及所述至少一漏极的相连接。
  2. 如权利要求1所述的薄膜晶体管的制作方法，其中所述制造方法更包含：形成一栅极在所述柔性基底上；形成一第一非晶硅层于所述栅极的上方，并以所述栅极为掩膜对所述第一非晶硅层进行准分子激光退火，使所述第一非晶硅层改质以形成所述有源层，所述有源层堆叠于所述栅极的上方。
  3. 如权利要求1所述的薄膜晶体管的制作方法，其中所述制作方法更包含一步骤：对所述有源层进行蚀刻，使得所述有源层与所述栅极具有相同的一宽度及一图形。
  4. 如权利要求3所述的薄膜晶体管的制作方法，其中所述制作方法于形成一第一非晶硅层的步骤之前更包含一步骤：提供一栅极绝缘层，设置于所述栅极及所述柔性基底的上方，所述栅极绝缘层具有一平坦表面；以及所述制作方法于提供所述重掺杂硅层于所述多个开口内的步骤中更包含：将所述重掺杂硅层设置于所述平坦表面的上方，并与所述平坦表面相接触。
  5. 如权利要求4所述的薄膜晶体管的制作方法，其中所述重掺杂硅层与所述有源层相连接为：所述重掺杂硅层通过与所述多个开口相接触的一侧壁而与所述有源层相连接。
  6. 如权利要求1所述的薄膜晶体管的制作方法，其中所述有源层的一投影面积大于所述栅极的一投影面积。
  7. 如权利要求6所述的薄膜晶体管的制作方法，其中所述有源层具有一上表面，所述重掺杂硅层与所述有源层的所述上表面相接触。
  8. 如权利要求7所述的薄膜晶体管的制作方法，其中形成所述有源层的步骤更包含一步骤：对所述有源层的一部分进行一第一重掺杂处理；以及提供所述重掺杂硅层的步骤更包含一步骤：对所述重掺杂硅层进行一第二重掺杂处理。
  9. 一种薄膜晶体管结构，其包含：
    一柔性基底，一有源层设置于所述柔性基底上；
    一介质层，设置于所述有源层的上方，所述介质层具有多个开口；
    一重掺杂硅层设置于所述多个开口内，并与所述有源层相连接，所述重掺杂硅层沿所述多个开口的一侧壁向上延伸并覆盖所述介质层的一上表面，所述重掺杂硅层配置为至少一源极及至少一漏极；以及
    一金属层设置所述多个开口内且于所述至少一源极及所述至少一漏极的上方并与所述至少一源极及所述至少一漏极的相连接。
  10. 如权利要求9所述的薄膜晶体管结构，其中所述薄膜晶体管结构更包含：一栅极设置在所述柔性基底上，所述有源层与所述栅极具有相同的一宽度及一图形。
  11. 如权利要求10所述的薄膜晶体管结构，其中所述薄膜晶体管结构更包含：一栅极绝缘层，设置于所述栅极及所述柔性基底的上方，所述栅极绝缘层具有一平坦表面；以及所述重掺杂硅层设置于所述平坦表面的上方，并与所述平坦表面相接触。
  12. 如权利要求11所述的薄膜晶体管结构，其中所述重掺杂硅层与所述有源层相连接为：所述重掺杂硅层通过与所述多个开口相接触的一侧壁而与所述有源层相连接。
  13. 如权利要求10所述的薄膜晶体管结构，其中所述有源层的一投影面积大于所述栅极的一投影面积。
  14. 如权利要求13所述的薄膜晶体管结构，其中所述有源层具有一上表面，所述重掺杂硅层与所述有源层的所述上表面相接触。
  15. 一种显示面板，其包含：
    一薄膜晶体管结构包含：
    一柔性基底，一有源层设置于所述柔性基底上；
    一介质层，设置于所述有源层的上方，所述介质层具有多个开口；
    一重掺杂硅层设置于所述多个开口内，并与所述有源层相连接，所述重掺杂硅层沿所述多个开口的一侧壁向上延伸并覆盖所述介质层的一上表面，所述重掺杂硅层配置为至少一源极及至少一漏极；以及
    一金属层设置所述多个开口内且于所述至少一源极及所述至少一漏极的上方并与所述至少一源极及所述至少一漏极的相连接。
  16. 如权利要求15所述的显示面板，其中所述薄膜晶体管结构更包含：一栅极设置在所述柔性基底上，所述有源层与所述栅极具有相同的一宽度及一图形。
  17. 如权利要求16所述的显示面板，其中所述薄膜晶体管结构更包含：一栅极绝缘层，设置于所述栅极及所述柔性基底的上方，所述栅极绝缘层具有一平坦表面；以及所述重掺杂硅层设置于所述平坦表面的上方，并与所述平坦表面相接触。
  18. 如权利要求17所述的显示面板，其中所述重掺杂硅层与所述有源层相连接为：所述重掺杂硅层通过与所述多个开口相接触的一侧壁而与所述有源层相连接。
  19. 如权利要求16所述的显示面板，其中所述有源层的一投影面积大于所述栅极的一投影面积。
  20. 如权利要求19所述的显示面板，其中所述有源层具有一上表面，所述重掺杂硅层与所述有源层的所述上表面相接触。
PCT/CN2018/122696 2018-07-12 2018-12-21 薄膜晶体管结构及其制作方法与显示面板 WO2020010804A1 (zh)

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