WO2020009003A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2020009003A1
WO2020009003A1 PCT/JP2019/025670 JP2019025670W WO2020009003A1 WO 2020009003 A1 WO2020009003 A1 WO 2020009003A1 JP 2019025670 W JP2019025670 W JP 2019025670W WO 2020009003 A1 WO2020009003 A1 WO 2020009003A1
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Prior art keywords
contact electrode
region
support substrate
active layer
hole
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English (en)
French (fr)
Japanese (ja)
Inventor
栄亮 伴野
修治 淺野
誠二 野間
晋一郎 上山
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Denso Corp
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Denso Corp
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Publication of WO2020009003A1 publication Critical patent/WO2020009003A1/ja
Priority to US17/137,751 priority Critical patent/US20210119001A1/en
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Definitions

  • the present disclosure relates to a semiconductor device having a contact electrode electrically connected to a support substrate and a method for manufacturing the same.
  • the active layer is divided into an element region and a drawing region by the trench isolation part.
  • a switching element is formed by forming a P-type diffusion region, an N-type diffusion region, and the like.
  • a through-hole is formed penetrating through the active layer and the buried insulating film to reach the support substrate, and a contact electrode electrically connected to the support substrate is arranged in the through-hole.
  • the through-hole has a cylindrical shape having a substantially constant opposing width
  • the contact electrode has a columnar shape along the shape of the through-hole.
  • the present disclosure has an object to provide a semiconductor device and a method for manufacturing the same, which can easily extract noise transmitted to a supporting substrate.
  • a semiconductor device includes a semiconductor substrate in which a support substrate, a buried insulating film, and an active layer are sequentially stacked, and a plurality of regions formed in the active layer and including the extracted region. And a contact electrode which is formed in the through-hole so as to reach the support substrate from the main surface of the semiconductor substrate in the extraction region, and is arranged in the through-hole and electrically connected to the support substrate.
  • the minimum width of the portion in contact with the support substrate is wider than the minimum width of the portion located in the active layer, in the width along the surface direction of the semiconductor substrate.
  • the contact area between the contact electrode and the support substrate can be increased as compared with the case where the minimum width of the contact electrode is constant at the minimum width of the portion located in the active layer, and the noise of the support substrate can be increased. Can be easily pulled out.
  • a semiconductor substrate is prepared, a trench forming a trench isolation portion is formed in an active layer, and a through hole reaching a buried insulating film is formed.
  • a hole and arranging an insulating film in the trench and the through hole forming a trench isolation portion in which the insulating film is arranged in the trench and removing the insulating film arranged in the through hole, Removing the buried insulating film exposed from the through hole, exposing the support substrate from the through hole by digging the through hole, and forming a contact electrode electrically connected to the support substrate in the through hole,
  • the minimum distance between the portions where the support substrate is exposed is reduced in the space between the opposing side surfaces.
  • the contact electrode so as to be wider than the minimum interval between the portions located in the active layer, the minimum width of the portion in contact with the
  • the minimum width of a portion of the contact electrode that contacts the support substrate is wider than the minimum width of a portion located in the active layer. That is, it is possible to manufacture a semiconductor device in which the contact area between the contact electrode and the support substrate is increased so that noise of the support substrate can be easily extracted.
  • the reference numerals in parentheses attached to the respective components and the like indicate an example of the correspondence between the components and the like and the specific components and the like described in the embodiments described later.
  • FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment.
  • FIG. 2 is a plan view of a drawing area shown in FIG. 1.
  • FIG. 2 is a schematic diagram illustrating a noise propagation path when noise occurs in the semiconductor device illustrated in FIG. 1.
  • FIG. 2 is a sectional view illustrating a manufacturing process of the semiconductor device illustrated in FIG. 1.
  • FIG. 4B is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 4A.
  • FIG. 4C is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 4B.
  • FIG. 4C is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 4C.
  • FIG. 4D is a cross-sectional view illustrating a manufacturing step of the semiconductor device following FIG. 4D.
  • FIG. 4G is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 4E.
  • FIG. 4C is a cross-sectional view showing a manufacturing step of the semiconductor device continued from FIG. 4F.
  • FIG. 4G is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 4G.
  • FIG. 4G is a cross-sectional view showing a manufacturing step of the semiconductor device following FIG. 4H.
  • FIG. 9 is a diagram for describing a problem that may occur when performing wet etching.
  • FIG. 4 is a diagram illustrating a relationship between an oxygen concentration of a support substrate and an amount of misalignment.
  • FIG. 4 is a diagram illustrating a relationship between an oxygen concentration of a support substrate and an amount of misalignment.
  • FIG. 9 is a schematic diagram when an abnormality determination of a trench isolation portion is performed in a wafer state, and is a schematic diagram when a contact electrode is independent.
  • FIG. 9 is a schematic diagram when an abnormality determination of a trench isolation portion is performed in a wafer state, and is a schematic diagram when a contact electrode is connected to a field electrode.
  • FIG. 6 is a cross-sectional view of a semiconductor device according to a second embodiment.
  • FIG. 11 is a plan view illustrating a positional relationship among an element region, a trench isolation portion, and a contact electrode in a second embodiment.
  • FIG. 11 is a plan view illustrating a positional relationship among an element region, a trench isolation portion, and a contact electrode according to a third embodiment.
  • FIG. 4 is a diagram illustrating a relationship between an interval between a first contact electrode and a second contact electrode, a noise propagation amount, and an area efficiency.
  • FIG. 9 is a plan view illustrating a positional relationship among an element region, a trench isolation portion, and a contact electrode according to another embodiment.
  • FIG. 9 is a plan view illustrating a positional relationship among an element region, a trench isolation portion, and a contact electrode according to another embodiment.
  • FIG. 9 is a plan view illustrating a positional relationship among an element region, a trench isolation portion, and a contact electrode according to another embodiment.
  • FIG. 9 is a plan view illustrating a positional relationship among an element region, a trench isolation portion, and a contact electrode according to another embodiment.
  • the semiconductor device of this embodiment has an SOI (Silicon On Insulator) substrate 10 as a semiconductor substrate in which an active layer 13 is laminated on a support substrate 11 via a buried insulating film 12. It is configured using SOI (Silicon On Insulator) substrate 10 as a semiconductor substrate in which an active layer 13 is laminated on a support substrate 11 via a buried insulating film 12. It is configured using SOI (Silicon On Insulator) substrate 10 as a semiconductor substrate in which an active layer 13 is laminated on a support substrate 11 via a buried insulating film 12. It is configured using SOI (Silicon On Insulator) substrate 10 as a semiconductor substrate in which an active layer 13 is laminated on a support substrate 11 via a buried insulating film 12. It is configured using SOI (Silicon On Insulator) substrate 10 as a semiconductor substrate in which an active layer 13 is laminated on a support substrate 11 via a buried insulating film 12. It is configured using SOI (Silicon On Insulator)
  • the support substrate 11 is formed of an N - type silicon substrate or the like. In the present embodiment, the support substrate 11 has an oxygen concentration of 1.27 to 1.69 ⁇ 10 18 atoms / cm 3 .
  • the buried insulating film 12 is formed of an oxide film or the like, and has a thickness of about several ⁇ m in order to maintain insulation between the support substrate 11 and the active layer 13. Active layer 13, in this embodiment, N-type impurities such as phosphorus N by being heat treated are ion-implanted into the P-type semiconductor layer - which is a type.
  • the surface of the active layer 13 of the SOI substrate 10 including the surface on the side opposite to the buried insulating film 12 side is also referred to as the main surface 10a of the SOI substrate 10.
  • the active layer 13 is partitioned into the element region 31, the extraction region 32, and the field region 33 by the trench isolation portion 20.
  • the active layer 13 is partitioned by the trench isolation portion 20 such that the field region 33 is disposed between the element region 31 and the extraction region 32.
  • a plurality of field regions 33 are formed, and are also formed on the side opposite to the element region 31 with the extraction region 32 interposed therebetween.
  • the trench isolation portion 20 is configured by disposing an insulating film 22 in a groove 21 formed from the main surface 10 a of the SOI substrate 10 to reach the buried insulating film 12 so as to fill the groove 21. .
  • the insulating film 22 is disposed in the groove 21 by embedding an insulating material by deposition or the like, as described later.
  • a switching element is formed in the element region 31 using a diffusion region formed by diffusing impurities. Specifically, in the element region 31, a p-type body region 41 having a higher impurity concentration than the active layer 13 is formed in a surface layer portion of the active layer 13. An N + type source region 42 is formed in the surface layer of the body region 41.
  • an N-type drift region 43 is formed in a surface layer portion of the active layer 13 and at a position away from the body region 41.
  • An N + -type drain region 44 having a higher impurity concentration than the drift region 43 is formed in the surface portion of the drift region 43.
  • an STI (Shallow Trench Isolation) isolation unit 50 is formed in the surface layer of the element region 31.
  • the STI isolation unit 50 forms a trench 51 having a predetermined depth in the surface layer of the active layer 13, fills the trench 51 with an insulating film 52, and planarizes the trench 51 by a CMP (Chemical Mechanical Polishing) method or the like. It is formed by doing.
  • the STI separation unit 50 is also formed in the extraction region 32 and the field region 33.
  • an opening 50a is formed in the element region 31 so that the body region 41, the source region 42, the drift region 43, and the drain region 44 are exposed.
  • an opening 50b is formed in the extraction region 32 so that a contact electrode 81 described later is exposed.
  • an opening for exposing a part of the field region 33 is also formed in a cross section different from that in FIG.
  • a gate electrode 62 is arranged via a gate insulating film 61.
  • the gate insulating film 61 is formed over a portion of the STI isolation portion 50 on the body region 41 side and over the body region 41, and the gate electrode 62 is formed on the gate insulating film 61.
  • a silicide layer 71 for reducing contact resistance with the first and second connection vias 131 and 132 is provided in the element region 31 at a portion connected to first and second connection vias 131 and 132 described later. 72 are formed.
  • the silicide layer 71 is formed on the source region 42, and the silicide layer 72 is formed on the drain region 44.
  • Each of the silicide layers 71 and 72 is made of, for example, cobalt silicon (CoSi).
  • an N-channel MOSFET (abbreviation for Metal Oxide Semiconductor Field Effect Transistor) element is thus formed in the element region 31.
  • the MOSFET element formed in the element region 31 in the present embodiment is used by being frequently switched between an ON state in which current flows by switching a voltage applied to the gate electrode 62 and an OFF state in which current does not flow. . Therefore, this MOSFET element may generate noise. That is, in the present embodiment, it can be said that a noise generating element that can generate noise is formed in the element region 31.
  • FIG. 2 is a plan view of the extraction region 32 of FIG. 1, but omits a third wiring portion 143, an interlayer insulating film 120, and a surface insulating film 110, which will be described later.
  • the extraction region 32 in FIG. 1 corresponds to a cross section taken along line II in FIG.
  • the through-hole 82 has a rectangular opening. Also, as shown in FIG. 1, the through hole 82 is formed such that the first minimum interval L1 of the portion exposing the support substrate 11 is the second minimum interval L2 of the portion located in the active layer 13 in the interval between the opposing side surfaces. Has been more extensive.
  • the contact electrode 81 is arranged so as to fill the through hole 82.
  • the minimum width (hereinafter, referred to as a first minimum width) L1 of a portion connected to the support substrate 11 is activated. It is wider than a minimum width (hereinafter, referred to as a second minimum width) L2 of a portion located in the layer 13.
  • the first minimum width L1 is about 2.9 ⁇ m
  • the second minimum width L2 is about 1.2 ⁇ m. Since the contact electrode 81 is arranged so as to fill the through hole 82, the first minimum width L1 is equal to the first minimum interval L1 of the through hole 82, and the second minimum width L2 is It is equal to the second minimum interval L2.
  • the contact electrode 81 is formed by embedding doped polysilicon. For this reason, in the through-hole 82, the minimum width of the portion where the main surface 10a is opened is also made wider than the second minimum interval L2 in order to improve the burying property of the doped polysilicon.
  • the contact electrode 81 is also arranged so as to bury the portion of the through hole 82 on the main surface 10a side. Therefore, it can be said that the contact electrode 81 of the present embodiment has a substantially I-shaped cross section.
  • the contact electrode 81 is made of N-type polysilicon doped with phosphorus or the like so as to match the conductivity type of the support substrate 11. Thereby, ohmic connection between the contact electrode 81 and the support substrate 11 can be achieved.
  • the N-type seepage layer 14 is formed on the support substrate 11 at a portion connected to the contact electrode 81. After the contact electrode 81 is disposed in the through hole 82, the seepage layer 14 is contacted when heat treatment for forming the source region 42, the drain region 44, and the like in the element region 31 is performed. The phosphorus contained in the electrode 81 is formed by seeping out into the support substrate 11. That is, the exudation layer 14 of the present embodiment is formed without performing a special process for forming the exudation layer 14.
  • a silicide layer 83 for reducing contact resistance with the third connection via 133 is formed at a portion connected to a third connection via 133 described later.
  • the silicide layer 83 is made of, for example, cobalt silicon, like the silicide layers 71 and 72 formed in the element region 31.
  • a wiring layer 100 is formed on the main surface 10a of the SOI substrate 10.
  • the surface insulating film 110 is formed on the main surface 10a, and the interlayer insulating film 120 is formed on the surface insulating film 110. Note that the surface insulating film 110 is formed so as to cover the gate insulating film 61 and the gate electrode 62.
  • a first contact hole 121 exposing the silicide layer 71 on the source region 42 and a second contact hole 122 exposing the silicide layer 72 on the drain region 44 are formed in the interlayer insulating film 120 and the surface insulating film 110.
  • a third contact hole 123 exposing the silicide layer 83 on the contact electrode 81 is formed in the interlayer insulating film 120 and the surface insulating film 110.
  • first to third connection vias 131 to 133 which are electrically connected to the silicide layers 71, 72, 83 by being buried with tungsten are arranged. ing.
  • a plurality of third contact holes 123 are formed so as to expose a plurality of portions of the contact electrode 81 as shown in FIGS. Specifically, a plurality of third contact holes 123 are formed along one direction of main surface 10a in two rows. The third connection via 133 is arranged in each third contact hole 123.
  • a fourth contact hole exposing the field region 33 is formed in the interlayer insulating film 120 and the surface insulating film 110.
  • the fourth contact via is arranged in the fourth contact hole by being buried with tungsten.
  • First to third wiring portions 141 to 143 made of aluminum or the like are formed on the interlayer insulating film 120 so as to be connected to the first to third connection vias 131 to 133, respectively.
  • the third wiring portion 143 is formed so as to be connected to each third connection via 133.
  • the third wiring portion 143 is connected to the contact electrode 81 via the third connection via 133, but is formed so as not to be electrically connected to another wiring portion, another region, or the like. Have been. That is, the third wiring portion 143 is a wiring portion connected to only the contact electrode 81, and is an independent wiring. Therefore, the contact electrode 81 is not connected to another region.
  • each of the field regions 33 a cross section different from that of FIG. 1 is electrically connected to a fourth wiring portion formed on the interlayer insulating film 120 via a fourth connection via.
  • the field regions 33 are electrically connected to each other through fourth wiring portions 144 as shown in FIG.
  • noise may be generated from the MOSFET element formed in the element region 31, and the noise may be transmitted to the support substrate 11.
  • the noise transmitted to the support substrate 11 is extracted by the contact electrode 81 as shown by an arrow A in FIG. 3, it is possible to suppress the noise from being transmitted to another region.
  • the contact electrode 81 has the first minimum width L1 wider than the second minimum width L2. Therefore, as compared with the case where the first minimum width L1 of the contact electrode 81 is the same as the second minimum width L2, the contact area between the contact electrode 81 and the support substrate 11 can be increased, and the noise of the support substrate 11 can be increased. Can be easily pulled out.
  • the method for manufacturing the MOSFET element formed in the element region 31 is the same as the conventional method, the method for manufacturing the contact electrode 81 formed in the extraction region 32 will be mainly described below. Further, in the present embodiment, the following steps are performed in a wafer state in which different chip areas are arranged with a scribe area interposed therebetween, and the same step is simultaneously performed on each chip area.
  • a wafer-like SOI substrate 10 having an STI separation portion 50 formed on the surface layer of the active layer 13 is prepared.
  • a hard mask is formed on the main surface 10a by sequentially forming a nitride film 210 and an oxide film 220 by a CVD (Chemical Vapor Deposition) method or the like. Then, the hard mask is patterned so that the regions where the grooves 21 and the through holes 82 are formed are exposed.
  • the groove 21 and the through hole 82 are simultaneously formed by performing dry etching.
  • an insulating film 22 such as an oxide film is buried in the groove 21 and the through hole 82.
  • the insulating film 22 is disposed in the groove 21 to form the trench isolation portion 20.
  • deposition is performed so that the insulating film is buried to the middle of the groove 21 and the through hole 82, and the deposition is performed again after performing the etch back.
  • a film of TEOS (abbreviation of tetraethylorthosilicate) or the like is formed by a CVD method or the like so that the groove 21 and the through hole 82 on the main surface 10a side are closed.
  • the oxide film 220 is removed by a CMP method or the like.
  • a nitride film 230 is formed again by the CVD method or the like.
  • the groove 21 and the through hole 82 are closed by the nitride film 230. That is, in the trench isolation portion 20, the nitride film 230 is disposed on the insulating film 22.
  • a photoresist 240 is disposed on the nitride film 230, and the photoresist 240 is patterned so that a portion of the nitride film 230 that closes the through hole 82 is exposed. Then, using the photoresist 240 as a mask, dry etching is performed so as to increase the width of the portion of the through hole 82 on the opening side. At this time, the insulating film 22 disposed on the opening side of the through hole 82 is also removed.
  • the insulating film 22 formed in the through hole 82 is removed by performing wet etching, and the buried insulating film 12 exposed from the through hole 82 is removed. At this time, the buried insulating film 12 is isotropically removed to perform wet etching. Therefore, in the through hole 82, the first minimum interval L 1 of the portion exposing the support substrate 11 is wider than the second minimum interval L 2 of the portion located in the active layer 13 in the interval between the opposing side surfaces.
  • buffered hydrofluoric acid or the like is used as an etchant.
  • the nitride film 230 is arranged so as to close the opening of the groove 21 in the step of FIG. 4D, the fact that the insulating film 22 of the trench isolation portion 20 is removed is considered. Can be suppressed. That is, as shown in FIG. 5, since the adhesion between the nitride film 210 and the photoresist 240 is low, the photoresist 240 peels off from the nitride film 210 during wet etching, and There is a possibility that a gap may be formed between the gap and the gap 210.
  • the nitride film 230 is not formed, there is a possibility that the etchant may enter from the opening side of the groove 21 through the gap to remove the insulating film 22. Then, if the insulating film 22 is removed, problems such as a decrease in withstand voltage of the trench isolation portion 20 and a decrease in flatness of the wiring layer 100 may occur.
  • the opening of the groove 21 is closed by the nitride film 230. Therefore, even if a gap is formed between the photoresist 240 and the nitride film 230, the removal of the insulating film 22 forming the trench isolation portion 20 can be suppressed.
  • a doped polysilicon film doped with phosphorus or the like is formed by a CVD method or the like so that the through holes 82 are buried, thereby forming the contact electrodes 81.
  • the doped polysilicon formed on the main surface 10a and the nitride films 210 and 230 are removed by a CMP method or the like.
  • the body region 41, the source region 42, the drift region 43, and the drain region 44 are formed by performing a plurality of heat treatments after appropriately implanting impurities into the element region 31.
  • the heat treatment is performed a plurality of times while appropriately setting the temperature.
  • the highest heat treatment temperature is about 1100 ° C.
  • the seepage layer 14 is formed on the support substrate 11. That is, in this embodiment, the seepage layer 14 is formed in the same step as the step of forming the regions 41 to 44 in the element region 31. Therefore, no special process for forming the seepage layer 14 is performed.
  • the support substrate 11 when the heat treatment is performed, the support substrate 11 is fixed in a heating furnace. However, if dislocation as a defect occurs in the support substrate 11, the support substrate 11 may warp. When the support substrate 11 is warped, misalignment of the source region 42 and the drain region 44 formed in the element region 31 occurs, and the characteristics of the semiconductor device change.
  • the supporting substrate 11 has a small number of oxygen atoms that hinder the extension of the generated dislocations, so that the dislocations are easily elongated and easily warped.
  • the oxygen concentration is too high, dislocations are easily generated by the oxygen atoms in the support substrate 11, and the support substrate 11 is easily warped. That is, in order to suppress the warpage of the support substrate 11, it is preferable to appropriately set the oxygen concentration.
  • the present inventors conducted experiments on the oxygen concentration of the support substrate 11 and the amount of misalignment of the source region 42, the drain region 44, and the like in the element region 31, and obtained the results shown in FIG. That is, as shown in FIG. 6, the amount of misalignment is smallest when the oxygen concentration of the support substrate 11 is 1.475 ⁇ 10 18 atoms / cm 3 .
  • the amount of misalignment increases as the oxygen concentration of the support substrate 11 becomes lower than 1.475 ⁇ 10 18 atoms / cm 3 . Further, the amount of misalignment increases as the oxygen concentration of the support substrate 11 becomes higher than 1.475 ⁇ 10 18 atoms / cm 3 .
  • the oxygen concentration of the support substrate 11 is set to 1.27 to 1.69 ⁇ 10 18 atoms / cm 3 .
  • a surface insulating film 110 and an interlayer insulating film 120 are sequentially formed. Then, first to third contact holes 121 to 123 and the like penetrating the interlayer insulating film 120 and the surface insulating film 110 are formed, and tungsten is buried in the first to third contact holes 121 to 123 to perform the first to third connection. Vias 131 to 133 are formed. Subsequently, after a metal layer made of aluminum is formed on the interlayer insulating film 120, the metal layer is patterned to form first to third wiring portions 141 to 143 and the like.
  • the fourth contact hole and the fourth connection via are respectively provided.
  • a fourth wiring portion are also formed.
  • the above steps are performed in a wafer state. Therefore, in the steps of forming the first to third contact holes 121 to 123, the first to third connection vias 131 to 133, and the first to third wiring portions 141 to 143, the fifth contacts for exposing the scribe regions are respectively provided.
  • a hole, a fifth connection via disposed in the fifth contact hole, and a fifth wiring portion electrically connected to the fifth connection via are also formed.
  • a fifth contact hole exposing the scribe region, a fifth connection via disposed in the fifth contact hole, and a fifth wiring portion electrically connected to the fifth connection via will be described later.
  • the abnormality of the trench isolation section 20 is determined.
  • the above steps are performed in a wafer state.
  • a first chip area 310 and a second chip area 320 are arranged with a scribe area 300 interposed therebetween. This will be described by taking an example of the case. That is, hereinafter, an example in which the abnormality determination of the trench isolation portion 20 in the first chip region 310 and the second chip region 320 is performed in a wafer state will be described.
  • the abnormality determination of the trench isolation unit 20 is performed by connecting the inspection device 400 to each of the wiring units 141 to 145, This is performed by determining whether or not a current flows during the period.
  • FIGS. 7 and FIG. 8, which will be described later, are schematic diagrams showing a connection state between the inspection apparatus 400 and each of the regions 31 to 33, and the first to fifth wiring portions 141 to 145 in the wiring layer 100 are indicated by dotted lines. It is shown in a simplified manner.
  • the fourth wiring section 144 in FIGS. 7 and 8 is a wiring section connected to each field region 33.
  • the fifth wiring portion 145 in FIGS. 7 and 8 is a wiring connected to the scribe region 300 via a fifth connection via disposed in a fifth contact hole formed in the interlayer insulating film 120 and the surface insulating film 110. Department.
  • the inspection device 400 has a first inspection unit 410 and a second inspection unit 420, the first inspection unit 410 is connected to the first chip area 310, and the second inspection unit 420 is connected to the second chip Connected to region 320.
  • the first inspection unit 410 is connected to the fourth wiring unit 144 in which the power supply 411 is connected to the field region 33.
  • the first inspection section 410 is connected to the first and second wiring sections 141 and 142 where the ground 412 is connected to the element area 31 and is connected to the fifth wiring section 145 which is connected to the scribe area 300. You. Then, the first inspection section 410 is connected to only the third wiring section 143 where the ground 413 is connected to the contact electrode 81. That is, in the present embodiment, the contact electrodes 81 of the first chip region 310 are independently connected to the ground 413 of the first inspection unit 410.
  • the second inspection unit 420 is connected to the fourth wiring unit 144 where the power supply 421 is connected to the field region 33. Further, the second inspection section 420 is connected to the first and second wiring sections 141 and 142 where the ground 422 is connected to the element area 31 and is connected to the fifth wiring section 145 which is connected to the scribe area 300. You. Then, the second inspection section 420 is connected only to the third wiring section 143 where the ground 423 is connected to the contact electrode 81. That is, in the present embodiment, the contact electrodes 81 of the second chip region 320 are independently connected to the ground 413 of the second inspection section 420.
  • the inspection device 400 determines whether a current flows in the first chip region 310 and the second chip region 320 in order, and thereby determines whether the trench isolation portion 20 and the second chip region The abnormality determination of the trench isolation part 20 of 320 is performed.
  • the contact electrode 81 is independent of the field region 33 without being connected thereto, but a problem that may occur when the contact electrode 81 is connected to the field region 33 will be described.
  • the contact electrode 81 when the contact electrode 81 is connected to the field region 33, for example, in the first chip region 310, the contact electrode 81 is also connected to the power supply 411. In this case, since the contact electrodes 81 of the chip regions 310 and 320 are connected to the support substrate 11, they are electrically connected via the support substrate 11. For example, in the second chip region 320, it is assumed that the abnormality D2 has occurred in the trench isolation portion 20 that divides the scribe region 300 and the field region 33.
  • the first inspection unit 410 erroneously determines that an abnormality has occurred in the trench isolation unit 20 in the first chip region 310 even though there is no abnormality in the trench isolation unit 20 in the first chip region 310. I will.
  • the contact electrode 81 is not connected to the field region 33.
  • an abnormality D1 has occurred in the trench isolation portion 20 that divides the scribe region 300 and the field region 33 in the second chip region 320, as follows. Become. That is, when the abnormality determination of the first chip region 310 is performed, no current flows through the first inspection unit 410 because the contact electrodes 81 are independent. Then, when performing an abnormality determination of the second chip area 320, a current flows through the second inspection unit 420 as indicated by an arrow B1 in FIG.
  • the abnormality determination of the trench isolation portion 20 is performed as described above. Therefore, it is possible to suppress erroneous determination when performing an abnormality determination of the trench isolation portion 20 of each of the chip regions 310 and 320. Thereafter, the semiconductor device including the region shown in FIG. 1 is manufactured by dividing the semiconductor device into chip units along the scribe region 300.
  • the first minimum width L1 of the portion connected to the support substrate 11 is wider than the second minimum width L2 of the portion located in the active layer 13. . Therefore, as compared with the case where the first minimum width L1 of the contact electrode 81 is the same as the second minimum width L2, the contact area between the contact electrode 81 and the support substrate 11 can be increased, and the noise of the support substrate 11 can be increased. Can be easily pulled out.
  • the seepage layer 14 is formed on the support substrate 11 at a portion in contact with the contact electrode 81. Therefore, the contact resistance between the contact electrode 81 and the support substrate 11 can be reduced, and noise can be easily extracted from the support substrate 11.
  • the contact electrode 81 is independently connected to the inspection device 400. Therefore, when performing an abnormality determination of the trench isolation portion 20 in each of the chip regions 310 and 320 in a wafer state, it is possible to suppress erroneous determination.
  • the active layer 13 is divided into the first element region 31 a, the second element region 31 b, the extraction region 32, and the field region 33 by the trench isolation part 20.
  • a MOSFET element having the body region 41, the source region 42, the drift region 43, and the drain region 44 described in the first embodiment is formed.
  • an N-channel MOSFET device is formed in the second device region 31b.
  • a P-type well layer 151 is formed in a surface layer portion of the active layer 13.
  • An N-type source region 152 and a drain region 153 are separately formed in the surface layer of the well layer 151.
  • gate electrode 155 is arranged at a portion between source region 152 and drain region 153 via gate insulating film 154.
  • a silicide layer 157 is formed on the source region 152, and a silicide layer 158 is formed on the drain region 153.
  • the silicide layers 157 and 158 are made of, for example, cobalt silicon (CoSi), like the silicide layers 71 and 72.
  • a sixth contact hole 126 exposing the silicide layer 157 on the source region 152 and a seventh contact hole 127 exposing the silicide layer 158 on the drain region 153 are formed in the interlayer insulating film 120 and the surface insulating film 110. . Then, in the sixth and seventh contact holes 126 and 127, sixth and seventh connection vias 136 and 137 which are electrically connected to the respective silicide layers 157 and 158 by being buried with tungsten are arranged. . Further, on the interlayer insulating film 120, sixth and seventh wiring portions 146 and 147 connected to the sixth and seventh connection vias 136 and 137 are formed.
  • the switching control interval of the MOSFET element formed in the second element region 31b is longer than that of the MOSFET element formed in the first element region 31a. Used as a part. For this reason, this MOSFET element hardly generates noise, and high-precision control is desired. That is, in the present embodiment, it can be said that a high-precision element for which high-precision control is desired is formed in the second element region 31b.
  • one field region 33 and one extraction region 32 are formed so as to surround the first element region 31a.
  • a contact electrode 81 is arranged so as to surround the element region 31. Note that the configuration of the contact electrode 81 is the same as the configuration of the contact electrode 81 described in the first embodiment.
  • FIG. 10 is a plan view, the contact electrodes 81 are hatched for easy understanding.
  • the contact electrode 81 is formed so as to surround the first element region 31a. That is, the contact electrode 81 is formed so as to surround the noise generating element. Therefore, even if the noise generated in the first element region 31a is transmitted to the support substrate 11, the noise can be easily extracted from the contact electrode 81 before the noise is transmitted from the support substrate 11 to the second element region 31b. . Therefore, propagation of noise to the second element region 31b can be suppressed. That is, propagation of noise to the high-precision element can be suppressed.
  • a third embodiment will be described. This embodiment is different from the second embodiment in that the contact electrodes 81 are doubly provided. The rest is the same as in the first embodiment, and a description thereof will not be repeated.
  • the first extraction region 32a and the second extraction region 32b are defined by the trench isolation portion 20 so as to surround the first element region 31a.
  • a first contact electrode 81a and a second contact electrode 81b are formed so as to surround the first element region 31a, respectively.
  • the first contact electrode 81a and the second contact electrode 81b are formed in the order of the first contact electrode 81a and the second contact electrode 81b from the element region 31 side.
  • the configurations of the first contact electrode 81a and the second contact electrode 81b are the same as those of the contact electrode 81 described in the first embodiment.
  • FIG. 11 is a plan view, the first contact electrode 81a and the second contact electrode 81b are hatched for easy understanding.
  • the noise generated in the first element region 31a generates the second contact electrode 81a and the second contact electrode 81b. Propagation to the element region 31b can be further suppressed.
  • the resistance value of the first contact electrode 81a and R SC1 the resistance value of the second contact electrode 81b and R SC2.
  • the resistance value of the first resistor R1 between the portion of the support substrate 11 facing the first element region 31a and the portion of the support substrate 11 facing the first contact electrode 81a is R SUB1
  • the first contact electrode of the support substrate 11 is
  • the resistance value of the second resistor R2 between the portion facing the second contact electrode 81b and the portion facing the second contact electrode 81b is R SUB2
  • the resistance value of the third resistor R3 between the portion of the support substrate 11 facing the second contact electrode 81b and the portion facing the second element region 31b is defined as R SUB3 .
  • the resistance value of the noise path until the noise transmitted from the first element region 31a of the support substrate 11 reaches the first contact electrode 81a is R SUB1 .
  • the resistance value of the noise path from the portion of the support substrate 11 facing the first contact electrode 81a to the second contact electrode 81b is R SUB2 .
  • the resistance value of the noise path from the portion of the support substrate 11 facing the second contact electrode 81b to the second element region 31b is R SUB3 .
  • the impedance in the embedded insulating film 12 and Z C is connected to the ground via a fourth resistor R4 having a resistance value of R LOAD .
  • the contact electrode 81 is made of doped polysilicon, it can be assumed that R SC1 , R SC2 ⁇ R SUB1 , R SUB2 , and R SUB3 . Further, since the buried insulating film 12 is formed thick, it can be assumed that Z C ⁇ R SUB1 , R SUB2 and R SUB3 .
  • V OUT is shown as follows. Then, when the above equations 1 to 3 are put together, V OUT is expressed as follows.
  • the resistance value of the second resistor R2 is R SUB2a when the distance between the first contact electrode 81a and the second contact electrode 81b is widened, V OUT1 is expressed as follows.
  • the resistance value of the support substrate 11 when the distance between the first contact electrode 81a and the second contact electrode 81b is increased is R SUB2a , so that R SUB2 ⁇ R SUB2a . Therefore, it is confirmed that when the distance between the first contact electrode 81a and the second contact electrode 81b is increased, the value of the second term in Expression 5 becomes smaller, so that V OUT1 becomes smaller than V OUT . That is, it is confirmed that when the distance between the first contact electrode 81a and the second contact electrode 81b is increased, noise transmitted to the second element region 31b can be reduced.
  • the overall size of the second contact electrode 81b is increased. That is, when viewed from the normal direction to the main surface 10a, the contact area between the second contact electrode 81b and the support substrate 11 increases as the distance between the first contact electrode 81a and the second contact electrode 81b increases. For this reason, the physique of the semiconductor device tends to increase.
  • the resistivity of the support substrate 11 is 40 ⁇ ⁇ cm, as shown in FIG. 13, when the distance between the first contact electrode 81a and the second contact electrode 81b is 300 ⁇ m or more, the area efficiency decreases. It is confirmed to start. For this reason, when the resistivity of the support substrate 11 is 40 ⁇ ⁇ cm, it is preferable that the distance between the first contact electrode 81a and the second contact electrode 81b is about 300 ⁇ m.
  • the distance between the first contact electrode 81a and the second contact electrode 81b is set based on the resistance value of the support substrate 11 so as to be near the area efficiency becomes maximum.
  • a P-channel type MOSFET device may be formed in the device region 31.
  • a P-channel MOSFET device may be formed in the first device region 31a, or a P-channel MOSFET device may be formed in the second device region 31b. .
  • the abnormality determination of the trench isolation portion 20 described in the first embodiment is also applicable to a case where the width of the contact electrode 81 is fixed. Further, the abnormality determination of the trench isolation section 20 is performed by using the inspection apparatus 400 having only the first inspection section 410 and sequentially connecting the inspection apparatuses 400 for each chip region to determine the abnormality of each trench isolation section 20. Is also good. In addition, the abnormality determination of the trench isolation unit 20 is performed by using the inspection apparatus 400 having a plurality of inspection units, connecting each inspection unit to each chip region, and then sequentially determining the abnormality of the trench isolation unit 20 in each chip region. You may do so.
  • the contact electrode 81 may not be formed to completely surround the element region 31.
  • the contact electrode 81 is partially separated and does not have to be completely surrounded. That is, the contact electrode 81 may be formed so as to surround the element region 31.
  • trench isolation portion 20 may be formed so as to surround each contact electrode 81. That is, the trench isolation portion 20 may be formed so that one trench isolation portion 20 surrounds one contact electrode 81. Further, as shown in FIG. 15B, trench isolation portion 20 may be formed such that one trench isolation portion 20 surrounds two contact electrodes 81. Further, although not particularly shown, the trench isolation portion 20 may be formed so that one trench isolation portion 20 surrounds three or more contact electrodes 81.
  • the field region 33 is not divided by the trench isolation portion 20. That is, the field regions 33 are connected to each other. For this reason, for example, when performing an abnormality determination of the trench isolation section 20, it is not necessary to arrange wirings and the like in the respective field regions 33, thereby simplifying layout work, inspection design, and inspection process. Can be achieved.
  • the contact electrode 81 when the switching elements serving as noise generating elements are arranged adjacent to each other, the contact electrode 81 is formed so as to collectively surround the element region 31 where each switching element is formed. May be.
  • the contact electrode 81 when two switch elements serving as noise generating elements are formed in the adjacent first element region 31a, the contact electrode 81 may be formed so as to surround the two first element regions 31a.
  • the first contact electrode 81a and the second contact electrode 81b may be formed so as to surround the two first element regions 31a.
  • the contact electrode 81 may be formed so as to surround the second element region 31b. Even with such a configuration, it is difficult for the noise generated in the first element region 31a to propagate to the second element region 31b, so that the same effect as in the second embodiment can be obtained. That is, if it is difficult for the noise generated from the noise generating element to propagate to the high-precision element, the contact electrode 81 may surround either the first element region 31a or the second element region 31b. Further, two contact electrodes 81 may be formed, one of which is formed to surround the first element region 31a, and the other is formed to surround the second element region 31b.
  • the distance between the first contact electrode 81a and the second contact electrode 81b is preferably set to be about 300 ⁇ m, the distance between the first contact electrode 81a and the second contact electrode 81b is different. May be formed. Note that when another element is formed in a region between the first contact electrode 81a and the second contact electrode 81b, it is preferable to form an element that is less affected by noise, for example, an element that performs digital processing. Are preferably formed.
  • the seepage layer 14 may be formed by a heat treatment different from the heat treatment for forming the source region 42 and the drain region 44 in the element region 31.
  • only one third contact hole 123 may be formed, and the third wiring portion 143 may be connected to one third connection via 133.
  • the contact electrode 81 may be made of P-type polysilicon doped with boron or the like. In this case, it is preferable that the support substrate 11 be P-type.
  • a substrate divided in units of chips may be prepared in advance.

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  • Chemical & Material Sciences (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Element Separation (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
PCT/JP2019/025670 2018-07-02 2019-06-27 半導体装置およびその製造方法 Ceased WO2020009003A1 (ja)

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JP2004207271A (ja) * 2002-12-20 2004-07-22 Nec Electronics Corp Ｓｏｉ基板及び半導体集積回路装置
JP2004363182A (ja) * 2003-06-02 2004-12-24 Sumitomo Mitsubishi Silicon Corp 貼り合わせ誘電体分離ウェーハおよびその製造方法
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