WO2020001271A1 - 低压差线性稳压器及其稳压方法 - Google Patents

低压差线性稳压器及其稳压方法 Download PDF

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Publication number
WO2020001271A1
WO2020001271A1 PCT/CN2019/090849 CN2019090849W WO2020001271A1 WO 2020001271 A1 WO2020001271 A1 WO 2020001271A1 CN 2019090849 W CN2019090849 W CN 2019090849W WO 2020001271 A1 WO2020001271 A1 WO 2020001271A1
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Prior art keywords
voltage
control signal
transistor
current
low
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PCT/CN2019/090849
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English (en)
French (fr)
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金宁
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北京集创北方科技股份有限公司
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Priority to KR1020197039010A priority Critical patent/KR102253323B1/ko
Priority to US16/628,011 priority patent/US11061422B2/en
Publication of WO2020001271A1 publication Critical patent/WO2020001271A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/59—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

Definitions

  • the invention relates to the technical field of electronic circuits, and in particular, to a low-dropout linear voltage regulator and a voltage stabilization method thereof.
  • Low dropout linear regulator (Low Dropout Regulator, LDO) is a circuit widely used in power systems to provide a stable output voltage Vout.
  • the output voltage Vout Vdd-Vdrop, where Vdd represents the power supply voltage, and Vdrop represents the voltage difference between the power supply voltage and the output voltage.
  • the LDO During the startup of the LDO, the LDO generates a charging current according to the reference voltage so that the output voltage Vout changes from 0V to the target voltage value.
  • the output current of the LDO needs to be limited to a certain range; when the output voltage Vout of the LDO is close to the target voltage value, if the output current cannot If the value of the charging current drops rapidly to the value of the load current, the output voltage of the LDO will overshoot. If the overshoot voltage amplitude caused by the overshoot phenomenon is too large, the subsequent load circuits connected to the LDO are likely to experience functional failure, overheating damage, and other phenomena. Therefore, how to ensure that the output voltage of the LDO can smoothly reach the target voltage value during the startup process to avoid or slow down the overshoot of the output voltage is a topic worthy of research.
  • FIG. 1 is a schematic circuit diagram of a conventional low-dropout linear regulator.
  • the conventional low-dropout linear regulator 1000 includes a differential amplifier OP0, a buffer unit 1100, a driving tube Pbuf0, a voltage feedback unit 1200, and a load capacitor Cload and a load resistor Rload.
  • the power supply terminal and the ground terminal of the differential amplifier OP0 receive the power supply voltage Vdd and the reference ground voltage Vgnd, respectively.
  • the differential amplifier OP0 generates a control signal V01 according to the difference between the reference voltage Vref0 and the feedback voltage Vfb0.
  • the buffer unit 1100 includes an N-channel. Type transistor N0 and P-channel type transistor P0. The transistors N0 and P0 are connected to the node A0.
  • the degree of conduction of the transistor N0 is controlled by the voltage value of the control signal V01, that is, the degree to which the voltage V02 of the node A0 is pulled down is controlled.
  • the control terminal of the transistor P0 is connected to the node A0; the control terminal of the driving tube Pbuf0 and the control terminal of the transistor P0 are connected to the node A0 to receive the voltage V02, so that the driving tube Pbuf0 can generate an output current Iout according to the voltage V02; output The current Iout acts on the load capacitor Cload to generate an output voltage Vout.
  • the voltage feedback unit 1200 samples the output voltage Vout by using the voltage dividing resistors R01 and R02 to obtain a feedback voltage Vfb0 for characterizing the output voltage.
  • the conventional low-dropout linear regulator 1000 implements the startup process and the voltage stabilization process of the output voltage Vout through a voltage feedback loop.
  • the control signal V01 turns on the transistor N0, thereby reducing the voltage V02 of the node A0, so that The driving tube Pbuf0 generates a larger output current Iout to continue to charge the load capacitor Cload, so as to achieve the purpose of increasing the output voltage Vout until the output voltage Vout reaches the target voltage value corresponding to the reference voltage Vref0.
  • FIG. 2 is a waveform diagram of the reference voltage Vref0 and the output voltage Vout of the low-dropout linear regulator in FIG. 1 during startup.
  • the reference voltage Vref0 instantly rises from the initial low-level voltage (for example, 0V) to the target value vref0_tg, so that the reference voltage Vref0 is much higher than the feedback voltage Vfb0, so the input
  • the difference between the reference voltage Vref0 and the feedback voltage Vfb0 to the differential amplifier OP0 is very large, which causes the control voltage V01 to approach the maximum value of the output voltage swing range of the differential amplifier OP1, and the voltage V02 of the node A0 is pulled down to a very low voltage. Level, so that the drive tube Pbuf0 is almost completely turned on.
  • the current value Ich (charging current value) of the output current Iout will be much higher than the output current Iout provided by the low-dropout linear regulator 1000 during the voltage stabilization process.
  • Current value Ist load current value
  • the traditional low-dropout linear regulator 1000 has the following disadvantages: During the startup process, because the reference voltage Vref0 will instantly rise to the target value vref0_tg, the output current Iout will instantly reach a very high current value Ich, which will shorten The lifetime of the drive tube Pbuf0 requires a certain width of the conductor traces in the layout, which results in an increase in layout area and difficulty in layout and routing; at the same time, during the startup process, when the output voltage Vout approaches the target When the voltage value is vout_tg, the low-dropout linear regulator needs to restore the output current Iout from a very high current value Ich to a lower current value Ist.
  • FIG. 3 is a waveform diagram of a reference voltage and an output voltage in such a conventional low-dropout linear regulator.
  • the reference voltage Vref0 will not directly increase from the low-level voltage to the target value vref0_tg, but gradually increase from the low-level voltage to the target value vref0_tg to prevent the start-up process.
  • the output current Iout is too high.
  • the output current Iout is limited, when the output voltage Vout approaches the target voltage value vout_tg, the time required for the output current Iout to recover to the load current value is shorter, so this existing technology can slow down the output voltage to a certain extent Vout overshoot.
  • the low-dropout linear regulator provided by the foregoing prior art still has an overshoot phenomenon of the output voltage.
  • a new low-dropout linear regulator is expected, which can limit the size of the output current during startup and effectively prevent the output voltage from overshooting, so that the output voltage can rise smoothly and steadily to Target voltage value.
  • the present invention implements automatic switching between the current feedback loop and the voltage feedback loop by setting a switching circuit, and limits the reference voltage with different voltage values at different stages in the startup process to limit
  • the magnitude of the output current prevents the output current from increasing instantaneously, and effectively prevents the output voltage from overshooting, so that the output voltage can rise smoothly and steadily to the target voltage value during the startup process.
  • a low-dropout linear voltage regulator comprising: a driving circuit that generates a first control signal according to a reference voltage and a feedback voltage, and generates an output current according to the first control signal
  • a load capacitor provides an output voltage according to the output current
  • a voltage feedback circuit obtains the feedback voltage according to the output voltage
  • a current feedback circuit generates a second control signal according to the output current
  • a switching circuit for The second control signal provides the reference voltage
  • a startup process of the low-dropout linear regulator includes a first stage and a second stage, and in the first stage, a voltage value of the reference voltage is less than or equal to Initial value
  • the current feedback circuit adjusts the first control signal to limit the output current according to the second control signal
  • the switching circuit adjusts the output current according to the second control signal.
  • the voltage value of the reference voltage is switched to a target value, and the initial value is smaller than the target value.
  • the output current increases as the voltage of the first control signal increases.
  • the current feedback circuit includes a first transistor, the first transistor is configured to provide a first current path between the first control signal and a reference ground, and a control terminal of the first transistor receives the first Two control signals.
  • the degree of conduction of the first transistor is controlled by the second control signal to adjust the first control signal.
  • the first transistor Turned off by the second control signal.
  • the first transistor includes a P-channel transistor.
  • the current feedback circuit further includes a current source, and when the voltage value of the feedback voltage rises to the initial value, the current source provides a charging current to the control terminal of the first transistor to charge the first The second control signal is raised to a high state.
  • the switching circuit includes a first switch and a second switch, and a first terminal of the first switch and a second terminal of the second switch receive a first reference voltage and a second reference voltage, respectively, and the The second terminal of the first switch is connected to the second terminal of the second switch to provide the reference voltage, and the voltage value of the first reference voltage and the voltage value of the second reference voltage are respectively equal to the initial value.
  • the target value and a logic circuit that controls on and off of the first switch and the second switch according to the second control signal, and when the second control signal is in a low-level state, The first switch is turned on and the second switch is turned off. When the second control signal is in a high-level state, the second switch is turned on and the first switch is turned off.
  • the logic circuit includes: a latch configured to generate a switch control signal according to a level state of the enable signal and the second control signal, and when the enable signal is valid, the first switch and One of the second switches is turned on under the control of the switch control signal.
  • the low-dropout linear voltage regulator further includes a reset circuit
  • the reset circuit includes: a holding capacitor, a first terminal of which is connected to the reference ground, and a second terminal of which is connected to the control terminal of the first transistor; And a reset transistor, when the enable signal is invalid, the reset transistor is turned on to short the first terminal and the second terminal of the holding capacitor.
  • the current feedback circuit further includes: a second transistor for sampling the output current to obtain a sampling current; and a third transistor for providing a second between the second control signal and a reference ground In a current path, the control terminal of the third transistor generates a sampling voltage according to the sampling current so that the conduction degree of the third transistor is controlled by the sampling voltage.
  • the second transistor includes a P-channel type transistor
  • the third transistor includes an N-channel type transistor.
  • the driving circuit includes: a differential amplifier that generates the first control signal according to a difference between the reference voltage and the feedback voltage; a buffer unit including at least a fourth transistor and a fifth transistor; The gate of the fifth transistor receives a third control signal, the fourth transistor is used to provide a third current path between the third control signal and the reference ground, and the degree of conduction of the fourth transistor is controlled The first control signal to adjust the third control signal; and a driving transistor for generating the output current according to the third control signal.
  • the fourth transistor includes an N-channel type transistor
  • the fifth transistor includes a P-channel type transistor.
  • the voltage feedback circuit includes a plurality of sampling resistors connected in series, and the plurality of sampling resistors are used to divide the output voltage to obtain the feedback voltage.
  • a method for stabilizing a low-dropout linear regulator comprises: generating a first control signal according to a reference voltage and a feedback voltage; and generating an output according to the first control signal.
  • the current feedback loop is turned on, and the set The voltage value of the reference voltage is less than or equal to the initial value, and the first control signal is adjusted to limit the output current according to the second control signal.
  • the current feedback loop is gradually closed, according to The second control signal switches a voltage value of the reference voltage to a target value, and the initial value is smaller than the target value.
  • the output current is set to increase as the voltage of the first control signal increases.
  • the step of adjusting the first control signal to limit the output current according to the second control signal includes: in the first stage, providing a first current between the first control signal and a reference ground Path, and controlling the degree of conduction of the first current path to adjust the voltage of the first control signal according to the second control signal; in the second phase, turning off the first control signal according to the second control signal First current path.
  • the step of switching the voltage value of the reference voltage to a target value according to the second control signal includes: when the voltage value of the feedback voltage rises to the initial value, providing a charging current to change the Raising the second control signal to a high-level state; when the second control signal is in a low-level state, setting the reference voltage equal to the initial value, and when the second control signal is in a high-level state When setting the reference voltage equal to the target value.
  • the voltage stabilization method further includes: providing an enable signal; and resetting the second control signal to a low-level state when the enable signal is invalid.
  • the step of generating a second control signal according to the output current includes: sampling the output current to obtain a sampling current, and obtaining a sampling voltage according to the sampling current; providing the second control signal between a reference ground A second current path of which is controlled by the sampling voltage.
  • the step of obtaining the feedback voltage according to the output voltage includes: dividing the output voltage to obtain the feedback voltage for characterizing the output voltage.
  • the low-dropout linear regulator and the voltage stabilization method of the embodiments of the present invention limit the output current by first providing a reference voltage less than or equal to the initial value during the startup process, and making the low-dropout linear regulator work in a current feedback mode. To prevent the output current from being too high and affecting the subsequent stage load circuit; at the same time, during the startup process, when the output voltage reaches a preset voltage value that is slightly lower than the target voltage value, the low dropout linear voltage regulation of the embodiments of the present invention
  • the voltage regulator and the voltage stabilization method can be automatically switched from the current feedback mode to the voltage feedback mode. Because the preset voltage value is close to the target voltage value, the low-dropout linear regulator is generated during the switching process from the current feedback mode to the voltage feedback mode.
  • the output current is limited, and the output voltage can be gradually increased from the preset voltage value to the target voltage value, which effectively controls the overshoot amplitude of the output voltage during the startup process and avoids the overshoot of the output circuit by the output voltage. influences.
  • FIG. 1 is a schematic circuit diagram of a conventional low-dropout linear regulator.
  • FIG. 2 is a waveform diagram of the reference voltage Vref0 and the output voltage Vout of the low-dropout linear regulator in FIG. 1 during startup.
  • FIG. 3 is a waveform diagram of a reference voltage and an output voltage in such a conventional low-dropout linear regulator.
  • FIG. 4 is a circuit diagram of a low-dropout linear regulator according to a first embodiment of the present invention.
  • FIG. 5 is a waveform diagram of the reference voltage and the output voltage in the low-dropout linear regulator shown in FIG. 4 during the startup process.
  • FIG. 6 shows a specific circuit diagram of a driving circuit, a current feedback circuit, and a voltage feedback circuit in the low-dropout linear regulator shown in FIG. 4.
  • FIG. 7 illustrates a specific circuit diagram of a switching circuit and a reset circuit in the low-dropout linear regulator shown in FIG. 4.
  • FIG. 8 is a schematic flowchart of a voltage stabilization method of a low-dropout linear regulator according to a second embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a low-dropout linear regulator according to a first embodiment of the present invention.
  • the low-dropout linear regulator 2000 of the first embodiment of the present invention includes a driving circuit 2100, a voltage feedback circuit 2200, a current feedback circuit 2300, a switching circuit 2400, and a reset circuit 2500.
  • the driving circuit 2100 generates a first control signal VC1 according to a difference between the reference voltage Vref and the feedback voltage Vfb, and generates an output current Iout according to the first control signal VC1.
  • a load capacitor Cload connected to the driving circuit 2100 receives the output current Iout, thereby generating an output voltage Vout according to the output current Iout, and the output voltage Vout acts on the load resistance Rload (for example, the equivalent resistance of a subsequent-stage load circuit).
  • the voltage feedback circuit 2200 is configured to obtain a feedback voltage Vfb according to the output voltage Vout, and provide the feedback voltage Vfb to the driving circuit 2100 to form a voltage feedback loop with the driving circuit 2100.
  • the current feedback circuit 2300 includes a transistor P1 and a current feedback control module 2310.
  • the current feedback control module 2310 is configured to generate a second control signal VC2 according to the output current Iout.
  • the control terminal of the transistor P1 is controlled by the second control signal VC2.
  • the first and second terminals of the transistor P1 are respectively connected to the driving circuit 2100 and the reference.
  • the ground gnd (the reference ground voltage Vgnd) is connected, so the transistor P1 can provide a current path from the first control signal VC1 to the reference ground gnd. Since the conduction degree of the transistor P1 is controlled by the second control signal VC2, the first control signal VC1 can be adjusted, so that the current feedback circuit 2300 and the driving circuit 2100 form a current feedback loop.
  • the switching circuit 2400 is configured to provide a reference voltage Vref according to the second control signal VC2. According to the level state of the second control signal VO2, the reference voltage Vref provided by the switching circuit 2400 has different voltage values.
  • the low-dropout linear regulator 2000 further includes a reset circuit 2500.
  • the reset circuit 2500 is controlled by an enable signal EN.
  • the enable signal EN is invalidated, and the reset circuit 2500 resets the second control signal VC2, so that the transistor P1 in the current feedback circuit 2300 is turned on, thereby further resetting the first control signal VC1.
  • the enable signal EN changes from inactive to effective, and the current feedback circuit 2300 adjusts the second control signal VC2 according to the output current Iout, so that the driving circuit 2100 is mainly in the first stage of the startup process Working in a current feedback loop; further preferably, the switching circuit 2400 is also controlled by the enable signal EN, and the switching circuit 2400 selects the voltage value of the reference voltage Vref according to the level state of the enable signal EN and the second control signal VC2.
  • FIG. 5 is a waveform diagram of the reference voltage and the output voltage in the low-dropout linear regulator shown in FIG. 4 during the startup process.
  • the working process of the low-dropout linear regulator 2000 includes a startup process (from the power-up / enable signal EN changes from inactive to valid until the output voltage Vout reaches the target voltage value vout_tg) and a stabilization process (The output voltage Vout maintains the target voltage value vout_tg).
  • the startup process includes a first stage Ts1 and a second stage Ts2:
  • the driving circuit 2100 mainly works in a current feedback loop, that is, the current feedback circuit 2300 adjusts the first control according to the second control signal VC2
  • the signal VC1 limits the amplitude of the output current Iout (the output current Iout is constant or approximately constant), so that the output voltage Vout is smoothly increased to avoid a large amplitude overshoot of the output voltage Vout.
  • the switching circuit 2400 provides The voltage value of the reference voltage Vref is equal to the initial value va1.
  • the output voltage Vout will eventually stabilize at a preset voltage value vout1 corresponding to the initial value va1 of the reference voltage.
  • the current feedback The second control signal VC2 provided by the circuit 2300 gradually changes from the first level state to the second level state, so that the transistor P1 is gradually turned off, and the switching circuit 2400 changes the voltage value of the reference voltage Vref under the action of the second control signal VC2. Switch to the target value va2, so that the driving circuit 2100 mainly works in the voltage feedback loop, that is, the driving circuit 2100 mainly works according to the voltage feedback voltage.
  • the output current Iout is limited, so the load capacitor Cout is approximately charged by constant current, so the amplitude of the overshoot voltage v_overshoot generated by the output voltage Vout due to the overshoot phenomenon is small; in the second stage In Ts2, by setting the difference between the initial value va1 and the target value va2 of the reference voltage Vref to be slightly greater than or equal to the amplitude of the overshoot voltage v_overshoot, the driving capability of the first control signal VC1 can be made weak, so the output voltage Vout The output voltage Vout can be gradually increased from the preset voltage value vout1 to the target voltage value vout_tg, thereby avoiding an overshoot phenomenon of the output voltage Vout in the second stage.
  • FIG. 6 shows a specific circuit diagram of a driving circuit, a current feedback circuit, and a voltage feedback circuit in the low-dropout linear regulator shown in FIG. 4.
  • the driving circuit (such as the driving circuit 2100 shown in FIG. 4) includes a differential amplifier OP1, a buffer unit, and a driving transistor Pbuf, where the buffer unit includes a transistor N1 and a transistor P2.
  • the differential amplifier OP1 generates a first control signal VC1 according to the difference between the reference voltage Vref and the feedback voltage Vfb.
  • the reference ground gnd is connected, the control terminal of the transistor P2 is controlled by the voltage VC3 (third control signal) of the node A1, and the second terminal of the transistor P2 is connected with the power supply voltage Vdd; the control terminal of the driving transistor Pbuf is also controlled by the node A1
  • the voltage VC3, the first terminal of the driving transistor Pbuf is connected to the power supply voltage Vdd, and the second terminal provides the output current Iout to the first terminal of the load capacitor Cload, so that the output voltage Vout is generated at the first terminal of the load capacitor Cload.
  • the second termination is the reference ground gnd.
  • the voltage feedback circuit 2200 includes a plurality of sampling resistors, thereby obtaining a feedback voltage Vfb capable of characterizing the output voltage Vout by dividing the output voltage Vout.
  • the voltage feedback circuit 2200 includes a sampling resistor R1 and R2 connected in series between the output voltage Vout and a reference ground gnd. A node connected between the sampling resistor R1 and R2 is connected to one of the input terminals of the differential amplifier OP1 in the driving circuit 2100. To provide a feedback voltage Vfb.
  • the current feedback circuit 2300 includes a transistor P1 and a current feedback control module.
  • the current feedback control module includes transistors N2 and P3, a current drain Ib2, and a current source Ib1.
  • the control terminal and the first terminal of the transistor P3 are connected to the control terminal and the first terminal of the driving transistor Pbuf, respectively, so that the ratio of the on-state current of the transistor P3 to the output current Iout provided by the driving transistor Pbuf is the same as that of the transistor P3 and the driving transistor Pbuf.
  • the size ratio is positively related, so that the transistor P3 realizes the sampling of the output current Iout.
  • the current drain Ib2 is connected between the second terminal of the transistor P3 and the reference ground gnd.
  • the second terminal of the transistor P3 provides the sampling voltage Vsamp.
  • the control terminal receives the sampling voltage Vsamp, the first terminal is connected to the reference ground gnd, and the second terminal is connected to the control terminal of the transistor P1 to provide a second control signal VC2.
  • the current source Ib1 is connected between the power supply voltage Vdd and the second terminal of the transistor N2. In order to change the second control signal VC2 from the first level state to the second level state during the startup process.
  • the transistors N1 and N2 shown in FIG. 6 are N-channel transistors, and the transistors P2, P3, and the driving transistor Pbuf are P-channel transistors.
  • the following will be used to linearly stabilize the low dropout voltage.
  • the structure and working principle of the press 2000 are described, but the embodiment of the present invention is not limited thereto.
  • Those skilled in the art can set the transistors N1, P2, and the driving transistor Pbuf to different types of transistors according to actual needs, and adaptively adjust related circuits to implement alternative embodiments of the present invention.
  • the driving circuit 2100 mainly works in a current feedback loop.
  • the output current Iout exceeds a certain value, the larger the output current Iout, the larger the conduction current provided by the transistor P3, and the higher the sampling voltage Vsamp, The higher the conduction degree of the transistor N2 and the stronger the pull-down capability, the lower the voltage of the second control signal VC2, and the higher the conduction degree of the transistor P1 and the stronger the pull-down capability, so that the lower the voltage of the first control signal VC1, The smaller the conduction degree of the transistor N1 and the weaker the pull-down capability, the higher the voltage VC3 of the node A1, and the smaller the conduction degree of the driving transistor Pbuf, so the output current Iout is adjusted down.
  • the current feedback loop can limit the output current Iout generated by the driving circuit 2100 to a certain range, so that the output current is kept substantially constant during the first stage of the startup process, and the output voltage Vout can be smoothly increased to avoid Excessive overshoot voltage occurs.
  • the driving circuit 2100 mainly works in a voltage feedback loop.
  • Reference voltage Vref The higher the degree and the stronger the pull-down capability, the lower the voltage VC3 of the node A1, and the higher the conduction degree of the driving transistor Pbuf, so that the larger the output current Iout, the higher the voltage value of the output voltage Vout, until the feedback voltage Vfb reaches this.
  • Reference voltage Vref The higher the difference between the reference voltage Vref and the feedback voltage Vfb, the higher the voltage of the first control signal VC1, and the transistor N
  • FIG. 7 illustrates a specific circuit diagram of a switching circuit and a reset circuit in the low-dropout linear regulator shown in FIG. 4.
  • the reset circuit 2500 includes a holding capacitor C1, a reset transistor MR, and at least one inverter.
  • the first terminal of the holding capacitor C1 is connected to the reference ground gnd, and the second terminal is connected to the control terminal of the transistor P1 to adjust the second control voltage VC2.
  • the reset transistor MR is connected in parallel with the holding capacitor C1, and the control terminal of the reset transistor MR passes At least one inverter receives the enable signal EN, so that the reset transistor MR is controlled by the inverted signal ENB of the enable signal.
  • the holding capacitor C1 provides a second control signal VC2 under the joint action of the transistor N2 and the current source Ib1; in the second stage of the startup process, the transistor N2 is gradually turned off, and the holding capacitor C1 is blocked by the current source Ib1 Charging causes the second control signal VC2 to transition from a low state to a high state, so that the transistor P1 is turned off, and the low-dropout linear regulator 2000 is switched from the current feedback mode to the voltage feedback mode.
  • the charging time of the holding capacitor C1 by the current source Ib1 can be preset, thereby ensuring that the low-dropout linear regulator 2000 can be completely switched from the current feedback mode to the voltage feedback mode.
  • the enable signal EN When the enable signal EN is invalid, the low-dropout linear regulator 2000 is turned off, and the inversion signal ENB of the enable signal turns on the reset transistor MR, so that the holding capacitor C1 is discharged, thereby resetting the second control signal VC2 to be close to Low state of the ground reference voltage Vgnd. Therefore, when the low-dropout linear regulator 2000 is turned on again, the second control signal VC2 has an initial voltage close to the reference ground voltage Vgnd, and the transistor P1 is turned on so that the driving circuit 2100 mainly works in a current feedback loop.
  • the reset transistor MR is an N-channel type transistor.
  • the switching circuit 2400 includes a latch, switches MS1 and MS2, and a plurality of inverters.
  • the latch includes, for example, NAND gates NAND1 and NAND2, and a first input terminal of the NAND gate NAND1 obtains an inversion signal VC2_b of the second control signal VC2 through an odd number of inverters, a second input terminal, and a NAND gate.
  • the output of NAND2 is connected to receive the latch signal Vlock, the first input of NAND2 receives the enable signal EN, and the second input is connected to the output of NAND1 NAND1.
  • the first terminal of the switch MS1 and the first terminal of the switch MS2 receive the first reference voltage Vbias1 and the second reference voltage Vbias2, respectively.
  • the second terminal of the switch MS1 and the second terminal of the switch MS2 are connected to provide a reference voltage Vref.
  • the control terminal receives the latch signal Vlock or obtains the buffer signal S1A of the latch signal Vlock through an even number of inverters connected in series, and the control terminal of the switch MS2 obtains the inverted signal S1B of the latch signal Vlock through an odd number of inverters connected in series.
  • the voltage values of the first reference voltage Vbias1 and the second reference voltage Vbias2 are respectively equal to the initial value va1 and the target value va2 of the reference voltage Vref.
  • the switches MS1 and MS2 may be implemented by a device or a circuit having a switching function, such as a transistor or a transmission gate.
  • the enable signal EN is valid and the second control signal VC2 is close to a low state.
  • the latch signal Vlock is stabilized in the first state, the switch MS1 is turned on and the switch MS2 is turned off, so that the switch MS1
  • the first reference voltage Vbias1 is output as the reference voltage Vref, so that the reference voltage Vref has an initial value va1.
  • the enable signal is valid and the second control line number VC2 is charged to a high-level state.
  • the latch signal Vlock is stabilized in the second state, the switch MS1 is turned off and the switch MS2 is turned on, thereby switching.
  • MS2 outputs the second reference voltage Vbias2 as the reference voltage Vref, so that the reference voltage Vref has a target value va2.
  • the difference between the first reference voltage Vbias1 and the second reference voltage Vbias2 is equal to or slightly greater than the overshoot voltage v_overshoot that occurs during the first stage of the startup process of the load capacitor Cout. Because the magnitude of the overshoot voltage v_overshoot is small, the voltage value of the output voltage Vout during the startup process will not exceed the target voltage value vout_tg, that is, the output voltage Vout can smoothly rise to the target voltage value vout_tg during startup, avoiding The back-end load circuit receives an excessive output voltage Vout due to the overshoot phenomenon, which ensures that the back-end load circuit can work normally without being damaged. In a specific embodiment, a difference between the first reference voltage Vbias1 and the second reference voltage Vbias2 is, for example, 10 mV.
  • the reference voltage Vref is equal to the initial value in the first stage of the startup process.
  • the reference voltage Vref may have different voltage values that are less than or equal to the initial value in the first stage of the startup process.
  • the switching circuit 2400 correspondingly implements switching between different voltage values, so that the voltage value of the output voltage Vout can rise stepwise during the first stage of the driving process.
  • the low-dropout linear regulator of the first embodiment of the present invention first provides a reference voltage that is less than or equal to an initial value during startup, and causes the low-dropout linear regulator to operate in a current feedback mode, thereby limiting the magnitude of the output current to Preventing the output current from being too high and affecting the subsequent stage load circuit; at the same time, during the startup process, when the output voltage reaches a preset voltage value slightly lower than the target voltage value, the low dropout linear regulator of the first embodiment of the present invention can Automatically switches from the current feedback mode to the voltage feedback mode. Because the preset voltage value is close to the target voltage value, the output current generated by the low-dropout linear regulator during the switch from the current feedback mode to the voltage feedback mode is limited. The output voltage can be gradually increased from the preset voltage value to the target voltage value, which effectively controls the overshoot amplitude of the output voltage during the startup process and prevents the subsequent stage load circuit from being affected by the output voltage overshoot phenomenon.
  • FIG. 8 is a schematic flowchart of a voltage stabilization method of a low-dropout linear regulator according to a second embodiment of the present invention. It includes steps S310 to S390.
  • step S310 a first control signal is generated according to the reference voltage and the feedback voltage. Specifically, the first control signal is generated according to a difference between the reference voltage and the feedback voltage.
  • step S320 an output current is generated according to the first control signal.
  • the set output current increases as the voltage of the first control signal increases.
  • step S330 an output voltage is provided according to the output current.
  • step S340 a voltage feedback loop is provided to obtain a feedback voltage according to the output voltage.
  • the output voltage is divided to obtain a feedback voltage for characterizing the output voltage.
  • step S350 a current feedback loop is provided to generate a second control signal according to the output current.
  • the output current is sampled to obtain the sampling current, and the sampling voltage is obtained according to the sampling current; a second current path between the second control signal and the reference ground is provided, and the conduction degree of the second current path is controlled by the sampling voltage to Adjust the second control signal.
  • step S360 in the first stage of the startup process of the low-dropout linear regulator, the current feedback loop is started, the voltage value of the reference voltage is set to be less than or equal to the initial value (the initial value is less than the target value), and according to the second control signal The first control signal is adjusted to limit the output current.
  • a first current path between the first control signal and the reference ground is provided in the first stage of the startup process (the first current path is turned off by the second control signal in the second stage of the startup process), and according to the second
  • the control signal controls the conduction degree of the first current path to adjust the voltage of the first control signal, so as to implement current feedback control, so that the output current is equal to or approximately equal to a constant value, so that the output voltage can be smoothly stabilized during the first stage of the startup process.
  • rise to a preset voltage value preferably, the preset voltage value is slightly lower than the target voltage value).
  • step S370 in the second stage of the startup process of the low-dropout linear regulator, the current feedback loop is gradually closed, the voltage value of the reference voltage is switched to the target value according to the second control signal, and the reference is generated according to the second control signal Voltage.
  • a charging current is provided to raise the second control signal to a high-level state;
  • the reference voltage is set equal to the initial value;
  • the second control signal is in a high-level state, the reference voltage is set equal to the target value, so that the output voltage can rise smoothly to the target voltage value.
  • the voltage stabilizing method of the low-dropout linear regulator according to the second embodiment of the present invention further includes steps S380 and S390.
  • step S380 an enable signal is provided.
  • the enable signal changes from inactive to effective, the low-dropout linear regulator starts to enter the first stage of the startup process; when the enable signal is invalid, step S390 is performed.
  • step S390 the second control signal is reset to a low-level state.
  • the low-dropout linear regulator and the voltage stabilization method of the embodiments of the present invention limit the output current by first providing a reference voltage less than or equal to the initial value during the startup process, and making the low-dropout linear regulator work in a current feedback mode. To prevent the output current from being too high and affecting the subsequent stage load circuit; at the same time, during the startup process, when the output voltage reaches a preset voltage value that is slightly lower than the target voltage value, the low dropout linear voltage regulation of the embodiments of the present invention
  • the voltage regulator and the voltage stabilization method can be automatically switched from the current feedback mode to the voltage feedback mode. Because the preset voltage value is close to the target voltage value, the low-dropout linear regulator is generated during the switching process from the current feedback mode to the voltage feedback mode.
  • the output current is limited, and the output voltage can be gradually increased from the preset voltage value to the target voltage value, which effectively controls the overshoot amplitude of the output voltage during the startup process and avoids the overshoot of the output circuit by the output voltage. influences.

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Abstract

一种低压差线性稳压器（2000）及其稳压方法。低压差线性稳压器（2000）包括：驱动电路（2100），根据参考电压（Vref）和反馈电压（Vfb）产生第一控制信号（VC1），根据第一控制信号（VC1）产生输出电流，负载电容（Cload）根据输出电流（Iout）提供输出电压（Vout）；电压反馈电路（2200），根据输出电压（Vout）获得反馈电压（Vfb）；电流反馈电路（2300），根据输出电流（Iout）产生第二控制信号（VC2）；切换电路（2400），根据第二控制信号（VC2）提供参考电压（Vref）。其中，在启动过程的第一阶段（Ts1），参考电压（Vref）小于等于初始值，电流反馈电路（2300）根据第二控制信号（VC2）限制输出电流（Iout），在启动过程的第二阶段（Ts2），切换电路（2400）将参考电压（Vref）的电压值切换至目标值。低压差线性稳压器（2000）及其稳压方法能够在启动过程中有效地限制输出电流（Iout）并使输出电压（Vout）平缓地上升以减弱或避免过冲现象。

Description

低压差线性稳压器及其稳压方法
本申请要求了2018年6月25日提交的、申请号为201810664170.8、发明名称为“低压差线性稳压器及其稳压方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电子电路技术领域，具体地，涉及一种低压差线性稳压器及其稳压方法。
背景技术
低压差线性稳压器(Low Dropout Regulator,LDO)是一种广泛地应用在电源系统中的电路，用于提供稳定的输出电压Vout。通常，输出电压Vout＝Vdd-Vdrop，其中，Vdd表示电源电压，Vdrop表示电源电压与输出电压之间的电压差。
在LDO的启动过程中，LDO根据参考电压产生充电电流使得输出电压Vout由0V变化至目标电压值。在启动过程中：考虑到LDO的使用寿命、驱动能力以及内部电路的电流特性，LDO的输出电流需要被限制在一定的范围内；在LDO的输出电压Vout邻近目标电压值时，如果输出电流不能迅速从充电电流值下降到负载电流值，那么LDO的输出电压就会出现过冲现象。如果过冲现象带来的过冲电压幅度过大，则与LDO相连的后续负载电路很有可能出现功能失效、过热损坏等现象。所以如何在启动过程中保证LDO的输出电压能够平缓地达到目标电压值从而避免或减缓输出电压的过冲现象是一个值得研究的课题。
图1示出的一种传统的低压差线性稳压器的示意性电路图。
如图1所示，传统的低压差线性稳压器1000包括差分放大器OP0、缓冲单元1100、驱动管Pbuf0、电压反馈单元1200以及负载电容Cload和负载电阻Rload。其中，差分放大器OP0的电源端和接地端分别接收电源电压Vdd和参考地电压Vgnd，差分放大器OP0根据参考电压Vref0和反馈电压Vfb0之间的差值产生控制信号V01；缓冲单元1100包括N沟道型的晶体管N0以及P沟道型的晶体管P0，晶体管N0和P0相连于节点A0，晶体管N0的导通程度受控于控制信号V01的电压值，即节点A0的电压V02被下拉的程度受控于控制电压V01，晶体管P0的控制端与节点A0相连；驱动管Pbuf0的控制端与晶体管P0的控制端相连于节点A0以接收电压V02，从而驱动管Pbuf0能够根据电压V02产生输出电流Iout；输出电流Iout作用于负载电容Cload，从而产生输出电压Vout；电压反馈单元1200利用分压电阻R01和R02对输出电压Vout进行采样以 获得用于表征输出电压的反馈电压Vfb0。
传统的低压差线性稳压器1000通过电压反馈环路实现输出电压Vout的启动过程以及稳压过程。如图1所示，当输出电压Vout未达到参考电压Vref0对应的目标电压值时，反馈电压Vfb0会低于参考电压Vref0，因此控制信号V01导通晶体管N0，从而降低节点A0的电压V02，使得驱动管Pbuf0产生更大的输出电流Iout以对负载电容Cload继续充电，实现提高输出电压Vout的目的，直至输出电压Vout达到参考电压Vref0对应的目标电压值。
图2示出图1中的低压差线性稳压器在启动过程中的参考电压Vref0和输出电压Vout的波形示意图。
如图2和图1所示，在启动过程中，参考电压Vref0瞬间由初始的低电平电压(例如为0V)上升至目标值vref0_tg，使得参考电压Vref0远远高于反馈电压Vfb0，因此输入至差分放大器OP0的参考电压Vref0与反馈电压Vfb0之间的差值很大，导致控制电压V01接近差分放大器OP1的输出电压摆幅范围的最大值，节点A0的电压V02被下拉至很低的电压水平，使得驱动管Pbuf0处于几乎完全开启的状态，此时输出电流Iout的电流值Ich(充电电流值)会远远高于低压差线性稳压器1000在稳压过程中提供的输出电流Iout的电流值Ist(负载电流值)。
因此，传统的低压差线性稳压器1000存在以下不足之处：启动过程中，由于参考电压Vref0会瞬间上升至目标值vref0_tg，因此输出电流Iout会瞬间达到很高的电流值Ich，这会缩短驱动管Pbuf0的使用寿命，并要求版图(Layout)布局中导体的走线具有一定的宽度，从而导致版图面积的增大和布局布线难度的增加；同时，在启动过程中，当输出电压Vout接近目标电压值vout_tg时，低压差线性稳压器需要将输出电流Iout的电流值从很高的电流值Ich恢复至较低的电流值Ist，由于电压反馈环路需要一定的响应时间，因此这一恢复过程会导致输出电压Vout在一段时间内高于目标电压值，即出现过冲现象，当输出电压Vout与目标电压值vout_tg相比存在很大的过冲电压v_overshoot时，与低压差线性稳压器相连的后级负载电路会受到影响。
针对上述不足之处，一种现有技术对上述传统的低压差线性稳压器进行了改进。图3示出了这种现有技术的低压差线性稳压器中参考电压和输出电压的波形示意图。
如图3所示，在启动过程中，参考电压Vref0不会从低电平电压直接增大到目标值vref0_tg，而是从低电平电压逐级增大到目标值vref0_tg，以防止启动过程中输出电流Iout过高。另外，由于输出电流Iout被限制，因此当输出电压Vout接近目标电压值vout_tg时，输出电流Iout恢复至负载电流值所需的时间较短，因此这一现有技术能够在一定程度上减缓输出电压Vout的过冲现象。
然而，如图3所示，上述现有技术提供的低压差线性稳压器中仍然存在输出电压的过冲现象。
因此，期待一种新的低压差线性稳压器，其能够在启动过程中限制输出电流的大小，并有效 地防止输出电压出现过冲现象，使得输出电压能够在启动过程中平缓稳定地上升至目标电压值。
发明内容
为了解决上述现有技术存在的问题，本发明通过设置切换电路实现对电流反馈环和电压反馈环之间的自动切换，并通过在启动过程中的不同阶段设置具有不同电压值的参考电压以限制输出电流的大小，从而防止输出电流瞬间增大，并有效地防止输出电压出现过冲现象，使得输出电压能够在启动过程中平缓稳定地上升至目标电压值。
根据本发明的一方面，提供了一种低压差线性稳压器，其特征在于，包括：驱动电路，根据参考电压和反馈电压产生第一控制信号，并根据所述第一控制信号产生输出电流，负载电容根据所述输出电流提供输出电压；电压反馈电路，根据所述输出电压获得所述反馈电压；电流反馈电路，根据所述输出电流产生第二控制信号；以及切换电路，用于根据所述第二控制信号提供所述参考电压，其中，所述低压差线性稳压器的启动过程包括第一阶段和第二阶段，在所述第一阶段中，所述参考电压的电压值小于等于初始值，所述电流反馈电路根据所述第二控制信号调节所述第一控制信号以限制所述输出电流，在所述第二阶段中，所述切换电路根据所述第二控制信号将所述参考电压的电压值切换至目标值，所述初始值小于所述目标值。
优选地，在所述驱动电路中，所述输出电流随所述第一控制信号的电压的升高而增大。
优选地，所述电流反馈电路包括第一晶体管，所述第一晶体管用于提供所述第一控制信号到参考地之间的第一电流路径，所述第一晶体管的控制端接收所述第二控制信号，在所述第一阶段，所述第一晶体管的导通程度受控于所述第二控制信号以调节所述第一控制信号，在所述第二阶段，所述第一晶体管被所述第二控制信号关断。
优选地，所述第一晶体管包括P沟道型晶体管。
优选地，所述电流反馈电路还包括电流源，当所述反馈电压的电压值上升至所述初始值时，所述电流源对所述第一晶体管的控制端提供充电电流以将所述第二控制信号抬高至高电平状态。
优选地，所述切换电路包括：第一开关和第二开关，所述第一开关的第一端和所述第二开关的第二端分别接收第一基准电压和第二基准电压，所述第一开关的第二端和所述第二开关的第二端相连以提供所述参考电压，所述第一基准电压的电压值和所述第二基准电压的电压值分别等于所述初始值和所述目标值；以及逻辑电路，根据所述第二控制信号控制所述第一开关和所述第二开关的导通和关断，当所述第二控制信号处于低电平状态时，所述第一开关导通且所述第二开关关断，当所述第二控制信号处于高电平状态时，所述第二开关导通且所述第一开关关断。
优选地，所述逻辑电路包括：锁存器，用于根据使能信号和所述第二控制信号的电平状态产 生开关控制信号，在所述使能信号有效时，所述第一开关和所述第二开关之一在所述开关控制信号的控制下导通。
优选地，所述低压差线性稳压器还包括复位电路，所述复位电路包括：保持电容，其第一端与所述参考地相连，第二端与所述第一晶体管的控制端相连；以及复位晶体管，当所述使能信号无效时，所述复位晶体管导通以使所述保持电容的第一端和第二端短接。
优选地，所述电流反馈电路还包括：第二晶体管，用于对所述输出电流采样以获得采样电流；以及第三晶体管，用于提供所述第二控制信号到参考地之间的第二电流路径，所述第三晶体管的控制端根据所述采样电流产生采样电压以使所述第三晶体管的导通程度受控于所述采样电压。
优选地，所述第二晶体管包括P沟道型晶体管，所述第三晶体管包括N沟道型晶体管。
优选地，所述驱动电路包括：差分放大器，根据所述参考电压和所述反馈电压之间的差值产生所述第一控制信号；缓冲单元，至少包括第四晶体管和第五晶体管，所述第五晶体管的栅极接收第三控制信号，所述第四晶体管用于提供所述第三控制信号到所述参考地之间的第三电流路径，所述第四晶体管的导通程度受控于所述第一控制信号以调节所述第三控制信号；以及驱动晶体管，用于根据第三控制信号产生所述输出电流。
优选地，所述第四晶体管包括N沟道型的晶体管，所述第五晶体管包括P沟道型的晶体管。
优选地，所述电压反馈电路包括串联的多个采样电阻，所述多个采样电阻用于对所述输出电压分压以得到所述反馈电压。
根据本发明的另一方面，提供了一种低压差线性稳压器的稳压方法，其特征在于，包括：根据参考电压和反馈电压产生第一控制信号；根据所述第一控制信号产生输出电流；根据所述输出电流提供输出电压；提供电压反馈环路以根据所述输出电压获得所述反馈电压；提供电流反馈环路以根据所述输出电流产生第二控制信号；以及根据所述第二控制信号提供所述参考电压，其中，所述低压差线性稳压器的启动过程包括第一阶段和第二阶段，在所述第一阶段中，所述电流反馈环路开启，设置所述参考电压的电压值小于等于初始值，并根据所述第二控制信号调节所述第一控制信号以限制所述输出电流，在所述第二阶段中，所述电流反馈环路逐渐关闭，根据所述第二控制信号将所述参考电压的电压值切换至目标值，所述初始值小于所述目标值。
优选地，设置所述输出电流随所述第一控制信号的电压的升高而增大。
优选地，根据所述第二控制信号调节所述第一控制信号以限制所述输出电流的步骤包括：在所述第一阶段，提供所述第一控制信号到参考地之间的第一电流路径，并根据所述第二控制信号控制所述第一电流路径的导通程度以调节所述第一控制信号的电压；在所述第二阶段，根据所述第二控制信号关断所述第一电流路径。
优选地，在所述根据所述第二控制信号将所述参考电压的电压值切换至目标值的步骤包括：当所述反馈电压的电压值上升至所述初始值时，提供充电电流以将所述第二控制信号抬高至高电平状态；当所述第二控制信号处于低电平状态时，设置所述参考电压等于所述初始值，当所述第二控制信号处于高电平状态时，设置所述参考电压等于所述目标值。
优选地，所述稳压方法还包括：提供使能信号；当所述使能信号无效时，将所述第二控制信号复位至低电平状态。
优选地，根据所述输出电流产生第二控制信号的步骤包括：对所述输出电流采样以获得采样电流，并根据所述采样电流获得采样电压；提供所述第二控制信号到参考地之间的第二电流路径，所述第二电流路径的导通程度受控于所述采样电压。
优选地，根据所述输出电压获得所述反馈电压的步骤包括：对所述输出电压进行分压以得到用于表征所述输出电压的所述反馈电压。
本发明各实施例的低压差线性稳压器和稳压方法通过在启动过程中首先提供小于等于初始值的参考电压，并使低压差线性稳压器工作在电流反馈模式，从而限制了输出电流的大小以防止输出电流过高而影响后级负载电路；同时，在启动过程中，当输出电压达到略低于目标电压值的预设电压值时，本发明各实施例的低压差线性稳压器和稳压方法能够由电流反馈模式自动地切换至电压反馈模式，由于预设电压值与目标电压值相近，因此低压差线性稳压器在由电流反馈模式向电压反馈模式的切换过程中产生的输出电流受到限制，输出电压能够由预设电压值平缓地升高至目标电压值，有效地控制了输出电压在启动过程中的过冲幅度，避免后级负载电路被输出电压的过冲现象影响。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚。
图1示出的一种传统的低压差线性稳压器的示意性电路图。
图2示出图1中的低压差线性稳压器在启动过程中的参考电压Vref0和输出电压Vout的波形示意图。
图3示出了这种现有技术的低压差线性稳压器中参考电压和输出电压的波形示意图。
图4示出本发明第一实施例的低压差线性稳压器的电路示意图。
图5示出图4所示的低压差线性稳压器中参考电压和输出电压在启动过程中的波形示意图。
图6示出图4所示的低压差线性稳压器中驱动电路、电流反馈电路以及电压反馈电路的具体 电路示意图。
图7示出图4所示的低压差线性稳压器中切换电路和复位电路的具体电路示意图。
图8示出本发明第二实施例的低压差线性稳压器的稳压方法的流程示意图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，在图中没有画出除了对应驱动电极与感测电极之外的引出线，并且可能未示出某些公知的部分。
在下文中描述了本发明的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。
图4示出本发明第一实施例的低压差线性稳压器的电路示意图。
如图4所示，本发明第一实施例的低压差线性稳压器2000包括驱动电路2100、电压反馈电路2200、电流反馈电路2300、切换电路2400以及复位电路2500。
驱动电路2100根据参考电压Vref和反馈电压Vfb的差值产生第一控制信号VC1，并根据第一控制信号VC1产生输出电流Iout。与驱动电路2100相连的负载电容Cload接收输出电流Iout，从而根据输出电流Iout产生输出电压Vout，输出电压Vout作用于负载电阻Rload(例如为后级负载电路的等效电阻)。
电压反馈电路2200用于根据输出电压Vout获得反馈电压Vfb，并将反馈电压Vfb提供给驱动电路2100，从而与驱动电路2100形成电压反馈环路。
电流反馈电路2300包括晶体管P1和电流反馈控制模块2310。其中电流反馈控制模块2310用于根据输出电流Iout产生第二控制信号VC2；晶体管P1的控制端受控于第二控制信号VC2，晶体管P1的第一端和第二端分别与驱动电路2100和参考地gnd(提供参考地电压Vgnd)相连，因此晶体管P1能够提供第一控制信号VC1到参考地gnd之间的电流路径。由于晶体管P1的导通程度受控于第二控制信号VC2，因此第一控制信号VC1可以被调节，从而电流反馈电路2300与驱动电路2100形成电流反馈环路。
切换电路2400用于根据第二控制信号VC2提供参考电压Vref。根据第二控制信号VO2的电平状态，切换电路2400提供的参考电压Vref具有不同的电压值。
优选地，低压差线性稳压器2000还包括复位电路2500。复位电路2500受控于使能信号EN。在低压差线性稳压器2000开始启动之前，使能信号EN无效，复位电路2500将第二控制信号VC2 复位，使得电流反馈电路2300中的晶体管P1导通，从而进一步将第一控制信号VC1复位；在低压差线性稳压器2000开始启动时，使能信号EN由无效变为有效，电流反馈电路2300根据输出电流Iout调节第二控制信号VC2，使得驱动电路2100在启动过程的第一阶段主要工作在电流反馈环路中；进一步优选地，切换电路2400也受控于使能信号EN，切换电路2400根据使能信号EN和第二控制信号VC2的电平状态选择参考电压Vref的电压值。
图5示出图4所示的低压差线性稳压器中参考电压和输出电压在启动过程中的波形示意图。
如图4和图5所示，低压差线性稳压器2000的工作过程包括启动过程(从上电/使能信号EN由无效变为有效起至输出电压Vout达到目标电压值vout_tg)和稳定过程(输出电压Vout保持目标电压值vout_tg)。具体地，启动过程包括第一阶段Ts1和第二阶段Ts2：在第一阶段Ts1中，驱动电路2100主要工作在电流反馈环路中，即电流反馈电路2300根据第二控制信号VC2调节第一控制信号VC1以限制输出电流Iout的幅值(输出电流Iout恒定或近似于恒定)，使得输出电压Vout被平稳地升高以避免输出电压Vout出现幅度较大的过冲现象，此时切换电路2400提供的参考电压Vref的电压值等于初始值va1，在第一阶段结束时，输出电压Vout会最终稳定在与参考电压的初始值va1对应的预设电压值vout1；在第二阶段Ts2中，电流反馈电路2300提供的第二控制信号VC2逐渐由第一电平状态转变为第二电平状态，使得晶体管P1逐渐关断、切换电路2400在第二控制信号VC2的作用下将参考电压Vref的电压值切换至目标值va2，从而逐渐使得驱动电路2100主要工作在电压反馈环路中，即驱动电路2100主要根据电压反馈电路2200提供的反馈电压Vfb与参考电压Vref之间的差值调节输出电压Vout，在第二阶段中，输出电压Vout由预设电压值vout1被抬高至目标电压值vout_tg。由于在第一阶段Ts1中，输出电流Iout被限制，因此负载电容Cout近似于被恒流充电，因此输出电压Vout由于过冲现象而产生的过冲电压v_overshoot的幅值较小；在第二阶段Ts2中，通过设置参考电压Vref的初始值va1和目标值va2之间的差值略大于或等于过冲电压v_overshoot的幅值，可以使第一控制信号VC1的驱动能力较弱，因此输出电压Vout能够由预设电压值vout1平缓地上升至目标电压值vout_tg，从而避免输出电压Vout在第二阶段出现过冲现象。
图6示出图4所示的低压差线性稳压器中驱动电路、电流反馈电路以及电压反馈电路的具体电路示意图。
如图6所示，驱动电路(如图4所示的驱动电路2100)包括差分放大器OP1、缓冲单元以及驱动晶体管Pbuf，其中缓冲单元包括晶体管N1和晶体管P2。具体地，差分放大器OP1根据参考电压Vref和反馈电压Vfb的差值产生第一控制信号VC1，差分放大器OP1的电源端、接地端、正输入端、负输入端例如分别接收电源电压Vdd、参考地电压Vgnd、参考电压Vref以及反馈电 压Vfb；晶体管N1的控制端与差分放大器OP1的输出端相连，晶体管N1的第一端与晶体管P2的第一端相连于节点A1，晶体管N1的第二端与参考地gnd相连，晶体管P2的控制端受控于节点A1的电压VC3(第三控制信号)，晶体管P2的第二端与电源电压Vdd相连；驱动晶体管Pbuf的控制端同样受控于节点A1的电压VC3，驱动晶体管Pbuf的第一端与电源电压Vdd相连，第二端提供输出电流Iout至负载电容Cload的第一端，从而在负载电容Cload的第一端产生输出电压Vout，负载电容Cload的第二端接参考地gnd。
如图6所示，电压反馈电路2200包括多个采样电阻，从而通过对输出电压Vout进行分压而得到能够表征输出电压Vout的反馈电压Vfb。例如，电压反馈电路2200包括串联在输出电压Vout和参考地gnd之间的采样电阻R1和R2，采样电阻R1和R2之间相连的节点与驱动电路2100中的差分放大器OP1的输入端之一相连以提供反馈电压Vfb。
如图6所示，电流反馈电路2300包括晶体管P1和电流反馈控制模块。作为一种具体的实施例，电流反馈控制模块包括晶体管N2和P3、电流漏Ib2以及电流源Ib1。其中，晶体管P3的控制端和第一端分别与驱动晶体管Pbuf的控制端和第一端相连，使得晶体管P3的导通电流与驱动晶体管Pbuf提供的输出电流Iout之比与晶体管P3和驱动晶体管Pbuf的尺寸比正相关，从而晶体管P3实现了对输出电流Iout的采样，电流漏Ib2连接在晶体管P3的第二端和参考地gnd之间，晶体管P3的第二端提供采样电压Vsamp；晶体管N2的控制端接收采样电压Vsamp、第一端接参考地gnd、第二端与晶体管P1的控制端相连以提供第二控制信号VC2；电流源Ib1连接在电源电压Vdd和晶体管N2的第二端之间以在启动过程中将第二控制信号VC2由第一电平状态转变为第二电平状态。
作为一种具体的实施例，图6示出的晶体管N1和N2为N沟道型晶体管，晶体管P2、P3和驱动晶体管Pbuf为P沟道型晶体管，下面将以此为基础对低压差线性稳压器2000的结构和工作原理进行描述，但是本发明实施例不限于此。本领域技术人员可以根据实际需要将晶体管N1、P2以及驱动晶体管Pbuf设置为不同类型的晶体管，并适应性地调整相关电路以实现本发明的替代实施例。
在启动过程的第一阶段，驱动电路2100主要工作在电流反馈环路中，输出电流Iout超过一定值时，输出电流Iout越大，晶体管P3提供的导通电流越大，采样电压Vsamp越高，晶体管N2的导通程度越高、下拉能力越强，第二控制信号VC2的电压越低，晶体管P1的导通程度越高、下拉能力越强，从而第一控制信号VC1的电压越低，使得晶体管N1的导通程度越小、下拉能力越弱，节点A1的电压VC3越高，驱动晶体管Pbuf的导通程度越小，因此输出电流Iout被下调。根据这样的原理，电流反馈环路能够将驱动电路2100产生的输出电流Iout限制在一定的范围内， 使得输出电流在启动过程的第一阶段内基本保持恒定、输出电压Vout能够平稳地上升，避免出现过高的过冲电压。
在启动过程的第二阶段，驱动电路2100主要工作在电压反馈环路中，参考电压Vref和反馈电压Vfb之间的差值越大，第一控制信号VC1的电压越高，晶体管N1的导通程度越高、下拉能力越强，从而节点A1的电压VC3越低，驱动晶体管Pbuf的导通程度越高，从而输出电流Iout越大，输出电压Vout的电压值升高，直至反馈电压Vfb达到此时的参考电压Vref。
图7示出图4所示的低压差线性稳压器中切换电路和复位电路的具体电路示意图。
如图7所示，复位电路2500包括保持电容C1、复位晶体管MR以及至少一个反相器。其中，保持电容C1的第一端与参考地gnd相连，第二端与晶体管P1的控制端相连以调节第二控制电压VC2；复位晶体管MR与保持电容C1并联，且复位晶体管MR的控制端通过至少一个反相器接收使能信号EN，使得复位晶体管MR受控于使能信号的反相信号ENB。
当使能信号EN有效时，低压差线性稳压器2000开启，使能信号的反相信号ENB关断复位晶体管MR。在启动过程的第一阶段，保持电容C1在晶体管N2和电流源Ib1的共同作用下提供第二控制信号VC2；在启动过程的第二阶段，晶体管N2逐渐关断，保持电容C1被电流源Ib1充电以使第二控制信号VC2由低电平状态转变为高电平状态，从而晶体管P1关断，低压差线性稳压器2000由电流反馈模式切换至电压反馈模式。优选地，电流源Ib1对保持电容C1的充电时间可以预设，从而保证低压差线性稳压器2000能够从电流反馈模式完全地切换至电压反馈模式。
当使能信号EN无效时，低压差线性稳压器2000关断，使能信号的反相信号ENB导通复位晶体管MR，使得保持电容C1被放电，从而将第二控制信号VC2复位至接近于参考地电压Vgnd的低电平状态。因此，当低压差线性稳压器2000再次被开启时，第二控制信号VC2具有接近于参考地电压Vgnd的初始电压，晶体管P1被导通以使驱动电路2100主要工作在电流反馈环路中。
优选地，复位晶体管MR为N沟道型晶体管。
如图7所示，切换电路2400包括锁存器、开关MS1和MS2以及多个反相器。
具体地，锁存器例如包括与非门NAND1和NAND2，与非门NAND1的第一输入端通过奇数个反相器获得第二控制信号VC2的反相信号VC2_b、第二输入端和与非门NAND2的输出端相连以接收锁存信号Vlock，与非门NAND2的第一输入端接收使能信号EN、第二输入端与与非门NAND1的输出端相连。
开关MS1的第一端和开关MS2的第一端分别接收第一基准电压Vbias1和第二基准电压Vbias2，开关MS1的第二端和开关MS2的第二端相连以提供参考电压Vref，开关MS1的控制端接收锁存信号Vlock或通过偶数个串联的反相器获得锁存信号Vlock的缓冲信号S1A，开关MS2 的控制端通过奇数个串联的反相器获得锁存信号Vlock的反相信号S1B。其中第一基准电压Vbias1和第二基准电压Vbias2的电压值分别等于参考电压Vref的初始值va1和目标值va2。具体地，开关MS1和开关MS2可以由晶体管或传输门等具有开关功能的器件或电路实现。
在启动过程的第一阶段，使能信号EN有效且第二控制信号VC2接近低电平状态，此时锁存信号Vlock稳定在第一状态，开关MS1导通且开关MS2关断，从而开关MS1将第一基准电压Vbias1作为参考电压Vref输出，使得参考电压Vref具有初始值va1。
在启动过程的第二阶段，使能信号有效且第二控制线号VC2被充电至高电平状态，此时锁存信号Vlock稳定在第二状态，开关MS1关断且开关MS2导通，从而开关MS2将第二基准电压Vbias2作为参考电压Vref输出，使得参考电压Vref具有目标值va2。
在优选的实施例中，第一基准电压Vbias1和第二基准电压Vbias2之间的差值等于或略大于负载电容Cout在启动过程的第一阶段出现的过冲电压v_overshoot。由于该过冲电压v_overshoot的幅度较小，从而输出电压Vout在启动过程中的电压值不会超过目标电压值vout_tg，即输出电压Vout在启动过程中能够平缓地上升至目标电压值vout_tg，避免了后级负载电路因过冲现象而接收到过大的输出电压Vout，保证了后级负载电路能够正常工作且不被损坏。在具体的实施例中，第一基准电压Vbias1与第二基准电压Vbias2之间的差值例如为10mV。
上述实施例中，参考电压Vref在启动过程的第一阶段等于初始值，然而本发明实施例不限于此，参考电压Vref可以在启动过程的第一阶段具有小于等于初始值的不同的电压值，切换电路2400对应地实现对不同电压值之间的切换，从而输出电压Vout的电压值能够在驱动过程的第一阶段阶梯式地上升。
本发明第一实施例的低压差线性稳压器通过在启动过程中首先提供小于等于初始值的参考电压，并使低压差线性稳压器工作在电流反馈模式，从而限制了输出电流的大小以防止输出电流过高而影响后级负载电路；同时，在启动过程中，当输出电压达到略低于目标电压值的预设电压值时，本发明第一实施例的低压差线性稳压器能够由电流反馈模式自动地切换至电压反馈模式，由于预设电压值与目标电压值相近，因此低压差线性稳压器在由电流反馈模式向电压反馈模式的切换过程中产生的输出电流受到限制，输出电压能够由预设电压值平缓地升高至目标电压值，有效地控制了输出电压在启动过程中的过冲幅度，避免后级负载电路被输出电压的过冲现象影响。
图8示出本发明第二实施例的低压差线性稳压器的稳压方法的流程示意图。包括步骤S310至S390。
在步骤S310中，根据参考电压和反馈电压产生第一控制信号。具体地，根据参考电压和反馈电压的差值产生第一控制信号。
在步骤S320中，根据第一控制信号产生输出电流。优选地，设置输出电流随第一控制信号的电压的升高而增大。
在步骤S330中，根据输出电流提供输出电压。
在步骤S340中，提供电压反馈环路以根据输出电压获得反馈电压。优选地，对输出电压进行分压以得到用于表征输出电压的反馈电压。
在步骤S350中，提供电流反馈环路以根据输出电流产生第二控制信号。优选地，对输出电流采样以获得采样电流，并根据采样电流获得采样电压；提供第二控制信号到参考地之间的第二电流路径，第二电流路径的导通程度受控于采样电压以实现对第二控制信号的调节。
在步骤S360中，在低压差线性稳压器的启动过程的第一阶段，开启电流反馈环路，设置参考电压的电压值小于等于初始值(初始值小于目标值)，并根据第二控制信号调节第一控制信号以限制输出电流。优选地，在启动过程的第一阶段提供第一控制信号到参考地之间的第一电流路径(第一电流路径在启动过程的第二阶段被第二控制信号关断)，并根据第二控制信号控制第一电流路径的导通程度以调节第一控制信号的电压，从而实现电流反馈控制，使输出电流等于或近似地等于恒定值，从而输出电压能够在启动过程的第一阶段平稳地上升至预设电压值(优选地，预设电压值略低于目标电压值)。
在步骤S370中，在低压差线性稳压器的启动过程的第二阶段，逐渐关闭电流反馈环路，根据第二控制信号将参考电压的电压值切换至目标值，根据第二控制信号产生参考电压。优选地，当反馈电压的电压值上升至初始值时，提供充电电流以将第二控制信号抬高至高电平状态；当第二控制信号处于低电平状态时，设置参考电压等于初始值；当第二控制信号处于高电平状态时，设置参考电压等于目标值，从而输出电压能够平稳地上升到目标电压值。
优选地，本发明第二实施例的低压差线性稳压器的稳压方法还包括步骤S380和步骤S390。
在步骤S380中，提供使能信号。当使能信号由无效变为有效时，低压差线性稳压器开始进入启动过程的第一阶段；当使能信号无效时，执行步骤S390。
在步骤S390中，将第二控制信号复位至低电平状态。
本发明各实施例的低压差线性稳压器和稳压方法通过在启动过程中首先提供小于等于初始值的参考电压，并使低压差线性稳压器工作在电流反馈模式，从而限制了输出电流的大小以防止输出电流过高而影响后级负载电路；同时，在启动过程中，当输出电压达到略低于目标电压值的预设电压值时，本发明各实施例的低压差线性稳压器和稳压方法能够由电流反馈模式自动地切换至电压反馈模式，由于预设电压值与目标电压值相近，因此低压差线性稳压器在由电流反馈模式向电压反馈模式的切换过程中产生的输出电流受到限制，输出电压能够由预设电压值平缓地升高至 目标电压值，有效地控制了输出电压在启动过程中的过冲幅度，避免后级负载电路被输出电压的过冲现象影响。
应当说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (20)

  1. 一种低压差线性稳压器，其特征在于，包括：
    驱动电路，根据参考电压和反馈电压产生第一控制信号，并根据所述第一控制信号产生输出电流，负载电容根据所述输出电流提供输出电压；
    电压反馈电路，根据所述输出电压获得所述反馈电压；
    电流反馈电路，根据所述输出电流产生第二控制信号；以及
    切换电路，用于根据所述第二控制信号提供所述参考电压，
    其中，所述低压差线性稳压器的启动过程包括第一阶段和第二阶段，
    在所述第一阶段中，所述参考电压的电压值小于等于初始值，所述电流反馈电路根据所述第二控制信号调节所述第一控制信号以限制所述输出电流，
    在所述第二阶段中，所述切换电路根据所述第二控制信号将所述参考电压的电压值切换至目标值，所述初始值小于所述目标值。
  2. 根据权利要求1所述的低压差线性稳压器，其特征在于，在所述驱动电路中，所述输出电流随所述第一控制信号的电压的升高而增大。
  3. 根据权利要求2所述的低压差线性稳压器，其特征在于，所述电流反馈电路包括第一晶体管，所述第一晶体管用于提供所述第一控制信号到参考地之间的第一电流路径，所述第一晶体管的控制端接收所述第二控制信号，
    在所述第一阶段，所述第一晶体管的导通程度受控于所述第二控制信号以调节所述第一控制信号，
    在所述第二阶段，所述第一晶体管被所述第二控制信号关断。
  4. 根据权利要求3所述的低压差线性稳压器，其特征在于，所述第一晶体管包括P沟道型晶体管。
  5. 根据权利要求4所述的低压差线性稳压器，其特征在于，所述电流反馈电路还包括电流源，
    当所述反馈电压的电压值上升至所述初始值时，所述电流源对所述第一晶体管的控制端提供 充电电流以将所述第二控制信号抬高至高电平状态。
  6. 根据权利要求4所述的低压差线性稳压器，其特征在于，所述切换电路包括：
    第一开关和第二开关，所述第一开关的第一端和所述第二开关的第二端分别接收第一基准电压和第二基准电压，所述第一开关的第二端和所述第二开关的第二端相连以提供所述参考电压，所述第一基准电压的电压值和所述第二基准电压的电压值分别等于所述初始值和所述目标值；以及
    逻辑电路，根据所述第二控制信号控制所述第一开关和所述第二开关的导通和关断，当所述第二控制信号处于低电平状态时，所述第一开关导通且所述第二开关关断，当所述第二控制信号处于高电平状态时，所述第二开关导通且所述第一开关关断。
  7. 根据权利要求6所述的低压差线性稳压器，其特征在于，所述逻辑电路包括：
    锁存器，用于根据使能信号和所述第二控制信号的电平状态产生开关控制信号，在所述使能信号有效时，所述第一开关和所述第二开关之一在所述开关控制信号的控制下导通。
  8. 根据权利要求7所述的低压差线性稳压器，其特征在于，所述低压差线性稳压器还包括复位电路，所述复位电路包括：
    保持电容，其第一端与所述参考地相连，第二端与所述第一晶体管的控制端相连；以及
    复位晶体管，当所述使能信号无效时，所述复位晶体管导通以使所述保持电容的第一端和第二端短接。
  9. 根据权利要求4所述的低压差线性稳压器，其特征在于，所述电流反馈电路还包括：
    第二晶体管，用于对所述输出电流采样以获得采样电流；以及
    第三晶体管，用于提供所述第二控制信号到参考地之间的第二电流路径，所述第三晶体管的控制端根据所述采样电流产生采样电压以使所述第三晶体管的导通程度受控于所述采样电压。
  10. 根据权利要求9所述的低压差线性稳压器，其特征在于，所述第二晶体管包括P沟道型晶体管，所述第三晶体管包括N沟道型晶体管。
  11. 根据权利要求2所述的低压差线性稳压器，其特征在于，所述驱动电路包括：
    差分放大器，根据所述参考电压和所述反馈电压之间的差值产生所述第一控制信号；
    缓冲单元，至少包括第四晶体管和第五晶体管，所述第五晶体管的栅极接收第三控制信号，所述第四晶体管用于提供所述第三控制信号到所述参考地之间的第三电流路径，所述第四晶体管的导通程度受控于所述第一控制信号以调节所述第三控制信号；以及
    驱动晶体管，用于根据第三控制信号产生所述输出电流。
  12. 根据权利要求11所述的低压差线性稳压器，其特征在于，所述第四晶体管包括N沟道型的晶体管，所述第五晶体管包括P沟道型的晶体管。
  13. 根据权利要求1所述的低压差线性稳压器，其特征在于，所述电压反馈电路包括串联的多个采样电阻，所述多个采样电阻用于对所述输出电压分压以得到所述反馈电压。
  14. 一种低压差线性稳压器的稳压方法，其特征在于，包括：
    根据参考电压和反馈电压产生第一控制信号；
    根据所述第一控制信号产生输出电流；
    根据所述输出电流提供输出电压；
    提供电压反馈环路以根据所述输出电压获得所述反馈电压；
    提供电流反馈环路以根据所述输出电流产生第二控制信号；以及
    根据所述第二控制信号提供所述参考电压，
    其中，所述低压差线性稳压器的启动过程包括第一阶段和第二阶段，
    在所述第一阶段中，所述电流反馈环路开启，设置所述参考电压的电压值小于等于初始值，并根据所述第二控制信号调节所述第一控制信号以限制所述输出电流，
    在所述第二阶段中，所述电流反馈环路逐渐关闭，根据所述第二控制信号将所述参考电压的电压值切换至目标值，所述初始值小于所述目标值。
  15. 根据权利要求14所述的稳压方法，其特征在于，设置所述输出电流随所述第一控制信号的电压的升高而增大。
  16. 根据权利要求15所述的稳压方法，其特征在于，根据所述第二控制信号调节所述第一控制信号以限制所述输出电流的步骤包括：
    在所述第一阶段，提供所述第一控制信号到参考地之间的第一电流路径，并根据所述第二控 制信号控制所述第一电流路径的导通程度以调节所述第一控制信号的电压；
    在所述第二阶段，根据所述第二控制信号关断所述第一电流路径。
  17. 根据权利要求16所述的稳压方法，其特征在于，在所述根据所述第二控制信号将所述参考电压的电压值切换至目标值的步骤包括：
    当所述反馈电压的电压值上升至所述初始值时，提供充电电流以将所述第二控制信号抬高至高电平状态；
    当所述第二控制信号处于低电平状态时，设置所述参考电压等于所述初始值，当所述第二控制信号处于高电平状态时，设置所述参考电压等于所述目标值。
  18. 根据权利要求16所述的稳压方法，其特征在于，所述稳压方法还包括：
    提供使能信号；
    当所述使能信号无效时，将所述第二控制信号复位至低电平状态。
  19. 根据权利要求16所述的稳压方法，其特征在于，根据所述输出电流产生第二控制信号的步骤包括：
    对所述输出电流采样以获得采样电流，并根据所述采样电流获得采样电压；
    提供所述第二控制信号到参考地之间的第二电流路径，所述第二电流路径的导通程度受控于所述采样电压以调节所述第二控制信号。
  20. 根据权利要求14所述的稳压方法，其特征在于，根据所述输出电压获得所述反馈电压的步骤包括：
    对所述输出电压进行分压以得到用于表征所述输出电压的所述反馈电压。
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