WO2019232705A1 - 晶体管电路及其制造方法 - Google Patents

晶体管电路及其制造方法 Download PDF

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Publication number
WO2019232705A1
WO2019232705A1 PCT/CN2018/090060 CN2018090060W WO2019232705A1 WO 2019232705 A1 WO2019232705 A1 WO 2019232705A1 CN 2018090060 W CN2018090060 W CN 2018090060W WO 2019232705 A1 WO2019232705 A1 WO 2019232705A1
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Prior art keywords
line
signal line
transistor
insulating substrate
layer
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PCT/CN2018/090060
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English (en)
French (fr)
Inventor
赵冲
徐慧龙
刘荣江
Original Assignee
华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201880091420.1A priority Critical patent/CN111886801B/zh
Priority to PCT/CN2018/090060 priority patent/WO2019232705A1/zh
Publication of WO2019232705A1 publication Critical patent/WO2019232705A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a transistor circuit and a manufacturing method thereof.
  • transistor circuits such as power amplifiers
  • a transistor circuit generally includes an insulating substrate, and a transistor, an input signal line, and an output signal line provided on the insulating substrate.
  • the gate of the transistor is connected to the signal source through the input signal line, the first pole of the transistor is connected to the load through the output signal line, and the second pole of the transistor is grounded.
  • the transistor can adjust the amplitude of a signal of a certain frequency input by the signal source, and output the adjusted signal to a load.
  • a transistor in a transistor circuit in the related art can only adjust the amplitude of a signal of one frequency, and therefore, the function of the transistor circuit is relatively single.
  • the application provides a transistor circuit and a manufacturing method thereof, which can solve the problem that the function of the transistor circuit is relatively single.
  • the technical solution is as follows:
  • a transistor circuit in one aspect, includes: an insulating substrate, a transistor, a first signal line, a second signal line, m control lines and a controller, m ⁇ 1, the transistor, the The first signal line, the second signal line, and the m control lines are all disposed on the target side of the insulating substrate, the gate of the transistor is connected to the first signal line, and the first One pole is connected to the second signal line; the control line is overlapped on at least one of the first signal line and the second signal line, and the materials of the at least one signal line are A two-dimensional material, each of the control lines includes: an insulating layer and a conductive layer that are sequentially stacked in a direction away from the insulating substrate, and the controller is connected to the control line and is used to connect the control line to the A voltage is applied to the conductive layer.
  • the material of each signal line overlapped with the control line is It is a two-dimensional material. Therefore, when the controller applies a voltage to the conductive layer in the control line, the number of carriers in the signal line overlapped by the control line will change, so that the operating frequency of the transistor will change, and the transistor can The signal is processed to enrich the function of the transistor.
  • the operating frequency of each transistor circuit in the related art is fixed. Therefore, when signals of multiple different frequencies need to be processed, multiple transistor circuits are required in the related art. Since the working frequency of the transistor circuit provided by the embodiment of the present invention is adjustable, when a plurality of signals of different frequencies need to be processed, the working frequency of the transistor circuit can be adjusted through a controller and a control line, so as to achieve The purpose of a transistor circuit for processing multiple signals at different frequencies.
  • a ground line and a connection line are further provided on the target side of the insulating substrate, and two ends of the connection line are respectively connected to the ground line and the second electrode of the transistor.
  • the ground line, the first signal line, and the second signal line are all located on the target side of the insulating substrate. Therefore, the insulating substrate, the ground line, and the signal lines on the insulating substrate form a coplanar waveguide structure, which can reduce the signal Parasitic capacitance, parasitic resistance, and parasitic inductance are generated on the line, thereby preventing the parasitic capacitance, parasitic resistance, and parasitic inductance from affecting the transistor circuit.
  • a portion of the control line that is not overlapped with the signal line is in contact with the insulating substrate. That is, the conductive lines other than the signal lines are not provided under portions of the control lines that are not overlapped with the signal lines, so that the conductive lines can be prevented from affecting the control lines.
  • the control line and the ground line are arranged crosswise, the ground line includes: a plurality of ground line bodies connected through a first air bridge, and between each two adjacent ground line bodies One control line is provided, and the first air bridge is located on a side of the control line away from the insulating substrate.
  • the target side of the insulating substrate is provided with two of the ground lines and two of the connection lines connected one-to-one correspondingly, the transistor includes two of the second poles, and the The two second poles are respectively connected to the two connection lines one by one, the first signal line and the second signal line are parallel to each other, the ground line is parallel to the first signal line, and the connection And the control line are perpendicular to the first signal line, and the first signal line, the second signal line, and the connection line are all located between the two ground lines, and the two The connection line is connected through a second air bridge.
  • the first pole, the second pole, the channel layer of the transistor, the first signal line, the second signal line, the ground body, and the material of the connection line are two-dimensional materials.
  • each of the conductive layer and the gate includes: a layer of a first material and a layer of a second material sequentially stacked in a direction away from the insulating substrate, and the first material is in the insulation
  • the adhesion on the substrate is F1
  • the adhesion of the second material on the insulating substrate is F2
  • the adhesion of the second material on the first material is F3, and both F1 and F3 are greater than F2. That is, the second material may be attached to the insulating substrate 01 by the first material having a larger adhesion force on the insulating substrate 01.
  • a width of a portion where the control line is overlapped is greater than a width of a portion where the control line is not overlapped.
  • a width of a portion overlapped on the signal line is greater than a width of a portion not overlapped on the signal line.
  • the first pole, the second pole, the channel layer of the transistor, the first signal line, the second signal line, the ground body, and the material of the connection line Both are flexible and transparent two-dimensional materials; the materials of the insulating substrate and the insulating layer are both flexible and transparent insulating materials, and the material of the conductive layer in the connection line is a flexible and transparent conductive material. At this time, most areas of the transistor circuit are transparent and flexible. Therefore, the transistor circuit can be applied to a wearable device.
  • a method of manufacturing a transistor circuit includes: forming a transistor, a first signal line, a second signal line, and m control lines on a target side of an insulating substrate; The control line is connected, and the controller is used to apply a voltage to the conductive layer in the control line; where m ⁇ 1, the gate of the transistor is connected to the first signal line, and the first electrode of the transistor is connected to The second signal line is connected; the control line is overlapped on at least one of the first signal line and the second signal line, and the material of the at least one signal line is a two-dimensional material
  • Each of the control lines includes an insulating layer and a conductive layer that are sequentially stacked in a direction away from the insulating substrate.
  • the forming a transistor, a first signal line, a second signal line, and m control lines on a target side of an insulating substrate includes: forming a target pattern on a metal substrate, and the target pattern includes: the A first electrode, a second electrode of the transistor, the first signal line, the second signal line, and a channel layer of the transistor; transferring the target pattern to a target side of the insulating substrate; Forming the insulating layer and a gate dielectric layer in the transistor on the insulating substrate on which the target pattern is formed; and forming on the insulating substrate on which the insulating layer and the gate dielectric layer are formed The conductive layer and the gate.
  • the target pattern further includes an initial line and a connecting line, the initial line is grounded, and two ends of the connecting line are connected to the initial line and the second pole, respectively.
  • the target pattern has a structure located on a target region in the insulating substrate, and the target region is used to form a part of the control line that is not overlapped with the signal line.
  • the method further includes: removing a structure on the target region.
  • a portion of the initial line is located on the target area.
  • the remaining portion of the initial line includes a plurality of ground line bodies.
  • the method further includes: passing the plurality of ground wire bodies in the initial line through a first The air bridge is connected to obtain a ground line; wherein the ground line and the control line are arranged crosswise, and one control line is provided between every two adjacent ground line bodies.
  • the target side of the insulating substrate is provided with two of the ground lines and two of the connection lines connected one-to-one correspondingly, the transistor includes two of the second poles, and the The two second poles are respectively connected to the two connection lines one by one, the first signal line and the second signal line are parallel to each other, the ground line is parallel to the first signal line, and the connection And the control line are perpendicular to the first signal line, and the first signal line, the second signal line, and the connection line are all located between the two ground lines;
  • the method further includes: connecting the two connection lines through a second air bridge.
  • the forming a target pattern on a metal substrate includes: forming a first pattern on the metal substrate, a material of the first pattern is a two-dimensional material, and the first pattern includes: The first pole, the second pole, the first signal line, the second signal line, the initial line, and the connection line; the first pattern is not formed in the metal substrate A second pattern is formed in a region of the substrate.
  • the material of the second pattern is a two-dimensional material.
  • the second pattern includes a channel layer of the transistor.
  • the second layer includes the insulating layer and the gate dielectric layer.
  • the channel layer in the second pattern has good contact with the first and second electrodes in the first pattern, and the carriers It can smoothly transfer between the first electrode, the second electrode, and the channel layer, and the contact resistance between the first electrode, the second electrode, and the channel layer is small.
  • the forming the conductive layer and the gate on the insulating substrate on which the insulating layer and the gate dielectric layer are formed includes: forming the insulating layer and the gate on the insulating substrate.
  • a first film layer and a second film layer are sequentially formed on the insulating substrate of the dielectric layer.
  • the material of the first film layer is a first material
  • the material of the second film layer is a second material.
  • the adhesion of the first material on the insulating substrate is F1
  • the adhesion of the second material on the insulating substrate is F2
  • the adhesion of the second material on the first material F3, F1, and F3 are all larger than F2
  • patterning the first film layer and the second film layer to obtain a conductive pattern includes: the conductive layer and the gate.
  • a width of a portion where the control line is overlapped is greater than a width of a portion where the control line is not overlapped.
  • a width of a portion overlapped on the signal line is greater than a width of a portion not overlapped on the signal line.
  • the material of the first pattern is a flexible and transparent two-dimensional material
  • the materials of the insulating substrate and the insulating layer are both flexible and transparent insulating materials
  • the material of the conductive layer in the connecting line is flexible Transparent conductive material.
  • FIG. 1 is a schematic diagram of an application scenario of a transistor circuit according to an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a transistor circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of the transistor circuit shown in FIG. 2;
  • FIG. 4A is a schematic structural diagram of another transistor circuit according to an embodiment of the present invention.
  • 4B is a schematic structural diagram of a first signal line according to an embodiment of the present invention.
  • 4C is a schematic structural diagram of a second signal line according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of relative positions of a first material and a second material according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of another transistor circuit according to an embodiment of the present invention.
  • FIG. 7 is a flowchart of a method for manufacturing a transistor circuit according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a manufacturing process of a transistor circuit according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a manufacturing process of another transistor circuit according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a manufacturing process of another transistor circuit according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of a manufacturing process of another transistor circuit according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a manufacturing process of another transistor circuit according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram of a manufacturing process of another transistor circuit according to an embodiment of the present invention.
  • FIG. 14 is a schematic diagram of a manufacturing process of another transistor circuit according to an embodiment of the present invention.
  • 15 is a schematic diagram of a manufacturing process of another transistor circuit according to an embodiment of the present invention.
  • FIG. 16 is a schematic diagram of a manufacturing process of another transistor circuit according to an embodiment of the present invention.
  • a transistor circuit is a circuit commonly used in the semiconductor field. For example, a low noise amplifier, a power amplifier, a mixer, an oscillator, and the like are all transistor circuits.
  • a transistor circuit usually includes at least a transistor and two signal lines connected to the transistor. The transistor can be connected to other units through the two signal lines, respectively.
  • FIG. 1 is a schematic diagram of an application scenario of a transistor circuit according to an embodiment of the present invention. As shown in FIG. 1, when the transistor circuit 0 is a power amplifier, a unit connected to the transistor circuit 0 through a signal line may include: a signal Source 1 and load 2.
  • each transistor circuit in the related art is fixed, that is, each transistor circuit can only process an electric signal of one frequency input from the gate and output it from the drain.
  • An embodiment of the present invention provides a transistor circuit with adjustable operating frequency. By adjusting the operating frequency of the transistor circuit, the transistor circuit can process signals of multiple frequencies.
  • FIG. 2 is a schematic structural diagram of a transistor circuit according to an embodiment of the present invention.
  • the transistor circuit 0 may include: an insulating substrate 01, a transistor 02, a first signal line 03, a second signal line 04, and m.
  • Control lines 05 and controllers (not shown in Figure 2), m ⁇ 1.
  • the transistor 02, the first signal line 03, the second signal line 04, and the m control lines 05 are all disposed on the target side of the insulating substrate 01.
  • the gate 021 of the transistor 02 is connected to the first signal line 03.
  • the pole 022 is connected to the second signal line 04.
  • the transistor 02 may include a gate, a gate dielectric layer, a source, a drain, and a channel layer, and the source and the drain are symmetrical, so the source and the drain are interchangeable.
  • one electrode of the source electrode and the drain electrode is called a first electrode, and the other electrode is called a second electrode.
  • the transistor used in the embodiment of the present invention may be a P-type transistor or an N-type transistor, which is not limited in the embodiment of the present invention.
  • a control line 05 is overlapped on at least one of the first signal line 03 and the second signal line 04.
  • the first signal line 03 and the second signal line 04 are overlapped with the control line 05, and the number of the control lines 05 overlapped with the first signal line 03 is two, and the second signal
  • the number of control lines 05 overlapped on line 04 is one.
  • the first signal line 03 is overlapped with the control line 05 and the second signal line 04 is not overlapped with the control line 05, or the first signal line 03 is not overlapped with the control line 05 and Control lines 05 are overlapped on the second signal line 04; and the number of control lines overlapped on each signal line may not be the number shown in FIG. 2.
  • the first signal line 03 and the second signal line 04 are connected.
  • the number of overlapping control lines 05 may be the same or different, which is not limited in the embodiment of the present invention.
  • the material of the at least one signal line is a two-dimensional material.
  • the two-dimensional material refers to a material in which carriers can move freely (the motion is a plane motion) only on a non-nano scale (1 nm to 100 nm) in two dimensions.
  • the two-dimensional material may be graphene, molybdenum disulfide, tungsten disulfide, boron nitride, or black phosphorus.
  • Each control line 05 may include an insulating layer 051 and a conductive layer 052 which are sequentially stacked in a direction away from the insulating substrate 01. It should be noted that the rectangular region P2 in FIG. 2 shows a cross section of the control line 05 in the rectangular region P1 that is perpendicular to the insulating substrate 01. The controller is connected to the control line 05 for applying a voltage to the conductive layer 052 in the control line 05.
  • first signal line 03 and the second signal line 04 may be an input signal line
  • the other signal line may be an output signal line
  • the input signal line may be connected to a signal source and the output signal line Can be connected to a load.
  • the first signal line 03 is an input signal line
  • the second signal line 04 is an output signal line.
  • the first signal line 03 may also be an output signal line
  • the second signal Line 04 may be an input signal line, which is not limited in the embodiment of the present invention.
  • FIG. 3 is a schematic diagram of the transistor circuit shown in FIG. 2.
  • the first signal line 03 is connected to the gate 021 and the signal source 1 of the transistor 02
  • the second signal line 04 is connected to the first pole 022 and the load 2 of the transistor, each control line 05 Both are connected to the controller 06.
  • the controller 06 can adjust the operating frequency of the transistor 02 by applying a voltage to the m control lines 05 to adjust the impedance of the signal line overlapped by the control line 05.
  • the transistor circuit provided in the embodiment of the present invention, among the first signal line and the second signal line connected to the transistor, at least one signal line is overlapped with the control line, and each of the control lines is overlapped with the control line.
  • the materials of the signal lines are two-dimensional materials. Therefore, when the controller applies a voltage to the conductive layer in the control line, the number of carriers in the signal line overlapped by the control line will change, so that the operating frequency of the transistor will change, and the transistor can The signal is processed to enrich the function of the transistor.
  • the operating frequency of each transistor circuit in the related art is fixed. Therefore, when signals of multiple different frequencies need to be processed, multiple transistor circuits are required in the related art. Since the working frequency of the transistor circuit provided by the embodiment of the present invention is adjustable, when a plurality of signals of different frequencies need to be processed, the working frequency of the transistor circuit can be adjusted through a controller and a control line, so as to achieve The purpose of a transistor circuit for processing multiple signals at different frequencies.
  • the transistor circuit provided by the embodiment of the present invention may have multiple implementable modes, and several of the implementable modes will be exemplified below.
  • the transistor circuit in the first implementable manner may be as shown in FIGS. 4A, 4B, and 4C, and the rectangular region P3 in FIG. 4A shows the enlarged transistor 02.
  • the width may be larger than the width of the portion where the control line 05 is not overlapped.
  • the width D1 and the width D2 of the portion where the control line 05 is overlapped are larger than the width D3 of the portion where the control line 05 is not overlapped.
  • a width D4 of a portion where the control line 05 is overlapped is larger than a width D5 of a portion where the control line 05 is not overlapped.
  • D3 can be equal to D5.
  • the target side of the insulating substrate 01 may further be provided with a ground wire 07 and a connection wire 08, and the ground wire 07 is grounded (the state where the ground wire 07 is grounded is not shown in FIG. 4A).
  • the terminals are respectively connected to the ground line 07 and the second pole 023 of the transistor 02. That is, the second pole 023 of the transistor 02 is connected to the ground line 07 through the connection line 06, and is further grounded.
  • the ground line 07, the first signal line 03, and the second signal line 04 are all located on the target side of the insulating substrate 01, the insulating substrate 01, the ground line 07, and the signal lines on the insulating substrate 01 form a coplanar surface. Waveguide structure. This structure can reduce the parasitic capacitance, parasitic resistance, and parasitic inductance generated on the signal line, thereby preventing the parasitic capacitance, parasitic resistance, and parasitic inductance from affecting the transistor circuit.
  • a part of the control line 05 that is not overlapped on the signal line (such as the first signal line 03 or the second signal line 04) is directly in contact with the insulating substrate 01, that is, the control line 05 is not overlapped on the signal line 05.
  • No conductive material other than the signal line is provided under a portion of the signal line, so that the conductive material can be prevented from affecting the control line 05.
  • control line 05 may be arranged to cross the ground line 07.
  • each control line 05 may only cross one ground line.
  • the ground line 07 may include a plurality of ground line bodies 071 connected through the first air bridge 09, and a control line 05 is provided between every two adjacent ground line bodies 071.
  • the first air bridge 09 may be located at The control line 05 is away from the side of the insulating substrate 01.
  • first air bridge 09 can be suspended on the control line 05 and is not in contact with the control line 05, and the first air bridge 09 can conduct electricity, and two ends of the first air bridge 09 are respectively adjacent to The two ground wire bodies 06 are overlapped; optionally, an insulating block may be further provided between the first air bridge 09 and the control line 05.
  • the target side of the insulating substrate 01 may be provided with two ground wires 07 and two connection wires 08 connected one-to-one correspondingly.
  • the transistor 02 may include two second poles 023, one first pole 022, and two gates 021, and the two second poles 023 are respectively connected to the two connection lines 08 in a one-to-one manner, and the two gates 021 are both Connected to the first signal line 03.
  • the first signal line 03 and the second signal line 04 may be parallel to each other, the ground line 07 may be parallel to the first signal line 03, the connection line 08 and the control line 05 are perpendicular to the first signal line 03, and the first signal lines 03, The second signal line 04 and the connection line 08 are both located between the two ground lines 07, and the two connection lines 08 are connected through the second air bridge 010.
  • the structure of the second air bridge 010 reference may be made to the structure of the first air bridge 09, which is not described in this embodiment of the present invention.
  • the signal line, the ground line, and the control line are all straight lines.
  • the signal line, the ground line, and the control line in the embodiment of the present invention may also be curved lines. In the embodiment of the present invention This is not limited.
  • the first pole 022, the second pole 023, the channel layer of the transistor 02 (not shown in FIG. 4A), the first signal line 03, the second signal line 04, and the ground body 071
  • the material of the connection lines 08 may be a two-dimensional material.
  • the materials of the first pole 022, the second pole 023, the channel layer of the transistor 02, the first signal line 03, the second signal line 04, the ground body 071, and the connection line 08 may be the same two-dimensional material, or For different two-dimensional materials, this embodiment of the present invention does not limit this.
  • the material of the connection line 08 may be the two-dimensional material in a metal state
  • the material of the channel layer of the transistor 02 may be a two-dimensional material in a semiconductor state.
  • the thicknesses of the first pole 022, the second pole 023, the first signal line 03, the second signal line 04, the ground body 071, and the connection line 08 may be the first thickness
  • the thickness of the channel layer may be the first thickness. Two thicknesses, the first thickness may be greater than the second thickness.
  • the first pole 022, the second pole 023, the first signal line 03, the second signal line 04, the ground body 071, and the connection line 08 may each include at least ten layers of two-dimensional materials
  • the channel layer may include a Layer two-dimensional material
  • the channel layer may also include multiple layers of two-dimensional material.
  • the material of the insulating substrate 01 may be silicon, quartz, silicon or silicon carbide on the insulating substrate.
  • the gate dielectric layer of the transistor 02 may be an insulating material.
  • the material of the gate electrode 021 in the transistor 02 and the conductive layer in the control line 05 may include one material or multiple materials.
  • the one kind of material may be platinum, copper, nickel, gold, molybdenum carbide, tantalum carbide, or tungsten carbide. Please refer to FIGS. 4A and 5.
  • the conductive layer and the gate electrode 021 each include multiple materials, the multiple materials may include: a layer of a first material C1 and a layer which are sequentially stacked in a direction away from the insulating substrate 01.
  • the second material C2, and the adhesion of the first material C1 on the insulating substrate 01 is F1; the adhesion of the second material C2 on the insulating substrate 01 is F2; Focus is F3, F1 and F3 are both greater than F2. That is, the second material may be attached to the insulating substrate 01 by the first material having a larger adhesion force on the insulating substrate 01.
  • the conductivity of the second material C2 may be greater than the conductivity of the first material C1
  • the thickness of the second material C2 may be greater than the thickness of the first material C1.
  • the first material may be titanium, the thickness of the first material may be 10 nanometers, the second material may be gold, and the thickness of the second material may be 90 nanometers.
  • the first material may also be chromium, and the second material may be copper.
  • both the insulating substrate 01 and the insulating layer 051 may be flexible transparent insulating materials, and the material of the conductive layer in the control line 05 may be a flexible transparent conductive material.
  • the materials of each structure in the transistor may also be flexible and transparent materials.
  • the material of the conductor in the transistor may be a flexible transparent conductive material
  • the channel layer in the transistor may be a flexible and transparent semiconductor
  • the insulation in the transistor may be a flexible transparent insulating material.
  • the transistor circuit in the second implementation manner can be shown in FIG. 6.
  • two control lines may not be overlapped on the first signal line, and the control line may cross more than one ground line.
  • the first signal line 03 may be overlapped with a control line 05
  • the second signal line 04 may be overlapped with a control line 05
  • the control line 05 overlapped on the first signal line 03 may cross both ground lines 06.
  • a width of a portion overlapped on the signal line may be greater than a width of a portion not overlapped on the signal line.
  • a width of a portion overlapped on the first signal line 03 may be greater than a width of a portion not overlapped on the first signal line 03.
  • the transistor circuit may have other achievable manners.
  • the target side of the insulating substrate may not be provided with a ground line and a connection line
  • the auxiliary side of the insulating substrate may be provided with a ground electrode, and the ground electrode may be grounded.
  • the auxiliary side may be opposite to the target side, and a via hole for connecting the target side and the auxiliary side may be provided on the insulating substrate.
  • the second electrode of the transistor may be connected to the ground electrode through the via hole on the insulating substrate. In this implementable manner, the ground electrode, the insulating substrate, and the signal line form a microstrip line structure.
  • the transistor circuit provided in the embodiment of the present invention, among the first signal line and the second signal line connected to the transistor, at least one signal line is overlapped with the control line, and each of the control lines is overlapped with the control line.
  • the materials of the signal lines are two-dimensional materials. Therefore, when the controller applies a voltage to the conductive layer in the control line, the number of carriers in the signal line overlapped by the control line will change, so that the operating frequency of the transistor will change, and the transistor can The signal is processed to enrich the function of the transistor.
  • FIG. 7 is a flowchart of a method for manufacturing a transistor circuit according to an embodiment of the present invention.
  • the method can be used to manufacture the above-mentioned transistor circuit.
  • the method is used to manufacture the transistor circuit shown in FIG. 4A as an example As shown in Figure 7, the method may include:
  • Step 701 Form a first pattern on a metal substrate.
  • the material of the first pattern is a two-dimensional material.
  • the first pattern includes a first electrode, a second electrode, a first signal line, a second signal line, an initial line, and a connection. line.
  • a metal substrate 31 as shown in FIG. 8 may be provided first. Since the material of the first pattern is a two-dimensional material, and the two-dimensional material is relatively easy to be attached to the metal substrate, the embodiment of the present invention needs to form the first pattern on the metal substrate.
  • a two-dimensional material layer 32 as shown in FIG. 9 may be formed on the metal substrate 31.
  • the material of the two-dimensional material layer 32 may be graphene or other two-dimensional materials. In the embodiment of the present invention, graphene is used as example.
  • the two-dimensional material layer 32 may include at least ten layers of two-dimensional material.
  • the two-dimensional material layer 32 may be directly formed on the metal substrate 31 by using a chemical vapor deposition method. Alternatively, other substrates may be formed already.
  • the two-dimensional material layer 32 is transferred to the metal substrate 31, which is not limited in the embodiment of the present invention.
  • the first pattern may include one first pole 022 of the transistor, two second poles 023 of the transistor, one first signal line 03, one second signal line 04, two initial lines 34, and two connection lines 08. These two initial lines 34 are parallel to each other, and the first pole 022, the second pole 023, the first signal line 03, the second signal line 04, and the connection line 08 may be located between the two initial lines 34.
  • the two initial lines 34 can be connected one-to-one with the two connection lines 08, the two second poles 023 can be connected one-to-one with the two connection lines 08, and the connection line 0 can be perpendicular to the initial line 34 and the first signal line 03
  • the second signal line 04 is parallel to the initial line 34.
  • one patterning process may include: photoresist coating, exposure, development, etching, and photoresist stripping.
  • the exposure may be electron beam exposure or optical exposure, and the etching may be reactive ion etching or oxygen plasma etching.
  • the photoresist may be an anti-etching resist or polymethylmethacrylate (PMMA).
  • Using a one-time patterning process to process the two-dimensional material layer includes: coating a layer of photoresist on the two-dimensional material layer, and then exposing the photoresist with a mask to make the photoresist form a fully exposed area and a non-exposed The photoresist in the fully exposed area is removed, and the photoresist in the non-exposed area is retained. Then, the corresponding area of the fully exposed area on the two-dimensional material layer is etched, and the etching is completed.
  • the first pattern can be obtained by peeling off the photoresist in the non-exposed area.
  • Step 702 Form a second pattern in a region where the first pattern is not formed on the metal substrate.
  • the material of the second pattern is a two-dimensional material, and the second pattern includes a channel layer of a transistor.
  • the two-dimensional material can be continuously deposited on the metal substrate by the chemical vapor deposition method. Since the two-dimensional material is easier to adhere to the metal substrate and more difficult to adhere to other materials, it is difficult to adhere to the two-dimensional material.
  • a second pattern 35 shown in FIG. 11 is formed in a region of the metal substrate where the first pattern is not formed, and the first pattern is not covered with the two-dimensional material. .
  • the second pattern 35 may be located in all regions on the metal substrate where the first pattern is not formed, and the second pattern 35 may include a channel layer 36 of a transistor. Since the second pattern is directly deposited on the metal substrate on which the first pattern is formed, the channel layer 36 in the second pattern is in good contact with the first and second electrodes in the first pattern and carries current. The electrons can be smoothly transmitted between the first electrode, the second electrode, and the channel layer, and the contact resistance between the first electrode, the second electrode, and the channel layer is small.
  • Step 703 Transfer the first pattern and the second pattern to a target side of the insulating substrate.
  • the material of the insulating substrate may be silicon, quartz, silicon or silicon carbide on the insulating substrate.
  • the target pattern composed of the first pattern and the second pattern may be transferred to the target side of the insulating substrate 01 shown in FIG. 12 by a hot-press transfer method or a transfer method based on PMMA.
  • Step 704 Remove the structure on the target area in the insulating substrate.
  • the first region on the insulating substrate 01 is used to form a control line
  • the target region in the first region is used to form a portion of the control line that is not overlapped with the signal line.
  • Both the first pattern and the second pattern have structures located on the target region in the insulating substrate.
  • the initial line in the first pattern includes a portion on the target region
  • the second pattern also includes a portion on the target region. .
  • the remaining pattern may include a remaining portion of the initial line, and the remaining portion of the initial line may include a plurality of ground line bodies 071.
  • a photoresist layer may be first coated on the insulating substrate formed with the target pattern, and then the photoresist layer formed on the target area is removed by exposure, and the remaining photoresist layer is used. As a mask, the structure formed on the target area is etched away. Finally, the remaining photoresist layer is peeled off to obtain the remaining pattern.
  • Step 705 Form an insulating layer and a gate dielectric layer in the transistor on the insulating substrate on which the target pattern is formed.
  • an atomic layer deposition method may be used to form an insulating material layer on the insulating substrate 01 having the remaining pattern formed, and pattern the insulating material layer to obtain a control line to be formed.
  • the insulating layer 051 and the gate dielectric layer 38 in the transistor may be used to form an insulating material layer on the insulating substrate 01 having the remaining pattern formed, and pattern the insulating material layer to obtain a control line to be formed.
  • the material of the insulating material layer may be alumina, ytterbium hydroxide, or yttrium oxide.
  • the process of patterning the insulating material layer refer to the patterning process of step 701, which is not described in this embodiment of the invention.
  • Step 706 A conductive layer and a gate are formed on the insulating substrate on which the insulating layer and the gate dielectric layer are formed.
  • the conductive layer and the gate may be formed in the same layer, and both the conductive layer and the gate may be made of one material or multiple materials.
  • the first film layer and the second film layer may be sequentially formed on the insulating substrate 01 having the insulating layer and the gate dielectric layer formed by deposition.
  • the material of the first film layer is the first material
  • the material of the second film layer is the second material
  • the adhesion of the first material on the insulating substrate 01 is F1
  • the adhesion of the second material on the insulating substrate 01 is The focus is F2
  • the adhesion of the second material to the first material is F3, and both F1 and F3 are greater than F2. That is, the second material may be attached to the insulating substrate 01 by the first material having a larger adhesion force on the insulating substrate 01.
  • a patterning process may be performed on the first film layer and the second film layer to obtain a conductive layer 052 and a gate electrode 021 as shown in FIG. 15.
  • a process of patterning the first film layer and the second film layer reference may be made to the patterning process of step 701, which is not described in this embodiment of the present invention.
  • Step 707 Remove the portion of the second pattern other than the channel layer.
  • a portion other than the channel layer in the second pattern may be removed, so that the insulating substrate 01 is exposed.
  • Step 708 Connect multiple ground wire bodies in the initial line through a first air bridge to obtain a ground wire, and connect the two connection wires through a second air bridge.
  • step 703 since a part of the structure of the initial line is removed in step 703, a plurality of ground line bodies are formed. Therefore, in step 708, a plurality of ground line bodies 071 can be connected through the first air bridge 09. . In addition, the two connection lines 08 may be connected through the second air bridge 010.
  • an insulating block may be first formed on a region on the insulating substrate where an air bridge (such as the first air bridge and the second air bridge) is to be formed. Then, a conductive material layer is formed on the insulating substrate, and the conductive material layer is patterned to obtain a first air bridge and a second air bridge.
  • an air bridge such as the first air bridge and the second air bridge
  • Step 709 Connect the controller to the control line.
  • the transistor circuit manufactured by the method provided by the embodiment of the present invention among the first signal line and the second signal line connected to the transistor, at least one signal line is overlapped with a control line, and each overlap
  • the material of the signal line with the control line is a two-dimensional material. Therefore, when the controller applies a voltage to the conductive layer in the control line, the number of carriers in the signal line overlapped by the control line will change, so that the operating frequency of the transistor changes, and the transistor can respond to signals of different frequencies. Processing to enrich the functions of the transistor.
  • the method embodiments provided by the embodiments of the present invention can be cross-referenced with the corresponding embodiments of the transistor circuit, which is not limited in the embodiments of the present invention.
  • the order of the steps of the method embodiments provided by the embodiments of the present invention can be appropriately adjusted, and the steps can be increased or decreased according to the situation. Any person skilled in the art can easily think of changes within the technical scope disclosed by the present invention. The methods should all be covered by the protection scope of the present invention, so they will not be described again.

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Abstract

一种晶体管电路（0）及其制造方法，晶体管电路（0）包括：绝缘衬底（01），晶体管（02）、第一信号线（03）、第二信号线（04）和m条控制线（05）均设置在绝缘衬底（01）的目标侧，晶体管（02）的栅极（021）与第一信号线（03）连接，晶体管（02）的第一极（022）与第二信号线（04）连接；第一信号线（03）和第二信号线（04）中的至少一条信号线上搭接有控制线（05），且至少一条信号线的材料均为二维材料，每条控制线（05）包括：沿远离绝缘衬底（01）的方向依次叠加的绝缘层（051）和导电层（052），控制器（06）与控制线（05）连接，用于向控制线（05）中的导电层（052）施加电压。上述晶体管电路（0）解决了晶体管电路（0）的功能较单一的问题，丰富了晶体管电路（0）的功能。

Description

晶体管电路及其制造方法 技术领域
本申请涉及半导体技术领域，特别涉及一种晶体管电路及其制造方法。
背景技术
随着半导体技术的发展，晶体管电路(如功率放大器)得到了广泛的应用。
相关技术中，晶体管电路通常包括：绝缘衬底，以及设置在绝缘衬底上的晶体管、输入信号线和输出信号线。其中，晶体管的栅极通过输入信号线与信号源连接，晶体管的第一极通过输出信号线与负载连接，晶体管的第二极接地。晶体管能够对信号源输入的某种频率的信号的幅值进行调整，并将调整后的信号输出至负载。
但是，相关技术中晶体管电路中的晶体管只能够对一种频率的信号的幅值进行调整，因此，晶体管电路的功能较单一。
发明内容
本申请提供了一种晶体管电路及其制造方法，可以解决晶体管电路的功能较单一的问题。所述技术方案如下：
一方面，提供了一种晶体管电路，所述晶体管电路包括：绝缘衬底、晶体管、第一信号线、第二信号线、m条控制线和控制器，m≥1，所述晶体管、所述第一信号线、所述第二信号线和所述m条控制线均设置在所述绝缘衬底的目标侧，所述晶体管的栅极与所述第一信号线连接，所述晶体管的第一极与所述第二信号线连接；所述第一信号线和所述第二信号线中的至少一条信号线上搭接有所述控制线，且所述至少一条信号线的材料均为二维材料，每条所述控制线包括：沿远离所述绝缘衬底的方向依次叠加的绝缘层和导电层，所述控制器与所述控制线连接，用于向所述控制线中的导电层施加电压。
本发明实施例提供的晶体管电路中，连接晶体管的第一信号线和第二信号线中，存在至少一条信号线上搭接有控制线，且每个搭接有控制线的信号线的材料均为二维材料。因此，在控制器向控制线中的导电层施加电压时，该控制线搭接的信号线中的载流子数量会发生改变，从而使得晶体管的工作频率发生改变，使晶体管能够对不同频率的信号进行处理，丰富了晶体管的功能。
另外，相关技术中的每个晶体管电路的工作频率固定，因此，在需要对多种不同频率的信号进行处理时，相关技术中需要采用多个晶体管电路。而本发明实施例提供的晶体管电路由于工作频率可调，因此，在需要对多个不同频率的信号进行处理时，可以通过控制器和控制线对晶体管电路的工作频率进行调整，从而能够实现通过一个晶体管电路对多个不同频率的信号进行处理的目的。
可选的，所述绝缘衬底的所述目标侧还设置有地线和连接线，所述连接线的两端分别连接所述地线和所述晶体管的第二极。该地线、第一信号线和第二信号线均位于绝缘衬底 的目标侧，因此，绝缘衬底、地线以及绝缘衬底上的信号线形成共面波导结构，这种结构能够减少信号线上产生寄生电容、寄生电阻和寄生电感，进而防止该寄生电容、寄生电阻和寄生电感对晶体管电路的影响。
可选的，所述控制线中未搭接在所述信号线上的部分与所述绝缘衬底接触。也即，控制线中未搭接在信号线上的部分下并未设置有除信号线之外的其他导电材料，从而能够防止这些导电材料对控制线造成的影响。
可选的，所述控制线与所述地线交叉排布，所述地线包括：通过第一空气桥连接的多个地线本体，且每两个相邻的所述地线本体之间设置有一条所述控制线，所述第一空气桥位于所述控制线远离所述绝缘衬底的一侧。
可选的，所述绝缘衬底的所述目标侧设置有：一一对应连接的两条所述地线和两条所述连接线，所述晶体管包括两个所述第二极，所述两个第二极分别与两条所述连接线一一对应连接，所述第一信号线与所述第二信号线相互平行，所述地线平行于所述第一信号线，所述连接线和所述控制线均垂直于所述第一信号线，且所述第一信号线、所述第二信号线和所述连接线均位于两条所述地线之间，两条所述连接线通过第二空气桥连接。
可选的，所述第一极、所述第二极、所述晶体管的沟道层、所述第一信号线、所述第二信号线、所述地线本体和所述连接线的材料均为二维材料。
可选的，所述导电层和所述栅极均包括：沿远离所述绝缘衬底的方向依次叠加的一层第一材料和一层第二材料，且所述第一材料在所述绝缘衬底上的附着力为F1，所述第二材料在所述绝缘衬底上的附着力为F2，所述第二材料在所述第一材料上的附着力为F3，F1和F3均大于F2。也即，第二材料可以通过在绝缘衬底01上的附着力较大的第一材料附着在绝缘衬底01上。
可选的，在至少一条搭接有所述控制线的信号线中，搭接有所述控制线的部分的宽度大于未搭接有所述控制线的部分的宽度。
可选的，在所述m条控制线中的每条控制线中，搭接在信号线上的部分的宽度大于未搭接在信号线上的部分的宽度。
可选的，所述第一极、所述第二极、所述晶体管的沟道层、所述第一信号线、所述第二信号线、所述地线本体和所述连接线的材料均为柔性透明的二维材料；所述绝缘衬底和所述绝缘层的材料均为柔性透明绝缘材料，所述连接线中的导电层的材料为柔性透明导电材料。此时，该晶体管电路中的大部分区域具有透明柔性的特点，因此，该晶体管电路可以适用于可穿戴器件。
另一方面，提供了一种晶体管电路的制造方法，所述方法包括：在绝缘衬底的目标侧形成晶体管、第一信号线、第二信号线和m条控制线；将控制器与所述控制线连接，所述控制器用于向所述控制线中的导电层施加电压；其中，m≥1，所述晶体管的栅极与所述第一信号线连接，所述晶体管的第一极与所述第二信号线连接；所述第一信号线和所述第二信号线中的至少一条信号线上搭接有所述控制线，且所述至少一条信号线的材料均为二维材料，每条所述控制线包括：沿远离所述绝缘衬底的方向依次叠加的绝缘层和导电层。
可选的，所述在绝缘衬底的目标侧形成晶体管、第一信号线、第二信号线和m条控制线，包括：在金属衬底上形成目标图案，所述目标图案包括：所述第一极、所述晶体管的第二极、所述第一信号线、所述第二信号线和所述晶体管的沟道层；将所述目标图案转移 至所述绝缘衬底的目标侧；在形成有所述目标图案的所述绝缘衬底上形成所述绝缘层和所述晶体管中的栅介质层；在形成有所述绝缘层和所述栅介质层的所述绝缘衬底上形成所述导电层和所述栅极。
可选的，所述目标图案还包括：初始线和连接线，所述初始线接地，且所述连接线的两端分别连接所述初始线和所述第二极。
可选的，所述目标图案中存在位于所述绝缘衬底中目标区域上的结构，所述目标区域用于形成所述控制线中未搭接在所述信号线上的部分，在形成有所述目标图案的所述绝缘衬底上形成所述绝缘层和所述晶体管中的栅介质层之前，所述方法还包括：去除所述目标区域上的结构。
可选的，所述初始线中存在位于所述目标区域上的部分，在去除所述目标区域上的结构之后，所述初始线的剩余部分包括：多个地线本体，在形成有所述绝缘层和所述栅介质层的所述绝缘衬底上形成所述导电层和所述栅极之后，所述方法还包括：将所述初始线中的所述多个地线本体通过第一空气桥连接以得到地线；其中，所述地线与所述控制线交叉排布，且每两个相邻的所述地线本体之间设置有一条所述控制线。
可选的，所述绝缘衬底的所述目标侧设置有：一一对应连接的两条所述地线和两条所述连接线，所述晶体管包括两个所述第二极，所述两个第二极分别与两条所述连接线一一对应连接，所述第一信号线与所述第二信号线相互平行，所述地线平行于所述第一信号线，所述连接线和所述控制线均垂直于所述第一信号线，且所述第一信号线、所述第二信号线和所述连接线均位于两条所述地线之间；在形成有所述绝缘层和所述栅介质层的所述绝缘衬底上形成所述导电层和所述栅极之后，所述方法还包括：将两条所述连接线通过第二空气桥连接。
可选的，所述在金属衬底上形成目标图案，包括：在所述金属衬底上形成第一图案，所述第一图案的材料均为二维材料，所述第一图案包括：所述第一极、所述第二极、所述第一信号线、所述第二信号线、所述初始线和所述连接线；在所述金属衬底中未形成有所述第一图案的区域内形成第二图案，所述第二图案的材料为二维材料，所述第二图案包括所述晶体管的沟道层；在形成有所述绝缘层和所述栅介质层的所述绝缘衬底上形成所述导电层和所述栅极之后，所述方法还包括：去除所述第二图案中除所述沟道层之外的部分。
由于第二图案是在形成有第一图案的金属衬底上直接沉积得到的，因此第二图案中的沟道层和第一图案中的第一极、第二极的接触良好，载流子能够在第一极、第二极和沟道层之间顺利的传输，第一极、第二极和沟道层之间的接触电阻较小。
可选的，所述在形成有所述绝缘层和所述栅介质层的所述绝缘衬底上形成所述导电层和所述栅极，包括：在形成有所述绝缘层和所述栅介质层的所述绝缘衬底上依次形成第一膜层和第二膜层，其中，所述第一膜层的材料为第一材料，所述第二膜层的材料为第二材料，所述第一材料在所述绝缘衬底上的附着力为F1，所述第二材料在所述绝缘衬底上的附着力为F2，所述第二材料在所述第一材料上的附着力为F3，F1和F3均大于F2；对所述第一膜层和所述第二膜层进行图案化处理以得到导电图案，所述导电图案包括：所述导电层和所述栅极。
可选的，在至少一条搭接有所述控制线的信号线中，搭接有所述控制线的部分的宽度大于未搭接有所述控制线的部分的宽度。
可选的，在所述m条控制线中的至少一条控制线中，搭接在信号线上的部分的宽度大于未搭接在信号线上的部分的宽度。
可选的，所述第一图案的材料为柔性透明的二维材料，所述绝缘衬底和所述绝缘层的材料均为柔性透明绝缘材料，所述连接线中的导电层的材料为柔性透明导电材料。
附图说明
图1为本发明实施例提供的一种晶体管电路的应用场景示意图；
图2为本发明实施例提供的一种晶体管电路的结构示意图；
图3为图2所示的晶体管电路的原理图；
图4A为本发明实施例提供的另一种晶体管电路的结构示意图；
图4B为本发明实施例提供的一种第一信号线的结构示意图；
图4C为本发明实施例提供的一种第二信号线的结构示意图；
图5为本发明实施例提供的一种第一材料和第二材料的相对位置示意图；
图6为本发明实施例提供的另一种晶体管电路的结构示意图；
图7为本发明实施例提供的一种晶体管电路的制造方法的流程图；
图8为本发明实施例提供的一种晶体管电路的制造过程示意图；
图9为本发明实施例提供的另一种晶体管电路的制造过程示意图；
图10为本发明实施例提供的另一种晶体管电路的制造过程示意图；
图11为本发明实施例提供的另一种晶体管电路的制造过程示意图；
图12为本发明实施例提供的另一种晶体管电路的制造过程示意图；
图13为本发明实施例提供的另一种晶体管电路的制造过程示意图；
图14为本发明实施例提供的另一种晶体管电路的制造过程示意图；
图15为本发明实施例提供的另一种晶体管电路的制造过程示意图；
图16为本发明实施例提供的另一种晶体管电路的制造过程示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
晶体管电路是半导体领域内常见的一种电路，如低噪声放大器、功率放大器、混频器、振荡器等等均为晶体管电路。晶体管电路通常至少包括晶体管，以及与晶体管连接的两条信号线，晶体管可以通过这两条信号线分别与其他单元连接。示例的，图1为本发明实施例提供的一种晶体管电路的应用场景示意图，如图1所示，当晶体管电路0为功率放大器时，与晶体管电路0通过信号线连接的单元可以包括：信号源1和负载2。
需要说明的是，相关技术中每个晶体管电路的工作频率固定，也即每个晶体管电路仅能够对从栅极输入的一种频率的电信号进行处理，并从漏极输出。本发明实施例提供了一种工作频率可调节的晶体管电路，通过调节该晶体管电路的工作频率，能够使得该晶体管电路对多种频率的信号均能够进行处理。
图2为本发明实施例提供的一种晶体管电路的结构示意图，如图2所示，晶体管电路0 可以包括：绝缘衬底01、晶体管02、第一信号线03、第二信号线04、m条控制线05和控制器(图2中未示出)，m≥1。
晶体管02、第一信号线03、第二信号线04和m条控制线05均设置在绝缘衬底01的目标侧，晶体管02的栅极021与第一信号线03连接，晶体管02的第一极022与第二信号线04连接。需要说明的是，晶体管02可以包括：栅极、栅介质层、源极、漏极和沟道层，且源极和漏极是对称的，所以其源极、漏极是可以互换的。本发明实施例中，将源极和漏极中的一个电极称为第一极，另一个电极称为第二极。此外，本发明实施例所采用的晶体管可以为P型晶体管或N型晶体管，本发明实施例对此不作限定。
第一信号线03和第二信号线04中的至少一条信号线上搭接有控制线05。需要说明的是，图2中以第一信号线03和第二信号线04上均搭接有控制线05，且第一信号线03上搭接的控制线05的数量为2，第二信号线04上搭接的控制线05的数量均为1为例。可选的，还可以是第一信号线03上搭接有控制线05而第二信号线04上未搭接有控制线05，或者，第一信号线03上未搭接有控制线05而第二信号线04上搭接有控制线05；并且，每条信号线上搭接的控制线的数量也可以不为图2所示的数量，第一信号线03和第二信号线04上搭接的控制线05的数量可以相同也可以不相同，本发明实施例对此不作限定。
该至少一条信号线(搭接有控制线的信号线)的材料均为二维材料。其中，二维材料是指载流子仅可在两个维度的非纳米尺度(1纳米至100纳米)上自由运动(该运动为平面运动)的材料。可选的，二维材料可以为石墨烯、二硫化钼、二硫化钨、氮化硼或黑磷等材料。
每条控制线05可以包括：沿远离绝缘衬底01的方向依次叠加的绝缘层051和导电层052。需要说明的是，图2中的矩形区域P2中示出了矩形区域P1内的控制线05的垂直于绝缘衬底01的截面。控制器与控制线05连接，用于向控制线05中的导电层052施加电压。
需要说明的是，第一信号线03和第二信号线04中的一个信号线可以为输入信号线，另一个信号线可以为输出信号线，且输入信号线可以与信号源连接，输出信号线可以与负载连接。本发明实施例中以第一信号线03为输入信号线，且第二信号线04为输出信号线为例，可选的，该第一信号线03也可以为输出信号线，且第二信号线04可以为输入信号线，本发明实施例对此不作限定。
进一步的，图3为图2所示的晶体管电路的原理图。请结合图2和图3，第一信号线03分别与晶体管02的栅极021以及信号源1连接，第二信号线04分别与晶体管的第一极022和负载2连接，每条控制线05均与控制器06连接。控制器06可以通过向m条控制线05施加电压，以调节该控制线05搭接的信号线的阻抗，从而调整晶体管02的工作频率。
综上所述，本发明实施例提供的晶体管电路中，连接晶体管的第一信号线和第二信号线中，存在至少一条信号线上搭接有控制线，且每条搭接有控制线的信号线的材料均为二维材料。因此，在控制器向控制线中的导电层施加电压时，该控制线搭接的信号线中的载流子数量会发生改变，从而使得晶体管的工作频率发生改变，使晶体管能够对不同频率的信号进行处理，丰富了晶体管的功能。
另外，相关技术中的每个晶体管电路的工作频率固定，因此，在需要对多种不同频率的信号进行处理时，相关技术中需要采用多个晶体管电路。而本发明实施例提供的晶体管电路由于工作频率可调，因此，在需要对多个不同频率的信号进行处理时，可以通过控制 器和控制线对晶体管电路的工作频率进行调整，从而能够实现通过一个晶体管电路对多个不同频率的信号进行处理的目的。
本发明实施例提供的晶体管电路可以具有多种可实现方式，以下将对其中的几种可实现方式进行举例说明。
第一种可实现方式中的晶体管电路可以如图4A、图4B和图4C所示，且图4A中的矩形区域P3示出了放大后的晶体管02。
可选的，在图2所示的晶体管电路的基础上，如图4A、图4B和图4C所示，在至少一条搭接有控制线05的信号线中，搭接有控制线的部分的宽度可以大于未搭接有控制线05的部分的宽度。例如，在第一信号线03中，搭接有控制线05的部分的宽度D1和宽度D2均大于未搭接有控制线05的部分的宽度D3。在第二信号线04中，搭接有控制线05的部分的宽度D4大于未搭接有控制线05的部分的宽度D5。D3可以等于D5。
可选的，该绝缘衬底01的目标侧还可以设置有地线07和连接线08，地线07接地(图4A中未示出该地线07接地的状态)，且连接线08的两端分别连接地线07和晶体管02的第二极023。也即，晶体管02的第二极023通过连接线06连接至地线07，进而接地。另外，由于地线07、第一信号线03和第二信号线04均位于绝缘衬底01的目标侧，因此，绝缘衬底01、地线07以及绝缘衬底01上的信号线形成共面波导结构，这种结构能够减少信号线上产生寄生电容、寄生电阻和寄生电感，进而防止该寄生电容、寄生电阻和寄生电感对晶体管电路的影响。
可选的，控制线05中未搭接在信号线(如第一信号线03或第二信号线04)上的部分与绝缘衬底01直接接触，也即，控制线05中未搭接在信号线上的部分下并未设置有除信号线之外的其他导电材料，从而能够防止这些导电材料对控制线05造成的影响。
示例的，控制线05可以与地线07交叉排布，可选的，在图4A所示的晶体管电路中，每条控制线05可以仅与一条地线交叉。该地线07可以包括：通过第一空气桥09连接的多个地线本体071，且每两个相邻的地线本体071之间设置有一条控制线05，该第一空气桥09可以位于控制线05远离绝缘衬底01的一侧。需要说明的是，该第一空气桥09可以悬空在控制线05上，并与控制线05不接触，且第一空气桥09能够导电，该第一空气桥09的两端分别与相邻的两个地线本体06搭接；可选的，第一空气桥09与控制线05之间还可以设置有绝缘块。
请继续参考图4A，绝缘衬底01的目标侧可以设置有：一一对应连接的两条地线07和两条连接线08。该晶体管02可以包括两个第二极023、一个第一极022和两个栅极021，且这两个第二极023分别与两条连接线08一一对应连接，两个栅极021均与第一信号线03连接。第一信号线03与第二信号线04可以相互平行，地线07可以平行于第一信号线03，连接线08和控制线05均垂直于第一信号线03，且第一信号线03、第二信号线04和连接线08均位于两条地线07之间，两条连接线08通过第二空气桥010连接。该第二空气桥010的结构可以参考第一空气桥09的结构，本发明实施例在此不做赘述。
需要说明的是，图4A中以信号线、地线以及控制线均为直线为例，可选的，本发明实施例中的信号线、地线以及控制线还可以为曲线，本发明实施例对此不作限定。
进一步的，在该晶体管电路中，第一极022、第二极023、晶体管02的沟道层(图4A 中未标出)、第一信号线03、第二信号线04、地线本体071和连接线08的材料均可以为二维材料。且第一极022、第二极023、晶体管02的沟道层、第一信号线03、第二信号线04、地线本体071和连接线08的材料可以为同一种二维材料，也可以为不同的二维材料，本发明实施例对此不作限定。另外，对于具有金属状态和半导体状态这两种状态的二维材料(如二硫化钼)，第一极022、第二极023、第一信号线03、第二信号线04、地线本体071和连接线08的材料可以为金属状态的该二维材料，晶体管02的沟道层的材料可以为半导体状态的二维材料。
可选的，第一极022、第二极023、第一信号线03、第二信号线04、地线本体071和连接线08的厚度可以为第一厚度，沟道层的厚度可以为第二厚度，该第一厚度可以大于第二厚度。示例的，第一极022、第二极023、第一信号线03、第二信号线04、地线本体071和连接线08均可以包括至少十层二维材料，该沟道层可以包括一层二维材料，可选的，沟道层也可以包括多层二维材料。
绝缘衬底01的材料可以为硅、石英、绝缘衬底上的硅或碳化硅等。晶体管02的栅介质层可以为绝缘材料。晶体管02中的栅极021和控制线05中的导电层的材料均可以包括：一种材料或者多种材料。该一种材料可以为铂、铜、镍、金、碳化钼、碳化钽或碳化钨等。请结合图4A和图5，当该导电层和栅极021均包括多种材料时，该多种材料可以包括：沿远离绝缘衬底01的方向依次叠加的一层第一材料C1和一层第二材料C2，且第一材料C1在绝缘衬底01上的附着力为F1，第二材料C2在绝缘衬底01上的附着力为F2，第二材料C2在第一材料C1上的附着力为F3，F1和F3均大于F2。也即，第二材料可以通过在绝缘衬底01上的附着力较大的第一材料附着在绝缘衬底01上。可选的，该第二材料C2的导电率可以大于第一材料C1的导电率，且该第二材料C2的厚度可以大于第一材料C1的厚度。示例的，该第一材料可以为钛，且第一材料的厚度可以为10纳米，该第二材料可以为金，且第二材料的厚度可以为90纳米。可选的，第一材料也可以为铬，第二材料可以为铜。
另外，当第一极022、第二极023、晶体管02的沟道层、第一信号线03、第二信号线04、地线本体071和连接线08的材料均可以为透明柔性的二维材料(如石墨烯)时，绝缘衬底01和绝缘层051的材料均可以为柔性透明绝缘材料，该控制线05中的导电层的材料可以为柔性透明导电材料，此时，该晶体管电路中的大部分区域具有透明柔性的特点，因此，该晶体管电路可以适用于可穿戴器件。可选的，晶体管中的各个结构的材料也可以均为柔性透明材料，如晶体管中的导体的材料可以为柔性透明导电材料，晶体管中的沟道层可以为柔性透明的半导体，晶体管中的绝缘材料可以为柔性透明绝缘材料。
第二种可实现方式中的晶体管电路可以如图6所示。在图4A所示的晶体管电路的基础上，第一信号线上还可以不搭接有两条控制线，且控制线可以不止与一条地线交叉。
如图6所示，该第一信号线03上可以搭接有一条控制线05，第二信号线04上可以搭接有一条控制线05。并且，第一信号线03上搭接的控制线05可以与两条地线06均交叉。
可选的，在晶体管电路中的至少一条控制线05中，搭接在信号线上的部分的宽度可以大于未搭接在信号线上的部分的宽度。例如，在搭接在第一信号线03上的控制线05中，搭接在第一信号线03上的部分的宽度可以大于未搭接在第一信号线03上的部分的宽度。
另外，晶体管电路还可以具有其他可实现方式，例如，绝缘衬底的目标侧还可以未设 置有地线和连接线，并且，绝缘衬底的辅助侧可以设置有地电极，地电极可以接地。其中，该辅助侧可以与目标侧相对，绝缘衬底上还可以设置有用于连通目标侧和辅助侧的过孔，晶体管的第二极可以通过绝缘衬底上的过孔与地电极连接。在这种可实现方式中，地电极、绝缘衬底和信号线形成微带线结构。
综上所述，本发明实施例提供的晶体管电路中，连接晶体管的第一信号线和第二信号线中，存在至少一条信号线上搭接有控制线，且每个搭接有控制线的信号线的材料均为二维材料。因此，在控制器向控制线中的导电层施加电压时，该控制线搭接的信号线中的载流子数量会发生改变，从而使得晶体管的工作频率发生改变，使晶体管能够对不同频率的信号进行处理，丰富了晶体管的功能。
图7为本发明实施例提供的一种晶体管电路的制造方法的流程图，该方法可以用于制造上述晶体管电路，本发明实施例以该方法用于制造如图4A所示的晶体管电路为例，如图7所示，该方法可以包括：
步骤701、在金属衬底上形成第一图案，第一图案的材料为二维材料，第一图案包括：第一极、第二极、第一信号线、第二信号线、初始线和连接线。
在制造晶体管电路时，可以首先提供如图8所示的金属衬底31。由于第一图案的材料为二维材料，且二维材料较容易附着在金属衬底上，因此，本发明实施例中需要在金属衬底上形成该第一图案。
之后，可以在该金属衬底31上形成如图9所示的二维材料层32，该二维材料层32的材料可以为石墨烯或者其他二维材料，本发明实施例中以石墨烯为例。示例的，该二维材料层32可以包括至少十层二维材料。其中，在金属衬底31上形成二维材料层32时，可以直接采用化学气相沉积法在金属衬底31上形成二维材料层32，可选的，也可以将其他衬底上已经形成好的二维材料层32转移至金属衬底31，本发明实施例对此不作限定。
最后，可以采用一次构图工艺对该二维材料层32进行图案化处理，以得到如图10所示的第一图案。第一图案可以包括：晶体管的一个第一极022、晶体管的两个第二极023、一条第一信号线03、一条第二信号线04、两条初始线34和两条连接线08。这两条初始线34互相平行，第一极022、第二极023、第一信号线03、第二信号线04和连接线08均可以位于两条初始线34之间。两条初始线34可以与两条连接线08一一对应连接，两个第二极023分别与两条连接线08一一对应连接，连接线0可以垂直于初始线34，第一信号线03与第二信号线04均平行于初始线34。
其中，一次构图工艺可以包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离，曝光可以为电子束曝光或光学曝光，刻蚀可以为反应离子刻蚀或氧等离子刻蚀，光刻胶可以为抗刻蚀的胶或聚甲基丙烯酸甲酯(polymethyl methacrylate，PMMA)。采用一次构图工艺对二维材料层进行处理包括：在二维材料层上涂覆一层光刻胶，然后采用掩膜版对光刻胶进行曝光，使光刻胶形成完全曝光区和非曝光区，之后采用显影工艺进行处理，使完全曝光区的光刻胶被去除，非曝光区的光刻胶保留，之后对完全曝光区在二维材料层上的对应区域进行刻蚀，刻蚀完毕后剥离非曝光区的光刻胶即可得到第一图案。
步骤702、在金属衬底中未形成有第一图案的区域内形成第二图案，第二图案的材料为二维材料，第二图案包括晶体管的沟道层。
在形成第一图案后，可以在金属衬底上继续采用化学气相沉积法沉积二维材料，由于二维材料较容易附着在金属衬底上，而较难附着在其他材质上，因此。在步骤702中沉积二维材料的过程中，金属衬底中未形成有第一图案的区域内形成了如图11所示的第二图案35，且第一图案上并未覆盖有二维材料。
如图11所示，第二图案35可以位于金属衬底上未形成有第一图案的所有区域，且该第二图案35可以包括晶体管的沟道层36。由于第二图案是在形成有第一图案的金属衬底上直接沉积得到的，因此第二图案中的沟道层36和第一图案中的第一极、第二极的接触良好，载流子能够在第一极、第二极和沟道层之间顺利的传输，第一极、第二极和沟道层之间的接触电阻较小。
步骤703、将第一图案和第二图案转移至绝缘衬底的目标侧。
示例的，绝缘衬底的材料可以为硅、石英、绝缘衬底上的硅或碳化硅等。在步骤703中，可以通过热压转移法或基于PMMA的转移方法，将第一图案和第二图案组成的目标图案转移至如图12所示的绝缘衬底01的目标侧。
步骤704、去除绝缘衬底中目标区域上的结构。
需要说明的是，绝缘衬底01上的第一区域用于形成控制线，且该第一区域中的目标区域用于形成控制线中未搭接在信号线上的部分。第一图案和第二图案中均存在位于绝缘衬底中目标区域上的结构，如第一图案中的初始线中存在位于目标区域上的部分，第二图案中也存在位于目标区域上的部分。
为了防止待形成的控制线下存在除信号线之外的其他导电材料，进而防止这些导电材料对待形成的控制线造成的影响，在步骤704中需要将目标区域上的结构进行去除，以得到如图13所示的剩余图案。该剩余图案可以包括：初始线的剩余部分，该初始线中的剩余部分可以包括：多个地线本体071。示例的，步骤704中可以首先在形成有目标图案的绝缘衬底上涂覆光刻胶层，之后采用曝光的方式去除该目标区域上形成的光刻胶层，并以剩余的光刻胶层为掩膜，将该目标区域上形成的结构刻蚀掉，最后，剥离剩余的光刻胶层，即可得到剩余图案。
步骤705、在形成有目标图案的绝缘衬底上形成绝缘层和晶体管中的栅介质层。
如图14所示，在步骤705中可以采用原子层沉积法在形成有剩余图案的绝缘衬底01上形成绝缘材质层，并对该绝缘材质层进行图案化处理，以得到待形成的控制线中的绝缘层051和晶体管中的栅介质层38。
绝缘材质层的材质可以为氧化铝、氢氧化铪或氧化钇等，对该绝缘材质层进行图案化处理的过程可以参考步骤701的图案化处理过程，本发明实施例在此不做赘述。
步骤706、在形成有绝缘层和栅介质层的绝缘衬底上形成导电层和栅极。
可选的，该导电层和栅极可以同层形成，且导电层和栅极均可以由一种材料制成，也可以由多种材料制成。
示例的，在步骤706中，可以在形成有绝缘层和栅介质层的绝缘衬底01上采用沉积的方式依次形成第一膜层和第二膜层。其中，第一膜层的材料为第一材料，第二膜层的材料为第二材料，第一材料在绝缘衬底01上的附着力为F1，第二材料在绝缘衬底01上的附着力为F2，第二材料在第一材料上的附着力为F3，F1和F3均大于F2。也即，第二材料可以通过在绝缘衬底01上的附着力较大的第一材料附着在绝缘衬底01上。
在形成第一膜层和第二膜层之后，可以对第一膜层和第二膜层进行图案化处理以得到如图15所示的导电层052和栅极021。对该第一膜层和第二膜层进行图案化处理的过程可以参考步骤701的图案化处理过程，本发明实施例在此不做赘述。
步骤707、去除第二图案中除沟道层之外的部分。
如图16所示，在形成栅极021和导电层052后，还可以去除第二图案中除沟道层之外的部分，从而露出绝缘衬底01。
步骤708、将初始线中的多个地线本体通过第一空气桥连接以得到地线，以及将两条连接线通过第二空气桥连接。
如图4A所示，由于在步骤703中去除了初始线中的部分结构，形成了多个地线本体，因此，在步骤708中可以通过第一空气桥09将多个地线本体071进行连接。并且，还可以将两条连接线08通过第二空气桥010连接。
示例的，在形成第一空气桥09和第二空气桥010时，可以首先在绝缘衬底上待形成空气桥(如第一空气桥和第二空气桥)的区域上形成绝缘块。之后，再在绝缘衬底上形成导电材质层，并对该导电材质层进行图案化处理，以得到第一空气桥和第二空气桥。其中，对该导电材质层进行图案化处理的过程可以参考步骤701的图案化处理过程，本发明实施例在此不做赘述。
步骤709、将控制器与控制线连接。
综上所述，本发明实施例提供的方法所制造的晶体管电路中，连接晶体管的第一信号线和第二信号线中，存在至少一条信号线上搭接有控制线，且每个搭接有控制线的信号线的材料均为二维材料。因此，在控制器向控制线中的导电层施加电压时，该控制线搭接的信号线中的载流子数量会发生改变从而使得晶体管的工作频率发生改变，使晶体管能够对不同频率的信号进行处理，丰富了晶体管的功能。
需要说明的是，本发明实施例提供的方法实施例能够与相应的晶体管电路实施例相互参考，本发明实施例对此不做限定。本发明实施例提供的方法实施例步骤的先后顺序能够进行适当调整，步骤也能够根据情况进行相应增减，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本发明的保护范围之内，因此不再赘述。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (21)

  1. 一种晶体管电路，其特征在于，所述晶体管电路包括：绝缘衬底、晶体管、第一信号线、第二信号线、m条控制线和控制器，m≥1，
    所述晶体管、所述第一信号线、所述第二信号线和所述m条控制线均设置在所述绝缘衬底的目标侧，所述晶体管的栅极和第一极中的一个电极与所述第一信号线连接，另一个电极与所述第二信号线连接；
    所述第一信号线和所述第二信号线中的至少一条信号线上搭接有所述控制线，且所述至少一条信号线的材料均为二维材料，每条所述控制线包括：沿远离所述绝缘衬底的方向依次叠加的绝缘层和导电层，所述控制器与所述控制线连接，用于向所述控制线中的导电层施加电压。
  2. 根据权利要求1所述的晶体管电路，其特征在于，所述绝缘衬底的所述目标侧还设置有地线和连接线，所述连接线的两端分别连接所述地线和所述晶体管的第二极。
  3. 根据权利要求2所述的晶体管电路，其特征在于，所述控制线中未搭接在所述信号线上的部分与所述绝缘衬底接触。
  4. 根据权利要求3所述的晶体管电路，其特征在于，所述控制线与所述地线交叉排布，所述地线包括：通过第一空气桥连接的多个地线本体，且每两个相邻的所述地线本体之间设置有一条所述控制线，所述第一空气桥位于所述控制线远离所述绝缘衬底的一侧。
  5. 根据权利要求4所述的晶体管电路，其特征在于，所述绝缘衬底的所述目标侧设置有：一一对应连接的两条所述地线和两条所述连接线，所述晶体管包括两个所述第二极，所述两个第二极分别与两条所述连接线一一对应连接，
    所述第一信号线与所述第二信号线相互平行，所述地线平行于所述第一信号线，所述连接线和所述控制线均垂直于所述第一信号线，且所述第一信号线、所述第二信号线和所述连接线均位于两条所述地线之间，两条所述连接线通过第二空气桥连接。
  6. 根据权利要求4或5所述的晶体管电路，其特征在于，所述第一极、所述第二极、所述晶体管的沟道层、所述第一信号线、所述第二信号线、所述地线本体和所述连接线的材料均为二维材料。
  7. 根据权利要求1所述的晶体管电路，其特征在于，
    所述导电层和所述栅极均包括：沿远离所述绝缘衬底的方向依次叠加的一层第一材料和一层第二材料，且所述第一材料在所述绝缘衬底上的附着力为F1，所述第二材料在所述绝缘衬底上的附着力为F2，所述第二材料在所述第一材料上的附着力为F3，F1和F3均大于F2。
  8. 根据权利要求1所述的晶体管电路，其特征在于，在至少一条搭接有所述控制线的信 号线中，搭接有所述控制线的部分的宽度大于未搭接有所述控制线的部分的宽度。
  9. 根据权利要求1所述的晶体管电路，其特征在于，在所述m条控制线中的每条控制线中，搭接在信号线上的部分的宽度大于未搭接在信号线上的部分的宽度。
  10. 根据权利要求6所述的晶体管电路，其特征在于，
    所述第一极、所述第二极、所述晶体管的沟道层、所述第一信号线、所述第二信号线、所述地线本体和所述连接线的材料均为柔性透明的二维材料；
    所述绝缘衬底和所述绝缘层的材料均为柔性透明绝缘材料，所述连接线中的导电层的材料为柔性透明导电材料。
  11. 一种晶体管电路的制造方法，其特征在于，所述方法包括：
    在绝缘衬底的目标侧形成晶体管、第一信号线、第二信号线和m条控制线；
    将控制器与所述控制线连接，所述控制器用于向所述控制线中的导电层施加电压；
    其中，m≥1，所述晶体管的栅极和第一极中的一个电极与所述第一信号线连接，另一个电极与所述第二信号线连接；所述第一信号线和所述第二信号线中的至少一条信号线上搭接有所述控制线，且所述至少一条信号线的材料均为二维材料，每条所述控制线包括：沿远离所述绝缘衬底的方向依次叠加的绝缘层和导电层。
  12. 根据权利要求11所述的方法，其特征在于，所述在绝缘衬底的目标侧形成晶体管、第一信号线、第二信号线和m条控制线，包括：
    在金属衬底上形成目标图案，所述目标图案包括：所述第一极、所述晶体管的第二极、所述第一信号线、所述第二信号线和所述晶体管的沟道层；
    将所述目标图案转移至所述绝缘衬底的目标侧；
    在形成有所述目标图案的所述绝缘衬底上形成所述绝缘层和所述晶体管中的栅介质层；
    在形成有所述绝缘层和所述栅介质层的所述绝缘衬底上形成所述导电层和所述栅极。
  13. 根据权利要求12所述的方法，其特征在于，所述目标图案还包括：初始线和连接线，所述初始线接地，且所述连接线的两端分别连接所述初始线和所述第二极。
  14. 根据权利要求13所述的方法，其特征在于，所述目标图案中存在位于所述绝缘衬底中目标区域上的结构，所述目标区域用于形成所述控制线中未搭接在所述信号线上的部分，
    在形成有所述目标图案的所述绝缘衬底上形成所述绝缘层和所述晶体管中的栅介质层之前，所述方法还包括：去除所述目标区域上的结构。
  15. 根据权利要求14所述的方法，其特征在于，所述初始线中存在位于所述目标区域上的部分，在去除所述目标区域上的结构之后，所述初始线的剩余部分包括：多个地线本体，在形成有所述绝缘层和所述栅介质层的所述绝缘衬底上形成所述导电层和所述栅极之后，所述方法还包括：
    将所述初始线中的所述多个地线本体通过第一空气桥连接以得到地线；
    其中，所述地线与所述控制线交叉排布，且每两个相邻的所述地线本体之间设置有一条所述控制线。
  16. 根据权利要求15所述的方法，其特征在于，所述绝缘衬底的所述目标侧设置有：一一对应连接的两条所述地线和两条所述连接线，所述晶体管包括两个所述第二极，所述两个第二极分别与两条所述连接线一一对应连接，
    所述第一信号线与所述第二信号线相互平行，所述地线平行于所述第一信号线，所述连接线和所述控制线均垂直于所述第一信号线，且所述第一信号线、所述第二信号线和所述连接线均位于两条所述地线之间；
    在形成有所述绝缘层和所述栅介质层的所述绝缘衬底上形成所述导电层和所述栅极之后，所述方法还包括：将两条所述连接线通过第二空气桥连接。
  17. 根据权利要求15或16任一所述的方法，其特征在于，所述在金属衬底上形成目标图案，包括：
    在所述金属衬底上形成第一图案，所述第一图案的材料均为二维材料，所述第一图案包括：所述第一极、所述第二极、所述第一信号线、所述第二信号线、所述初始线和所述连接线；
    在所述金属衬底中未形成有所述第一图案的区域内形成第二图案，所述第二图案的材料为二维材料，所述第二图案包括所述晶体管的沟道层；
    在形成有所述绝缘层和所述栅介质层的所述绝缘衬底上形成所述导电层和所述栅极之后，所述方法还包括：
    去除所述第二图案中除所述沟道层之外的部分。
  18. 根据权利要求12所述的方法，其特征在于，所述在形成有所述绝缘层和所述栅介质层的所述绝缘衬底上形成所述导电层和所述栅极，包括：
    在形成有所述绝缘层和所述栅介质层的所述绝缘衬底上依次形成第一膜层和第二膜层，其中，所述第一膜层的材料为第一材料，所述第二膜层的材料为第二材料，所述第一材料在所述绝缘衬底上的附着力为F1，所述第二材料在所述绝缘衬底上的附着力为F2，所述第二材料在所述第一材料上的附着力为F3，F1和F3均大于F2；
    对所述第一膜层和所述第二膜层进行图案化处理以得到导电图案，所述导电图案包括：所述导电层和所述栅极。
  19. 根据权利要求11所述的方法，其特征在于，在至少一条搭接有所述控制线的信号线中，搭接有所述控制线的部分的宽度大于未搭接有所述控制线的部分的宽度。
  20. 根据权利要求11所述的方法，其特征在于，在所述m条控制线中的至少一条控制线中，搭接在信号线上的部分的宽度大于未搭接在信号线上的部分的宽度。
  21. 根据权利要求17所述的方法，其特征在于，
    所述第一图案的材料为柔性透明的二维材料，所述绝缘衬底和所述绝缘层的材料均为柔性透明绝缘材料，所述连接线中的导电层的材料为柔性透明导电材料。
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