WO2019227695A1 - 一种阵列基板、显示面板及显示设备 - Google Patents

一种阵列基板、显示面板及显示设备 Download PDF

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Publication number
WO2019227695A1
WO2019227695A1 PCT/CN2018/101640 CN2018101640W WO2019227695A1 WO 2019227695 A1 WO2019227695 A1 WO 2019227695A1 CN 2018101640 W CN2018101640 W CN 2018101640W WO 2019227695 A1 WO2019227695 A1 WO 2019227695A1
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WO
WIPO (PCT)
Prior art keywords
fan
signal line
data signal
touch signal
signal lines
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PCT/CN2018/101640
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English (en)
French (fr)
Inventor
尹伟红
戴荣磊
Original Assignee
武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/211,430 priority Critical patent/US20190361553A1/en
Publication of WO2019227695A1 publication Critical patent/WO2019227695A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices

Definitions

  • the present application relates to the field of display manufacturing technology, and in particular, to an array substrate, a display panel, and a display device.
  • the traces from the driver chip output to the effective display area are fan-out traces.
  • the existing fan-out traces are usually two-layer metal structures.
  • the structure usually uses a first metal layer (M1 layer) arranged on the same layer as the gate line and a second metal layer (M2 layer) arranged on the same layer as the data line. Routing method. This method requires two layers of metal. Among them, the resistance of the M1 metal is relatively large, which easily leads to impedance mismatch in the routing area and affects the display quality.
  • the present application mainly provides an array substrate, a display panel, and a display device, which can solve the problem of impedance mismatch between two layers of metal traces.
  • a technical solution adopted in the present application is to provide an array substrate, including: a substrate, a plurality of data signal lines, a plurality of touch signal lines, a plurality of first fan-out traces, and a plurality of second Fan-out wiring; substrate includes display area and non-display area, non-display area includes fan-out area, the fan-out area is adjacent to the display area; multiple data signal lines and multiple touch signal lines are arranged in the display area; multiple The first fan-out traces and multiple second fan-out traces are arranged in the fan-out area.
  • multiple first fan-out traces are connected to multiple data signal lines one by one, and multiple second fan-out traces are in contact with multiple contacts.
  • the control signal wires are connected one-to-one correspondingly; the first fan-out wiring is the same as the second fan-out wiring and is arranged on the same layer.
  • the array substrate includes: a substrate, a plurality of data signal lines, a plurality of touch signal lines, and a plurality of first substrates.
  • first fan-out traces are connected to multiple data signal lines one by one, and multiple The second fan-out traces are connected one-to-one with multiple touch signal lines.
  • the first fan-out traces are the same as the second fan-out traces and are located on the same layer.
  • the first fan-out traces and the second fan-out traces It is set on the same layer as the data signal line / touch signal line; the data signal line and the touch signal line are arranged on different layers, and multiple vias are formed between the layer where the data signal line is located and the layer where the touch signal line is located; Line through vias and data signal lines One-to-one corresponding connections, or the second fan-out traces are one-to-one connected to the touch signal lines through vias.
  • a display device including at least a display panel, the display panel including at least an array substrate;
  • the array substrate includes: a substrate, a plurality of data signal lines, a plurality of Touch signal line, multiple first fan-out traces and multiple second fan-out traces;
  • substrate includes display area and non-display area, non-display area includes fan-out area, and fan-out area is adjacent to display area;
  • multiple data Signal lines and multiple touch signal lines are set in the display area;
  • multiple first fan-out lines and multiple second fan-out lines are set in the fan-out area, among which multiple first fan-out lines and multiple data signals
  • the wires are connected one-to-one, and the second fan-out traces are connected one-to-one with the touch signal lines.
  • the first fan-out traces are the same as the second fan-out traces and are arranged on the same layer.
  • the array substrate includes: a substrate, a plurality of data signal lines, a plurality of touch signal lines, and a plurality of first fan-out traces.
  • the substrate includes a display area and a non-display area, and the non-display area includes a fan-out area, and the fan-out area is adjacent to the display area; multiple data signal lines and multiple touch signal lines are arranged on the display In the area; multiple first fan-out traces and multiple second fan-out traces are arranged in the fan-out area, of which multiple first fan-out traces are connected to multiple data signal lines one by one, and multiple second fan-out traces The wires are connected one-to-one with a plurality of touch signal lines; the first fan-out wiring is the same as the second fan-out wiring and is disposed on the same layer.
  • the first fan-out trace and the second fan-out trace are made of the same material, and there is no problem of impedance mismatch, which is conducive to improving display quality.
  • the two fan-out traces are located on the same layer, which can reduce the process and simplify the process.
  • FIG. 1 is a schematic plan view of a first embodiment of an array substrate of the present application
  • FIG. 2 is a schematic cross-sectional structure view along the extending direction of the gate line in the display area AA in FIG. 1;
  • FIG. 3 is a schematic cross-sectional structure view along BB in the fan-out area FN in FIG. 1;
  • FIG. 4 is a schematic diagram of a connection layout of a data signal line, a touch signal line, a first fan-out trace, a second fan-out trace, and a driving chip in the first embodiment of the array substrate of the present application;
  • FIG. 5 is a schematic diagram of a layout of a data signal line connected to a first fan-out line through a metal swap line in a first embodiment of an array substrate of the present application;
  • FIG. 6 is a schematic cross-sectional structure view along a gate line extending direction in a second embodiment of an array substrate of the present application
  • FIG. 7 is a schematic layout diagram of a wiring layout in which a data signal line is connected to a first fan-out trace through a metal wire in a second embodiment of an array substrate of the present application;
  • FIG. 8 is a schematic structural diagram of an embodiment of a display panel according to the present application.
  • FIG. 9 is a schematic structural diagram of an embodiment of a display device of the present application.
  • the array substrate 10 includes: a substrate 101, a plurality of data signal lines 102, a plurality of touch signal lines 103, a plurality of first fan-out traces 104, and a plurality of The second fan-out line 105.
  • the substrate 101 includes a display area AA and a non-display area NAA.
  • the non-display area NAA includes a fan-out area FN, which is adjacent to the display area AA.
  • the plurality of data signal lines 102 and the plurality of touch signal lines 103 are disposed in the display area AA; the plurality of first fan-out traces 104 and the plurality of second fan-out traces 105 are disposed in the fan-out area FN, among which, The multiple first fan-out traces 104 are connected to the multiple data signal lines 102 one-to-one, and the multiple second fan-out traces 105 are connected to the touch-control signal lines 103 one-to-one; The second fan-out traces 105 are made of the same material and are disposed on the same layer.
  • the material of the first fan-out trace 104 and the second fan-out trace 105 may be a metal material with a relatively low resistance (such as M2), such as aluminum, copper, or gold, so the resistance of the wiring is small.
  • M2 metal material with a relatively low resistance
  • the load of data signal lines or touch signal lines in the fanout area (Fanout, FN) is relatively small, which is beneficial to improving display quality.
  • the materials of the first fan-out wiring 104 and the second fan-out wiring 105 can also be made of other materials, such as ITO, which are not specifically limited herein.
  • the gate signal line 106 and the data signal line 102 are intersected, and the touch signal line 103 and the data signal line 102 are disposed on the same layer.
  • a gate signal line 106 is disposed on a surface of the substrate 101, and a first insulating layer 21 is disposed on a surface of the gate signal line 106 far from the substrate 101, and the first insulating layer 21 is far from the gate signal.
  • the surface of the line 106 is provided with a plurality of touch signal lines 103 and a plurality of data signal lines 102, and the touch signal lines 103 and the data signal lines 102 may be alternately arranged.
  • the arrangement of the touch signal line 103 and the data signal line 102 can be set according to actual needs, such as two data signal lines 102, one touch signal line 103, and two data signal lines. Arrangement of 102 and so on.
  • a first fan-out line 104 is connected to a data signal line 102, and a second fan-out line 105 is connected to a touch signal line 103, wherein the first fan-out line 104
  • the correspondence relationship with the data signal line 102 and the correspondence relationship between the second fan-out trace 105 and the touch signal line 103 can be set according to the pin positions of the driving chip 107, which is not specifically limited here.
  • the first fan-out trace 104 and the second fan-out trace 105 are disposed on the same layer. For example, as shown in FIG. 3, a second insulating layer 31 is formed on the surface of the substrate 101 in the non-display area NAA.
  • the second insulating layer 31 may be disposed on the same layer as the first insulating layer 21 of the display area AA.
  • the second insulating layer 31 is provided with the first fan-out wiring 104 and the second fan-out wiring 105 on the surface away from the substrate 101.
  • the third insulation layer 32 (or a flat layer) covers the first fan-out trace 104, the second fan-out trace 105 and the second insulation layer 31.
  • the array substrate 10 further includes: a driving chip 107 disposed in the non-display area NAA.
  • the driving chip 107 includes a plurality of first pins 1071 and a plurality of second pins. 1072.
  • One end of the first fan-out trace 104 is connected to the data signal line 102, the other end is connected to the corresponding first pin 1071 on the driving chip 107, one end of the second fan-out trace 105 is connected to one end of the touch signal line 103, and the other One end is connected to a corresponding second pin 1072 on the driving chip 107.
  • the extending direction of the first fan-out line 104 and the second fan-out line 105 are the same, for example, as shown in FIG. 4, they are parallel to each other.
  • the shapes and extension directions of the first fan-out wiring and the second fan-out wiring can be set according to actual needs, and are not specifically limited herein.
  • the driving chip 107 may be an interlace integrated chip (Interlace IC), the interleaved integrated chip 107 includes first pins 1071 and second pins 1072 arranged alternately.
  • the driving chip 107 may also be another type of chip, which is not specifically limited herein.
  • the arrangement of the first pins 1071 and the second pins 1072 of the driving chip 107 can be arranged with the arrangement of the first fan-out wiring 104 and the second fan-out wiring 105.
  • the modes correspond one-to-one, that is, as shown in FIG.
  • the first fan-out trace 104 and the second fan-out trace 105 extend parallel to each other and are connected to corresponding first pins 1071 and second pins 1072, and No jumper / punching is required, so that the first pin 1071 can transmit the driving signal to the corresponding data signal line 102 through the first fan-out trace 104, and the second pin 1072 can also be routed through the second fan-out
  • the line 105 transmits a driving signal to the corresponding touch signal line 103.
  • the data signal line 102 and the touch signal line 103 are disposed on the same layer, if the data signal line 102 and the touch signal line 103 are arranged in the same manner as the first pin 1071 and the second pin of the driving chip 107
  • the arrangement of 1072 corresponds one-to-one, then the first fan-out trace 104 and the second fan-out trace 105 can directly connect the corresponding data signal line 102 and the touch signal line 103, and then extend in a direction to connect the corresponding First pin 1071 and second pin 1072 without jumpers / punches.
  • the wiring of the first fan-out trace 104 and the second fan-out trace 105 can be set so that the data signal line 102 is connected to the corresponding first pin 1071 through the first fan-out trace 104, and the touch signal The line 103 is connected to the corresponding second pin 1072 through the second fan-out line 105.
  • the first fan-out wiring 104 and / or the second fan-out wiring 105 can be adjusted by a metal wire exchange, and the arrangement order of the first fan-out wiring 104 and / or the second fan-out wiring 105 can be adjusted.
  • the data signal line 102 is connected to the first fan-out trace 104 at the corresponding position, and the touch signal line 103 is connected to the second fan-out trace 105 at the corresponding position.
  • a data signal line 102 is used as an example.
  • a first through hole 501 is formed at a position corresponding to one end of the data signal line 102 for connecting to the first fan-out line 104.
  • the first fan-out line 104 A second through hole 502 is formed at a position corresponding to one end of the data signal line 102.
  • One end of the metal change line 503 is connected to the data signal line 102 through the first through hole 501, and the other end is connected through the second through hole 502.
  • the first fan-out wiring 104 connects the first fan-out wiring 104 and the corresponding data signal line 102 through the metal switching wire 503.
  • the metal switching wire 503 can use a metal different from the first fan-out wiring 104. (Such as M1), the touch signal line 103 can also be connected to the second fan-out line 105 by a similar method, and the metal change line can be the same metal as the second fan-out line 105 (such as M2).
  • the data signal line 102, the touch signal line 103, the first fan-out trace 104, and the second fan-out trace 105 can be disposed on the same layer.
  • the The data signal line 102, the touch signal line 103, the first fan-out trace 104, and the second fan-out trace 105 can be fabricated at the same time, and can be fabricated with the same metal layer, which can save manufacturing processes and reduce costs.
  • the data signal line and the touch signal line may be disposed in different layers.
  • the array substrate 20 is similar to the array substrate 10, and the same points are not described again.
  • the difference is that the data signal line 102 and the touch signal line 103 are in different layers. Settings.
  • the first fan-out trace 104 and the second fan-out trace 105 are disposed on the same layer.
  • the first fan-out trace 104 and the second fan-out trace 105 are disposed on the same layer as the data signal line 102 / touch signal line 103.
  • the first fan-out line 601 can directly communicate with the corresponding data signal line 102 Connection
  • the second fan-out trace 105 needs to be connected one-to-one with the touch signal line 103 through the via 601, so as to directly connect to the corresponding pin of the driving chip through the second fan-out trace 105, without the need for further Jumper / replacement to reduce wiring difficulty, and the fan-out area is located on the layer where the data signal line is located.
  • the distance between the second fan-out line 105 and the common electrode (COM) Larger, it is beneficial to reduce the parasitic capacitance between the second fan-out trace 105 and COM.
  • the via 601 is provided with a metal wire 602.
  • the metal wire 602 is located between the layer of the data signal line 102 and the layer of the touch signal line 103 through the via 601. One end of the metal wire 602 is connected. The other end of the touch signal line 103 is connected to the second fan-out line 105.
  • the material of the metal change line 602 may be the same as that of the second fan-out line 105 (for example, M1 metal is used), or may be different (for example, the second fan-out line 105 is M1 metal, and the metal change line 602 is M2 metal ).
  • the first fan-out trace 104 and the second fan-out trace 105 may also be disposed on the same layer as the touch signal line 103. The specific implementation manner is similar to the above process, and is not repeated here.
  • the first fan-out trace 104 and the second fan-out trace 105 may also be disposed on other layers than the film layer where the data signal line 102 and the touch signal line 103 are located, and may be based on the actual display panel.
  • the data signal line 102 and the touch signal line 103 can be connected to the corresponding first fan-out trace 104 and the second fan-out trace 105 through a metal wire exchange.
  • the specific implementation method is similar to the above process. , Which will not be repeated here.
  • the first fanout trace and the second fanout trace are made of the same material, and there is no problem of impedance mismatch, which is conducive to improving display quality, and the first fanout trace and the second fanout trace
  • the lines are on the same layer, which can reduce the process and simplify the process.
  • the display panel 80 includes at least an array substrate 801.
  • the array substrate 801 reference may be made to the structure of the first or second embodiment of the array substrate of the present application. repeat.
  • the display panel 80 may further include a color filter substrate and a liquid crystal layer according to the type of the display panel, which is not specifically limited herein.
  • the first fanout trace and the second fanout trace are made of the same material, there is no problem of impedance mismatch, which is beneficial to improving the display quality, and the first fanout trace and the second The fan-out traces are located on the same layer, which can reduce the process and simplify the process.
  • the display device 90 includes at least a display panel 901.
  • the display panel 901 may refer to the structure of an embodiment of the display panel of the present application, and is not repeated here.
  • the first fan-out trace and the second fan-out trace are made of the same material, and there is no problem of impedance mismatch, which is conducive to improving display quality, and the first The fan-out trace and the second fan-out trace are located on the same layer, which can reduce the process and simplify the process.

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Abstract

一种阵列基板（10）、显示面板及显示设备，该阵列基板（10）包括：基板（101）、多条数据信号线（102）、多条触控信号线（103）、多条第一扇出走线（104）和多条第二扇出走线（105）；基板（101）包括显示区（AA）和非显示区（NAA），非显示区（NAA）包括扇出区（FN），扇出区（FN）与显示区（AA）相邻；多条数据信号线（102）和多条触控信号线（103）设置于显示区（AA）内；多条第一扇出走线（104）和多条第二扇出走线（105）设置于扇出区（FN）内，其中多条第一扇出走线（104）与多条数据信号线（105）一一对应连接，多条第二扇出走线（105）与多条触控信号线（103）一一对应连接；第一扇出走线（104）与第二扇出走线材料（105）相同，且设置于同一层。

Description

一种阵列基板、显示面板及显示设备
【技术领域】
本申请涉及显示制造技术领域，特别是涉及一种阵列基板、显示面板及显示设备。
【背景技术】
显示面板中，从驱动芯片输出到有效显示区之间的走线为扇出走线。现有扇出走线通常为两层金属结构，该结构通常采用与栅极线同层设置的第一金属层（M1层）和与数据线同层设置的第二金属层（M2层）交错的走线方式，此方式需要两层金属，其中M1金属的阻抗较大，容易导致走线区域阻抗不匹配，影响显示质量。
【发明内容】
本申请主要是提供一种阵列基板、显示面板及显示设备，能够解决两层金属走线阻抗不匹配的问题。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种阵列基板，包括：基板、多条数据信号线、多条触控信号线、多条第一扇出走线和多条第二扇出走线；基板包括显示区和非显示区，非显示区包括扇出区，扇出区与显示区相邻；多条数据信号线和多条触控信号线设置于显示区内；多条第一扇出走线和多条第二扇出走线设置于扇出区内，其中多条第一扇出走线与多条数据信号线一一对应连接，多条第二扇出走线与多条触控信号线一一对应连接；第一扇出走线与第二扇出走线材料相同，且设置于同一层。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种显示面板，至少一阵列基板；该阵列基板包括：基板、多条数据信号线、多条触控信号线、多条第一扇出走线和多条第二扇出走线；基板包括显示区和非显示区，非显示区包括扇出区，扇出区与显示区相邻；多条数据信号线和多条触控信号线设置于显示区内；多条第一扇出走线和多条第二扇出走线设置于扇出区内，其中多条第一扇出走线与多条数据信号线一一对应连接，多条第二扇出走线与多条触控信号线一一对应连接；第一扇出走线与第二扇出走线材料相同，且设置于同一层；其中，第一扇出走线、第二扇出走线与数据信号线/触控信号线同层设置；数据信号线和触控信号线异层设置，数据信号线所在层和触控信号线所在层之间形成有多个过孔；第一扇出走线通过过孔与数据信号线一一对应连接，或者，第二扇出走线通过过孔与触控信号线一一对应连接。
为解决上述技术问题，本申请采用的又一个技术方案是：提供显示设备，至少包括一显示面板，该显示面板至少包括一阵列基板；该阵列基板包括：基板、多条数据信号线、多条触控信号线、多条第一扇出走线和多条第二扇出走线；基板包括显示区和非显示区，非显示区包括扇出区，扇出区与显示区相邻；多条数据信号线和多条触控信号线设置于显示区内；多条第一扇出走线和多条第二扇出走线设置于扇出区内，其中多条第一扇出走线与多条数据信号线一一对应连接，多条第二扇出走线与多条触控信号线一一对应连接；第一扇出走线与第二扇出走线材料相同，且设置于同一层。
本申请的有益效果是：区别于现有技术的情况，本申请的部分实施例中，阵列基板，包括：基板、多条数据信号线、多条触控信号线、多条第一扇出走线和多条第二扇出走线；基板包括显示区和非显示区，非显示区包括扇出区，扇出区与显示区相邻；多条数据信号线和多条触控信号线设置于显示区内；多条第一扇出走线和多条第二扇出走线设置于扇出区内，其中多条第一扇出走线与多条数据信号线一一对应连接，多条第二扇出走线与多条触控信号线一一对应连接；第一扇出走线与第二扇出走线材料相同，且设置于同一层。通过上述方式，本申请的阵列基板中，该第一扇出走线和第二扇出走线采用同一种材料，不存在阻抗不匹配问题，有利于提高显示质量，且该第一扇出走线和第二扇出走线位于同一层，可以减少制程，简化工序。
【附图说明】
图1是本申请阵列基板第一实施例的平面结构示意图；
图2是图1中显示区AA中沿栅极线延伸方向的截面结构示意图；
图3是图1中扇出区FN中沿BB的截面结构示意图；
图4是本申请阵列基板第一实施例中数据信号线、触控信号线、第一扇出走线、第二扇出走线和驱动芯片的连接布局示意图；
图5是本申请阵列基板第一实施例中数据信号线通过金属换线连接到第一扇出走线的走线布局示意图；
图6是本申请阵列基板第二实施例中沿栅极线延伸方向的截面结构示意图；
图7是本申请阵列基板第二实施例中数据信号线通过金属换线连接到第一扇出走线的走线布局示意图；
图8是本申请显示面板一实施例的结构示意图；
图9是本申请显示设备一实施例的结构示意图。
【具体实施方式】
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
如图1所示，本申请阵列基板第一实施例中，阵列基板10包括：基板101、多条数据信号线102、多条触控信号线103、多条第一扇出走线104和多条第二扇出走线105。
其中，该基板101包括显示区AA和非显示区NAA，该非显示区NAA包括扇出区FN，该扇出区FN与显示区AA相邻。
该多条数据信号线102和多条触控信号线103设置于显示区AA内；该多条第一扇出走线104和多条第二扇出走线105设置于扇出区FN内，其中，该多条第一扇出走线104与多条数据信号线102一一对应连接，多条第二扇出走线105与多条触控信号线103一一对应连接；该第一扇出走线104与该第二扇出走线105材料相同，且设置于同一层。
其中，该第一扇出走线104和该第二扇出走线105的材料可以均采用一种阻抗较小的金属材料（如M2），例如铝、铜或金等，则走线阻抗较小，相对于现有技术，数据信号线或触控信号线在该扇出区（Fanout，FN）布线的负载较小，有利于提高显示质量。当然，该第一扇出走线104和该第二扇出走线105的材料也可以采用其他材料，例如ITO等，此处不做具体限定。
具体地，结合图2所示，在一个应用例中，该显示区AA中，该栅极信号线106与该数据信号线102交叉设置，该触控信号线103和数据信号线102同层设置，例如图2所示，该基板101表面设置有栅极信号线106，该栅极信号线106远离该基板101的表面设置有第一绝缘层21，该第一绝缘层21远离该栅极信号线106的表面设置有多条触控信号线103和多条数据信号线102，该触控信号线103和该数据信号线102可以交替排布。当然，在其他应用例中，可以根据实际需求设置该触控信号线103和该数据信号线102的排布，例如两根数据信号线102、一根触控信号线103和两根数据信号线102的排布方式等。
在非显示区NAA，一根第一扇出走线104与一根数据信号线102连接，一根第二扇出走线105与一根触控信号线103连接，其中，该第一扇出走线104与数据信号线102的对应关系，以及第二扇出走线105和触控信号线103的对应关系可以根据驱动芯片107的引脚位置设置，此处不做具体限定。其中，该第一扇出走线104与该第二扇出走线105设置于同一层，例如结合图3所示，在该非显示区NAA，衬底基板101表面形成有第二绝缘层31，该第二绝缘层31可以是与该显示区AA第一绝缘层21同层设置，该第二绝缘层31远离该基板101表面设置有该第一扇出走线104与该第二扇出走线105，该第三绝缘层32（或平坦层）覆盖该第一扇出走线104、该第二扇出走线105和该第二绝缘层31。
可选地，结合图1和图4所示，该阵列基板10进一步包括：设置于非显示区NAA的驱动芯片107，该驱动芯片107包括多个第一引脚1071和多个第二引脚1072。该第一扇出走线104一端与该数据信号线102连接，另一端与驱动芯片107上对应的第一引脚1071连接，该第二扇出走线105一端与触控信号线103一端连接，另一端与驱动芯片107上对应的第二引脚1072连接。其中，该第一扇出走线104与该第二扇出走线105的延伸方向相同，例如图4所示相互平行。其中，该第一扇出走线和该第二扇出走线的形状和延伸方向等可以根据实际需求设置，此处不做具体限定。
可选地，该驱动芯片107可以是交错集成芯片（Interlace IC），该交错集成芯片107包括交替排布的第一引脚1071和第二引脚1072。当然，在其他实施例中，该驱动芯片107也可以是其他类型的芯片，此处不做具体限定。
进一步参阅图4，上述应用例中，该驱动芯片107的第一引脚1071和第二引脚1072的排布方式可以与该第一扇出走线104和该第二扇出走线105的排布方式一一对应，即如图4所示，该第一扇出走线104和该第二扇出走线105是相互平行地延伸并连接到对应的第一引脚1071和第二引脚1072，而不需要进行跳线/打孔，则可以使得第一引脚1071可以通过第一扇出走线104将驱动信号输送到对应的数据信号线102，该第二引脚1072也可以通过第二扇出走线105将驱动信号输送到对应的触控信号线103。其中，由于该数据信号线102和触控信号线103同层设置，若该数据信号线102和触控信号线103的排布方式与该驱动芯片107的第一引脚1071和第二引脚1072的排布方式一一对应，则该第一扇出走线104和该第二扇出走线105可以直接连接对应的数据信号线102和触控信号线103后，沿一方向延伸至连接对应的第一引脚1071和第二引脚1072，而不需要进行跳线/打孔。
当然，在其他实施例中，若该驱动芯片107的第一引脚1071和第二引脚1072的排布方式与该数据信号线102和触控信号线103的排布方式并不是一一对应的，则可以通过该第一扇出走线104和该第二扇出走线105的布线设置，使得数据信号线102通过该第一扇出走线104与对应的第一引脚1071连接，触控信号线103通过该第二扇出走线105与对应的第二引脚1072连接。其中，该第一扇出走线104和/或该第二扇出走线105可以通过金属换线的方式，将该第一扇出走线104和/或该第二扇出走线105的排列顺序进行调整，使得数据信号线102连接到对应位置的该第一扇出走线104，触控信号线103连接到对应位置的该第二扇出走线105。具体如图5所示，以数据信号线102为例，该数据信号线102用于连接该第一扇出走线104的一端对应的位置形成有第一通孔501，该第一扇出走线104用于连接该数据信号线102的一端对应的位置形成有第二通孔502，金属换线503一端通过该第一通孔501连接该数据信号线102，另一端通过该第二通孔502连接该第一扇出走线104，从而通过该金属换线503将该第一扇出走线104和对应的数据信号线102连接，该金属换线503可以采用区别于该第一扇出走线104的金属（如M1），该触控信号线103也可以通过类似的方法对应连接第二扇出走线105，其金属换线可以采用与该第二扇出走线105相同的金属（如M2）。
本实施例中，该数据信号线102、该触控信号线103、该第一扇出走线104和该第二扇出走线105可以同层设置，则在该阵列基板10的制作过程中，该数据信号线102、该触控信号线103、该第一扇出走线104和该第二扇出走线105可以同时制作，且可以采用同一种金属层制作，从而可以节省制程，减低成本。
当然，在其他实施例中，该数据信号线和该触控信号线也可以异层设置。
具体如图6所示，本申请阵列基板第二实施例中，该阵列基板20与阵列基板10类似，相同之处不再赘述，区别在于该数据信号线102和该触控信号线103异层设置。
其中，结合图3所示，该第一扇出走线104和第二扇出走线105同层设置。
可选地，该第一扇出走线104、第二扇出走线105与数据信号线102/触控信号线103同层设置。
具体地，在一个应用例中，结合图7所示，由于该数据信号线102和该触控信号线103异层设置，若该第一扇出走线104和第二扇出走线105设置于该数据信号线102所在层，则该数据信号线102所在层和触控信号线103所在层之间形成有多个过孔601，则该第一扇出走线601可以直接与对应的数据信号线102连接，该第二扇出走线105需要通过该过孔601与触控信号线103一一对应连接，以通过该第二扇出走线105直接连接到驱动芯片对应的引脚，而不需要再进行跳线/换线，从而减少布线难度，并且扇出区走线设置于数据信号线所在层，相对于现有两层结构，该第二扇出走线105与公共电极（COM）之间的距离更大，有利于减少第二扇出走线105和COM之间的寄生电容。
其中，过孔601中设置有金属换线602，该金属换线602通过该过孔601跨设于数据信号线102所在层和触控信号线103所在层之间，该金属换线602一端连接该触控信号线103，另一端连接第二扇出走线105。其中，该金属换线602的材料可以与该第二扇出走线105相同（如均采用M1金属），也可以不同（如第二扇出走线105采用M1金属，该金属换线602采用M2金属）。在其他应用例中，该第一扇出走线104和第二扇出走线105也可以设置于该触控信号线103所在层，具体实现方式与上述过程类似，此处不再重复。
当然，在其他实施例中，该第一扇出走线104、第二扇出走线105也可以设置于除了该数据信号线102和触控信号线103所在膜层的其他层，可以根据实际显示面板的负载状况进行选择，则该数据信号线102和触控信号线103均可以通过金属换线方式连接到对应的第一扇出走线104和第二扇出走线105，具体实现方式与上述过程类似，此处不再重复。
本实施例的阵列基板中，该第一扇出走线和第二扇出走线采用同一种材料，不存在阻抗不匹配问题，有利于提高显示质量，且该第一扇出走线和第二扇出走线位于同一层，可以减少制程，简化工序。
如图8所示，本申请显示面板一实施例中，该显示面板80至少包括一阵列基板801，该阵列基板801可以参考本申请阵列基板第一或第二实施例的结构，此处不再重复。
其中，该显示面板80还可以根据显示面板类型进一步包括彩膜基板、液晶层等，此处不做具体限定。
本实施例显示面板的阵列基板中，该第一扇出走线和第二扇出走线采用同一种材料，不存在阻抗不匹配问题，有利于提高显示质量，且该第一扇出走线和第二扇出走线位于同一层，可以减少制程，简化工序。
如图9所示，本申请显示设备一实施例中，该显示设备90至少包括一显示面板901，该显示面板901可以参考本申请显示面板一实施例的结构，此处不再重复。
本实施例的显示设备中，该显示面板的阵列基板中，该第一扇出走线和第二扇出走线采用同一种材料，不存在阻抗不匹配问题，有利于提高显示质量，且该第一扇出走线和第二扇出走线位于同一层，可以减少制程，简化工序。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种显示面板，其中，至少包括一阵列基板；
    所述阵列基板包括：基板、多条数据信号线、多条触控信号线、多条第一扇出走线和多条第二扇出走线；
    所述基板包括显示区和非显示区，所述非显示区包括扇出区，所述扇出区与所述显示区相邻；
    所述多条数据信号线和所述多条触控信号线设置于所述显示区内；
    所述多条第一扇出走线和所述多条第二扇出走线设置于所述扇出区内，其中所述多条第一扇出走线与所述多条数据信号线一一对应连接，所述多条第二扇出走线与所述多条触控信号线一一对应连接；
    所述第一扇出走线与所述第二扇出走线材料相同，且设置于同一层；
    其中，所述第一扇出走线、所述第二扇出走线与所述数据信号线/所述触控信号线同层设置；
    所述数据信号线和所述触控信号线异层设置，所述数据信号线所在层和所述触控信号线所在层之间形成有多个过孔；
    所述第一扇出走线通过所述过孔与所述数据信号线一一对应连接，或者，所述第二扇出走线通过所述过孔与所述触控信号线一一对应连接。
  2. 根据权利要求1所述的显示面板，其中，所述阵列基板进一步包括：金属换线，所述金属换线通过所述过孔跨设于所述数据信号线所在层和所述触控信号线所在层之间，所述金属换线一端连接所述数据信号线/所述触控信号线，另一端连接所述第一扇出走线/所述第二扇出走线。
  3. 根据权利要求1所述的显示面板，其中，所述阵列基板进一步包括：驱动芯片，设置于所述非显示区，所述驱动芯片包括多个第一引脚和多个第二引脚；所述第一扇出走线一端与所述数据信号线连接，另一端与所述驱动芯片上对应的所述第一引脚连接；所述第二扇出走线一端与所述触控信号线一端连接，另一端与所述驱动芯片上对应的所述第二引脚连接。
  4. 根据权利要求1所述的显示面板，其中，所述驱动芯片是交错集成芯片，所述交错集成芯片包括交替排布的所述第一引脚和所述第二引脚。
  5. 一种阵列基板，其中，包括：基板、多条数据信号线、多条触控信号线、多条第一扇出走线和多条第二扇出走线；
    所述基板包括显示区和非显示区，所述非显示区包括扇出区，所述扇出区与所述显示区相邻；
    所述多条数据信号线和所述多条触控信号线设置于所述显示区内；
    所述多条第一扇出走线和所述多条第二扇出走线设置于所述扇出区内，其中所述多条第一扇出走线与所述多条数据信号线一一对应连接，所述多条第二扇出走线与所述多条触控信号线一一对应连接；
    所述第一扇出走线与所述第二扇出走线材料相同，且设置于同一层。
  6. 根据权利要求5所述的阵列基板，其中，所述第一扇出走线、所述第二扇出走线与所述数据信号线/所述触控信号线同层设置。
  7. 根据权利要求5所述的阵列基板，其中，所述数据信号线和所述触控信号线异层设置，所述数据信号线所在层和所述触控信号线所在层之间形成有多个过孔；
    所述第一扇出走线通过所述过孔与所述数据信号线一一对应连接，或者，所述第二扇出走线通过所述过孔与所述触控信号线一一对应连接。
  8. 根据权利要求7所述的阵列基板，其中，进一步包括：金属换线，所述金属换线通过所述过孔跨设于所述数据信号线所在层和所述触控信号线所在层之间，所述金属换线一端连接所述数据信号线/所述触控信号线，另一端连接所述第一扇出走线/所述第二扇出走线。
  9. 根据权利要求5所述的阵列基板，其中，进一步包括：驱动芯片，设置于所述非显示区，所述驱动芯片包括多个第一引脚和多个第二引脚；
    所述第一扇出走线一端与所述数据信号线连接，另一端与所述驱动芯片上对应的所述第一引脚连接；所述第二扇出走线一端与所述触控信号线一端连接，另一端与所述驱动芯片上对应的所述第二引脚连接。
  10. 根据权利要求9所述的阵列基板，其中，所述驱动芯片是交错集成芯片，所述交错集成芯片包括交替排布的所述第一引脚和所述第二引脚。
  11. 根据权利要求5所述的阵列基板，其中，所述第一扇出走线与所述第二扇出走线均采用金属材料。
  12. 根据权利要求5所述的阵列基板，其中，所述第一扇出走线与所述第二扇出走线的延伸方向相同。
  13. 一种显示设备，其中，至少包括一显示面板，所述显示面板至少包括一阵列基板；
    所述阵列基板包括：基板、多条数据信号线、多条触控信号线、多条第一扇出走线和多条第二扇出走线；
    所述基板包括显示区和非显示区，所述非显示区包括扇出区，所述扇出区与所述显示区相邻；
    所述多条数据信号线和所述多条触控信号线设置于所述显示区内；
    所述多条第一扇出走线和所述多条第二扇出走线设置于所述扇出区内，其中所述多条第一扇出走线与所述多条数据信号线一一对应连接，所述多条第二扇出走线与所述多条触控信号线一一对应连接；
    所述第一扇出走线与所述第二扇出走线材料相同，且设置于同一层。
  14. 根据权利要求13所述的显示设备，其中，所述第一扇出走线、所述第二扇出走线与所述数据信号线/所述触控信号线同层设置。
  15. 根据权利要求13所述的显示设备，其中，所述数据信号线和所述触控信号线异层设置，所述数据信号线所在层和所述触控信号线所在层之间形成有多个过孔；
    所述第一扇出走线通过所述过孔与所述数据信号线一一对应连接，或者，所述第二扇出走线通过所述过孔与所述触控信号线一一对应连接。
  16. 根据权利要求15所述的显示设备，其中，所述阵列基板进一步包括：金属换线，所述金属换线通过所述过孔跨设于所述数据信号线所在层和所述触控信号线所在层之间，所述金属换线一端连接所述数据信号线/所述触控信号线，另一端连接所述第一扇出走线/所述第二扇出走线。
  17. 根据权利要求13所述的显示设备，其中，所述阵列基板进一步包括：驱动芯片，设置于所述非显示区，所述驱动芯片包括多个第一引脚和多个第二引脚；
    所述第一扇出走线一端与所述数据信号线连接，另一端与所述驱动芯片上对应的所述第一引脚连接；所述第二扇出走线一端与所述触控信号线一端连接，另一端与所述驱动芯片上对应的所述第二引脚连接。
  18. 根据权利要求17所述的显示设备，其中，所述驱动芯片是交错集成芯片，所述交错集成芯片包括交替排布的所述第一引脚和所述第二引脚。
  19. 根据权利要求13所述的显示设备，其中，所述第一扇出走线与所述第二扇出走线均采用金属材料。
  20. 根据权利要求13所述的显示设备，其中，所述第一扇出走线与所述第二扇出走线的延伸方向相同。
PCT/CN2018/101640 2018-05-28 2018-08-22 一种阵列基板、显示面板及显示设备 WO2019227695A1 (zh)

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