WO2019210642A1 - 一种新型的时间数字转化器 - Google Patents

一种新型的时间数字转化器 Download PDF

Info

Publication number
WO2019210642A1
WO2019210642A1 PCT/CN2018/108108 CN2018108108W WO2019210642A1 WO 2019210642 A1 WO2019210642 A1 WO 2019210642A1 CN 2018108108 W CN2018108108 W CN 2018108108W WO 2019210642 A1 WO2019210642 A1 WO 2019210642A1
Authority
WO
WIPO (PCT)
Prior art keywords
output
trigger
clock
signal
state
Prior art date
Application number
PCT/CN2018/108108
Other languages
English (en)
French (fr)
Inventor
王岩
Original Assignee
晶晨半导体(上海)股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 晶晨半导体(上海)股份有限公司 filed Critical 晶晨半导体(上海)股份有限公司
Priority to US16/323,181 priority Critical patent/US11275344B2/en
Publication of WO2019210642A1 publication Critical patent/WO2019210642A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the master-slave type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3562—Bistable circuits of the master-slave type
    • H03K3/35625—Bistable circuits of the master-slave type using complementary field-effect transistors

Definitions

  • the present invention relates to the field of communication technologies, and in particular, to a novel time digital converter.
  • the traditional three-stage time-to-digital converter based on phase-locked loop is mainly used to quantize the time interval by using a phase-locked loop to generate clocks with different frequencies and phases.
  • the time-to-digital converter is divided into high, medium and low segments, mainly for high precision and wide range.
  • a simple inverter is used to form a ring oscillator, and the time interval is quantized by the rise and fall delays of the inverter; the period of the ring oscillator is used as a large unit of measurement and can be recycled, so this can A wide range is achieved when giving a point area.
  • inverter as a single time interval quantization scale can achieve high resolution; but the range and area achieved are positively correlated, and the wide range means larger area and power consumption.
  • the present invention proposes a novel time digital converter, which includes:
  • a polarity detecting module including two clock input ports for receiving a clock signal, and including a first clock output port, a second clock output port, and a state output port;
  • the polarity detecting module performs timing analysis on the clock signals input by the two clock input ports, and outputs the clock signal with the timing advance from the first clock output port, and the clock signal with the timing lag Outputting from the second clock output port, and outputting a timing comparison result signal of two of the clock signals from the state output port;
  • a time digital conversion module comprising a digital coding unit, a ring shock enable unit, a plurality of differential delay units sequentially forming a closed loop in series, and a plurality of trigger units;
  • the ring shock enable unit is respectively connected to the closed loop and the first clock output port to receive and control the turn-on and turn-off of the closed loop according to the clock signal advanced by timing;
  • Each of the differential delay units includes a first input, a second input, a first output, and a second output; the first output and the second output of each of the differential delay units The output of the terminal is a complementary differential signal;
  • Each of the trigger units respectively includes two trigger input ports, two trigger output ports and a clock signal port; each of the trigger units respectively corresponding to the first output end of one of the differential delay units And a second output terminal for outputting two sets of two trigger signals from the two trigger output ports according to the complementary differential signals; the clock signal port of each of the flip-flop units is connected to the second clock An output port to receive the clock signal of the sequence lag;
  • the digital encoding unit is respectively connected to the state output port of the polarity detecting module and the two trigger output ports of each of the trigger units to receive and compare result signals according to the timing and each group
  • the trigger signal generates an encoded signal.
  • the time digital converter wherein the first output port or the second output port of the differential delay unit of the final stage is further connected to a counter, and the counter is used for the trigger of the last stage
  • the trigger signal output by the unit performs a calculation of an oscillating period
  • the counter is further connected to the digital coding unit to output a count signal including the oscillation period to the digital coding unit;
  • the digital encoding unit processes a range parameter according to the counting signal.
  • each of the differential delay units further includes a first delayer from the first input end toward the first output end, from the second input end toward the first a second delay of the second output, a third delay from the first output toward the second output, and a fourth delay from the second output toward the first output.
  • each of the flip-flop units includes a sense amplifier structure.
  • the timing comparison result signal outputted by the state output port includes a first state and a second state.
  • the above-described time digital converter wherein the first state is a high state and the second state is a low state.
  • a novel time digital converter proposed by the present invention significantly improves the rise and fall time of the inverter and the mismatch of the flip-flop sampling, so that the signal entering the trigger unit is a phase complementary signal, thereby improving the digital conversion. Linearity.
  • FIG. 1 is a schematic structural diagram of a time digital converter according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a time-to-digital conversion module according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a differential delay unit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a trigger unit according to an embodiment of the present invention.
  • a novel time digital converter is proposed, which may include:
  • the polarity detecting module 10 includes two clock input ports for receiving a clock signal (the first clock input port CLK1 and the second clock input port CLK2 in this embodiment), and includes a first clock output port START and a second Clock output port STOP and status output port Polar;
  • the polarity detecting module 10 performs timing analysis on the clock signals input by the two clock input ports, outputs a timing-leading clock signal from the first clock output port, and outputs a clock signal with a timing lag from the second clock output port STOP, and Outputting the timing comparison result signals of the two clock signals from the state output port Polar;
  • the time-to-digital conversion module 20 includes a digital encoding unit 21, a ring shock enabling unit 22, a multi-stage differential delay unit that sequentially forms a closed loop 23 in series, and a plurality of flip-flop units 24 (only a single one is shown in FIG. 2)
  • the trigger unit is configured to indicate the connection relationship therein;
  • the ring shock enable unit 22 is respectively connected to the closed loop 23 and the first clock output port START to receive and control the turn-on and turn-off of the closed loop 23 according to the timing advance clock signal;
  • each differential delay unit includes a first input terminal IN1, a second input terminal IN2, a first output terminal OUT1, and a second output terminal OUT2; a first output terminal OUT1 of each differential delay unit 230 And the output of the second output terminal OUT2 is a complementary differential signal;
  • each of the trigger units 24 includes two trigger input ports (the first trigger input port D and the second trigger input port Db in this embodiment) and two trigger output ports (in this embodiment).
  • the two trigger input ports of each flip-flop unit 24 are respectively connected to the first output terminal OUT1 and the first differential delay unit
  • the two output terminals OUT2 output two sets of two trigger signals from the two trigger output ports according to the complementary differential signals;
  • the clock signal port CLK of each flip-flop unit 24 is connected to the second clock output port STOP to receive the sequence lag Clock signal
  • the digital encoding unit 21 is respectively connected to the state output port Polar of the polarity detecting module 10 and the two trigger output ports of each flip-flop unit 24 to receive and generate an encoded signal according to the timing comparison result signal and each set of trigger signals.
  • each trigger unit 24 is specifically that the first trigger input port D is connected to the first output end OUT1 of the corresponding differential delay unit, and the second trigger input port Db is connected to the corresponding differential delay unit.
  • the first output port OUT1 or the second output port OUT2 of the differential delay unit of the final stage is further connected to a counter for oscillating the trigger signal outputted by the flip-flop unit 24 of the final stage. Calculation of the period;
  • the counter is further connected to the digital encoding unit 21 to output the counting signal including the oscillation period to the digital encoding unit 21;
  • the digital encoding unit 21 processes a range parameter according to the counting signal.
  • each differential delay unit 23 further includes a first delay from the first input IN1 toward the first output OUT1, and from the second input IN2. a second delay of the second output terminal OUT2, a third delay from the first output terminal OUT1 toward the second output terminal OUT2, and a fourth delay device from the second output terminal OUT2 toward the first output terminal OUT1 .
  • the delay values of the first delay device, the second delay device, the third delay device and the fourth delay device may be the same, but this is only a preferred case, and may be other Happening.
  • each of the flip-flop units 24 may include a sense amplifier structure to increase the linearity of the trigger signals output by the first trigger output port Q and the second trigger output port Qb.
  • the timing comparison result signal output by the state output port Polar includes a first state and a second state.
  • the first state is a high level state
  • the second state is a low level state
  • the clock signal corresponding to the first clock input port CLK1 may be delayed compared to the clock signal input by the second clock input port CLK2 when the comparison result signal is in the high level state; otherwise, the comparison result signal is low.
  • the clock signal corresponding to the input of the second clock input port CLK2 in the flat state is delayed from the clock signal input from the first clock input port CLK1; however, this is only a preferred case and should not be construed as limiting the present invention.
  • the present invention provides a novel time digital converter comprising: a polarity detecting module; a time digital converting module comprising a digital encoding unit, a ring shock enabling unit, and a plurality of stages forming a closed loop in series a differential delay unit and a plurality of flip-flop units; each differential delay unit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal; a first output terminal of each differential delay unit And the output of the second output is a complementary differential signal; the difference between the rise and fall times of the inverter and the sampling of the flip-flop can be significantly improved, so that the signal entering the flip-flop unit is a phase complementary signal, thereby improving the linearity of the digital conversion. .

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

本发明涉及通讯技术领域，尤其涉及一种新型的时间数字转化器，包括：极性检测模块；时间数字转换模块，包括数字编码单元、环震使能单元、依次串联形成闭合环路的多级的差分延时单元以及多个触发器单元；每个差分延时单元包括第一输入端、第二输入端、第一输出端和第二输出端；每个差分延时单元的第一输出端和第二输出端输出的是互补的差分信号；能够明显改善反相器上升下降时间和触发器采样的不匹配，使得进入触发器单元的信号为相位互补的信号，进而提高数字转换的线性度。

Description

一种新型的时间数字转化器 技术领域
本发明涉及通讯技术领域，尤其涉及一种新型的时间数字转化器。
背景技术
时间间隔的测量技术，尤其是高精度的时间间隔(皮秒1ps＝10E-12s量级)的测量技术意义重大，不论是电信通讯，芯片设计和数字示波器等工程领域，还是原子物理、天文观测等理论研究，以及激光测距、卫星定位等航天军事技术领域都离不开高精度的时间间隔测量技术。
传统的采用基于锁相环的三段式时间数字转换器，主要关键是通过锁相环产生不同频率和相位均匀分布的时钟对时间间隔进行量化。时间数字转换器分为高、中、低段位，主要是完成高精度和宽量程。
传统的采用简单的反向器组成环形振荡器，通过反向器的上升、下降延时进行时间间隔的量化；环形振荡器的周期作为一个较大的度量单位并且可以循环利用，故这种可以在给点面积时实现宽量程。
传统的采用反向器作为单个时间间隔的量化刻度，可以实现高分辨率；但实现的量程和面积成正相关，宽量程意味着较大的面积和功耗。
发明内容
针对上述问题，本发明提出了一种新型的时间数字转化器，其中， 包括：
极性检测模块，包括用于接收时钟信号的两个时钟输入口，以及包括第一时钟输出口、第二时钟输出口和状态输出口；
所述极性检测模块对两个所述时钟输入口输入的所述时钟信号进行时序分析，将时序超前的所述时钟信号从所述第一时钟输出口输出，将时序滞后的所述时钟信号从所述第二时钟输出口输出，以及将两个所述时钟信号的时序比较结果信号从所述状态输出口输出；
时间数字转换模块，包括数字编码单元、环震使能单元、依次串联形成闭合环路的多级的差分延时单元以及多个触发器单元；
环震使能单元分别与所述闭合环路和第一时钟输出口连接，以接收并根据时序超前的所述时钟信号控制所述闭合环路的导通与关断；
每个所述差分延时单元包括第一输入端、第二输入端、第一输出端和第二输出端；每个所述差分延时单元的所述第一输出端和所述第二输出端输出的是互补的差分信号；
每个所述触发器单元分别包括两个触发输入口、两个触发输出口和一时钟信号口；每个所述触发器单元分别对应连接一个所述差分延时单元的所述第一输出端和第二输出端，以根据互补的所述差分信号从两个所述触发输出口输出成组的两个触发信号；每个所述触发器单元的所述时钟信号口连接所述第二时钟输出口，以接收序滞后的所述时钟信号；
所述数字编码单元分别连接所述极性检测模块的所述状态输出口以及每个所述触发器单元的两个所述触发输出口，以接收并根据所述时序比较结果信号和每组所述触发信号生成编码信号。
上述的时间数字转化器，其中，末级的所述差分延时单元的所述 第一输出口或所述第二输出口还连接一计数器，所述计数器用于对末级的所述触发器单元输出的所述触发信号进行震荡周期的计算；
所述计数器还与所述数字编码单元连接，以将包含所述震荡周期的计数信号输出至所述数字编码单元中；
所述数字编码单元根据所述计数信号处理得到一量程参数。
上述的时间数字转化器，其中，每个所述差分延时单元还包括从所述第一输入端朝向所述第一输出端的第一延时器，从所述第二输入端朝向所述第二输出端的第二延时器，从所述第一输出端朝向所述第二输出端的第三延时器，以及从所述第二输出端朝向所述第一输出端的第四延时器。
上述的时间数字转化器，其中，每个所述触发器单元包括灵敏放大器结构。
上述的时间数字转化器，其中，所述状态输出口输出的所述时序比较结果信号包括一第一状态和一第二状态。
上述的时间数字转化器，其中，所述第一状态为高电平状态，所述第二状态为低电平状态。
有益效果：本发明提出的一种新型的时间数字转化器，明显改善反相器上升下降时间和触发器采样的不匹配，使得进入触发器单元的信号为相位互补的信号，进而提高数字转换的线性度。
附图说明
图1为本发明一实施例中时间数字转化器的结构原理图；
图2为本发明一实施例中时间数字转换模块的结构原理图；
图3为本发明一实施例中差分延时单元的结构原理图；
图4为本发明一实施例中触发器单元的结构原理图。
具体实施方式
下面结合附图和实施例对本发明进行进一步说明。
如图1和图2所示，在一个较佳的实施例中，提出了一种新型的时间数字转化器，其中，可以包括：
极性检测模块10，包括用于接收时钟信号的两个时钟输入口(该实施例中为第一时钟输入口CLK1和第二时钟输入口CLK2)，以及包括第一时钟输出口START、第二时钟输出口STOP和状态输出口Polar；
极性检测模块10对两个时钟输入口输入的时钟信号进行时序分析，将时序超前的时钟信号从第一时钟输出口START输出，将时序滞后的时钟信号从第二时钟输出口STOP输出，以及将两个时钟信号的时序比较结果信号从状态输出口Polar输出；
时间数字转换模块20，包括数字编码单元21、环震使能单元22、依次串联形成闭合环路23的多级的差分延时单元以及多个触发器单元24(图2中仅显示了单个的触发器单元作以表示其中的连接关系)；
环震使能单元22分别与闭合环路23和第一时钟输出口START连接，以接收并根据时序超前的时钟信号控制闭合环路23的导通与关断；
如图3所示，每个差分延时单元包括第一输入端IN1、第二输入端IN2、第一输出端OUT1和第二输出端OUT2；每个差分延时单元230的第一输出端OUT1和第二输出端OUT2输出的是互补的差分信号；
如图4所示，每个触发器单元24分别包括两个触发输入口(本实施例中为第一触发输入口D和第二触发输入口Db)、两个触发输出口(本实施例中为第一触发输出口Q和第二触发输出口Qb)和一时钟信号口CLK；每个触发器单元24的两个触发输入口分别对应连接一个差分延时单元的第一输出端OUT1和第二输出端OUT2，以根据互补的差分信号从两个触发输出口输出成组的两个触发信号；每个触发器单元24的时钟信号口CLK连接第二时钟输出口STOP，以接收序滞后的时钟信号；
数字编码单元21分别连接极性检测模块10的状态输出口Polar以及每个触发器单元24的两个触发输出口，以接收并根据时序比较结果信号和每组触发信号生成编码信号。
上述技术方案中，每个触发器单元24的连接具体为第一触发输入口D连接对应的差分延时单元的第一输出端OUT1，第二触发输入口Db连接对应的差分延时单元的第二输出端OUT2；由于每个差分延时单元23中输出的信号为几乎不存在延迟的相位互补的信号，从而使数字转换的线性度更高；生成的编码信号可以输出至外部的系统或电路或设备中进行处理或显示。
在一个较佳的实施例中，末级的差分延时单元的第一输出口OUT1或第二输出口OUT2还连接一计数器，计数器用于对末级的触发器单元24输出的触发信号进行震荡周期的计算；
计数器还与数字编码单元21连接，以将包含震荡周期的计数信号输出至数字编码单元21中；
数字编码单元21根据计数信号处理得到一量程参数。
如图3所示，在一个较佳的实施例中，每个差分延时单元23还包 括从第一输入端IN1朝向第一输出端OUT1的第一延时器，从第二输入端IN2朝向第二输出端OUT2的第二延时器，从第一输出端OUT1朝向第二输出端OUT2的第三延时器，以及从第二输出端OUT2朝向第一输出端OUT1的第四延时器。
上述技术方案中，第一延时器、第二延时器、第三延时器和第四延时器的延时值可以是相同的，但这只是一种优选的情况，还可以是其他情况。
如图4，在一个较佳的实施例中，每个触发器单元24可以包括灵敏放大器结构，以提高第一触发输出口Q和第二触发输出口Qb输出的触发信号的线性度。
在一个较佳的实施例中，状态输出口Polar输出的时序比较结果信号包括一第一状态和一第二状态。
上述实施例中，优选地，第一状态为高电平状态，第二状态为低电平状态。
上述技术方案中，可以是比较结果信号为高电平状态时对应为第一时钟输入口CLK1输入的时钟信号较第二时钟输入口CLK2输入的时钟信号有延迟；反之，比较结果信号为低电平状态时对应为第二时钟输入口CLK2输入的时钟信号较第一时钟输入口CLK1输入的时钟信号有延迟；但这只是一种优选的情况，不应视为是对本发明的限制。
综上所述，本发明提出的一种新型的时间数字转化器，包括：极性检测模块；时间数字转换模块，包括数字编码单元、环震使能单元、依次串联形成闭合环路的多级的差分延时单元以及多个触发器单元；每个差分延时单元包括第一输入端、第二输入端、第一输出端和第二输出端；每个差分延时单元的第一输出端和第二输出端输出的是互补 的差分信号；能够明显改善反相器上升下降时间和触发器采样的不匹配，使得进入触发器单元的信号为相位互补的信号，进而提高数字转换的线性度。
通过说明和附图，给出了具体实施方式的特定结构的典型实施例，基于本发明精神，还可作其他的转换。尽管上述发明提出了现有的较佳实施例，然而，这些内容并不作为局限。
对于本领域的技术人员而言，阅读上述说明后，各种变化和修正无疑将显而易见。因此，所附的权利要求书应看作是涵盖本发明的真实意图和范围的全部变化和修正。在权利要求书范围内任何和所有等价的范围与内容，都应认为仍属本发明的意图和范围内。

Claims (6)

  1. 一种新型的时间数字转化器，其特征在于，包括：
    极性检测模块，包括用于接收时钟信号的两个时钟输入口，以及包括第一时钟输出口、第二时钟输出口和状态输出口；
    所述极性检测模块对两个所述时钟输入口输入的所述时钟信号进行时序分析，将时序超前的所述时钟信号从所述第一时钟输出口输出，将时序滞后的所述时钟信号从所述第二时钟输出口输出，以及将两个所述时钟信号的时序比较结果信号从所述状态输出口输出；
    时间数字转换模块，包括数字编码单元、环震使能单元、依次串联形成闭合环路的多级的差分延时单元以及多个触发器单元；
    环震使能单元分别与所述闭合环路和第一时钟输出口连接，以接收并根据时序超前的所述时钟信号控制所述闭合环路的导通与关断；
    每个所述差分延时单元包括第一输入端、第二输入端、第一输出端和第二输出端；每个所述差分延时单元的所述第一输出端和所述第二输出端输出的是互补的差分信号；
    每个所述触发器单元分别包括两个触发输入口、两个触发输出口和一时钟信号口；每个所述触发器单元分别对应连接一个所述差分延时单元的所述第一输出端和第二输出端，以根据互补的所述差分信号从两个所述触发输出口输出成组的两个触发信号；每个所述触发器单元的所述时钟信号口连接所述第二时钟输出口，以接收序滞后的所述时钟信号；
    所述数字编码单元分别连接所述极性检测模块的所述状态输出口以及每个所述触发器单元的两个所述触发输出口，以接收并根据所述时序比较结果信号和每组所述触发信号生成编码信号。
  2. 根据权利要求1所述的时间数字转化器，其特征在于，末级的所述差分延时单元的所述第一输出口或所述第二输出口还连接一计数器，所述计数器用于对末级的所述触发器单元输出的所述触发信号进行震荡周期的计算；
    所述计数器还与所述数字编码单元连接，以将包含所述震荡周期的计数信号输出至所述数字编码单元中；
    所述数字编码单元根据所述计数信号处理得到一量程参数。
  3. 根据权利要求1所述的时间数字转化器，其特征在于，每个所述差分延时单元还包括从所述第一输入端朝向所述第一输出端的第一延时器，从所述第二输入端朝向所述第二输出端的第二延时器，从所述第一输出端朝向所述第二输出端的第三延时器，以及从所述第二输出端朝向所述第一输出端的第四延时器。
  4. 根据权利要求1所述的时间数字转化器，其特征在于，每个所述触发器单元包括灵敏放大器结构。
  5. 根据权利要求1所述的时间数字转化器，其特征在于，所述状态输出口输出的所述时序比较结果信号包括一第一状态和一第二状态。
  6. 根据权利要求5所述的时间数字转化器，其特征在于，所述第一状态为高电平状态，所述第二状态为低电平状态。
PCT/CN2018/108108 2018-05-02 2018-09-27 一种新型的时间数字转化器 WO2019210642A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/323,181 US11275344B2 (en) 2018-05-02 2018-09-27 Time to digital converter

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810065618.4 2018-05-02
CN201810065618.4A CN108333910B (zh) 2018-05-02 2018-05-02 一种新型的时间数字转化器

Publications (1)

Publication Number Publication Date
WO2019210642A1 true WO2019210642A1 (zh) 2019-11-07

Family

ID=62925399

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/108108 WO2019210642A1 (zh) 2018-05-02 2018-09-27 一种新型的时间数字转化器

Country Status (3)

Country Link
US (1) US11275344B2 (zh)
CN (1) CN108333910B (zh)
WO (1) WO2019210642A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108333910B (zh) * 2018-05-02 2019-12-31 晶晨半导体(上海)股份有限公司 一种新型的时间数字转化器
CN116090399B (zh) * 2023-04-06 2023-06-16 中国人民解放军国防科技大学 基于数据输出端建立时间裕量的触发器转换方法及装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1274200A (zh) * 1999-05-15 2000-11-22 三星电子株式会社 时间数字转换器以及利用该转换器的锁定电路和方法
CN102104384A (zh) * 2009-12-18 2011-06-22 中国科学院微电子研究所 差分延时链单元及包括其的时间数字转换器
US20110279299A1 (en) * 2010-05-13 2011-11-17 Postech Academy-Industry Foundation Sub-exponent time-to-digital converter using phase-difference enhancement device
CN103676622A (zh) * 2013-10-28 2014-03-26 中国电子科技集团公司第四十一研究所 一种高精度的正负时间间隔测量方法及装置
CN103957005A (zh) * 2014-04-30 2014-07-30 华为技术有限公司 时间数字转换器、全数字锁相环电路及方法
CN108333910A (zh) * 2018-05-02 2018-07-27 晶晨半导体(上海)股份有限公司 一种新型的时间数字转化器

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100539428C (zh) * 2007-03-12 2009-09-09 启攀微电子（上海）有限公司 一种高性能时间数字转换器电路架构
US8994573B2 (en) * 2013-03-15 2015-03-31 Intel Mobile Communications GmbH Digital-to-time converter and calibration of digital-to-time converter
US9438265B2 (en) * 2014-01-14 2016-09-06 Intel Corporation Phase multiplexer
CN104614976B (zh) * 2015-02-12 2017-03-29 中国科学技术大学 一种基于fpga的时间数字变换器
JP6604859B2 (ja) * 2016-01-21 2019-11-13 ザインエレクトロニクス株式会社 クロック生成装置およびクロックデータ復元装置
EP3249817B1 (en) * 2016-05-25 2018-12-26 IMEC vzw Dtc-based pll and method for operating the dtc-based pll
CN107870557B (zh) * 2016-09-27 2021-04-27 精工爱普生株式会社 电路装置、物理量测定装置、电子设备和移动体
CN106527099B (zh) * 2016-12-09 2019-07-26 深圳市锐能微科技股份有限公司 一种时间数字转换器及其时间测量电路与方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1274200A (zh) * 1999-05-15 2000-11-22 三星电子株式会社 时间数字转换器以及利用该转换器的锁定电路和方法
CN102104384A (zh) * 2009-12-18 2011-06-22 中国科学院微电子研究所 差分延时链单元及包括其的时间数字转换器
US20110279299A1 (en) * 2010-05-13 2011-11-17 Postech Academy-Industry Foundation Sub-exponent time-to-digital converter using phase-difference enhancement device
CN103676622A (zh) * 2013-10-28 2014-03-26 中国电子科技集团公司第四十一研究所 一种高精度的正负时间间隔测量方法及装置
CN103957005A (zh) * 2014-04-30 2014-07-30 华为技术有限公司 时间数字转换器、全数字锁相环电路及方法
CN108333910A (zh) * 2018-05-02 2018-07-27 晶晨半导体(上海)股份有限公司 一种新型的时间数字转化器

Also Published As

Publication number Publication date
US20210349425A1 (en) 2021-11-11
CN108333910A (zh) 2018-07-27
US11275344B2 (en) 2022-03-15
CN108333910B (zh) 2019-12-31

Similar Documents

Publication Publication Date Title
CN107643674B (zh) 一种基于FPGA进位链的Vernier型TDC电路
Hwang et al. A high-precision time-to-digital converter using a two-level conversion scheme
US10693481B2 (en) Time-to-digital converter and digital phase locked loop
CN106059574B (zh) 用于数字化相位差的电路、pll电路及用于其的方法
US10725433B2 (en) Time-to-digital conversion circuitry
KR20090010663A (ko) 계층구조 위상 디지털 변환기
EP3407145B1 (en) Fpga-based square-wave generator and square-wave generation method
WO2019210642A1 (zh) 一种新型的时间数字转化器
KR20170053990A (ko) 래치 회로, 그 래치 기반의 이중 데이터 레이트 링 카운터, 하이브리드 카운팅 장치, 아날로그-디지털 변환 장치, 및 씨모스 이미지 센서
US20140340250A1 (en) Time integrator and delta-sigma time-to-digital converter
CN112838851A (zh) 一种基于差分采样的剩余时间采样电路和时间数字转换器
CN110824889B (zh) 一种基于新型时间放大器的时间数字转换器
CN106788345B (zh) 利用电阻结构的斜坡信号发生器
CN105425926B (zh) 异步复位同步释放带宽可控的复位电路
CN110311682B (zh) 时间至数字转换器
CN214480526U (zh) 一种基于差分采样的剩余时间采样电路和时间数字转换器
CN115685723A (zh) 一种基于脉冲展宽的时间数字转换器
CN109889200B (zh) 一种基于频率量化器的电压信号转频率信号的电路
CN205263743U (zh) 异步复位同步释放带宽可控的复位电路
KR100879593B1 (ko) 위상 분리기를 이용한 지연 동기 회로 및 이를 이용한 지연동기 방법
Chen et al. A coarse-fine time-to-digital converter
Huang et al. A new cycle-time-to-digital converter with two level conversion scheme
CN114690611A (zh) 一种低功耗的时间数字转换器及转换方法
Abdelmejeed et al. A novel 10-bit high-throughput two-stage TDC with reduced power and improved linearity
TWI545904B (zh) 環狀微刻度時間數位轉換器

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18917435

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 09/02/2021)

122 Ep: pct application non-entry in european phase

Ref document number: 18917435

Country of ref document: EP

Kind code of ref document: A1