WO2019210584A1 - 一种基于p阱浮空技术的采样开关及控制方法 - Google Patents

一种基于p阱浮空技术的采样开关及控制方法 Download PDF

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WO2019210584A1
WO2019210584A1 PCT/CN2018/096090 CN2018096090W WO2019210584A1 WO 2019210584 A1 WO2019210584 A1 WO 2019210584A1 CN 2018096090 W CN2018096090 W CN 2018096090W WO 2019210584 A1 WO2019210584 A1 WO 2019210584A1
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sampling switch
switch
sampling
nmos transistor
well
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PCT/CN2018/096090
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French (fr)
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徐代果
胡刚毅
徐学良
王健安
陈光炳
付东兵
王育新
徐世六
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中国电子科技集团公司第二十四研究所
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0612—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic over the full range of the converter, e.g. for correcting differential non-linearity

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  • the invention belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a sampling switch and a control method based on a P-well floating pwell technology.
  • the high-precision analog-to-digital converter puts forward higher requirements on the sampling switch.
  • the NMOS tube is used as the sampling switch.
  • the conventional voltage bootstrap sampling switch structure can ensure the source and gate of the sampling switch when the input voltage changes. The difference in voltage remains the same, allowing the sampling switch to maintain a certain degree of linearity.
  • a PN+ diode is formed between the source and the drain of the sampling NMOS transistor and the substrate, respectively.
  • the PN+ diode Since the substrate is grounded and the input signal is usually greater than zero, the PN+ diode is in a reverse bias state, which causes the parasitic The capacitance changes with the input signal. In high-precision applications, the above effects will seriously affect the linearity of the sampling switch.
  • the traditional sampling switch is not suitable for the work with higher precision.
  • Capacitor C T A schematic diagram of the space charge region of the PN junction is shown in Figure 1.
  • the barrier capacitance can be expressed as:
  • the simplification of the barrier capacitance can be expressed as:
  • a 1 is the PN+ junction area
  • ⁇ S is the material dielectric constant
  • q is the unit charge amount
  • N A is the P region doping concentration
  • V is the voltage difference between the cathode and the anode.
  • FIG. 2 The schematic diagram of the conventional sampling switch is shown in FIG. 2, wherein the gate of the NMOS transistor MN1 for sampling is connected to the output terminal of the voltage bootstrap circuit BOOST, and the input terminal of the voltage bootstrap circuit BOOST is connected to the sampling NMOS transistor MN1.
  • the source is connected to the input signal VIN, and the drain of the NMOS transistor MN1 for sampling is used as the output end of the sampling signal.
  • a sectional view of a conventional sampling switch is given, as shown in FIG.
  • DNW represents a deep N-well
  • NW connected to the deep N-well DNW represents an N-well
  • N+ in the N-well NW represents an N+ implanted region for extracting the potential of NW
  • the region surrounded by the deep N-well DNW and the N-well NW is P Well P-WELL
  • P+ in P-well P-WELL represents P+ implant region, which is used to draw the potential of P-WELL
  • N+ in P-well P-WELL represents N+
  • the implantation region is the source-drain region of the deep N-well tube NM1
  • G represents the gate of the deep-N well tube NM1.
  • the NMOS transistor MN1 used for sampling uses a deep N-well tube. Except as described in the schematic diagram of FIG. 2, it can be seen that the substrate of the NM1 tube passes through P+ ground, and the deep N-well potential passes through the N+ in the NW to the power supply VDD. There is a parasitic PN+ diode D1 between the source N+ and the drain N+ of the NM1 tube and the substrate P-WELL.
  • V in equation (2) is the input signal VIN in FIG. 3.
  • the barrier capacitance is:
  • a 1 is the PN+ junction area
  • ⁇ S is the material dielectric constant
  • q is the unit charge quantity
  • N A is the P-zone doping concentration
  • VIN is the input voltage.
  • the remaining physical quantities are determined according to the specific process, that is, the remaining physical quantities cannot be changed by the circuit designer.
  • equation (3) the CV curve of the potential capacitance C T of the PN+ diode D1 with the input signal VIN in the reverse bias state is as shown in FIG. 4, where VIN is the input signal and also the PN+ diode cathode voltage, PN+ diode. The anode is grounded.
  • the barrier capacitance C T of the PN+ diode D1 gradually decreases. It is precisely because of the variation of the PN+ diode barrier capacitance in Fig. 4 that changes with the input signal, which causes the nonlinear problem of the sampling switch.
  • FIGS. 5 and 6 The scheme for solving the above problem by using a non-floating well technique is shown in FIGS. 5 and 6.
  • the sampling switch NM1 When the sampling switch NM1 is in the off state, the switch S is turned off, the switch SN is turned on, and the sampling switch NM1 is lining. The bottom potential is pulled down to 0; when the sampling switch is in the sampling state, the switch S is turned on, the switch SN is turned off, and the input end of the sampling tube is directly connected to the substrate.
  • This method eliminates the parasitic diode D1 in the conventional technique shown in FIG. The parasitic capacitance introduced.
  • the disadvantage of this method is that a new parasitic diode is introduced.
  • this method introduces the parasitic diode D1 between the substrate of the sampling switch NM1 and the DNW.
  • the parasitic capacitance of diode D1 changes as the input signal changes, which also causes the linearity of the sampling switch to decrease.
  • the solution to solve the above problem by using floating Nwell technology is shown in Figures 7 and 8.
  • the potential of the deep N-well is pulled up to VDD; when the sampling switch NM1 is in the sampling state, the switch S is turned on, the switch SN is turned off, and the deep N-well DNW is in a floating state, at this time, there is Two parasitic diodes, one is the parasitic diode D1 between P-WELL and DNW, the other is the parasitic diode D2 between P-SUB and DNW, the cathodes of D1 and D2 are connected, and both are in a reverse bias state, and two The diodes are in series. That is to say, the parasitic capacitance generated by D1 and D2 is only the barrier capacitance, and the two barrier capacitances are in series.
  • the sampling tube NM1 When the sampling tube NM1 is in the sampling state, the voltage difference between the anode and the cathode of the diode D1 changes and the voltage difference between the anode and the cathode of the diode D2 does change, which indicates the capacitance of the parasitic capacitance generated by D1 and D2 at this time.
  • the change trend is reversed so that when the sampling tube NM1 is in the sampling state, the parasitic capacitance at the input does not change with the change of the input signal.
  • the disadvantage of this scheme is that three switching tubes are used to realize the large parasitic capacitance in the implementation process, especially the presence of the switch S, which causes a large parasitic capacitance at the input end of the sampling tube NM1. , thereby increasing the nonlinearity of the sampling tube.
  • the present invention provides a sampling switch based on a P-well floating technology, the acquisition switch comprising a boosting circuit, a sampling switch NMOS tube NM1 and a switch SN, one end of the sampling switch being used as an input end VIN, the other end of the sampling switch is used as the output terminal OUT, the input terminal VIN is respectively connected to the input end of the boosting circuit, the input end of the sampling switch NMOS tube NM1, and the output end OUT is connected to the output end of the sampling switch NMOS tube NM1, the boosting circuit
  • the output terminal is connected to the gate of the sampling switch NMOS transistor NM1; the switch SN is connected between the substrate of the sampling switch NMOS transistor NM1 and the ground.
  • the boosting circuit is a bootstrap structure BOOST circuit.
  • the switch SN is turned on, and the substrate P well potential of the sampling switch NMOS transistor NM1 is clamped to 0 by the switch SN.
  • the switch SN is turned off, and the substrate P well of the sampling switch NMOS transistor NM1 is in a floating state.
  • the present invention also provides a control method for a sampling switch based on a P-well floating technique, the sampling switch including a boosting circuit, a sampling switch NMOS tube NM1, and a switch SN, the sampling switch One end is used as the input terminal VIN, the other end of the sampling switch is used as the output terminal OUT, the input terminal VIN is respectively connected to the input end of the boosting circuit, the input end of the sampling switch NMOS tube NM1, and the output end OUT is connected to the output end of the sampling switch NMOS tube NM1.
  • the output end of the boosting circuit is connected to the gate of the sampling switch NMOS transistor NM1; the switch SN is connected between the substrate of the sampling switch NMOS transistor NM1 and the ground; when the sampling switch NMOS transistor NM1 is in the off state, the switch SN Turning on, the substrate P well potential of the sampling switch NMOS transistor NM1 is clamped to zero by the switch SN.
  • the present invention also provides a control method for a sampling switch based on a P-well floating technique, the sampling switch including a boosting circuit, a sampling switch NMOS tube NM1, and a switch SN, the sampling switch One end is used as the input terminal VIN, the other end of the sampling switch is used as the output terminal OUT, the input terminal VIN is respectively connected to the input end of the boosting circuit, the input end of the sampling switch NMOS tube NM1, and the output end OUT is connected to the output end of the sampling switch NMOS tube NM1.
  • the output end of the boosting circuit is connected to the gate of the sampling switch NMOS transistor NM1; the switch SN is connected between the substrate of the sampling switch NMOS transistor NM1 and the ground; when the sampling switch NMOS transistor NM1 is in the sampling state, the switch SN is broken. On, the substrate P well of the sampling switch NMOS transistor NM1 is in a floating state.
  • the sampling switch and the control method based on the P-well floating technology of the present invention have the following beneficial effects:
  • the structure shown in the present invention is very simple, and only one additional switch is introduced, which minimizes the extra parasitic capacitance of the sampling tube, and the circuit implementation is simpler than the conventional technique.
  • the capacitance values of the two parasitic capacitors in series are changed in opposite directions, thereby realizing mutual compensation of the capacitance values, so that the parasitic capacitance of the input tube does not change with the change of the input signal amplitude.
  • the linearity of the sampling switch is further improved.
  • a diode D2 is connected in series on the basis of the original parasitic diode D1, and the series connection of the diodes is realized by series connection of the diodes, thereby reducing the size of the overall parasitic capacitance, and the conventional Compared with the technology, the linearity of the sampling switch is improved.
  • Figure 1 is a schematic diagram of the space charge region of the PN junction
  • Figure 2 is a schematic diagram of a conventional sampling switch
  • Figure 3 is a cross-sectional view of a conventional sampling switch
  • Figure 4 is a C-V curve of the barrier capacitance and the input voltage of MN1 in the reverse bias state of the PN+ diode;
  • Figure 5 is a schematic diagram of a sampling switch using a non-floating technique
  • Figure 6 is a schematic diagram of a sampling switch using a non-floating technique
  • Figure 7 is a schematic diagram of a sampling switch using a floating Nwell technique
  • Figure 8 is a schematic diagram of a sampling switch using a floating Nwell technique
  • FIG. 9 is a schematic diagram of a sampling switch based on a P-well floating pwell technique according to the present invention.
  • FIG. 10 is a cross-sectional view of a sampling switch based on a P-well floating pwell technique according to the present invention.
  • Figure 11 is a comparison of the linearity changes of the three techniques with the input frequency
  • Figure 12 is a comparison of the linearity variations of the three techniques with the amplitude of the input signal.
  • the embodiment provides a sampling switch based on a P-well floating technology
  • the collection switch includes a boosting circuit, a sampling switch NMOS tube NM1 and a switch SN, and one end of the sampling switch is used as an input terminal VIN.
  • the other end of the sampling switch is used as the output terminal OUT, the input terminal VIN is respectively connected to the input end of the boosting circuit, the input end of the sampling switch NMOS tube NM1, and the output terminal OUT is connected to the output end of the sampling switch NMOS tube NM1, and the output end of the boosting circuit Connected to the gate of the sampling switch NMOS transistor NM1; the switch SN is connected between the substrate of the sampling switch NMOS transistor NM1 and the ground.
  • the boost circuit is a bootstrap structure BOOST circuit.
  • the switch SN When the sampling switch NMOS transistor NM1 is in the off state, the switch SN is turned on, and the substrate P well potential of the sampling switch NMOS transistor NM1 is clamped to 0 by the switch SN.
  • the switch SN When the sampling switch NM1 is in the sampling state, the switch SN is turned off, and the substrate P well of the sampling switch NMOS tube NM1 is in a floating state, so that the parasitic capacitance of the input end of the sampling switch NMOS tube NM1 does not change with the change of the input signal, thereby Increase the linearity of the sampling switch.
  • FIG. 10 a cross-sectional view of the sampling switch NMOS transistor NM1 is shown in FIG.
  • P-SUB represents the P substrate of the chip
  • DNW represents the deep N well
  • P-WELL represents the substrate as the sampling switch NMOS transistor NM1
  • P+ represents the P+ implant region
  • N+ represents the N+ implant region.
  • D1 there is a parasitic diode D1 between the P-WELL and the N+ implant region of the input terminal of the sampling switch NMOS transistor NM1; meanwhile, there is also a parasitic diode D2 between the P-WELL and the DNW.
  • the cathode of diode D1 is the input terminal VIN of the sampling switch NMOS tube NM1, the anode of the diode D1 is the substrate P-WELL of the sampling switch NMOS tube NM1; the cathode of the diode D2 is DNW, and the anode of the diode D2 is the sampling switch NMOS tube NM1 The substrate P-WELL, whereby the anodes of the diodes D1 and D2 are connected.
  • the barrier capacitance This capacitor exists only when the diode is in the reverse bias state.
  • the other is the diffusion capacitor.
  • the sampling switch NMOS transistor NM1 When the sampling switch NMOS transistor NM1 is in the sampling state, the diodes D1 and D2 are in a reverse bias state, and the diode in the reverse biased state only has a barrier capacitance. Since the sampling switch NMOS transistor NM1 is in the sampling state, the substrate P-WELL is in a floating state, so the parasitic capacitance seen at the signal input terminal can be equivalent to the parasitic barrier capacitance C1 of the diode D1 and the parasitic of the diode D2. The total capacitance obtained after the barrier capacitor C2 is connected in series.
  • the present invention Since the capacitance value is significantly reduced after the capacitors are connected in series, the present invention has a significantly reduced parasitic capacitance at the input end of the sampling switch compared with the conventional technology, which improves the linearity of the sampling switch. Further, since the two capacitors are connected in series, a partial voltage effect is generated. Therefore, when the input signal VIN increases, the voltage V A of the anodes of the two diodes D1 and D2 increases, thereby, the cathode and the anode of the diode D1. The voltage difference between the two will increase. It is known from the transistor principle that this will reduce the capacitance of the barrier capacitor C1.
  • the voltage difference between the cathode and the anode of the diode D2 will decrease. According to the principle related knowledge, this will increase the capacitance of the barrier capacitance C2. If the values of C1 and C2 are properly set, the values of the capacitor C1 and the capacitor C2 are mutually compensated, so that the parasitic capacitance at the input end of the sampling switch does not change with the amplitude of the input signal, so the linearity of the sampling switch of the present invention is obtained. Further improvement. Finally, the structure shown in the present invention introduces only one additional switch SN, so that the structure shown in the present invention is very simple, and the circuit structure is significantly simplified compared with the prior art, reducing the manufacturing cost of the circuit.
  • the three structures described in FIGS. 5-10 are carefully designed in a 65 nm CMOS process, and the same sampling tube size is used for the three structures described in FIGS.
  • the capacitance value is taken as 120fF.
  • the linearity variation of the three techniques varies with the input frequency as shown in FIG.
  • the linearity variation of the three techniques varies with the amplitude of the input signal as shown in FIG. It can be seen from FIG. 11 and FIG. 12 that the linearity of the sampling switch is improved by using the floating pwell, and the advantages of the present invention are more obvious as the frequency and amplitude of the input signal increase.

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Abstract

本发明提供一种基于P阱浮空技术的采样开关及控制方法，该采样开关包括升压电路、采样开关NMOS管NM1和开关SN，所述采样开关的一端作为输入端VIN，采样开关的另一端作为输出端OUT，输入端VIN分别连接升压电路的输入端、采样开关NMOS管NM1的输入端，输出端OUT连接采样开关NMOS管NM1的输出端，升压电路的输出端与采样开关NMOS管NM1的栅极连接；所述开关SN连接于采样开关NMOS管NM1的衬底与地之间。本发明所示结构非常简单，只引入了一个额外的开关，最大程度减小了采样管的额外寄生电容，和传统技术相比，电路实现也更为简单。

Description

一种基于P阱浮空技术的采样开关及控制方法 技术领域
本发明属于模拟或数模混合集成电路技术领域，涉及一种基于P阱浮空(floating pwell)技术的采样开关及控制方法。
背景技术
近年来，随着模数转换器性能指标的进一步提高，特别是随着集成电路工艺技术的不断发展，对高精度模数转换器的研究也越来越深入。高精度模数转换器对采样开关提出了更高的要求，通常采用NMOS管作为采样开关，传统的电压自举采样开关结构，虽然在输入电压变化时，能保证采样开关源极和栅极的电压之差保持不变，从而使得采样开关能保持一定的线性度。但是，采样NMOS管的源极和漏极分别和衬底之间会形成一个PN+二极管，由于衬底接地，而输入信号通常大于零，从而造成上述PN+二极管处于反偏状态，这会使得上述寄生电容随着输入信号的变化而变化，在高精度应用时，上述效应会严重影响采样开关的线性度，传统的采样开关不能胜任更高精度下的工作需求。
为了更详细的描述上述问题，先来分析PN结的电容特性，由晶体管原理的知识可知，PN结存在两种电容，第一种是势垒电容C T，在PN结反偏和正偏情况下，这种电容均存在，第二种是扩散电容C D，只存在于PN结正偏情况下，由于本发明所涉及的PN结都工作在反偏状态，所以这里只讨论PN结的势垒电容C T。PN结的空间电荷区示意图如图1所示，势垒电容可表示为：
Figure PCTCN2018096090-appb-000001
对于PN+二极管而言，经过化简，势垒电容可以表示为：
Figure PCTCN2018096090-appb-000002
其中，A 1为PN+结面积，ε S为材料介电常数，q为单位电荷电量，N A为P区掺杂浓度，V为阴极相对于阳极的电压差。
传统采样开关的原理图如图2所示，其中用于采样的NMOS管MN1的栅极接电压自举电路BOOST的输出端，电压自举电路BOOST的输入端接用于采样的NMOS管MN1的源极， 同时接输入信号VIN，用于采样的NMOS管MN1的漏极作为采样信号的输出端。为了更方便说明寄生效应，给出传统采样开关的剖面图，如图3所示。其中DNW表示深N阱，和深N阱DNW相连的NW表示N阱，N阱NW中的N+表示N+注入区，用来引出NW的电位，深N阱DNW和N阱NW包围的区域为P阱P-WELL，P-WELL作为深N阱管NM1的衬底，P阱P-WELL中的P+表示P+注入区，用来引出P-WELL的电位，P阱P-WELL中的N+表示N+注入区，是深N阱管NM1的源漏区，G表示深N阱管NM1的栅极。用于采样的NMOS管MN1采用深N阱管，除了图2中原理图的描述之外，可以看到，NM1管的衬底通过P+接地，而深N阱电位通过NW中的N+接电源VDD，NM1管的源极N+和漏极N+与衬底P-WELL之间分别有一个寄生PN+二极管D1。
现在来分析PN+寄生二极管D1在反向偏压下的势垒电容状态。前文中，式(2)中的V即是图3中的输入信号VIN，现结合图3的结构，其势垒电容为：
Figure PCTCN2018096090-appb-000003
其中，A 1为PN+结面积，ε S为材料介电常数，q为单位电荷电量，N A为P区掺杂浓度，VIN为输入电压。除了输入电压VIN之外，其余的物理量都是根据具体工艺来确定的，也就是说，其余物理量是电路设计人员无法改变的。根据式(3)可知，PN+二极管D1的势垒电容C T在反偏状态下随输入信号VIN的C-V曲线如图4所示，此时VIN为输入信号，同时也是PN+二极管阴极电压，PN+二极管的阳极接地。从图4中可以看到，随着阴极电压VIN的增加，PN+二极管D1的势垒电容C T逐渐减小。正是由于图4中的这种PN+二极管势垒电容随输入信号变化而变化的特点，导致了采样开关的非线性问题。
基于上述问题，现对目前提出的两种解决方案的优缺点进行分析。采用非浮空阱(non-floating well)技术解决上述问题的方案如图5、6所示，当采样开关NM1处于关断状态时，开关S关断，开关SN导通，采样开关NM1的衬底电位被下拉到0；当采样开关处于采样状态时，开关S导通，开关SN关断，采样管输入端和衬底直接相连，这种方法消除了图3所示传统技术中寄生二极管D1引入的寄生电容。但这种方法的缺点在于，又引入了一个新的寄生二极管，如图5、6所示，这种方法引入了采样开关NM1的衬底到DNW之间的寄生二极管D1，在采样过程中，二极管D1的寄生电容会随着输入信号的变化而变化，同样会导致采样开关线性度的下降。采用浮空N阱(floating nwell)技术解决上述问题的方案如图7、8所示，当采样开关NM1处于关断状态时，开关S关断，开关SN导通，采样开关NM1的衬底电位被下拉到0，深N阱的电位被上拉到VDD；当采样开关NM1处于采样状态时，开关S导通， 开关SN关断，此时深N阱DNW处于浮空状态，此时，存在两个寄生二极管，一个是P-WELL和DNW之间的寄生二极管D1，另一个是P-SUB和DNW之间的寄生二极管D2，D1和D2的阴极相连，并且都处于反偏状态，并且两个二极管处于串联状态。也就是说D1和D2所产生的寄生电容都只有势垒电容，并且两个势垒电容处于串联状态。当采样管NM1处于采样状态时，二极管D1阳极和阴极之间的电压差变化和二极管D2阳极和阴极之间的电压差变化确实相反，这说明此时D1和D2所产生的寄生电容的容值变化趋势相反，从而使得采样管NM1处于采样状态时，输入端的寄生电容不随输入信号的变化而变化。但这种方案的缺点在于，使用了三个开关管来实现，在实现过程中会带来较大的寄生电容，特别是开关S的存在，会使得采样管NM1输入端存在较大的寄生电容，从而增加采样管的非线性。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种基于P阱浮空技术的采样开关及控制方法，以解决现有技术增加采样管的非线性的技术问题。
为实现上述目的及其他相关目的，本发明提供一种基于P阱浮空技术的采样开关，该采集开关包括升压电路、采样开关NMOS管NM1和开关SN，所述采样开关的一端作为输入端VIN，采样开关的另一端作为输出端OUT，输入端VIN分别连接升压电路的输入端、采样开关NMOS管NM1的输入端，输出端OUT连接采样开关NMOS管NM1的输出端，升压电路的输出端与采样开关NMOS管NM1的栅极连接；所述开关SN连接于采样开关NMOS管NM1的衬底与地之间。
优选地，所述升压电路为自举结构BOOST电路。
优选地，当采样开关NMOS管NM1处于关断状态时，开关SN导通，采样开关NMOS管NM1的衬底P阱电位被开关SN钳位为0。
优选地，当采样开关NMOS管NM1处于采样状态时，开关SN断开，采样开关NMOS管NM1的衬底P阱处于浮空状态。
为实现上述目的及其他相关目的，本发明还提供一种基于P阱浮空技术的采样开关的控制方法，该采样开关包括升压电路、采样开关NMOS管NM1和开关SN，所述采样开关的一端作为输入端VIN，采样开关的另一端作为输出端OUT，输入端VIN分别连接升压电路的输入端、采样开关NMOS管NM1的输入端，输出端OUT连接采样开关NMOS管NM1的输出端，升压电路的输出端与采样开关NMOS管NM1的栅极连接；所述开关SN连接于采样开关NMOS管NM1的衬底与地之间；当采样开关NMOS管NM1处于关断状态时，开关SN导通， 采样开关NMOS管NM1的衬底P阱电位被开关SN钳位为0。
为实现上述目的及其他相关目的，本发明还提供一种基于P阱浮空技术的采样开关的控制方法，该采样开关包括升压电路、采样开关NMOS管NM1和开关SN，所述采样开关的一端作为输入端VIN，采样开关的另一端作为输出端OUT，输入端VIN分别连接升压电路的输入端、采样开关NMOS管NM1的输入端，输出端OUT连接采样开关NMOS管NM1的输出端，升压电路的输出端与采样开关NMOS管NM1的栅极连接；所述开关SN连接于采样开关NMOS管NM1的衬底与地之间；当采样开关NMOS管NM1处于采样状态时，开关SN断开，采样开关NMOS管NM1的衬底P阱处于浮空状态。
如上所述，本发明的一种基于P阱浮空技术的采样开关及控制方法，具有以下有益效果：
1、本发明所示结构非常简单，只引入了一个额外的开关，最大程度减小了采样管的额外寄生电容，和传统技术相比，电路实现也更为简单。
2、通过引入P阱浮空技术，使得串联的两个寄生电容的容值变化方向相反，从而实现了容值的相互补偿，使得输入管的寄生电容容值不随输入信号幅度的变化而变化，和传统技术相比，进一步提高了采样开关的线性度。
3、通过引入P阱浮空技术，在原有寄生二极管D1的基础上，再串联了一个二极管D2，通过二极管的串联，实现了寄生电容的串联，从而减小了整体寄生电容的大小，和传统技术相比，提高了采样开关的线性度。
附图说明
图1为PN结的空间电荷区原理图；
图2为传统采样开关原理图；
图3为传统采样开关剖面图；
图4为PN+二极管反偏状态下势垒电容与MN1输入电压的C-V曲线；
图5为采用非浮空阱(non floating)技术的采样开关的原理图；
图6为采用非浮空阱(non floating)技术的采样开关的原理图；
图7为采用浮空N阱(floating nwell)技术的采样开关的原理图；
图8为采用浮空N阱(floating nwell)技术的采样开关的原理图；
图9为本发明提出的一种基于P阱浮空(floating pwell)技术的采样开关的原理图；
图10为本发明提出的一种基于P阱浮空(floating pwell)技术的采样开关的剖面图；
图11为三种技术的线性度变化随输入频率的变化对比图；
图12为三种技术的线性度变化随输入信号幅度的变化对比图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图9所示，本实施例提供一种基于P阱浮空技术的采样开关，该采集开关包括升压电路、采样开关NMOS管NM1和开关SN，所述采样开关的一端作为输入端VIN，采样开关的另一端作为输出端OUT，输入端VIN分别连接升压电路的输入端、采样开关NMOS管NM1的输入端，输出端OUT连接采样开关NMOS管NM1的输出端，升压电路的输出端与采样开关NMOS管NM1的栅极连接；所述开关SN连接于采样开关NMOS管NM1的衬底与地之间。所述升压电路为自举结构BOOST电路。
当采样开关NMOS管NM1处于关断状态时，开关SN导通，采样开关NMOS管NM1的衬底P阱电位被开关SN钳位为0。当采样开关NM1处于采样状态时，开关SN断开，采样开关NMOS管NM1的衬底P阱处于浮空状态，实现采样开关NMOS管NM1的输入端寄生电容不随输入信号变化而变化的目的，从而提高采样开关的线性度。
为了进一步说明本实施例的优点，采样开关NMOS管NM1的剖面图如图10所示。其中P-SUB表示芯片的P衬底，DNW表示深N阱，P-WELL表示作为采样开关NMOS管NM1的衬底，P+表示P+注入区，N+表示N+注入区。由图10可知，在P-WELL和采样开关NMOS管NM1的输入端的N+注入区之间，存在一个寄生二极管D1；同时，在P-WELL和DNW之间也存在一个寄生二极管D2。二极管D1的阴极为采样开关NMOS管NM1的输入端VIN，二极管D1的阳极为采样开关NMOS管NM1的衬底P-WELL；二极管D2的阴极为DNW，二极管D2的阳极为采样开关NMOS管NM1的衬底P-WELL，由此，二极管D1和D2的阳极相连。由晶体管原理知识可知，二极管存在两种寄生电容，一种是势垒电容，这种电容只在二极管处于反偏状态下存在；另一种是扩散电容，这种在二极管处于反偏和正偏情况下都存在。当 采样开关NMOS管NM1处于采样状态时，二极管D1和D2都处于反偏状态，而处于反偏状态的二极管只存在势垒电容。由于采样开关NMOS管NM1处于采样状态时，其衬底P-WELL处于浮空状态，因此，可以将信号输入端看到的寄生电容等效为二极管D1的寄生势垒电容C1和二极管D2的寄生势垒电容C2串联后所得到的总电容。由于电容串联之后容值会明显减小，所以本发明和传统技术相比，采样开关输入端的寄生电容明显减小，提升了采样开关的线性度。进一步，由于两个电容串联后，会产生一个分压的效果，所以，当输入信号VIN增加时，两个二极管D1和D2阳极的电压V A会有所增加，从而，二极管D1阴极和阳极之间的电压差会增加，由晶体管原理相关知识可知，这会使得势垒电容C1的容值减小；由于V A电压的增加，二极管D2阴极和阳极之间的电压差会减小，由晶体管原理相关知识可知，这会使得势垒电容C2的容值增加。如果合理设置C1和C2的值，会使得电容C1和电容C2的值相互补偿，从而，使得采样开关输入端的寄生电容不随输入信号幅度的变化而变化，因此本发明所示采样开关的线性度得到了进一步提升。最后，本发明所示结构只引入了一个额外的开关SN，使得本发明所示结构非常简单，和目前现有相关技术相比，电路结构明显简化，降低了电路的制造成本。
为了进一步验证本发明的上述优点，在65nmCMOS工艺下，对图5～10所述的三种结构进行了仔细的设计，对于图5～10所述的三种结构采用相同的采样管尺寸，采样电容容值都取120fF。在输入信号Vp-p＝1V，采样频率Fsample＝320MHz情况下，三种技术的线性度变化随输入频率的变化如图11所示。在输入信号频率Fin＝85MHz，采样频率Fsample＝320MHz情况下，三种技术的线性度变化随输入信号幅度的变化如图12所示。由图11和图12可知，采用本技术(floating pwell)后，采样开关的线性度得到了提升，随着输入信号频率和幅度的增加，本发明的优势更为明显。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (6)

  1. 一种基于P阱浮空技术的采样开关，其特征在于，该采集开关包括升压电路、采样开关NMOS管NM1和开关SN，所述采样开关的一端作为输入端VIN，采样开关的另一端作为输出端OUT，输入端VIN分别连接升压电路的输入端、采样开关NMOS管NM1的输入端，输出端OUT连接采样开关NMOS管NM1的输出端，升压电路的输出端与采样开关NMOS管NM1的栅极连接；所述开关SN连接于采样开关NMOS管NM1的衬底与地之间。
  2. 根据权利要求1所述的一种基于P阱浮空技术的采样开关，其特征在于，所述升压电路为自举结构BOOST电路。
  3. 根据权利要求1所述的一种基于P阱浮空技术的采样开关，其特征在于，当采样开关NMOS管NM1处于关断状态时，开关SN导通，采样开关NMOS管NM1的衬底P阱电位被开关SN钳位为0。
  4. 根据权利要求1或3所述的一种基于P阱浮空技术的采样开关，其特征在于，当采样开关NMOS管NM1处于采样状态时，开关SN断开，采样开关NMOS管NM1的衬底P阱处于浮空状态。
  5. 一种基于P阱浮空技术的采样开关的控制方法，其特征在于，该采样开关包括升压电路、采样开关NMOS管NM1和开关SN，所述采样开关的一端作为输入端VIN，采样开关的另一端作为输出端OUT，输入端VIN分别连接升压电路的输入端、采样开关NMOS管NM1的输入端，输出端OUT连接采样开关NMOS管NM1的输出端，升压电路的输出端与采样开关NMOS管NM1的栅极连接；所述开关SN连接于采样开关NMOS管NM1的衬底与地之间；当采样开关NMOS管NM1处于关断状态时，开关SN导通，采样开关NMOS管NM1的衬底P阱电位被开关SN钳位为0。
  6. 一种基于P阱浮空技术的采样开关的控制方法，其特征在于，该采样开关包括升压电路、采样开关NMOS管NM1和开关SN，所述采样开关的一端作为输入端VIN，采样开关的另一端作为输出端OUT，输入端VIN分别连接升压电路的输入端、采样开关NMOS管NM1的输入端，输出端OUT连接采样开关NMOS管NM1的输出端，升压电路的输出端与采样开关NMOS管NM1的栅极连接；所述开关SN连接于采样开关NMOS管NM1的衬底与地之间；当采样开关NMOS管NM1处于采样状态时，开关SN断开，采样开关NMOS管NM1的衬底P阱处于浮空状态。
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