WO2019205637A1 - 集成电路芯片的数据写入方法、系统、装置、设备及介质 - Google Patents

集成电路芯片的数据写入方法、系统、装置、设备及介质 Download PDF

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Publication number
WO2019205637A1
WO2019205637A1 PCT/CN2018/118930 CN2018118930W WO2019205637A1 WO 2019205637 A1 WO2019205637 A1 WO 2019205637A1 CN 2018118930 W CN2018118930 W CN 2018118930W WO 2019205637 A1 WO2019205637 A1 WO 2019205637A1
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WO
WIPO (PCT)
Prior art keywords
integrated circuit
circuit chip
data
power supply
programmer
Prior art date
Application number
PCT/CN2018/118930
Other languages
English (en)
French (fr)
Inventor
朱威行
Original Assignee
天浪创新科技（深圳）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from PCT/CN2018/084246 external-priority patent/WO2019204982A1/zh
Priority claimed from CN201810373882.4A external-priority patent/CN108363581B/zh
Priority claimed from CN201811271213.2A external-priority patent/CN109542465B/zh
Application filed by 天浪创新科技（深圳）有限公司 filed Critical 天浪创新科技（深圳）有限公司
Priority to JP2019508808A priority Critical patent/JP6799143B2/ja
Priority to US16/322,588 priority patent/US11410711B2/en
Publication of WO2019205637A1 publication Critical patent/WO2019205637A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/61—Installation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Definitions

  • the present application belongs to the field of integrated circuit technology, and in particular, to a data writing method, system, device, device and medium for an integrated circuit chip.
  • Electrically erasable programmable read only memory Electrically Erasable Programmable Read Only Memory (EEPROM), Flash (Flash), Programmable Logic Device (Programmable) Logic Device, PLD, etc. are favored in the electronics industry due to their programmable functions.
  • EEPROM Electrically Erasable Programmable Read Only Memory
  • Flash Flash
  • Programmable Logic Device Programmable Logic Device
  • PLD Programmable Logic Device
  • the embodiment of the present application provides a data writing method, system, device, device and medium for an integrated circuit chip, so as to solve the problem that the data writing method of the integrated circuit chip in the prior art is inflexible and the production efficiency of the finished product is low.
  • a first aspect of the embodiments of the present application provides a data writing method for an integrated circuit chip, which is applied to a programmer, and the integrated circuit chip is electrically connected to the burner through a power supply positive electrode and a power supply negative electrode; the integration
  • the circuit chip has built-in or external memory; the data writing means that the integrated circuit chip writes data to the memory through the programmer; the data writing method includes:
  • the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command;
  • data is written to the integrated circuit chip by controlling electrical parameters of the integrated circuit chip power supply positive or power supply negative input voltage.
  • a second aspect of the present application provides a data writing method for an integrated circuit chip, where the integrated circuit chip is connected to a programmer through a power supply positive electrode and a power supply negative electrode; and the data writing method includes:
  • the integrated circuit chip receives the data write command sent by the programmer, and enters a data write mode
  • the integrated circuit chip determines the data transmitted by the programmer by detecting an electrical parameter of the power supply positive pole or the power supply negative input voltage controlled by the burner;
  • the integrated circuit chip enables data transmitted by the programmer.
  • a third aspect of the embodiments of the present application provides a data writing system for an integrated circuit chip, the data writing system including a programmer and an integrated circuit chip, the programmer including a main control and a first signal conversion circuit The main control is electrically connected to the power supply positive pole and the power supply negative pole of the integrated circuit chip through the first signal conversion circuit;
  • the master control is used for controlling
  • the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command;
  • the first signal conversion circuit controls the electrical parameters of the integrated circuit chip power supply positive electrode or the power supply negative input voltage to perform data writing on the integrated circuit chip.
  • a fourth aspect of the embodiments of the present application provides a data writing device for an integrated circuit chip, configured in a programmer, wherein the integrated circuit chip is electrically connected to the programmer through a power supply positive electrode and a power supply negative electrode.
  • the data writing device includes:
  • a sending unit configured to send a data write command to the integrated circuit chip; the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command;
  • control execution unit configured to perform data writing on the integrated circuit chip by controlling an electrical parameter of the integrated circuit chip power supply positive electrode or the power supply negative input voltage after the integrated circuit chip enters the data write mode.
  • a fifth aspect of the embodiments of the present application provides a data writing device for an integrated circuit chip, configured in an integrated circuit chip, wherein the integrated circuit chip is electrically connected to a burner through a power supply positive electrode and a power supply negative electrode;
  • the device includes:
  • a receiving unit configured to receive a data write command sent by the programmer, and enter a data writing mode
  • a detecting execution unit configured to determine data transmitted by the programmer by detecting an electrical parameter of the power supply positive pole or the power supply negative input voltage controlled by the programmer;
  • An enabling unit for enabling data transmitted by the programmer is a unit for enabling data transmitted by the programmer.
  • a sixth aspect of an embodiment of the present application provides a data writing device of an integrated circuit chip, including a memory, a processor, and computer readable instructions stored in the memory and operable on the processor, features The steps of the method of the first aspect or the second aspect are implemented when the processor executes the computer readable instructions.
  • a seventh aspect of the embodiments of the present application provides a computer readable storage medium storing computer readable instructions, wherein the computer readable instructions are implemented by a processor The steps of the method of the aspect or the second aspect.
  • the power supply positive electrode and the power supply negative electrode of the integrated circuit chip are electrically connected to the programmer, and the programmer sends a data write command to the integrated circuit chip; after the integrated circuit chip enters the data write mode, The electrical parameters of the integrated circuit chip power supply positive electrode or the power supply negative input voltage input data to the integrated circuit chip, which solves the technical problem that the data writing method of the integrated circuit chip is inflexible and the production efficiency of the finished product is low.
  • FIG. 1 is a schematic flowchart showing an implementation process of a data writing method of an integrated circuit chip according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a data writing system of an integrated circuit chip according to an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a data writing system of another integrated circuit chip according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of controlling a magnitude of an input voltage in a data writing method of an integrated circuit chip according to an embodiment of the present application
  • FIG. 5 is a schematic diagram of controlling a frequency of an electrical signal superimposed on an input voltage in a data writing method of an integrated circuit chip according to an embodiment of the present application;
  • FIG. 6 is a schematic flowchart showing an implementation of a data writing method of another integrated circuit chip according to an embodiment of the present application.
  • FIG. 7 is a schematic flowchart showing an implementation of a data writing method of another integrated circuit chip according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a data writing system of another integrated circuit chip according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a data writing system of another integrated circuit chip according to an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a data writing device of an integrated circuit chip according to an embodiment of the present application.
  • FIG. 11 is a schematic diagram of another data writing device of an integrated circuit chip according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a data writing device of an integrated circuit chip according to an embodiment of the present application.
  • FIG. 13 is a schematic flowchart showing an implementation of a data writing method of another integrated circuit chip according to an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a data writing system of another integrated circuit chip according to an embodiment of the present application.
  • 15 is a schematic structural diagram of a data writing system of another integrated circuit chip according to an embodiment of the present application.
  • 16 is a schematic flowchart showing an implementation of a data writing method of another integrated circuit chip according to an embodiment of the present application.
  • 17 is a schematic flowchart showing an implementation of a data writing method of another integrated circuit chip according to an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of a data writing system of another integrated circuit chip according to an embodiment of the present application.
  • FIG. 19 is a schematic structural diagram of a data writing system of another integrated circuit chip according to an embodiment of the present application.
  • FIG. 20 is a schematic diagram of a data writing device of an integrated circuit chip according to an embodiment of the present application.
  • FIG. 1 is a schematic flowchart showing an implementation process of a data writing method of an integrated circuit chip according to an embodiment of the present application.
  • the data writing method is suitable for the case where data is written to the integrated circuit chip, and is applied to the programmer, and can be implemented by software and/or hardware.
  • the data writing method includes the steps of: S101 to S103.
  • S101 Send a data write command to the integrated circuit chip.
  • the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command, and return a feedback signal.
  • the integrated circuit chip refers to an integrated circuit that can be independently used after being designed, manufactured, packaged, and tested, and has a data processing function, a built-in or an external memory.
  • the integrated circuit chip may be a micro control unit (Microcontroller) Unit, MCU), central processing unit (Central Processing Unit, CPU), Digital Signal Processing (DSP) or PLD.
  • the memory may be an EEPROM or a Flash or the like.
  • the programmer is a tool capable of writing data to an integrated circuit chip, and is mainly used for programming a chip such as a single chip/memory.
  • the integrated circuit chip is electrically connected to the programmer directly through its own power supply positive electrode and the power supply negative electrode. Specifically, the integrated circuit chip is electrically connected to the burner through the input 2 line of the power supply positive pole and the power supply negative pole, and the burner is externally connected to the power source to form a circuit loop.
  • the power supply positive electrode may be a power supply positive VCC (Volt Current) Condenser), can also be the power supply positive VDD (Voltage Drain Drain), select and determine according to the specific integrated circuit chip.
  • the power supply negative electrode may be a power supply negative electrode VSS, or may be a power ground (Ground, GND), and is determined according to a specific integrated circuit chip. Since the integrated circuit chip is typically powered by a single power supply, the negative supply is grounded.
  • the integrated circuit chip is electrically connected to the burner through its own power supply positive electrode and the power supply negative electrode, as shown in FIG. 2, and the power supply positive electrode is used as the power supply positive electrode.
  • VCC the negative pole of the power supply is GND, and the programmer writes data of the integrated circuit chip by controlling the electrical parameters of the positive input voltage of the integrated circuit chip for example.
  • a battery holder for powering the product is generally provided, and the battery holder is connected to the power supply positive pole of the integrated circuit chip and the power supply negative input 2 line. Isolating the battery on the battery holder or taking out the power supply battery from the battery holder, and electrically connecting the integrated circuit chip to the burner directly through the power source positive pole and the power source negative contact on the battery holder. ,As shown in Figure 3.
  • the programmer is externally connected to a power source to form a circuit loop.
  • the programmer sends a data write command to the integrated circuit chip; the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command, and return a feedback signal.
  • the data writing mode refers to a preparation state in which the integrated circuit chip responds to data writing by the programmer.
  • the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command, and return a feedback signal. Returning the feedback signal to the integrated circuit chip means that the integrated circuit chip feeds back a signal that it has entered the data write mode to the programmer.
  • the programmer includes a master control, and sends an instruction to the integrated circuit chip through the master control; after receiving the instruction sent by the programmer, the integrated circuit chip passes the built-in or external second signal.
  • the conversion circuit detects and determines the sent command. If the sent command is a data write command, the integrated circuit chip enters the data write mode and sends a feedback signal to the programmer.
  • the integrated circuit chip is also connected with an LED and/or a speaker. After the integrated circuit chip successfully enters the data writing mode, the LED light electrically connected to the integrated circuit chip is controlled to flash and/or the speaker emits a sound to prompt the integrated circuit chip to successfully enter the data writing mode.
  • the feedback signal returned by the integrated circuit chip refers to the integrated circuit chip feeding back a signal that it has entered the data writing mode to the programmer.
  • the programmer After receiving the feedback signal returned by the integrated circuit chip, the programmer inputs data to the integrated circuit chip by controlling electrical parameters of the positive input voltage of the integrated circuit chip.
  • S103 Write data to the integrated circuit chip by controlling an electrical parameter of the positive input voltage of the integrated circuit chip.
  • the data writing means that the programmer transmits data that needs to be written by the integrated circuit chip to the integrated circuit chip, thereby updating information in the built-in or external storage of the integrated circuit chip.
  • the electrical parameter for controlling the input voltage of the positive electrode of the integrated circuit chip may be the size of the positive input voltage of the integrated circuit chip, such as a square wave voltage, or may be an electrical signal superimposed on the positive input voltage of the integrated circuit chip.
  • Frequency of For example, controlling the frequency of the sinusoidal signal superimposed on the positive input voltage of the integrated circuit chip power supply; for example, controlling the frequency of the triangular wave, the sawtooth wave, and the like which are superimposed on the positive input voltage of the integrated circuit chip. It should be noted that the description is merely exemplary and is not to be construed as limiting the application.
  • the programmer includes a first signal conversion circuit, and the programmer controls the electrical parameters of the positive input voltage of the integrated circuit chip through its built-in signal conversion circuit to write data to the integrated circuit chip.
  • the programmer writes data to the integrated circuit chip by controlling the magnitude of the input voltage of the positive electrode of the integrated circuit chip, which means that the programmer changes its built-in first signal conversion circuit.
  • the size of the input voltage of the positive pole of the integrated circuit chip is transmitted to transfer binary data "0" and "1".
  • VCC refers to the input voltage of the integrated circuit chip power supply positive VCC, generally 1.8V, 3V, or 5V.
  • the value range of ⁇ is (0, VCC).
  • the larger the number of input voltage values the higher the transmission efficiency of the transmitted data, thereby further improving the efficiency of data writing.
  • two input voltage values VCC- ⁇ and VCC are selected for transmission respectively. Binary data "0" and "1".
  • the programmer writes data to the integrated circuit by controlling the frequency of the sinusoidal signal superimposed on the input voltage of the positive electrode of the integrated circuit chip, which means that the burner passes through the built-in first
  • the signal conversion circuit changes the frequency of the sinusoidal signal superimposed on the input voltage of the positive electrode of the integrated circuit chip to transmit binary data "0" and "1".
  • the current programmer is to write data to a memory integrated or external to the integrated circuit chip through a specific interface of the integrated circuit chip, such as a JTAG interface, and at least four wires are used, and the technical solution provided by the present application is only utilized.
  • the power supply positive pole of the integrated circuit chip and the power supply negative input 2 line can complete the data writing, which is simpler and more convenient; in addition, since the data writing of the present application no longer depends on a specific interface such as JTAG, the manufacturer's binding chip is skillfully reduced. cost.
  • the integrated circuit chip enters the data writing mode and returns a feedback signal to enable the programmer to write data to the integrated circuit chip.
  • the integrated circuit chip enters the data write mode after receiving the data write command, regardless of the feedback signal of the integrated circuit chip to indicate that it successfully enters the data write mode, or returns to successfully enter the data write mode.
  • the programmer can perform data writing on the integrated circuit chip.
  • the manner in which the integrated circuit chip returns the feedback signal in this embodiment is merely an exemplary description and cannot be construed as a specific limitation on the present application.
  • the assembled electronic product generally cannot perform data writing to complete the function replacement, or needs to perform extremely cumbersome disassembly to enable data writing to complete the function replacement, and adopt the technology provided by the present application.
  • the solution, for the assembled electronic product can directly complete the data writing by means of the positive power supply of the built-in integrated circuit chip of the product, the positive electrode contact and the negative contact of the battery base power supply corresponding to the electrical input negative input, thereby realizing the assembly.
  • Functional updates of good electronic products Since these contacts are externally visible, they do not require cumbersome disassembly and are easy and flexible to implement.
  • FIG. 6 is a schematic flowchart showing the implementation of a data writing method of another integrated circuit chip according to an embodiment of the present application.
  • the data writing method includes the steps of: S601 to S604.
  • S601 Send a data write command to the integrated circuit chip.
  • the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command, and return a feedback signal.
  • S603. Perform current frame data writing on the integrated circuit chip by controlling an electrical parameter of the positive input voltage of the integrated circuit chip.
  • the data transmission of the programmer uses frame data transmission, and the integrated circuit chip feeds back the frame data reception success signal to the programmer after each frame data is successfully received. With this arrangement, the reliability of communication between the programmer and the integrated circuit chip is ensured.
  • the programmer writes the current frame data to the integrated circuit chip by controlling the electrical parameter of the positive input voltage of the integrated circuit chip, and receives the frame data received by the integrated circuit chip after receiving the current frame data successfully. When the signal is applied, the next frame of data is written. Until the data is completely transferred.
  • the integrated circuit chip enters the data writing mode and returns a feedback signal to enable the programmer to write data to the integrated circuit chip.
  • the integrated circuit chip enters the data write mode after receiving the data write command, regardless of the feedback signal of the integrated circuit chip to indicate that it successfully enters the data write mode, or returns to successfully enter the data write mode.
  • the programmer can perform data writing on the integrated circuit chip.
  • the manner in which the integrated circuit chip returns the feedback signal in this embodiment is merely an exemplary description and cannot be construed as a specific limitation on the present application.
  • FIG. 7 is a schematic flowchart showing an implementation process of a data writing method of an integrated circuit chip according to an embodiment of the present application.
  • the data writing method is suitable for the case of writing data to an integrated circuit chip, and is applied to a product having an integrated circuit chip or an integrated circuit chip, which can be implemented by software and/or hardware.
  • a product having an integrated circuit chip or an integrated circuit chip which can be implemented by software and/or hardware.
  • the data writing method includes the steps of: S701 to S703.
  • the integrated circuit chip receives a data write command sent by the programmer, enters a data write mode, and returns a feedback signal.
  • the integrated circuit chip determines the data transmitted by the programmer by detecting an electrical parameter of the power supply positive input voltage controlled by the programmer.
  • the integrated circuit chip determines the electrical parameter of the positive input voltage of the power supply, and determines the detection result according to a preset rule with the programmer, thereby determining the data transmitted by the programmer.
  • the preset rule includes a correspondence between an electrical parameter and transmission data.
  • it includes the correspondence between the magnitude of the input voltage and the transmitted data.
  • two different sized input voltages correspond to transmission data “0” and “1” respectively; for example, eight different sized input voltages correspond to transmission data “0", “1", “2”, “3”, respectively. "4", "5", "6” and “7”.
  • the correspondence between the frequency of the electrical signal superimposed on the input voltage and the transmitted data is included.
  • input voltages of two frequency sizes correspond to transmission data “0” and “1”, respectively; for example, eight different input voltages respectively correspond to transmission data “0”, “1”, “2” “3”, “4", "5", “6” and “7”.
  • the integrated circuit chip detects an electrical parameter of a power supply positive input voltage through a built-in or external second signal conversion circuit.
  • the second signal conversion circuit is a circuit such as an A/D converter or a comparator. For example, if the size of the input voltage of the positive control chip of the integrated circuit chip is switched between two values, such as VCC- ⁇ and VCC, the integrated circuit chip determines the transmission of the programmer by a preset rule.
  • the preset rule may be: VCC- ⁇ corresponds to the transmitted data is "0", VCC corresponds to the transmitted data is "1"; the preset rule may also be: VCC- ⁇ The corresponding transmitted data is “1”, and the VCC corresponding transmitted data is "0".
  • the integrated circuit chip determines, by using a preset rule, that the data transmitted by the writer is “0”, “1”, “2”, “3”, “4", “5", “6” or “7”, after the judgment is completed, the corresponding binary data "000”, “001”, “010”, “011” are converted. , “100”, “101”, “110”, “111”. It can be seen that compared with the data transmission using two input voltage values, data transmission using multiple input voltage values can greatly accelerate the data transmission efficiency.
  • using multiple frequency values for data transmission can also speed up data transmission efficiency compared to data transmission using two frequency values.
  • the integrated circuit chip enables data transmitted by the programmer.
  • the integrated circuit chip enables data transmitted by the programmer, that is, the integrated circuit chip transmits data in the built-in or external memory through the programmer. After successfully enabling the data transmitted by the programmer, the integrated circuit chip feeds back the data update success signal to the programmer.
  • the integrated circuit chip enters the data writing mode and returns a feedback signal to enable the programmer to write data to the integrated circuit chip.
  • the integrated circuit chip enters the data write mode after receiving the data write command, regardless of the feedback signal of the integrated circuit chip to indicate that it successfully enters the data write mode, or returns to successfully enter the data write mode.
  • the programmer can perform data writing on the integrated circuit chip.
  • the manner in which the integrated circuit chip returns the feedback signal in this embodiment is merely an exemplary description and cannot be construed as a specific limitation on the present application.
  • FIG. 2 and FIG. 3 is a schematic structural diagram of a data writing system of an integrated circuit chip according to an embodiment of the present application.
  • the data writing system includes a programmer and an integrated circuit chip, and the programmer electrically connects the power supply positive electrode and the power supply negative electrode of the integrated circuit chip.
  • the programmer is configured to send a data write command to the integrated circuit chip; the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command And returning a feedback signal; receiving a feedback signal returned by the integrated circuit chip; and writing data to the integrated circuit chip by controlling an electrical parameter of the positive input voltage of the integrated circuit chip.
  • the programmer is electrically connected to the integrated circuit chip through the power supply positive and negative input lines of the integrated circuit chip, and the burner is externally connected with the power supply to form a circuit loop.
  • the integrated circuit chip is configured to receive a data write command sent by the programmer, enter a data write mode, and return a feedback signal; determine an electrical parameter by detecting an electrical parameter of the positive input voltage of the power supply controlled by the programmer Data transmitted by the recorder; the data transmitted by the programmer is enabled.
  • the two-way communication mode is adopted between the programmer and the integrated circuit chip. After the integrated circuit chip successfully enables the data transmitted by the programmer, the data update success signal is fed back to the programmer.
  • the programmer includes a main control and a first signal conversion circuit, and the main control is electrically connected to the power supply positive electrode and the power supply negative electrode of the integrated circuit chip through the first signal conversion circuit.
  • the master is used to:
  • the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command, and return a feedback signal;
  • the programmer further includes a power input circuit, the power input circuit is electrically connected to the main control and the first signal conversion circuit, respectively, and the power input circuit is used for external connection. a power source that supplies power to the main control and the first signal conversion circuit.
  • the data writing system further includes a second signal conversion circuit, the second signal conversion circuit is electrically connected to the first signal conversion circuit, and the integrated circuit chip passes the The two signal conversion circuit detects an electrical parameter of the power supply positive input voltage controlled by the programmer, and determines data transmitted by the programmer.
  • the second signal conversion circuit may be externally connected or built in the integrated circuit chip.
  • the integrated circuit chip detects the electrical parameter of the power supply positive input voltage through the second signal conversion circuit, such as the magnitude of the input voltage or the frequency of the electrical signal superimposed on the input voltage, and according to a preset rule with the programmer The detection result is judged to determine the data specifically transmitted by the programmer.
  • the data writing system further includes an isolation circuit electrically connected to the integrated circuit chip, and the integrated circuit chip is isolated from the integrated circuit chip by the isolation circuit
  • the signal transmission with the programmer causes a signal of interference.
  • the isolation circuit can externally connect the integrated circuit chip.
  • the integrated circuit chip enters the data writing mode and returns a feedback signal to enable the programmer to write data to the integrated circuit chip.
  • the integrated circuit chip enters the data write mode after receiving the data write command, regardless of the feedback signal of the integrated circuit chip to indicate that it successfully enters the data write mode, or returns to successfully enter the data write mode.
  • the programmer can perform data writing on the integrated circuit chip.
  • the manner in which the integrated circuit chip returns the feedback signal in this embodiment is merely an exemplary description and cannot be construed as a specific limitation on the present application.
  • FIG. 9 is a schematic structural diagram of a data writing system of an integrated circuit chip according to an embodiment of the present application.
  • the fifth embodiment further improves the fourth embodiment.
  • the fifth embodiment is the same as the fourth embodiment.
  • FIG. 9 shows a first data conversion circuit built in the programmer to control the input voltage of the integrated circuit power supply positive electrode when switching between VCC and 0, that is, the communication level between the programmer and the integrated circuit chip.
  • the power input circuit of the programmer includes a power input interface J1, and the first signal conversion circuit of the programmer includes a programming output interface J2, and the power input interface J1 is electrically connected to the main control circuit of the burner and the first signal conversion circuit, respectively. It is used for external power supply to supply power to the main control circuit of the programmer and the first signal conversion circuit.
  • the second signal conversion circuit includes a programming input interface J3, and the programming input interface J3 establishes an electrical connection with the programming output interface J2 of the programmer.
  • the pin 2 of the programming input interface J3 is connected to the pin 2 of the programming output interface J2, and the pin 1 of the programming input interface J3 and the pin 1 of the programming output interface J2 are grounded.
  • a circuit loop can be formed between the programmer and the chip end of the integrated circuit.
  • the main control of the programmer includes the power supply input pins VDD and GND, and the external power supply through the power input interface J1 is the main control power supply.
  • the master of the programmer also includes input and output ports GPIO1, GPIO2, and GPIO3.
  • the first signal conversion circuit includes a burn-in output interface J2, PMOS transistors Q1 and Q2, and resistors R1, R2, R3, and R4.
  • the input and output port GPIO1 is electrically connected to one end of the resistor R2, the other end of the resistor R2 is electrically connected to the pin 2 of the programming output interface J2, and the pin 1 of the programming output interface J2 is grounded.
  • the input/output port GPIO2 is electrically connected to one end of the resistor R1, and the input/output port GPIO2 is also electrically connected to the gate of the PMOS transistor Q1.
  • the other end of the resistor R1 and the source of the PMOS transistor Q1 are connected to the power source VCC, and the drain of the PMOS transistor Q1. It is electrically connected to pin 2 of the programming output interface J2.
  • the input/output port GPIO3 is electrically connected to one end of the resistor R3, the input/output port GPIO3 is also electrically connected to the gate of the PMOS transistor Q2, the other end of the resistor R3, the source of the PMOS transistor Q2 and the pin 2 of the programming output interface J2. Electrically connected, the drain of the PMOS transistor Q2 is electrically connected to one end of the resistor R4, and the other end of the resistor R4 is grounded.
  • the integrated circuit chip includes a PORT1 pin, a VDD pin, and a GND pin, and the GND pin is grounded.
  • the second signal conversion circuit includes a programming input interface J3 and a resistor R5; the isolation circuit includes a diode D1 and a capacitor C1.
  • the PORT1 pin is an input and output interface of the integrated circuit chip.
  • the pin 2 of the programming input interface J3 is electrically connected to one end of the resistor R5, and the other end of the resistor R5 is electrically connected to the PORT1 pin of the integrated circuit chip.
  • the pin 2 of the programming input interface J3 is also electrically connected to the anode of the diode D1, and the cathode of the diode D1 is electrically connected to the VDD pin of the integrated circuit chip, the positive terminal of the capacitor C1, and the negative terminal of the capacitor C1 is grounded.
  • the input/output port GPIO2 of the programmer master is used to control the PMOS transistor Q1 to be turned on or off. Specifically, when the input/output port GPIO2 is low level 0, the PMOS transistor Q1 is turned on. At this time, the VCC level of the source of the PMOS transistor Q1 can be turned from its source to its drain due to the leakage of the PMOS transistor Q1.
  • the pole is electrically connected to the pin 2 of the programming output interface J2, so the VCC level is turned on to the pin 2 of the programming output interface J2; when the port GPIO2 is high level 1, the PMOS transistor Q1 is turned off, at this time, the PMOS The VCC level of the source of the transistor Q1 cannot be turned on to pin 2 of the programming output interface J2. It can be seen that the voltage of pin 2 of the programming output interface J2 can be switched between the voltage values of VCC and 0 through the port GPIO2 of the main control circuit of the programmer.
  • the voltage of the source of the PMOS transistor Q2, that is, the programming output interface J2 can be made by keeping the input/output port GPIO3 of the writer master controlled to a low level for a period of time.
  • the voltage of the pin 2 is turned on to the drain of the PMOS transistor Q2. Since the drain of the PMOS transistor Q2 is grounded through the resistor R4, the pin 2 of the programming output interface J2 can be discharged.
  • the input and output port GPIO1 of the programmer master can receive the feedback signal sent by the integrated circuit chip.
  • the integrated circuit chip determines the voltage of the PORT1 pin according to a preset rule with the programmer, so that the data specifically transmitted by the writer can be determined. In particular, when the voltage of pin 2 of the programming input interface J3 is VCC, the capacitor C1 can be charged.
  • the single-conductivity of the diode D1 helps to isolate the programming.
  • the GND signal of the device cleverly ensure that the capacitor C1 only discharges the VDD pin of the integrated circuit chip to maintain the normal operation of the integrated circuit chip.
  • the time for the PMOS transistor Q1 to be continuously turned off is controlled within a reasonable time range, thereby avoiding the voltage of the pin 2 of the programming input interface J3 being long.
  • a time of 0 causes the integrated circuit chip to fail to work properly.
  • the manner in which the PMOS transistor Q1 is maintained to be turned on for a predetermined period of time after data of a specific byte is transferred by level switching can be employed.
  • the preset time period can be set in conjunction with the actual required data transmission efficiency.
  • the integrated circuit chip can send a feedback signal to the input/output port GPIO1 of the programmer master.
  • the integrated circuit chip enters the data writing mode and returns a feedback signal to enable the programmer to write data to the integrated circuit chip.
  • the integrated circuit chip enters the data write mode after receiving the data write command, regardless of the feedback signal of the integrated circuit chip to indicate that it successfully enters the data write mode, or returns to successfully enter the data write mode.
  • the programmer can perform data writing on the integrated circuit chip.
  • the manner in which the integrated circuit chip returns the feedback signal in this embodiment is merely an exemplary description and cannot be construed as a specific limitation on the present application.
  • FIG. 10 is a schematic structural diagram of a data writing device of an integrated circuit chip according to an embodiment of the present application.
  • the data writing device of the integrated circuit chip is disposed in the programmer.
  • the integrated circuit chip is electrically connected to the programmer through the power supply positive electrode and the power supply negative electrode.
  • the data writing device includes a transmitting unit 101, a receiving unit 102, and a control executing unit 103.
  • the sending unit 101 is configured to send a data write command to the integrated circuit chip, where the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command, and Return feedback signal;
  • the receiving unit 102 is configured to receive a feedback signal returned by the integrated circuit chip
  • the control execution unit 103 is configured to perform data writing on the integrated circuit chip by controlling an electrical parameter of the integrated circuit chip to supply a positive input voltage.
  • control execution unit 103 is specifically configured to:
  • Data writing is performed on the integrated circuit chip by controlling the frequency of the electrical signal superimposed on the positive input voltage of the integrated circuit chip.
  • control execution unit 103 is specifically configured to: perform current frame data writing on the integrated circuit chip by controlling an electrical parameter of the integrated circuit chip power supply positive input voltage.
  • the receiving unit 102 is further configured to: when receiving the frame data receiving success signal fed back by the integrated circuit chip after successfully receiving the current frame data, perform the next frame data writing.
  • the integrated circuit chip enters the data writing mode and returns a feedback signal to enable the programmer to write data to the integrated circuit chip.
  • the integrated circuit chip enters the data write mode after receiving the data write command, regardless of the feedback signal of the integrated circuit chip to indicate that it successfully enters the data write mode, or returns to successfully enter the data write mode.
  • the programmer can perform data writing on the integrated circuit chip, that is, the transmitting unit returns the feedback signal in the data writing device of the integrated circuit chip of the embodiment, and the receiving unit receives the feedback signal.
  • the manners are merely exemplary and are not to be construed as limiting the specifics of the application.
  • FIG. 11 is a schematic structural diagram of another data writing device of an integrated circuit chip according to an embodiment of the present application.
  • the data writing device of the integrated circuit chip is disposed on the integrated circuit chip.
  • the integrated circuit chip is electrically connected to the programmer through the power supply positive electrode and the power supply negative electrode.
  • the data writing device includes a receiving unit 111, a detecting execution unit 112, and an enabling unit 113.
  • the receiving unit 111 is configured to receive a data write command sent by the programmer, enter a data write mode, and return a feedback signal;
  • the detecting execution unit 112 is configured to determine data transmitted by the programmer by detecting an electrical parameter of the power supply positive input voltage controlled by the programmer;
  • the enabling unit 113 is configured to enable data transmitted by the programmer.
  • the detecting execution unit 112 is specifically configured to:
  • Determining data transmitted by the programmer by detecting the magnitude of the positive input voltage of the power supply controlled by the programmer; or
  • the data transmitted by the programmer is determined by detecting the frequency of the electrical signal superimposed on the positive input voltage of the power supply controlled by the programmer.
  • the integrated circuit chip enters the data writing mode and returns a feedback signal to enable the programmer to write data to the integrated circuit chip.
  • the integrated circuit chip enters the data write mode after receiving the data write command, regardless of the feedback signal of the integrated circuit chip to indicate that it successfully enters the data write mode, or returns to successfully enter the data write mode.
  • the programmer can perform data writing on the integrated circuit chip, that is, the manner in which the receiving unit returns the feedback signal in the data writing device of the integrated circuit chip of the embodiment is merely an exemplary description. It should not be construed as a specific limitation on this application.
  • FIG. 12 is a schematic diagram of a data writing device of an integrated circuit chip according to an embodiment of the present application.
  • the device 12 of this embodiment includes a processor 120, a memory 121, and computer readable instructions 122 stored in the memory 121 and executable on the processor 120.
  • the processor 120 executes the computer readable instructions 122 to implement the steps in the data writing method embodiment of the respective integrated circuit chips, such as steps 101 to 103 shown in FIG. 1; 701 to 703.
  • the processor 120 executes the computer readable instructions 122, the functions of the modules/units in the foregoing device embodiments are implemented, such as the functions of the modules 101 to 103 shown in FIG. 10; The function to 113.
  • the computer readable instructions 122 may be partitioned into one or more modules/units that are stored in the memory 121 and executed by the processor 120, To complete this application.
  • the one or more modules/units may be a series of computer readable instruction instruction segments capable of performing a particular function, the instruction segments being used to describe the computer readable instructions 122 at the data writing device 12 of the integrated circuit chip. The execution process in .
  • the computer readable instructions 122 may be divided into a transmitting unit, a receiving unit, and a control executing unit (units in a virtual device), the specific functions of each unit being as follows:
  • a sending unit configured to send a data write command to the integrated circuit chip, where the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command, and return a feedback signal ;
  • a receiving unit configured to receive a feedback signal returned by the integrated circuit chip
  • control execution unit configured to perform data writing on the integrated circuit chip by controlling an electrical parameter of the positive input voltage of the integrated circuit chip.
  • the computer readable instructions 122 can be divided into a receiving unit, a detecting execution unit, and an enabling unit (a unit in a virtual device), the specific functions of each unit being as follows:
  • a receiving unit configured to receive a data write command sent by the programmer, enter a data write mode, and return a feedback signal
  • a detecting execution unit configured to determine data transmitted by the programmer by detecting an electrical parameter of the power supply positive input voltage controlled by the programmer;
  • An enabling unit for enabling data transmitted by the programmer is a unit for enabling data transmitted by the programmer.
  • the integrated circuit chip enters the data writing mode and returns a feedback signal to enable the programmer to write data to the integrated circuit chip.
  • the integrated circuit chip enters the data write mode after receiving the data write command, regardless of the feedback signal of the integrated circuit chip to indicate that it successfully enters the data write mode, or returns to successfully enter the data write mode.
  • the programmer can perform data writing on the integrated circuit chip, that is, the receiving unit included in the computer readable instruction 122 of the data writing device of the integrated circuit chip of the embodiment returns a feedback signal.
  • the manners are merely exemplary and are not to be construed as limiting the specifics of the application.
  • the data writing device 12 of the integrated circuit chip may be a computing device such as a desktop computer, a notebook, a palmtop computer, and a cloud server.
  • the data writing device may include, but is not limited to, the processor 120 and the memory 121. It will be understood by those skilled in the art that FIG. 12 is merely an example of the data writing device 12, does not constitute a limitation on the data writing device 12, may include more or less components than those illustrated, or may combine certain components. Or different components, such as the data writing device, may also include input and output devices, network access devices, buses, and the like.
  • the so-called processor 120 can be a CPU, and can also be other general-purpose processors, DSPs, and application specific integrated circuits (Application Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, etc.
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the memory 121 may be an internal storage unit of the data writing device 12, such as a hard disk or memory of the data writing device 12.
  • the memory 121 may also be an external storage device of the data writing device 12, such as a plug-in hard disk equipped with the data writing device 12, a smart memory card (SMC), and a secure digital (Secure) Digital, SD) cards, flash cards, etc. Further, the memory 121 may also include both an internal storage unit of the data writing device 12 and an external storage device.
  • the memory 121 is configured to store the computer readable instructions and other programs and data required by the data writing device 12.
  • the memory 121 can also be used to temporarily store data that has been output or is about to be output.
  • each functional unit and module described above is exemplified. In practical applications, the above functions may be assigned to different functional units as needed.
  • the module is completed by dividing the internal structure of the device into different functional units or modules to perform all or part of the functions described above.
  • Each functional unit and module in the embodiment may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit, and the integrated unit may be hardware.
  • Formal implementation can also be implemented in the form of software functional units.
  • the specific names of the respective functional units and modules are only for the purpose of facilitating mutual differentiation, and are not intended to limit the scope of protection of the present application.
  • For the specific working process of the unit and the module in the foregoing system reference may be made to the corresponding process in the foregoing method embodiment, and details are not described herein again.
  • a data writing method, system, device, device and medium for an integrated circuit chip are provided.
  • the burner is controlled by an integrated circuit chip to supply power of a positive input voltage.
  • the parameter writes data to the integrated circuit chip, but when the integrated circuit chip is externally connected with a Zener diode, an LDO (Low dropout regulator), a booster DC circuit or a power supply circuit, due to these components or
  • the circuit has voltage regulation, that is, the characteristic of suppressing voltage fluctuation, which causes the data loaded by the programmer to be input on the positive input voltage of the integrated circuit chip to be effectively transmitted to the integrated circuit chip, so that the writer cannot realize the data writing to the integrated circuit chip.
  • the following embodiments will describe a method, system, apparatus, device, and medium for writing data to an integrated circuit chip by controlling electrical parameters of a power supply negative input voltage of an integrated circuit chip.
  • FIG. 13 is a schematic flowchart showing the implementation of a data writing method of another integrated circuit chip according to an embodiment of the present application.
  • the data writing method is suitable for the case where data is written to the integrated circuit chip, and is applied to the programmer, and can be implemented by software and/or hardware.
  • the data writing method includes the steps of: S101' to S102'.
  • the integrated circuit chip is electrically connected to the burner through its own power supply positive electrode and the power supply negative electrode, as shown in FIG. VCC, the negative pole of the power supply is GND, and the programmer writes data of the integrated circuit chip by controlling the electrical parameters of the negative input voltage of the integrated circuit chip for example.
  • a battery holder for powering the product is generally provided, and the battery holder is connected to the power supply positive pole of the integrated circuit chip and the power supply negative input 2 line. Isolating the battery on the battery holder or taking out the power supply battery from the battery holder, and electrically connecting the integrated circuit chip to the burner directly through the power source positive pole and the power source negative contact on the battery holder. , as shown in Figure 15.
  • the programmer is externally connected to a power source to form a circuit loop.
  • the programmer sends a data write command to the integrated circuit chip; the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command.
  • the data writing mode refers to a preparation state in which the integrated circuit chip responds to data writing by the programmer.
  • the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command.
  • the programmer includes a master control, and sends an instruction to the integrated circuit chip through the master control; after receiving the instruction sent by the programmer, the integrated circuit chip passes the built-in or external second signal.
  • the conversion circuit detects and determines the sent command. If the sent command is a data write command, the integrated circuit chip enters the data write mode, and can also send a feedback signal that has entered the data write mode.
  • the sending of the feedback signal by the integrated circuit chip into the data write mode means that the integrated circuit chip feeds back a signal that it has entered the data write mode to the programmer, or the integrated circuit chip is electrically connected thereto by control.
  • the LED light flashes and/or the speaker emits a sound to indicate that the integrated circuit chip has successfully entered the data write mode.
  • step S101 For details that are not described in detail in this step, refer to the corresponding description of step S101 in the first embodiment.
  • the data writing means that the programmer transmits data that needs to be written by the integrated circuit chip to the integrated circuit chip, thereby updating information in the built-in or external storage of the integrated circuit chip.
  • the electrical parameter for controlling the input voltage of the negative electrode of the integrated circuit chip may be the size of the input negative voltage of the integrated circuit chip, such as a square wave voltage, or may be an electrical signal superimposed on the negative input voltage of the integrated circuit chip.
  • Frequency of For example, controlling the frequency of the sinusoidal signal superimposed on the negative input voltage of the integrated circuit chip; for example, controlling the frequency of the triangular wave, the sawtooth wave and the like which are superimposed on the negative input voltage of the integrated circuit chip. It should be noted that the description is merely exemplary and is not to be construed as limiting the application.
  • the programmer includes a first signal conversion circuit, and the programmer controls the electrical parameters of the negative input voltage of the integrated circuit chip through its built-in signal conversion circuit to write data to the integrated circuit chip.
  • the programmer writes data to the integrated circuit chip by controlling the magnitude of the input voltage of the negative electrode of the integrated circuit chip, which means that the programmer changes its built-in first signal conversion circuit.
  • the size of the input voltage of the negative electrode of the integrated circuit chip is used to transmit binary data "0" and "1".
  • the programmer writes data to the integrated circuit by controlling the frequency of the sinusoidal signal superimposed on the input voltage of the power supply negative pole of the integrated circuit chip, which means that the programmer passes the built-in first
  • the signal conversion circuit changes the frequency of the sinusoidal signal superimposed on the input voltage of the power supply negative pole of the integrated circuit chip to transmit binary data "0" and "1".
  • the current programmer is to write data to a memory integrated or external to the integrated circuit chip through a specific interface of the integrated circuit chip, such as a JTAG interface, and at least four wires are used, and the technical solution provided by the present application is only utilized.
  • the power supply positive pole of the integrated circuit chip and the power supply negative input 2 line can complete the data writing, which is simpler and more convenient; in addition, since the data writing of the present application no longer depends on a specific interface such as JTAG, the manufacturer's binding chip is skillfully reduced. Cost; and in the technical solution provided by the application, the programmer writes data to the integrated circuit chip by controlling the electrical parameters of the negative input voltage of the integrated circuit chip, and the integrated circuit chip is well connected with the voltage regulator device. When the data is loaded on the positive input voltage of the integrated circuit chip power supply, the data cannot be effectively transmitted to the integrated circuit chip, and the technical problem of data writing of the integrated circuit chip cannot be realized.
  • step S103 For details that are not described in detail in this step, refer to the corresponding description of step S103 in the first embodiment.
  • FIG. 16 is a schematic flowchart showing the implementation of a data writing method of another integrated circuit chip according to an embodiment of the present application.
  • the data writing method includes the steps of: S601' to S603'.
  • the programmer writes the current frame data to the integrated circuit chip by controlling the electrical parameter of the negative input voltage of the integrated circuit chip, and receives the frame data received by the integrated circuit chip after receiving the current frame data successfully.
  • the signal is signaled, the next frame of data is written until the data is completely transmitted.
  • step S603 For details that are not described in detail in this step, refer to the description of step S603 in the second embodiment.
  • FIG. 17 is a schematic flowchart showing the implementation of a data writing method of another integrated circuit chip according to an embodiment of the present application.
  • the data writing method is suitable for the case of writing data to an integrated circuit chip, and is applied to a product having an integrated circuit chip or an integrated circuit chip, which can be implemented by software and/or hardware.
  • a product having an integrated circuit chip or an integrated circuit chip which can be implemented by software and/or hardware.
  • the data writing method includes the steps of: S701' to S703'.
  • the integrated circuit chip receives the data write command sent by the programmer, and enters a data write mode.
  • the integrated circuit chip determines the data transmitted by the programmer by detecting an electrical parameter of the power supply negative input voltage controlled by the programmer.
  • the integrated circuit chip determines the electrical parameter of the power supply negative input voltage, and determines the detection result according to a preset rule with the programmer, thereby determining the data transmitted by the programmer.
  • the integrated circuit chip detects an electrical parameter of a power supply negative input voltage through a built-in or external second signal conversion circuit.
  • the second signal conversion circuit is a circuit such as an A/D converter or a comparator. For example, if the size of the input voltage of the burner control integrated circuit chip power supply negative electrode is switched between two values, such as VCC- ⁇ and VCC, the integrated circuit chip determines the transmission of the programmer by a preset rule.
  • the preset rule may be: VCC- ⁇ corresponds to the transmitted data is "0", VCC corresponds to the transmitted data is "1"; the preset rule may also be: VCC- ⁇ The corresponding transmitted data is “1”, and the VCC corresponding transmitted data is "0".
  • the integrated circuit chip determines that the data transmitted by the programmer is “0” by a preset rule. “1”, “2”, “3”, “4", “5", “6” or “7”, after the judgment is completed, the corresponding binary data "000”, “001”, “010”, “011” are converted. , “100”, “101”, “110”, “111”. It can be seen that compared with the data transmission using two input voltage values, data transmission using multiple input voltage values can greatly accelerate the data transmission efficiency.
  • using multiple frequency values for data transmission can also speed up data transmission efficiency compared to data transmission using two frequency values.
  • the integrated circuit chip enables data transmitted by the programmer.
  • the integrated circuit chip enables data transmitted by the programmer, that is, the integrated circuit chip transmits data in the built-in or external memory through the programmer. After successfully enabling the data transmitted by the programmer, the integrated circuit chip feeds back the data update success signal to the programmer.
  • FIG. 14 and FIG. 15 are schematic diagrams showing the structure of a data writing system of another integrated circuit chip according to an embodiment of the present application.
  • the data writing system includes a programmer and an integrated circuit chip, and the programmer electrically connects the power supply positive electrode and the power supply negative electrode of the integrated circuit chip.
  • the programmer is configured to send a data write command to the integrated circuit chip; the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command After the integrated circuit chip enters the data writing mode, data is written to the integrated circuit chip by controlling an electrical parameter of the integrated circuit chip to supply a negative input voltage.
  • the programmer is electrically connected to the integrated circuit chip through the power supply positive and negative input lines of the integrated circuit chip, and the burner is externally connected with the power supply to form a circuit loop.
  • the integrated circuit chip is configured to receive a data write command sent by the programmer, and enter a data write mode; determine the data transmitted by the programmer by detecting an electrical parameter of the negative input voltage of the power supply controlled by the programmer ; enable data transmitted by the writer.
  • the data update success signal is fed back to the programmer.
  • the programmer includes a main control and a first signal conversion circuit, and the main control is electrically connected to the power supply positive electrode and the power supply negative electrode of the integrated circuit chip through the first signal conversion circuit.
  • the master is used to:
  • the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command;
  • the programmer further includes a power input circuit electrically connected to the main control and the first signal conversion circuit, and the power input circuit is used for external connection. a power source that supplies power to the main control and the first signal conversion circuit.
  • the data writing system further includes a second signal conversion circuit, the second signal conversion circuit is electrically connected to the first signal conversion circuit, and the integrated circuit chip passes the The two signal conversion circuit detects an electrical parameter of the power supply negative input voltage controlled by the programmer, and determines data transmitted by the programmer.
  • the second signal conversion circuit may be externally connected or built in the integrated circuit chip.
  • the integrated circuit chip detects an electrical parameter of the power supply negative input voltage through the second signal conversion circuit, such as the magnitude of the input voltage or the frequency of the electrical signal superimposed on the input voltage, and according to a preset rule with the programmer The detection result is judged to determine the data specifically transmitted by the programmer.
  • the data writing system further includes an isolation circuit electrically connected to the integrated circuit chip, and the integrated circuit chip isolates the integrated circuit chip by the isolation circuit
  • the signal transmission with the programmer causes a signal of interference.
  • the isolation circuit can externally connect the integrated circuit chip.
  • FIG. 19 is a schematic structural diagram of a data writing system of another integrated circuit chip according to an embodiment of the present application.
  • the thirteenth embodiment further improves the above-described embodiment twelve.
  • the thirteenth embodiment is the same as the embodiment 12, and the description of the twelfth embodiment is omitted. Only the differences from the twelfth embodiment will be described.
  • Figure 19 shows the first data conversion circuit built into the programmer to control the input voltage of the integrated circuit power supply negative terminal when switching between VCC and 0, that is, the communication level between the programmer and the integrated circuit chip.
  • the power input circuit of the programmer includes a power input interface J4, and the first signal conversion circuit of the programmer includes a programming output interface J5, and the power input interface J4 is electrically connected to the main control circuit of the writer and the first signal conversion circuit, respectively. It is used for external power supply to supply power to the main control circuit of the programmer and the first signal conversion circuit.
  • the second signal conversion circuit includes a programming input interface J6, and the programming input interface J6 establishes an electrical connection with the programming output interface J5 of the programmer.
  • Pin 2 of the programming input interface J6 is connected to pin 2 of the programming output interface J5, and pin 2 of the programming output interface J5 is connected to the power supply VCC.
  • the power supply input interface J4 of the programmer is externally connected to the power supply, a circuit loop can be formed between the programmer and the chip end of the integrated circuit.
  • the main control of the programmer includes the power supply input pins VDD and GND, and the external power supply through the power input interface J4 is the main control power supply.
  • the master of the programmer also includes input and output ports GPIO4, GPIO5, and GPIO6.
  • the first signal conversion circuit includes a programming output interface J5, a PMOS transistor Q3, and an NMOS transistor Q4, and resistors R10, R11, and R12.
  • the input/output port GPIO4 is electrically connected to one end of the resistor R11, and the other end of the resistor R11 is electrically connected to the pin 1 of the programming output interface J5.
  • the input/output port GPIO5 is electrically connected to one end of the resistor R10, and the input/output port GPIO5 is also electrically connected to the gate of the PMOS transistor Q3.
  • the other end of the resistor R10 and the source of the PMOS transistor Q3 are connected to the power source VCC, and the drain of the PMOS transistor Q3. It is electrically connected to pin 1 of the programming output interface J5.
  • the input/output port GPIO6 is electrically connected to one end of the resistor R12, the input/output port GPIO6 is also electrically connected to the gate of the NMOS transistor Q4, the other end of the resistor R12, the source of the NMOS transistor Q4 are grounded, and the drain of the NMOS transistor Q4 is burned. Pin 1 of the recording output interface J5 is electrically connected.
  • the integrated circuit chip includes a PORT2 pin, a VDD pin, and a GND pin.
  • the second signal conversion circuit includes a programming input interface J6 and a resistor R14; the isolation circuit includes a diode D2 and a capacitor C2.
  • the PORT2 pin is an input and output interface of the integrated circuit chip.
  • the pin 1 of the programming input interface J6 is electrically connected to one end of the resistor R14, and the other end of the resistor R14 is electrically connected to the PORT2 pin of the integrated circuit chip.
  • Pin 1 of the programming input interface J6 is also electrically connected to the cathode of the diode D2.
  • the anode of the diode D2 is electrically connected to the GND pin of the integrated circuit chip, and the GND pin of the integrated circuit chip is grounded.
  • the pin 2 of the programming input interface J6 is electrically connected to the VDD pin of the integrated circuit chip, the positive terminal of the capacitor C2, and the negative terminal of the capacitor C2 is grounded.
  • the interface between the programmer and the integrated circuit chip end Form a circuit loop.
  • the input/output port GPIO5 of the writer main control is used to control the PMOS tube Q3 to be turned on or off
  • the input/output port GPIO6 of the writer main control is used to control the NMOS tube Q4 to be turned on or off.
  • the input and output ports GPIO5 and GPIO6 are low level 0, the PMOS transistor Q3 is turned on, and the NMOS transistor Q4 is turned off.
  • the VCC level of the source of the PMOS transistor Q3 can be turned from its source to its drain. Since the drain of the PMOS transistor Q3 is electrically connected to the pin 1 of the programming output interface J5, the VCC level is turned on to the pin 1 of the programming output interface J5; when the ports GPIO5 and GPIO6 are at the high level 1, The PMOS transistor Q3 is turned off, and the NMOS transistor Q4 is turned on. At this time, the drain and the source of the NMOS transistor Q4 are turned on. Since the drain of the NMOS transistor Q4 is electrically connected to the pin 1 of the programming output interface J5, the programming output interface is burned. The level of pin 1 of J5 is pulled down to the GND by the source of NMOS transistor Q4. It can be seen that the voltage of pin 1 of the programming output interface J5 can be switched between the voltage values of VCC and 0 through the ports GPIO5 and GPIO6 of the main control circuit of the programmer.
  • port GPIO5 When port GPIO5 is high level 1 and GPIO6 is low level 0, when PMOS transistor Q3 and NMOS transistor Q4 are both off, the PORT2 pin is set as output, and the input and output port GPIO4 of the programmer master can be The feedback signal sent by the pin 1 of the integrated circuit chip is received through the pin 1 of the programming output interface J5.
  • the integrated circuit chip judges the voltage of the PORT2 pin according to a preset rule with the programmer, so that the data specifically transmitted by the writer can be determined. In particular, when the voltage of pin 1 of the programming input interface J6 is 0, the capacitor C2 can be charged.
  • the single-conductivity of the diode D2 helps to isolate the programming.
  • Input interface J6 pin 1 and the GND pin of the integrated circuit chip so as to ensure that the capacitor C2 discharges the VDD pin of the integrated circuit chip to maintain the normal operation of the integrated circuit chip, and ensure that the voltage of the pin 1 of the programming input interface J6 passes through the resistor.
  • R14 is input to the PORT2 pin of the integrated circuit chip.
  • the integrated circuit chip can send a feedback signal to the input/output port GPIO4 of the writer master through the PORT2 pin.
  • the programming input interface J6 When the integrated circuit chip is in a normal working state, the programming input interface J6 is electrically connected to the BT2 battery or the DC power supply terminal connected to the power supply interface J7. When the programmer writes data to the integrated circuit chip, the programming input interface J6 is disconnected from the power supply interface J7, and the programming input interface J6 is electrically connected with the programming output interface J5.
  • the programmer or the integrated circuit chip terminal does not transmit and receive at the same time.
  • the programmer needs to send a data write command to the integrated circuit chip, and immediately switches to the input circuit after transmitting the data write command, waiting for receiving the signal sent by the integrated circuit chip. .
  • the time for the PMOS transistor Q3 to be continuously turned on and the NMOS transistor Q4 to be continuously turned off is controlled within a reasonable time range, thereby avoiding the programming of the input interface J6.
  • the voltage of the pin 1 causes the integrated circuit chip to malfunction due to the long time of VCC.
  • the preset time period can be set in conjunction with the actual required data transmission efficiency.
  • the main control model of the burner is GD32F150G8U6, or STM32F103CBT6, TR16F801B
  • the integrated circuit chip is TR16F064B
  • GD32 series mother STM32 series mother body
  • sexual descriptions are not to be construed as limiting the application.
  • the diode D2 and the resistor R14 of the integrated circuit chip end in this embodiment may also be disposed inside the integrated circuit chip.
  • the circuit in this embodiment is for fully explaining the process of writing data to the integrated circuit chip by controlling the electrical parameters of the negative input voltage of the integrated circuit chip by the programmer, and does not implement the integrated circuit chip for implementing the programmer.
  • the circuit for supplying the electrical parameters of the negative input voltage is limited.
  • the diode D2 of the integrated circuit chip end can be replaced by a MOS tube, and can also be replaced by a triode or other gate circuit.
  • the circuit including Q3 and Q4 at the device end can also be realized by a device or circuit having the same function as a motor drive, a switch circuit, etc., and the circuits formed by these alternatives are all within the protection scope of the present application.
  • FIG. 20 is a schematic structural diagram of another data writing device of an integrated circuit chip according to an embodiment of the present application.
  • the data writing device of the integrated circuit chip is disposed in the programmer.
  • the integrated circuit chip is electrically connected to the programmer through the power supply positive electrode and the power supply negative electrode.
  • the data writing device includes a transmitting unit 101' and a control executing unit 102'.
  • the sending unit 101' is configured to send a data write command to the integrated circuit chip; the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command;
  • the control execution unit 102' is configured to perform data writing on the integrated circuit chip by controlling an electrical parameter of the integrated circuit chip to supply a negative input voltage after the integrated circuit chip enters the data write mode.
  • control execution unit 102' is specifically configured to:
  • Data writing is performed on the integrated circuit chip by controlling the frequency of the electrical signal superimposed on the negative input voltage of the integrated circuit chip.
  • control execution unit 102' is specifically configured to: perform current frame data writing on the integrated circuit chip by controlling an electrical parameter of the integrated circuit chip to supply a negative input voltage.
  • control execution unit 102' is further configured to: when receiving the frame data reception success signal fed back by the integrated circuit chip after successfully receiving the current frame data, perform the next frame data writing.
  • FIG. 11 is a schematic structural diagram of another data writing device of an integrated circuit chip according to an embodiment of the present application.
  • the data writing device of the integrated circuit chip is disposed on the integrated circuit chip.
  • the integrated circuit chip is electrically connected to the programmer through the power supply positive electrode and the power supply negative electrode.
  • the data writing device includes a receiving unit 111, a detecting execution unit 112, and an enabling unit 113.
  • the receiving unit 111 is configured to receive a data write command sent by the programmer, and enter a data write mode.
  • the detecting execution unit 112 is configured to determine data transmitted by the programmer by detecting an electrical parameter of the power supply negative input voltage controlled by the programmer;
  • the enabling unit 113 is configured to enable data transmitted by the programmer.
  • the detecting execution unit 112 is specifically configured to:
  • Determining data transmitted by the programmer by detecting a magnitude of a negative input voltage of the power supply controlled by the programmer;
  • the data transmitted by the programmer is determined by detecting the frequency of the electrical signal superimposed on the power supply negative input voltage controlled by the programmer.
  • FIG. 12 is a schematic diagram of a data writing device of an integrated circuit chip according to an embodiment of the present application.
  • the device 12 of this embodiment includes a processor 120, a memory 121, and computer readable instructions 122 stored in the memory 121 and executable on the processor 120.
  • the processor 120 executes the computer readable instructions 122
  • the steps in the embodiment of the data writing method of the respective integrated circuit chips are implemented, for example, steps 101' to 103' shown in FIG. 13; Steps 701' to 703'.
  • the processor 120 executes the computer readable instructions 122
  • the functions of the modules/units in the foregoing device embodiments are implemented, such as the functions of the modules 101' to 103' shown in FIG. 20;
  • the functions of the modules 111 to 113 shown in FIG. 11 are described in FIG.
  • the computer readable instructions 122 may be partitioned into one or more modules/units that are stored in the memory 121 and executed by the processor 120, To complete this application.
  • the one or more modules/units may be a series of computer readable instruction instruction segments capable of performing a particular function, the instruction segments being used to describe the computer readable instructions 122 at the data writing device 12 of the integrated circuit chip. The execution process in .
  • the computer readable instructions 122 may be partitioned into a transmitting unit and a control executing unit (units in a virtual device), the specific functions of each unit being as follows:
  • a sending unit configured to send a data write command to the integrated circuit chip, where the data write command is used to instruct the integrated circuit chip to enter the data write mode after receiving the data write command;
  • control execution unit configured to perform data writing on the integrated circuit chip by controlling an electrical parameter of the integrated circuit chip to supply a negative input voltage after the integrated circuit chip enters the data writing mode.
  • the computer readable instructions 122 can be divided into a receiving unit, a detecting execution unit, and an enabling unit (a unit in a virtual device), the specific functions of each unit being as follows:
  • a receiving unit configured to receive a data write command sent by the programmer, and enter a data writing mode
  • a detecting execution unit configured to determine data transmitted by the programmer by detecting an electrical parameter of the power supply negative input voltage controlled by the programmer;
  • An enabling unit for enabling data transmitted by the programmer is a unit for enabling data transmitted by the programmer.
  • the disclosed apparatus/device and method may be implemented in other manners.
  • the device/device embodiments described above are merely illustrative.
  • the division of the modules or units is only a logical functional division, and may be implemented in another manner, such as multiple units or Components can be combined or integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • the integrated modules/units if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium.
  • the present application implements all or part of the processes in the foregoing embodiments, and may also be implemented by computer readable instructions, which may be stored in a computer readable storage medium.
  • the computer readable instructions when executed by a processor, may implement the steps of the various method embodiments described above.
  • the computer readable instructions comprise computer readable instruction code, which may be in the form of source code, an object code form, an executable file or some intermediate form or the like.
  • the computer readable medium may include any entity or device capable of carrying the computer readable instruction code, a recording medium, a USB flash drive, a removable hard disk, a magnetic disk, an optical disk, a computer memory, a read only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), electrical carrier signals, telecommunications signals, and software distribution media. It should be noted that the content contained in the computer readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in a jurisdiction, for example, in some jurisdictions, according to legislation and patent practice, computer readable media Does not include electrical carrier signals and telecommunication signals.

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Abstract

一种集成电路芯片的数据写入方法、系统、装置、设备及介质，适用于集成电路技术领域，该数据写入方法应用于烧录器，所述集成电路芯片通过供电正极和供电负极与所述烧录器电连接；所述数据写入方法包括：发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式；在集成电路芯片进入数据写入模式后，通过控制所述集成电路芯片供电正极或供电负极输入电压的电性参数对集成电路芯片进行数据写入。解决了集成电路芯片的数据写入方法不灵活，成品生产效率低的技术问题。

Description

集成电路芯片的数据写入方法、系统、装置、设备及介质
本申请要求于2018年04月24日提交中国专利局、申请号为201810373882.4、发明名称为“集成电路芯片的数据写入方法、系统、装置、设备及介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中；本申请要求于2018年04月24日提交世界知识产权组织(WIPO)、申请号为PCT/CN2018/084246、发明名称为“集成电路芯片的数据写入方法、系统、装置、设备及介质”的国际专利申请的优先权，其全部内容通过引用结合在本申请中；本申请要求于2018年10月29日提交中国专利局、申请号为201811271213.2、发明名称为“集成电路芯片的数据写入方法、系统、装置、设备及介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于集成电路技术领域，尤其涉及一种集成电路芯片的数据写入方法、系统、装置、设备及介质。
 背景技术
随着半导体技术的快速发展，电路板中使用可编程集成电路芯片也越来越多。电可擦可编程只读存储器(Electrically Erasable Programmable Read Only Memory，EEPROM)、闪存（Flash）、可编程逻辑器件（Programmable Logic Device，PLD）等因具备可编程功能而在电子行业中倍受青睐。
然而，目前的可编程集成电路芯片，一般需要通过特定接口来完成数据写入，这些特定接口可能是联合测试工作组(Joint Test Action Group，JTAG)接口、在电路编程(In-circuit programmer，ICP）接口、在线系统编程(In-System Programming，ISP)接口或通用异步收发传输器（Universal Asynchronous Receiver/Transmitter，UART）接口，而通过这些特定接口完成数据写入至少需要使用4根线，并且还需要在将可编程集成电路芯片绑定或者贴片到印刷电路板组件（Printed Circuit Board Assembly，PCBA）之前完成，可见，这种传统数据写入方法很不灵活，也会导致相应的成品生产模式固定，周期过长，使得成品的生产效率远远落后于行业当前需求的增长速度。
 技术问题
本申请实施例提供了一种集成电路芯片的数据写入方法、系统、装置、设备及介质，以解决现有技术中集成电路芯片的数据写入方法不灵活，成品生产效率低的问题。
 技术解决方案
本申请实施例的第一方面提供了一种集成电路芯片的数据写入方法，应用于烧录器，所述集成电路芯片通过供电正极和供电负极与所述烧录器电连接；所述集成电路芯片内置或外接存储器；所述数据写入是指所述集成电路芯片通过所述烧录器写数据至所述存储器；所述数据写入方法包括：
发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式；
在所述集成电路芯片进入数据写入模式后，通过控制所述集成电路芯片供电正极或供电负极输入电压的电性参数对集成电路芯片进行数据写入。
本申请实施例的第二方面提供了一种集成电路芯片的数据写入方法，所述集成电路芯片通过供电正极和供电负极与烧录器连接；所述数据写入方法包括：
集成电路芯片接收烧录器发送的数据写入指令，进入数据写入模式；
集成电路芯片通过检测所述烧录器控制的供电正极或供电负极输入电压的电性参数，确定烧录器传输的数据；
集成电路芯片启用所述烧录器传输的数据。
本申请实施例的第三方面提供了一种集成电路芯片的数据写入系统，所述数据写入系统包括烧录器和集成电路芯片，所述烧录器包括主控和第一信号转换电路，所述主控通过所述第一信号转换电路电连接所述集成电路芯片的供电正极和供电负极；
所述主控，用于
发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式；
在所述集成电路芯片进入数据写入模式后，通过所述第一信号转换电路控制所述集成电路芯片供电正极或供电负极输入电压的电性参数对集成电路芯片进行数据写入。
本申请实施例的第四方面提供了一种集成电路芯片的数据写入装置，配置于烧录器，其特征在于，所述集成电路芯片通过供电正极和供电负极与所述烧录器电连接；所述数据写入装置包括：
发送单元，用于发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式，；
控制执行单元，用于在所述集成电路芯片进入数据写入模式后，通过控制所述集成电路芯片供电正极或供电负极输入电压的电性参数对集成电路芯片进行数据写入。
本申请实施例的第五方面提供了一种集成电路芯片的数据写入装置，配置于集成电路芯片，所述集成电路芯片通过供电正极和供电负极与烧录器电连接；所述数据写入装置包括：
接收单元，用于接收烧录器发送的数据写入指令，进入数据写入模式；
检测执行单元，用于通过检测所述烧录器控制的供电正极或供电负极输入电压的电性参数，确定烧录器传输的数据；
启用单元，用于启用所述烧录器传输的数据。
本申请实施例的第六方面提供了一种集成电路芯片的数据写入设备，包括存储器、处理器以及存储在所述存储器中并可在所述处理器上运行的计算机可读指令，其特征在于，所述处理器执行所述计算机可读指令时实现如第一方面或第二方面所述方法的步骤。
本申请实施例的第七方面提供了一种计算机可读存储介质，所述计算机可读存储介质存储有计算机可读指令，其特征在于，所述计算机可读指令被处理器执行时实现如第一方面或第二方面所述方法的步骤。
 有益效果
本申请实施例通过将集成电路芯片的供电正极和供电负极与烧录器电连接，烧录器发送数据写入指令至所述集成电路芯片；在集成电路芯片进入数据写入模式后，通过控制所述集成电路芯片供电正极或供电负极输入电压的电性参数对集成电路芯片进行数据写入，解决了集成电路芯片的数据写入方法不灵活，成品生产效率低的技术问题。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种集成电路芯片的数据写入方法的实现流程示意图；
图2是本申请实施例提供的一种集成电路芯片的数据写入系统结构示意图；
图3是本申请实施例提供的另一种集成电路芯片的数据写入系统结构示意图；
图4是本申请实施例提供的一种集成电路芯片的数据写入方法中控制输入电压大小的示意图；
图5是本申请实施例提供的一种集成电路芯片的数据写入方法中控制输入电压上叠加的电信号的频率的示意图；
图6是本申请实施例提供的另一种集成电路芯片的数据写入方法的实现流程示意图；
图7是本申请实施例提供的另一种集成电路芯片的数据写入方法的实现流程示意图；
图8是本申请实施例提供的另一种集成电路芯片的数据写入系统结构示意图；
图9是本申请实施例提供的另一种集成电路芯片的数据写入系统结构示意图；
图10是本申请实施例提供的一种集成电路芯片的数据写入装置的示意图；
图11是本申请实施例提供的另一种集成电路芯片的数据写入装置的示意图；
图12是本申请实施例提供的集成电路芯片的数据写入设备的示意图；
图13是本申请实施例提供的另一种集成电路芯片的数据写入方法的实现流程示意图；
图14是本申请实施例提供的另一种集成电路芯片的数据写入系统结构示意图；
图15是本申请实施例提供的另一种集成电路芯片的数据写入系统结构示意图；
图16是本申请实施例提供的另一种集成电路芯片的数据写入方法的实现流程示意图；
图17是本申请实施例提供的另一种集成电路芯片的数据写入方法的实现流程示意图；
图18是本申请实施例提供的另一种集成电路芯片的数据写入系统结构示意图；
图19是本申请实施例提供的另一种集成电路芯片的数据写入系统结构示意图；
图20是本申请实施例提供的一种集成电路芯片的数据写入装置的示意图。
 本发明的实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之类的具体细节，以便透彻理解本申请实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本申请。在其它情况中，省略对众所周知的系统、装置、电路以及方法的详细说明，以免不必要的细节妨碍本申请的描述。
为了说明本申请所述的技术方案，下面通过具体实施例来进行说明。
实施例一
如图1所示，为本申请实施例提供的一种集成电路芯片的数据写入方法的实现流程示意图。该数据写入方法适用于对集成电路芯片进行数据写入的情形，应用于烧录器，可由软件和/或硬件实现。
如图1所示，该数据写入方法包括步骤：S101至S103。
S101，发送数据写入指令至集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式，并返回反馈信号。
其中，所述集成电路芯片是指集成电路通过设计、制造、封装和测试后可以独立使用的整体，具备数据处理功能，内置或外接存储器。所述数据写入是指所述集成电路芯片通过所述烧录器写数据至所述存储器，也就是说，集成电路芯片可以通过烧录器传输数据以更新其内置或外接存储器内的信息。所述集成电路芯片可以是微控制单元(Microcontroller Unit，MCU)，中央处理单元(Central Processing Unit，CPU)，数字信号处理器(Digital Signal Processing，DSP)或 PLD等。所述存储器可以是EEPROM或Flash等。
所述烧录器为能够编写数据至集成电路芯片的工具，主要用于单片机/存储器之类的芯片的编程。
本申请实施例中，所述集成电路芯片直接通过其自身供电正极和供电负极与所述烧录器电连接。具体地，集成电路芯片通过供电正极和供电负极的输入2线与烧录器电连接，烧录器外接电源，从而形成电路回路。
所述供电正极可以是电源正极VCC（Volt Current Condenser），也可以是电源正极VDD（Voltage Drain Drain），根据具体集成电路芯片来选择确定。所述供电负极可以是电源负极VSS，还可以是电源地（Ground，GND），根据具体集成电路芯片来选择确定。由于所述集成电路芯片通常由单电源供电，因此供电负极接地。为了更清楚地说明本申请，在后续具体实施例的描述中，所述集成电路芯片通过自身供电正极和供电负极与烧录器电连接的方式，如图2所示，以供电正极为电源正极VCC，供电负极为GND，烧录器通过控制集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行数据写入为例进行说明。
需要说明的是，在集成电路芯片封装成为产品后，一般设置有为产品运行而供电的电池座，所述电池座与所述集成电路芯片的供电正极和供电负极输入2线连接，这时可以隔离所述电池座上的电池供电或者将供电电池从所述电池座上取出，直接通过所述电池座上的电源正极和电源负极触片将所述集成电路芯片与所述烧录器电连接，如图3所示。所述烧录器外接电源，从而形成电路回路。
烧录器发送数据写入指令至集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式，并返回反馈信号。
其中，所述数据写入模式是指所述集成电路芯片响应所述烧录器进行数据写入的准备状态。所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式，并返回反馈信号。集成电路芯片返回反馈信号是指所述集成电路芯片反馈其已进入数据写入模式的信号至所述烧录器。
作为本申请一实施例，所述烧录器包括主控，通过主控发送指令至集成电路芯片；所述集成电路芯片接收到烧录器发来的指令后，通过内置或外接的第二信号转换电路对发来的指令进行检测判断，若发来的指令为数据写入指令，则集成电路芯片进入数据写入模式，并发送反馈信号至烧录器。在本申请其他实施例中，所述集成电路芯片还连接有LED和/或喇叭。还可以在所述集成电路芯片成功进入数据写入模式后，控制与集成电路芯片电连接的LED灯闪烁和/或喇叭发出声音，来提示所述集成电路芯片已成功进入数据写入模式。通过这种设置，让监测数据写入的工程师能够更快捷且直观地确定集成电路芯片已经成功进入数据写入模式，便于工程师对整个流程进行监控，进一步提高了效率。
S102，接收所述集成电路芯片返回的反馈信号。
其中，集成电路芯片返回的反馈信号是指所述集成电路芯片反馈其已进入数据写入模式的信号至所述烧录器。烧录器接收集成电路芯片返回的反馈信号后，通过控制所述集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行数据写入。
S103，通过控制所述集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行数据写入。
其中，所述数据写入是指所述烧录器将所述集成电路芯片需要写入的数据传输至所述集成电路芯片，从而更新所述集成电路芯片内置或外接存储内的信息。
所述控制集成电路芯片供电正极的输入电压的电性参数，可以是控制集成电路芯片供电正极输入电压的大小，比如方波电压，还可以是控制集成电路芯片供电正极输入电压上叠加的电信号的频率。例如，控制集成电路芯片供电正极输入电压上叠加的正弦信号的频率；又如，控制集成电路芯片供电正极输入电压上叠加的三角波、锯齿波等电信号的频率。需要说明的是，此处仅为示例性描述，不解释为对本申请的限制。
在本申请实施例中，所述烧录器包括第一信号转换电路，烧录器通过其内置的信号转换电路控制所述集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行数据写入。
作为本申请一实施例，烧录器通过控制集成电路芯片供电正极的输入电压的大小来对集成电路芯片进行数据写入，是指所述烧录器通过其内置的第一信号转换电路改变所述集成电路芯片供电正极的输入电压的大小来传输二进制数据“0”和“1”。
其中，不同大小的输入电压，可以从范围[VCC-δ，VCC]中进行选择。VCC指集成电路芯片供电正极VCC的输入电压，一般为1.8V、3V、或5V等。δ的取值范围为(0，VCC] 。此外，还可以从[VCC-δ，VCC]中选取不同数量的输入电压值，可以选择2个，还可以选择8个或16个等。通过选择输入电压值的数量越大，可以使得传输数据的传输效率更高，从而进一步提高数据写入的效率。例如，如图4所示，选择2个输入电压值VCC-δ和VCC，分别来传输二进制数据“0”和“1”。
作为本申请另一实施例，烧录器通过控制叠加在集成电路芯片供电正极的输入电压上的正弦信号的频率对集成电路进行数据写入，是指所述烧录器通过其内置的第一信号转换电路改变叠加在所述集成电路芯片供电正极的输入电压上的正弦信号的频率来传输二进制数据“0”和“1”。
此外，还可以选择在输入电压上叠加不同数量的正弦信号频率，可以至少选择2个，还可以选择3个或4个以上等。通过选择正弦信号频率的数量越大，可以使得传输数据的传输效率更高，从而进一步提高数据写入的效率。例如，如图5所示，控制叠加在所述集成电路供电正极的输入电压上的正弦信号的频率在f1、f2之间切换，来传输二进制数据“0”和“1”。
目前的烧录器是通过集成电路芯片特定的接口，如JTAG接口等，且至少使用4根线，对集成电路芯片内置或外接的存储器进行数据写入，而本申请所提供的技术方案仅利用集成电路芯片的供电正极和供电负极输入2线便可以完成数据写入，更加简单方便；此外，由于本申请的数据写入不再依赖JTAG等特定接口，很巧妙地降低了厂商绑定芯片的成本。
需要说明的是，在本申请实施例中，集成电路芯片在进入数据写入模式，并返回反馈信号，以使得烧录器对集成电路芯片进行数据写入。但本领域技术人员知晓，集成电路芯片在接收到数据写入指令后会进入数据写入模式，不管集成电路芯片以何种反馈信号表征自己成功进入数据写入模式，或是否返回成功进入数据写入模式的反馈信号的情况下，烧录器都可对集成电路芯片进行数据写入，本实施例集成电路芯片返回反馈信号的方式仅为示例性描述，不能解释为对本申请的具体限制。
现有技术中，对集成电路芯片内置或外接存储的数据写入需要在将其封装为成品之前完成，导致成品的生产周期过长，无法匹配当前快速增长的行业成品需求。而采用本申请所提供的技术方案，在数据写入的先后顺序上，不仅可以与传统模式一样，在有实际需求时，不仅可以先对集成电路芯片进行数据写入，再将完成数据写入后的集成电路芯片制成所需要的成品；还可以先将未进行数据写入的集成电路芯片制成半成品，然后根据其具体的功能需求对早已完成的半成品统一进行数据写入。可见，本申请的技术方案相比传统模式，很巧妙且很大程度地缩短了从确定产品需求到生产完所需产品的周期，更加灵活可控。
此外，现有技术中，装配好的电子产品一般无法进行数据写入以完成功能更换，或者需要完成极其繁琐的拆卸才有可能进行数据写入以完成功能更换，而采用本申请所提供的技术方案，对于装配好的电子产品，可以直接借助于产品内置集成电路芯片的供电正级、供电负极输入对应电连接的电池座电源正极触片和负极触片来完成数据写入，从而实现对装配好的电子产品的功能更新。由于这些触片外部可见，无需繁琐拆卸，实施起来方便且灵活。
实施例二
在上述实施例一的基础上，为保证烧录器和集成电路芯片之间通信的可靠性，本申请实施例二对上述实施例一作进一步改进，实施例二与实施例一相同之处不再赘述，请参见实施例一的对应描述。如图6所示，为本申请实施例提供的另一种集成电路芯片的数据写入方法的实现流程示意图。该数据写入方法包括步骤：S601至S604。
S601，发送数据写入指令至集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式，并返回反馈信号。
S602，接收所述集成电路芯片返回的反馈信号。
S603，通过控制所述集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行当前帧数据写入。
其中，烧录器的数据传输采用分帧数据传输，集成电路芯片在每一帧数据接收成功后反馈帧数据接收成功信号至烧录器。通过这种设置，保证烧录器和集成电路芯片之间通信的可靠性。
烧录器通过控制所述集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行当前帧数据写入，当接收到所述集成电路芯片在成功接收当前帧数据后反馈的帧数据接收成功信号时，进行下一帧数据写入。直至数据全部传输完毕。
S604，当接收到所述集成电路芯片在成功接收当前帧数据后反馈的帧数据接收成功信号时，进行下一帧数据写入。
成功信号时，进行下一帧数据写入。
需要说明的是，本申请实施例中，集成电路芯片在进入数据写入模式，并返回反馈信号，以使得烧录器对集成电路芯片进行数据写入。但是本领域技术人员知晓，集成电路芯片在接收到数据写入指令后会进入数据写入模式，不管集成电路芯片以何种反馈信号表征自己成功进入数据写入模式，或是否返回成功进入数据写入模式的反馈信号的情况下，烧录器都可对集成电路芯片进行数据写入，本实施例集成电路芯片返回反馈信号的方式仅为示例性描述，不能解释为对本申请的具体限制。
实施例三
如图7所示，为本申请实施例提供的一种集成电路芯片的数据写入方法的实现流程示意图。该数据写入方法适用于对集成电路芯片进行数据写入的情形，应用于具有集成电路芯片的产品或集成电路芯片，可由软件和/或硬件实现。该实施例三中未详细描述之处请参见实施例一和实施例二对应描述之处。
如图7所示，该数据写入方法包括步骤：S701至S703。
S701，集成电路芯片接收烧录器发送的数据写入指令，进入数据写入模式，并返回反馈信号。
S702，集成电路芯片通过检测所述烧录器控制的供电正极输入电压的电性参数，确定烧录器传输的数据。
集成电路芯片通过检测其供电正极输入电压的电性参数，并根据与烧录器之间的预设规则对检测结果进行判断，从而确定所述烧录器传输的数据。
所述预设规则包括电性参数与传输数据的对应关系。一方面，包括输入电压的大小与传输数据的对应关系。例如，两个不同大小的输入电压分别对应传输数据“0”和“1”；又如，8个不同大小的输入电压分别对应传输数据“0”、“1”、“2”“3”、“4”、“5”“6”和“7”。另一方面，包括输入电压上叠加的电信号的频率与传输数据的对应关系。例如，两个频率大小的输入电压分别对应传输数据“0”和“1”；又如，8个不同大小的输入电压分别对应传输数据“0”、“1”、“2”“3”、“4”、“5”“6”和“7”。
作为本申请一实施例，所述集成电路芯片通过其内置或外接的第二信号转换电路检测其供电正极输入电压的电性参数。其中，第二信号转换电路，如A/D转换器或者比较器等电路。例如，若烧录器控制集成电路芯片供电正极的输入电压的大小在2个值，如VCC-δ和VCC之间切换，则所述集成电路芯片通过预设规则判断所述烧录器传输的数据是“0”还是“1”，其中，预设规则可以为：VCC-δ对应传输的数据是“0”，VCC对应传输的数据是“1”；预设规则也可以为：VCC-δ对应传输的数据是“1”，VCC对应传输的数据是“0”。
又如，若烧录器控制集成电路芯片供电正极的输入电压的大小在8个值之间切换，则所述集成电路芯片通过预设规则判断所述烧录器传输的数据是“0”、“1”、“2”“3”、“4”、“5”“6”或“7”，判断完后转换为对应的二进制数据“000”、“001”、“010”、“011”、“100”、“101”、“110”、“111”。可见，与采用2个输入电压值进行数据传输相比，采用多个输入电压值进行数据传输可以很好地加快数据传输效率。
同样的，与采用2个频率值进行数据传输相比，采用多个频率值进行数据传输也可以加快数据传输效率。
S703，集成电路芯片启用所述烧录器传输的数据。
其中，集成电路芯片启用烧录器传输的数据，即集成电路芯片通过烧录器传输数据更新其内置或外接存储器内的信息。在成功启用烧录器传输的数据后，集成电路芯片反馈数据更新成功信号至烧录器。
需要说明的是，本申请实施例中，集成电路芯片在进入数据写入模式，并返回反馈信号，以使得烧录器对集成电路芯片进行数据写入。但是本领域技术人员知晓，集成电路芯片在接收到数据写入指令后会进入数据写入模式，不管集成电路芯片以何种反馈信号表征自己成功进入数据写入模式，或是否返回成功进入数据写入模式的反馈信号的情况下，烧录器都可对集成电路芯片进行数据写入，本实施例集成电路芯片返回反馈信号的方式仅为示例性描述，不能解释为对本申请的具体限制。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
实施例四
继续参见如图2和图3所示，为本申请实施例提供的一种集成电路芯片的数据写入系统的结构示意图。数据写入系统包括烧录器和集成电路芯片，所述烧录器电连接集成电路芯片的供电正极和供电负极。
其中，所述烧录器，用于发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式，并返回反馈信号；接收所述集成电路芯片返回的反馈信号；通过控制所述集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行数据写入。
在本申请实施例中，烧录器通过集成电路芯片的供电正极与负极输入2线与集成电路芯片电连接，烧录器外接电源，以形成电路回路。
所述集成电路芯片，用于接收烧录器发送的数据写入指令，进入数据写入模式，并返回反馈信号；通过检测所述烧录器控制的供电正极输入电压的电性参数，确定烧录器传输的数据；启用所述烧录器传输的数据。
其中，烧录器和集成电路芯片之间采用双向通信方式。集成电路芯片在成功启用所述烧录器传输的数据后，会反馈数据更新成功信号至烧录器。
进一步地，如图8所示，所述烧录器包括主控和第一信号转换电路，所述主控通过所述第一信号转换电路电连接所述集成电路芯片的供电正极和供电负极。
所述主控，用于：
发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式，并返回反馈信号；
接收所述集成电路芯片返回的反馈信号；
通过所述第一信号转换电路控制所述集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行数据写入。
进一步地，如图8所示，所述烧录器还包括电源输入电路，所述电源输入电路分别与所述主控和所述第一信号转换电路电连接，所述电源输入电路用于外接电源，对所述主控和所述第一信号转换电路进行供电。
进一步地，如图8所示，所述数据写入系统还包括第二信号转换电路，所述第二信号转换电路与所述第一信号转换电路电连接，所述集成电路芯片通过所述第二信号转换电路检测所述烧录器控制的供电正极输入电压的电性参数，确定所述烧录器传输的数据。
其中，所述第二信号转换电路可以外接或者内置于所述集成电路芯片。集成电路芯片通过第二信号转换电路检测供电正极输入电压的电性参数，例如输入电压的大小或叠加在所述输入电压上的电信号的频率，并根据与烧录器之间的预设规则对检测结果进行判断，从而确定所述烧录器具体传输的数据。
进一步地，如图8所示，所述数据写入系统还包括隔离电路，所述隔离电路与所述集成电路芯片电连接，所述集成电路芯片通过所述隔离电路隔离对所述集成电路芯片和烧录器之间的数据传输造成干扰的信号。
其中，所述隔离电路可以外接所述集成电路芯片。
需要说明的是，本申请实施例中，集成电路芯片在进入数据写入模式，并返回反馈信号，以使得烧录器对集成电路芯片进行数据写入。但是本领域技术人员知晓，集成电路芯片在接收到数据写入指令后会进入数据写入模式，不管集成电路芯片以何种反馈信号表征自己成功进入数据写入模式，或是否返回成功进入数据写入模式的反馈信号的情况下，烧录器都可对集成电路芯片进行数据写入，本实施例集成电路芯片返回反馈信号的方式仅为示例性描述，不能解释为对本申请的具体限制。
实施例五
如图9所示，为本申请实施例提供的一种集成电路芯片的数据写入系统的结构示意图。该实施例五对上述实施例四作进一步改进。实施例五与实施例四相同之处不再赘述，请参见实施例四的对应描述，仅描述与实施例四的不同之处。
图9示出了烧录器内置的第一数据转换电路控制集成电路供电正极的输入电压在VCC和0两个值之间切换时，也即烧录器和集成电路芯片之间的通信电平可在VCC和GND之间切换时的电路图。
烧录器的电源输入电路包括供电输入接口J1，烧录器的第一信号转换电路包括烧录输出接口J2，供电输入接口J1分别与烧录器主控电路、第一信号转换电路电连接，用于外接电源为烧录器主控电路和第一信号转换电路供电。第二信号转换电路包括烧录输入接口J3，烧录输入接口J3与烧录器的烧录输出接口J2建立电连接。
烧录输入接口J3的引脚2与烧录输出接口J2的引脚2相连接，烧录输入接口J3的引脚1与烧录输出接口J2的引脚1都接地。当烧录器供电输入接口J1外接电源时，烧录器和集成电路芯片端之间即可形成电路回路。
烧录器的主控包括供电输入引脚VDD和GND，通过供电输入接口J1外接电源为主控供电。烧录器的主控还包括输入输出端口GPIO1、GPIO2、和GPIO3。第一信号转换电路包括烧录输出接口J2、PMOS管Q1和Q2，电阻R1、R2、R3和R4。
其中，输入输出端口GPIO1与电阻R2的一端电连接，电阻R2的另一端与烧录输出接口J2的引脚2电连接，烧录输出接口J2的引脚1接地。输入输出端口GPIO2与电阻R1的一端电连接，输入输出端口GPIO2还与PMOS管Q1的栅极电连接，电阻R1的另一端和PMOS管Q1的源极都连接电源VCC，PMOS管Q1的漏极与烧录输出接口J2的引脚2电连接。输入输出端口GPIO3与电阻R3的一端电连接，输入输出端口GPIO3还与PMOS管Q2的栅极电连接，电阻R3的另一端、PMOS管Q2的源极都与烧录输出接口J2的引脚2电连接，PMOS管Q2的漏极与电阻R4的一端电连接，电阻R4的另一端接地。
集成电路芯片包括PORT1引脚、VDD引脚和GND引脚，GND引脚接地。第二信号转换电路包括烧录输入接口J3和电阻R5；所述隔离电路包括二极管D1和电容C1。其中，PORT1引脚为集成电路芯片的一个输入输出接口。
其中，烧录输入接口J3的引脚2与电阻R5的一端电连接，电阻R5的另一端与集成电路芯片的PORT1引脚电连接。烧录输入接口J3的引脚2还与二极管D1的正极电连接，二极管D1的负极分别电连接于集成电路芯片的VDD引脚、电容C1正极，电容C1负极接地。
当第二信号转换电路通过烧录输入接口J3与烧录器的烧录输出接口J2建立电连接，且烧录器的供电输入接口J1外接电源后，烧录器和集成电路芯片端之间即形成电路回路。此时，烧录器主控的输入输出端口GPIO2用于控制PMOS管Q1打开或关闭。具体的，当输入输出端口GPIO2是低电平0时，PMOS管Q1打开，此时，PMOS管Q1源极的VCC电平可以从其源极导通至其漏极，由于PMOS管Q1的漏极与烧录输出接口J2的引脚2电连接，故VCC电平导通至烧录输出接口J2的引脚2；当端口GPIO2是高电平1时，PMOS管Q1关闭，此时，PMOS管Q1源极的VCC电平无法导通至烧录输出接口J2的引脚2。可见，通过烧录器主控电路的端口GPIO2，可以巧妙地实现烧录输出接口J2引脚2的电压在VCC和0两个电压数值之间切换。
当PMOS管Q1处于关闭状态时，通过使烧录器主控的输入输出端口GPIO3在一段时间内保持为低电平0，可使PMOS管Q2源极的电压，也即烧录输出接口J2引脚2的电压导通至PMOS管Q2的漏极，由于PMOS管Q2的漏极通过电阻R4接地，故可实现对烧录输出接口J2引脚2放电。
当PMOS管Q1和Q2都处于关闭状态时，烧录器主控的输入输出端口GPIO1即可实现接收集成电路芯片发送的反馈信号。
当烧录器的烧录输出接口J2引脚2的电压在VCC和0两个数值之间切换时，由于集成电路芯片端的烧录输入接口J3的引脚2与烧录输出接口J2的引脚2是电连接的，则集成电路芯片端的烧录输入接口J3引脚2的电压也会在VCC和0两个数值之间切换，并通过电阻R5输入到集成电路芯片的PORT1引脚，此时，集成电路芯片根据与烧录器之间的预设规则对PORT1引脚的电压进行判断，从而可以确定所述烧录器具体传输的数据。特别的，当烧录输入接口J3引脚2的电压为VCC时，可以为电容C1充电，当烧录输入接口J3引脚2的电压为0时，二极管D1的单向导通性帮助隔离烧录器的GND信号，从而巧妙地保证电容C1只对集成电路芯片VDD引脚放电以维持集成电路芯片正常工作。
此外，为了保证集成电路芯片在整个数据写入过程中都能正常工作，会将PMOS管Q1连续关闭的时间控制在合理的时间范围内，从而避免烧录输入接口J3引脚2的电压因长时间为0而导致集成电路芯片无法正常工作的情况发生。比如，可以采用在通过电平切换来传输特定字节的数据后将PMOS管Q1在一预设时间段内维持为打开的方式。该预设时间段可结合实际需要的数据传输效率来设定。
当PMOS管Q1和Q2都处于关闭状态时，集成电路芯片可以发送反馈信号至烧录器主控的输入输出端口GPIO1。
需要说明的是，本申请实施例中，集成电路芯片在进入数据写入模式，并返回反馈信号，以使得烧录器对集成电路芯片进行数据写入。但是本领域技术人员知晓，集成电路芯片在接收到数据写入指令后会进入数据写入模式，不管集成电路芯片以何种反馈信号表征自己成功进入数据写入模式，或是否返回成功进入数据写入模式的反馈信号的情况下，烧录器都可对集成电路芯片进行数据写入，本实施例集成电路芯片返回反馈信号的方式仅为示例性描述，不能解释为对本申请的具体限制。
实施例六
如图10所示，为本申请实施例提供的一种集成电路芯片的数据写入装置的结构示意图。该集成电路芯片的数据写入装置，配置于烧录器。在本申请实施例中，集成电路芯片通过供电正极和供电负极与所述烧录器电连接。
如图10所示，所述数据写入装置包括：发送单元101、接收单元102、和控制执行单元103。
其中，发送单元101，用于发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式，并返回反馈信号；
接收单元102，用于接收所述集成电路芯片返回的反馈信号；
控制执行单元103，用于通过控制所述集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行数据写入。
可选地，所述控制执行单元103，具体用于：
通过控制所述集成电路芯片供电正极输入电压的大小对集成电路芯片进行数据写入；或
通过控制所述集成电路芯片供电正极输入电压上叠加的电信号的频率对集成电路芯片进行数据写入。
可选地，所述控制执行单元103，具体用于：通过控制所述集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行当前帧数据写入。
相应的，所述接收单元102还用于：当接收到所述集成电路芯片在成功接收当前帧数据后反馈的帧数据接收成功信号时，进行下一帧数据写入。
需要说明的是，本申请实施例中，集成电路芯片在进入数据写入模式，并返回反馈信号，以使得烧录器对集成电路芯片进行数据写入。但是本领域技术人员知晓，集成电路芯片在接收到数据写入指令后会进入数据写入模式，不管集成电路芯片以何种反馈信号表征自己成功进入数据写入模式，或是否返回成功进入数据写入模式的反馈信号的情况下，烧录器都可对集成电路芯片进行数据写入，也就是说本实施例集成电路芯片的数据写入装置中发送单元返回反馈信号，接收单元接收反馈信号的方式仅为示例性描述，不能解释为对本申请的具体限制。
实施例七
如图11所示，为本申请实施例提供的另一种集成电路芯片的数据写入装置的结构示意图。该集成电路芯片的数据写入装置，配置于集成电路芯片。在本申请实施例中，集成电路芯片通过供电正极和供电负极与所述烧录器电连接。
如图11所示，所述数据写入装置包括：接收单元111、检测执行单元112和启用单元113。
其中，接收单元111，用于接收烧录器发送的数据写入指令，进入数据写入模式，并返回反馈信号；
检测执行单元112，用于通过检测所述烧录器控制的供电正极输入电压的电性参数，确定烧录器传输的数据；
启用单元113，用于启用所述烧录器传输的数据。
可选地，所述检测执行单元112，具体用于：
通过检测所述烧录器控制的供电正极输入电压的大小，确定烧录器传输的数据；或
通过检测所述烧录器控制的供电正极输入电压上叠加的电信号的频率，确定烧录器传输的数据。
在上述实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
需要说明的是，本申请实施例中，集成电路芯片在进入数据写入模式，并返回反馈信号，以使得烧录器对集成电路芯片进行数据写入。但是本领域技术人员知晓，集成电路芯片在接收到数据写入指令后会进入数据写入模式，不管集成电路芯片以何种反馈信号表征自己成功进入数据写入模式，或是否返回成功进入数据写入模式的反馈信号的情况下，烧录器都可对集成电路芯片进行数据写入，也就是说本实施例集成电路芯片的数据写入装置中接收单元返回反馈信号的方式仅为示例性描述，不能解释为对本申请的具体限制。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
实施例八
图12是本申请一实施例提供的一种集成电路芯片的数据写入设备的示意图。如图12所示，该实施例的设备12包括：处理器120、存储器121以及存储在所述存储器121中并可在所述处理器120上运行的计算机可读指令122。所述处理器120执行所述计算机可读指令122时实现上述各个集成电路芯片的数据写入方法实施例中的步骤，例如图1所示的步骤101至103；又如图7所示的步骤701至703。或者，所述处理器120执行所述计算机可读指令122时实现上述各装置实施例中各模块/单元的功能，例如图10所示模块101至103的功能；又如图11所示模块111至113的功能。
示例性的，所述计算机可读指令122可以被分割成一个或多个模块/单元，所述一个或者多个模块/单元被存储在所述存储器121中，并由所述处理器120执行，以完成本申请。所述一个或多个模块/单元可以是能够完成特定功能的一系列计算机可读指令指令段，该指令段用于描述所述计算机可读指令122在所述集成电路芯片的数据写入设备12中的执行过程。
例如，所述计算机可读指令122可以被分割成发送单元、接收单元、和控制执行单元（虚拟装置中的单元），各单元具体功能如下：
发送单元，用于发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式，并返回反馈信号；
接收单元，用于接收所述集成电路芯片返回的反馈信号；
控制执行单元，用于通过控制所述集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行数据写入。
又如，所述计算机可读指令122可以被分割成接收单元、检测执行单元和启用单元（虚拟装置中的单元），各单元具体功能如下：
接收单元，用于接收烧录器发送的数据写入指令，进入数据写入模式，并返回反馈信号；
检测执行单元，用于通过检测所述烧录器控制的供电正极输入电压的电性参数，确定烧录器传输的数据；
启用单元，用于启用所述烧录器传输的数据。
需要说明的是，本申请实施例中，集成电路芯片在进入数据写入模式，并返回反馈信号，以使得烧录器对集成电路芯片进行数据写入。但是本领域技术人员知晓，集成电路芯片在接收到数据写入指令后会进入数据写入模式，不管集成电路芯片以何种反馈信号表征自己成功进入数据写入模式，或是否返回成功进入数据写入模式的反馈信号的情况下，烧录器都可对集成电路芯片进行数据写入，也就是说本实施例集成电路芯片的数据写入设备中计算机可读指令122包含的接收单元返回反馈信号的方式仅为示例性描述，不能解释为对本申请的具体限制。
所述集成电路芯片的数据写入设备12可以是桌上型计算机、笔记本、掌上电脑及云端服务器等计算设备。所述数据写入设备可包括，但不仅限于，处理器120、存储器121。本领域技术人员可以理解，图12仅仅是数据写入设备12的示例，并不构成对数据写入设备12的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件，例如所述数据写入设备还可以包括输入输出设备、网络接入设备、总线等。
所称处理器120可以是CPU，还可以是其他通用处理器、DSP、专用集成电路 (Application Specific Integrated Circuit，ASIC)、现场可编程门阵列 (Field-Programmable Gate Array，FPGA) 或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
所述存储器121可以是所述数据写入设备12的内部存储单元，例如数据写入设备12的硬盘或内存。所述存储器121也可以是所述数据写入设备12的外部存储设备，例如所述数据写入设备12上配备的插接式硬盘，智能存储卡（Smart Media Card，SMC），安全数字（Secure Digital，SD）卡，Flash卡等。进一步地，所述存储器121还可以既包括所述数据写入设备12的内部存储单元也包括外部存储设备。所述存储器121用于存储所述计算机可读指令以及所述数据写入设备12所需的其他程序和数据。所述存储器121还可以用于暂时地存储已经输出或者将要输出的数据。
所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，仅以上述各功能单元、模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能单元、模块完成，即将所述装置的内部结构划分成不同的功能单元或模块，以完成以上描述的全部或者部分功能。实施例中的各功能单元、模块可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中，上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。另外，各功能单元、模块的具体名称也只是为了便于相互区分，并不用于限制本申请的保护范围。上述系统中单元、模块的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
上述实施例中提供了集成电路芯片的数据写入方法、系统、装置、设备及介质，该方法、系统、装置、设备及介质中，烧录器通过控制集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行数据写入，但是当集成电路芯片外接有稳压管、LDO（Low dropout regulator，低压差线性稳压器）、升压等DC电路或电源电路时，由于这些元器件或电路具备稳压，即抑制电压波动的特性，会导致烧录器加载在集成电路芯片供电正极输入电压上的数据无法有效传输到集成电路芯片，致使烧录器无法实现对集成电路芯片的数据写入。下述实施例将介绍通过控制集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行数据写入的方法、系统、装置、设备及介质。
实施例九
如图13所示，为本申请实施例提供的另一种集成电路芯片的数据写入方法的实现流程示意图。该数据写入方法适用于对集成电路芯片进行数据写入的情形，应用于烧录器，可由软件和/或硬件实现。
该实施例中未详细描述之处请参见实施例一对应描述之处。
如图13所示，该数据写入方法包括步骤：S101’至S102’。
S101’，发送数据写入指令至集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式。
为了更清楚地说明本申请，在后续具体实施例的描述中，所述集成电路芯片通过自身供电正极和供电负极与烧录器电连接的方式，如图14所示，以供电正极为电源正极VCC，供电负极为GND，烧录器通过控制集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行数据写入为例进行说明。
需要说明的是，在集成电路芯片封装成为产品后，一般设置有为产品运行而供电的电池座，所述电池座与所述集成电路芯片的供电正极和供电负极输入2线连接，这时可以隔离所述电池座上的电池供电或者将供电电池从所述电池座上取出，直接通过所述电池座上的电源正极和电源负极触片将所述集成电路芯片与所述烧录器电连接，如图15所示。所述烧录器外接电源，从而形成电路回路。
烧录器发送数据写入指令至集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式。
其中，所述数据写入模式是指所述集成电路芯片响应所述烧录器进行数据写入的准备状态。所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式。
作为本申请一实施例，所述烧录器包括主控，通过主控发送指令至集成电路芯片；所述集成电路芯片接收到烧录器发来的指令后，通过内置或外接的第二信号转换电路对发来的指令进行检测判断，若发来的指令为数据写入指令，则集成电路芯片进入数据写入模式，还可以发送已进入数据写入模式的反馈信号。集成电路芯片发送已进入数据写入模式的反馈信号是指所述集成电路芯片反馈其已进入数据写入模式的信号至所述烧录器，或者是所述集成电路芯片通过控制与其电连接的LED灯闪烁和/或喇叭发出声音，以提示所述集成电路芯片已成功进入数据写入模式，通过这种设置，让监测数据写入的工程师能够更快捷且直观地确定集成电路芯片已经成功进入数据写入模式，便于工程师对整个流程进行监控，进一步提高了效率。
该步骤中未详细描述之处请参见实施例一步骤S101对应描述之处。
S102’，在集成电路芯片进入数据写入模式后，通过控制所述集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行数据写入。
其中，所述数据写入是指所述烧录器将所述集成电路芯片需要写入的数据传输至所述集成电路芯片，从而更新所述集成电路芯片内置或外接存储内的信息。
所述控制集成电路芯片供电负极的输入电压的电性参数，可以是控制集成电路芯片供电负极输入电压的大小，比如方波电压，还可以是控制集成电路芯片供电负极输入电压上叠加的电信号的频率。例如，控制集成电路芯片供电负极输入电压上叠加的正弦信号的频率；又如，控制集成电路芯片供电负极输入电压上叠加的三角波、锯齿波等电信号的频率。需要说明的是，此处仅为示例性描述，不解释为对本申请的限制。
在本申请实施例中，所述烧录器包括第一信号转换电路，烧录器通过其内置的信号转换电路控制所述集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行数据写入。
作为本申请一实施例，烧录器通过控制集成电路芯片供电负极的输入电压的大小来对集成电路芯片进行数据写入，是指所述烧录器通过其内置的第一信号转换电路改变所述集成电路芯片供电负极的输入电压的大小来传输二进制数据“0”和“1”。
作为本申请另一实施例，烧录器通过控制叠加在集成电路芯片供电负极的输入电压上的正弦信号的频率对集成电路进行数据写入，是指所述烧录器通过其内置的第一信号转换电路改变叠加在所述集成电路芯片供电负极的输入电压上的正弦信号的频率来传输二进制数据“0”和“1”。
此外，还可以选择在输入电压上叠加不同数量的正弦信号频率，可以至少选择2个，还可以选择3个或4个以上等。通过选择正弦信号频率的数量越大，可以使得传输数据的传输效率更高，从而进一步提高数据写入的效率。例如，如图5所示，控制叠加在所述集成电路供电负极的输入电压上的正弦信号的频率在f1、f2之间切换，来传输二进制数据“0”和“1”。
目前的烧录器是通过集成电路芯片特定的接口，如JTAG接口等，且至少使用4根线，对集成电路芯片内置或外接的存储器进行数据写入，而本申请所提供的技术方案仅利用集成电路芯片的供电正极和供电负极输入2线便可以完成数据写入，更加简单方便；此外，由于本申请的数据写入不再依赖JTAG等特定接口，很巧妙地降低了厂商绑定芯片的成本；并且本申请所提供的技术方案中，烧录器通过控制集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行数据写入，很好地解决了集成电路芯片外接有稳压器件时，导致烧录器加载在集成电路芯片供电正极输入电压上的数据无法有效传输到集成电路芯片，无法实现集成电路芯片的数据写入的技术问题。
该步骤中未详细描述之处请参见实施例一步骤S103对应描述之处。
实施例十
在上述实施例九的基础上，为保证烧录器和集成电路芯片之间通信的可靠性，本申请实施例十对上述实施例九作进一步改进，实施例十与实施例九相同之处不再赘述，请参见实施例九的对应描述。如图16所示，为本申请实施例提供的另一种集成电路芯片的数据写入方法的实现流程示意图。该数据写入方法包括步骤：S601’至S603’。
S601’，发送数据写入指令至集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式。
S602’，在所述集成电路芯片进入数据写入模式后，通过控制所述集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行当前帧数据写入。
烧录器通过控制所述集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行当前帧数据写入，当接收到所述集成电路芯片在成功接收当前帧数据后反馈的帧数据接收成功信号时，进行下一帧数据写入，直至数据全部传输完毕。
该步骤中未详细描述之处请参见实施例二步骤S603对应描述之处。
S603’，当接收到所述集成电路芯片在成功接收当前帧数据后反馈的帧数据接收成功信号时，进行下一帧数据写入。
实施例十一
如图17所示，为本申请实施例提供的另一种集成电路芯片的数据写入方法的实现流程示意图。该数据写入方法适用于对集成电路芯片进行数据写入的情形，应用于具有集成电路芯片的产品或集成电路芯片，可由软件和/或硬件实现。该实施例十一中未详细描述之处请参见实施例九和实施例十对应描述之处。
如图17所示，该数据写入方法包括步骤：S701’至S703’。
S701’，集成电路芯片接收烧录器发送的数据写入指令，进入数据写入模式。
S702’，集成电路芯片通过检测所述烧录器控制的供电负极输入电压的电性参数，确定烧录器传输的数据。
集成电路芯片通过检测其供电负极输入电压的电性参数，并根据与烧录器之间的预设规则对检测结果进行判断，从而确定所述烧录器传输的数据。
作为本申请一实施例，所述集成电路芯片通过其内置或外接的第二信号转换电路检测其供电负极输入电压的电性参数。其中，第二信号转换电路，如A/D转换器或者比较器等电路。例如，若烧录器控制集成电路芯片供电负极的输入电压的大小在2个值，如VCC-δ和VCC之间切换，则所述集成电路芯片通过预设规则判断所述烧录器传输的数据是“0”还是“1”，其中，预设规则可以为：VCC-δ对应传输的数据是“0”，VCC对应传输的数据是“1”；预设规则也可以为：VCC-δ对应传输的数据是“1”，VCC对应传输的数据是“0”。
又如，若烧录器控制集成电路芯片供电负极的输入电压的大小在8个值之间切换，则所述集成电路芯片通过预设规则判断所述烧录器传输的数据是“0”、“1”、“2”“3”、“4”、“5”“6”或“7”，判断完后转换为对应的二进制数据“000”、“001”、“010”、“011”、“100”、“101”、“110”、“111”。可见，与采用2个输入电压值进行数据传输相比，采用多个输入电压值进行数据传输可以很好地加快数据传输效率。
同样的，与采用2个频率值进行数据传输相比，采用多个频率值进行数据传输也可以加快数据传输效率。
该步骤中未详细描述之处请参见实施例三步骤S702对应描述之处。
S703’，集成电路芯片启用所述烧录器传输的数据。
其中，集成电路芯片启用烧录器传输的数据，即集成电路芯片通过烧录器传输数据更新其内置或外接存储器内的信息。在成功启用烧录器传输的数据后，集成电路芯片反馈数据更新成功信号至烧录器。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
实施例十二
继续参见如图14和图15所示，为本申请实施例提供的另一种集成电路芯片的数据写入系统的结构示意图。数据写入系统包括烧录器和集成电路芯片，所述烧录器电连接集成电路芯片的供电正极和供电负极。
其中，所述烧录器，用于发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式；在所述集成电路芯片进入数据写入模式后，通过控制所述集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行数据写入。
在本申请实施例中，烧录器通过集成电路芯片的供电正极与负极输入2线与集成电路芯片电连接，烧录器外接电源，以形成电路回路。
所述集成电路芯片，用于接收烧录器发送的数据写入指令，进入数据写入模式；通过检测所述烧录器控制的供电负极输入电压的电性参数，确定烧录器传输的数据；启用所述烧录器传输的数据。
集成电路芯片在成功启用所述烧录器传输的数据后，会反馈数据更新成功信号至烧录器。
进一步地，如图18所示，所述烧录器包括主控和第一信号转换电路，所述主控通过所述第一信号转换电路电连接所述集成电路芯片的供电正极和供电负极。
所述主控，用于：
发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式；
通过所述第一信号转换电路控制所述集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行数据写入。
进一步地，如图18所示，所述烧录器还包括电源输入电路，所述电源输入电路分别与所述主控和所述第一信号转换电路电连接，所述电源输入电路用于外接电源，对所述主控和所述第一信号转换电路进行供电。
进一步地，如图18所示，所述数据写入系统还包括第二信号转换电路，所述第二信号转换电路与所述第一信号转换电路电连接，所述集成电路芯片通过所述第二信号转换电路检测所述烧录器控制的供电负极输入电压的电性参数，确定所述烧录器传输的数据。
其中，所述第二信号转换电路可以外接或者内置于所述集成电路芯片。集成电路芯片通过第二信号转换电路检测供电负极输入电压的电性参数，例如输入电压的大小或叠加在所述输入电压上的电信号的频率，并根据与烧录器之间的预设规则对检测结果进行判断，从而确定所述烧录器具体传输的数据。
进一步地，如图18所示，所述数据写入系统还包括隔离电路，所述隔离电路与所述集成电路芯片电连接，所述集成电路芯片通过所述隔离电路隔离对所述集成电路芯片和烧录器之间的数据传输造成干扰的信号。
其中，所述隔离电路可以外接所述集成电路芯片。
实施例十三
如图19所示，为本申请实施例提供的另一种集成电路芯片的数据写入系统的结构示意图。该实施例十三对上述实施例十二作进一步改进。实施例十三与实施例十二相同之处不再赘述，请参见实施例十二的对应描述，仅描述与实施例十二的不同之处。
图19示出了烧录器内置的第一数据转换电路控制集成电路供电负极的输入电压在VCC和0两个值之间切换时，也即烧录器和集成电路芯片之间的通信电平可在VCC和GND之间切换时的电路图。
烧录器的电源输入电路包括供电输入接口J4，烧录器的第一信号转换电路包括烧录输出接口J5，供电输入接口J4分别与烧录器主控电路、第一信号转换电路电连接，用于外接电源为烧录器主控电路和第一信号转换电路供电。第二信号转换电路包括烧录输入接口J6，烧录输入接口J6与烧录器的烧录输出接口J5建立电连接。
烧录输入接口J6的引脚2与烧录输出接口J5的引脚2相连接，烧录输出接口J5的引脚2接电源VCC。当烧录器供电输入接口J4外接电源时，烧录器和集成电路芯片端之间即可形成电路回路。
烧录器的主控包括供电输入引脚VDD和GND，通过供电输入接口J4外接电源为主控供电。烧录器的主控还包括输入输出端口GPIO4、GPIO5、和GPIO6。第一信号转换电路包括烧录输出接口J5、PMOS管Q3和NMOS管Q4，电阻R10、R11、R12。
其中，输入输出端口GPIO4与电阻R11的一端电连接，电阻R11的另一端与烧录输出接口J5的引脚1电连接。输入输出端口GPIO5与电阻R10的一端电连接，输入输出端口GPIO5还与PMOS管Q3的栅极电连接，电阻R10的另一端和PMOS管Q3的源极都连接电源VCC，PMOS管Q3的漏极与烧录输出接口J5的引脚1电连接。输入输出端口GPIO6与电阻R12的一端电连接，输入输出端口GPIO6还与NMOS管Q4的栅极电连接，电阻R12的另一端、NMOS管Q4的源极都接地，NMOS管Q4的漏极与烧录输出接口J5的引脚1电连接。
集成电路芯片包括PORT2引脚、VDD引脚和GND引脚。第二信号转换电路包括烧录输入接口J6和电阻R14；隔离电路包括二极管D2和电容C2。其中，PORT2引脚为集成电路芯片的一个输入输出接口。
其中，烧录输入接口J6的引脚1与电阻R14的一端电连接，电阻R14的另一端与集成电路芯片的PORT2引脚电连接。烧录输入接口J6的引脚1还与二极管D2的负极电连接，二极管D2的正极电连接于集成电路芯片的GND引脚，集成电路芯片的GND引脚接地。烧录输入接口J6的引脚2分别电连接于集成电路芯片的VDD引脚、电容C2正极，电容C2负极接地。
当第二信号转换电路通过烧录输入接口J6与烧录器的烧录输出接口J5建立电连接，且烧录器的供电输入接口J4外接电源后，烧录器和集成电路芯片端之间即形成电路回路。此时，烧录器主控的输入输出端口GPIO5用于控制PMOS管Q3打开或关闭，烧录器主控的输入输出端口GPIO6用于控制NMOS管Q4打开或关闭。具体的，当输入输出端口GPIO5、GPIO6是低电平0时，PMOS管Q3打开，NMOS管Q4关闭，此时，PMOS管Q3源极的VCC电平可以从其源极导通至其漏极，由于PMOS管Q3的漏极与烧录输出接口J5的引脚1电连接，故VCC电平导通至烧录输出接口J5的引脚1；当端口GPIO5、GPIO6是高电平1时，PMOS管Q3关闭，NMOS管Q4打开，此时，NMOS管Q4的漏极和源极导通，由于NMOS管Q4的漏极与烧录输出接口J5的引脚1电连接，故烧录输出接口J5的引脚1的电平被NMOS管Q4的源极拉低为GND。可见，通过烧录器主控电路的端口GPIO5和GPIO6，可以巧妙地实现烧录输出接口J5引脚1的电压在VCC和0两个电压数值之间切换。
当端口GPIO5是高电平1且GPIO6是低电平0时，PMOS管Q3和NMOS管Q4都处于关闭状态时，将PORT2引脚设置为输出，烧录器主控的输入输出端口GPIO4即可实现通过烧录输出接口J5的引脚1接收集成电路芯片PORT2引脚发送的反馈信号。
当烧录器的烧录输出接口J5引脚1的电压在VCC和0两个数值之间切换时，由于集成电路芯片端的烧录输入接口J6的引脚1与烧录输出接口J5的引脚1是电连接的，集成电路芯片的PORT2引脚设为输入，则集成电路芯片端的烧录输入接口J6引脚1的电压也会在VCC和0两个数值之间切换，并通过电阻R14输入到集成电路芯片的PORT2引脚，此时，集成电路芯片根据与烧录器之间的预设规则对PORT2引脚的电压进行判断，从而可以确定所述烧录器具体传输的数据。特别的，当烧录输入接口J6引脚1的电压为0时，可以为电容C2充电，当烧录输入接口J6引脚1的电压为VCC时，二极管D2的单向导通性帮助隔离烧录输入接口J6引脚1和集成电路芯片的GND引脚，从而巧妙地保证电容C2对集成电路芯片VDD引脚放电以维持集成电路芯片正常工作，确保烧录输入接口J6引脚1的电压通过电阻R14输入到集成电路芯片的PORT2引脚。
当PMOS管Q3和NMOS管Q4都处于关闭状态时，集成电路芯片可以通过PORT2引脚发送反馈信号至烧录器主控的输入输出端口GPIO4。
当集成电路芯片处于正常工作状态时，是将烧录输入接口J6电连接于供电接口J7连接的BT2电池或DC供电端。当烧录器对集成电路芯片进行数据写入时，烧录输入接口J6与供电接口J7断开连接，烧录输入接口J6与烧录输出接口J5建立电连接。
烧录器或集成电路芯片端不同时进行发送和接收，烧录器需要发送数据写入指令至集成电路芯片，在发送数据写入指令后立即切换为输入电路，等待接收集成电路芯片发送的信号。
此外，为了保证集成电路芯片在整个数据写入过程中都能正常工作，会将PMOS管Q3连续打开且NMOS管Q4连续关闭的时间控制在合理的时间范围内，从而避免烧录输入接口J6引脚1的电压因长时间为VCC而导致集成电路芯片无法正常工作的情况发生。比如，可以采用在通过电平切换来传输特定字节的数据后在一预设时间段内将PMOS管Q3维持为关闭且将NMOS管Q4维持为打开的方式。该预设时间段可结合实际需要的数据传输效率来设定。
本实施例中，烧录器的主控型号为GD32F150G8U6，或者是STM32F103CBT6、TR16F801B，集成电路芯片为TR16F064B、GD32系列母体、STM32系列母体，此处仅为烧录器主控和集成电路芯片型号示例性描述，不解释为对本申请的限制。
需要说明的是，本实施例中集成电路芯片端的二极管D2和电阻R14也可设置于集成电路芯片内部。此外，本实施例中的电路是为了充分说明烧录器通过控制集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行数据写入的过程，而并不对实现烧录器控制集成电路芯片供电负极输入电压的电性参数的电路进行限定，实际上能够实现该过程的电路有多种，如集成电路芯片端的二极管D2可以用MOS管替代，还可以用三极管或其他门电路替代，烧录器端包括Q3和Q4的电路也可以用马达驱动、开关电路等具备同种功能的器件或电路来实现，这些替代所形成的电路均在本申请的保护范围之内。
实施例十四
如图20所示，为本申请实施例提供的另一种集成电路芯片的数据写入装置的结构示意图。该集成电路芯片的数据写入装置，配置于烧录器。在本申请实施例中，集成电路芯片通过供电正极和供电负极与所述烧录器电连接。
如图20所示，所述数据写入装置包括：发送单元101’、和控制执行单元102’。
其中，发送单元101’，用于发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式；
控制执行单元102’，用于在所述集成电路芯片进入数据写入模式后，通过控制所述集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行数据写入。
可选地，所述控制执行单元102’，具体用于：
通过控制所述集成电路芯片供电负极输入电压的大小对集成电路芯片进行数据写入；或
通过控制所述集成电路芯片供电负极输入电压上叠加的电信号的频率对集成电路芯片进行数据写入。
可选地，所述控制执行单元102’，具体用于：通过控制所述集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行当前帧数据写入。
相应的，所述控制执行单元102’还用于：当接收到所述集成电路芯片在成功接收当前帧数据后反馈的帧数据接收成功信号时，进行下一帧数据写入。
实施例十五
如图11所示，为本申请实施例提供的另一种集成电路芯片的数据写入装置的结构示意图。
该集成电路芯片的数据写入装置，配置于集成电路芯片。在本申请实施例中，集成电路芯片通过供电正极和供电负极与所述烧录器电连接。
如图11所示，所述数据写入装置包括：接收单元111、检测执行单元112和启用单元113。
其中，接收单元111，用于接收烧录器发送的数据写入指令，进入数据写入模式；
检测执行单元112，用于通过检测所述烧录器控制的供电负极输入电压的电性参数，确定烧录器传输的数据；
启用单元113，用于启用所述烧录器传输的数据。
可选地，所述检测执行单元112，具体用于：
通过检测所述烧录器控制的供电负极输入电压的大小，确定烧录器传输的数据；或
通过检测所述烧录器控制的供电负极输入电压上叠加的电信号的频率，确定烧录器传输的数据。
在上述实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
实施例十六
图12是本申请一实施例提供的一种集成电路芯片的数据写入设备的示意图。如图12所示，该实施例的设备12包括：处理器120、存储器121以及存储在所述存储器121中并可在所述处理器120上运行的计算机可读指令122。所述处理器120执行所述计算机可读指令122时实现上述各个集成电路芯片的数据写入方法实施例中的步骤，例如图13所示的步骤101’至103’；又如图17所示的步骤701’至703’。或者，所述处理器120执行所述计算机可读指令122时实现上述各装置实施例中各模块/单元的功能，例如图20所示模块101’至103’的功能；又如上述实施例十五中所述图11所示模块111至113的功能。
示例性的，所述计算机可读指令122可以被分割成一个或多个模块/单元，所述一个或者多个模块/单元被存储在所述存储器121中，并由所述处理器120执行，以完成本申请。所述一个或多个模块/单元可以是能够完成特定功能的一系列计算机可读指令指令段，该指令段用于描述所述计算机可读指令122在所述集成电路芯片的数据写入设备12中的执行过程。
例如，所述计算机可读指令122可以被分割成发送单元和控制执行单元（虚拟装置中的单元），各单元具体功能如下：
发送单元，用于发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式；
控制执行单元，用于在所述集成电路芯片进入数据写入模式后，通过控制所述集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行数据写入。
又如，所述计算机可读指令122可以被分割成接收单元、检测执行单元和启用单元（虚拟装置中的单元），各单元具体功能如下：
接收单元，用于接收烧录器发送的数据写入指令，进入数据写入模式；
检测执行单元，用于通过检测所述烧录器控制的供电负极输入电压的电性参数，确定烧录器传输的数据；
启用单元，用于启用所述烧录器传输的数据。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述或记载的部分，可以参见其它实施例的相关描述。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的实施例中，应该理解到，所揭露的装置/设备和方法，可以通过其它的方式实现。例如，以上所描述的装置/设备实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通讯连接可以是通过一些接口，装置或单元的间接耦合或通讯连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
所述集成的模块/单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实现上述实施例方法中的全部或部分流程，也可以通过计算机可读指令来指令相关的硬件来完成，所述的计算机可读指令可存储于一计算机可读存储介质中，该计算机可读指令在被处理器执行时，可实现上述各个方法实施例的步骤。其中，所述计算机可读指令包括计算机可读指令代码，所述计算机可读指令代码可以为源代码形式、对象代码形式、可执行文件或某些中间形式等。所述计算机可读介质可以包括：能够携带所述计算机可读指令代码的任何实体或装置、记录介质、U盘、移动硬盘、磁碟、光盘、计算机存储器、只读存储器（Read-Only Memory，ROM）、随机存取存储器（Random Access Memory，RAM）、电载波信号、电信信号以及软件分发介质等。需要说明的是，所述计算机可读介质包含的内容可以根据司法管辖区内立法和专利实践的要求进行适当的增减，例如在某些司法管辖区，根据立法和专利实践，计算机可读介质不包括电载波信号和电信信号。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

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  1. 一种集成电路芯片的数据写入方法，应用于烧录器，其特征在于，所述集成电路芯片通过供电正极和供电负极与所述烧录器电连接；所述集成电路芯片内置或外接存储器；所述数据写入是指所述集成电路芯片通过所述烧录器写数据至所述存储器；所述数据写入方法包括：
    发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式；
    在所述集成电路芯片进入数据写入模式后，通过控制所述集成电路芯片供电正极或供电负极输入电压的电性参数对集成电路芯片进行数据写入。
  2. 如权利要求1所述的数据写入方法，其特征在于，所述通过控制所述集成电路芯片供电正极或供电负极输入电压的电性参数对集成电路芯片进行数据写入，包括：
    通过控制所述集成电路芯片供电正极或供电负极输入电压的大小对集成电路芯片进行数据写入；或
    通过控制所述集成电路芯片供电正极或供电负极输入电压上叠加的电信号的频率对集成电路芯片进行数据写入。
  3. 如权利要求2所述的数据写入方法，其特征在于，所述通过控制所述集成电路芯片供电正极或供电负极输入电压的大小对集成电路进行数据写入，包括：
    通过控制所述集成电路芯片供电负极或供电正极输入电压的大小在VCC和0之间切换以对集成电路芯片进行数据写入。
  4. 如权利要求1至3任一项所述的数据写入方法，其特征在于，所述通过控制所述集成电路芯片供电正极或供电负极输入电压的电性参数对集成电路芯片进行数据写入，包括：
    通过控制所述集成电路芯片供电正极或供电负极输入电压的电性参数对集成电路芯片进行当前帧数据写入；
    相应的，所述数据写入方法还包括：当接收到所述集成电路芯片在成功接收当前帧数据后反馈的帧数据接收成功信号时，进行下一帧数据写入。
  5. 一种集成电路芯片的数据写入方法，其特征在于，所述集成电路芯片通过供电正极和供电负极与烧录器连接；所述数据写入方法包括：
    集成电路芯片接收烧录器发送的数据写入指令，进入数据写入模式；
    集成电路芯片通过检测所述烧录器控制的供电正极或供电负极输入电压的电性参数，确定烧录器传输的数据；
    集成电路芯片启用所述烧录器传输的数据。
  6. 如权利要求5所述的数据写入方法，其特征在于，所述集成电路芯片通过检测所述烧录器控制的供电正极或供电负极输入电压的电性参数，确定烧录器传输的数据，包括：
    所述集成电路芯片通过检测所述烧录器控制的供电正极或供电负极输入电压的大小，确定烧录器传输的数据；或
    所述集成电路芯片通过检测所述烧录器控制的供电正极或供电负极输入电压上叠加的电信号的频率，确定烧录器传输的数据。
  7. 如权利要求6所述的数据写入方法，其特征在于，所述集成电路芯片通过检测所述烧录器控制的供电正极或供电负极输入电压的大小，确定烧录器传输的数据，包括：
    所述集成电路芯片通过检测所述烧录器控制的供电正极或供电负极输入电压的大小为VCC还是0以确定烧录器传输的二进制数据。
  8. 如权利要求5-7任一项所述的数据写入方法，其特征在于，所述集成电路芯片通过检测所述烧录器控制的供电正极或供电负极输入电压的电性参数，确定烧录器传输的数据，还包括：
    在确定成功接收所述烧录器传输的当前帧数据后，反馈帧数据接收成功信号至烧录器以指示所述烧录器对集成电路芯片进行下一帧数据写入。
  9. 一种集成电路芯片的数据写入系统，其特征在于，所述数据写入系统包括烧录器和集成电路芯片，所述烧录器包括主控和第一信号转换电路，所述主控通过所述第一信号转换电路电连接所述集成电路芯片的供电正极和供电负极；
    所述主控，用于
    发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式；
    在所述集成电路芯片进入数据写入模式后，通过所述第一信号转换电路控制所述集成电路芯片供电正极或供电负极输入电压的电性参数对集成电路芯片进行数据写入。
  10. 如权利要求9所述的数据写入系统，其特征在于，还包括第二信号转换电路，所述第二信号转换电路外接或者内置于所述集成电路芯片，所述第二信号转换电路与所述第一信号转换电路电连接，所述集成电路芯片通过所述第二信号转换电路检测所述烧录器控制的供电正极或供电负极输入电压的电性参数，确定所述烧录器传输的数据。
  11. 如权利要求10所述的数据写入系统，其特征在于，还包括隔离电路，所述隔离电路与所述集成电路芯片电连接，所述集成电路芯片通过所述隔离电路隔离对所述集成电路芯片和烧录器之间的数据传输造成干扰的信号。
  12. 如权利要求9所述的数据写入系统，其特征在于，所述烧录器还包括电源输入电路，所述电源输入电路分别与所述主控和所述第一信号转换电路电连接，所述电源输入电路用于外接电源，对所述主控和所述第一信号转换电路进行供电。
  13. 如权利要求9至12任一项所述的数据写入系统，其特征在于，当通过所述第一信号转换电路控制所述集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行数据写入时，所述主控包括第一输入输出端口、第二输入输出端口和第三输入输出端口；所述第一信号转换电路包括烧录输出接口，PMOS管Q1和Q2，电阻R1、R2、R3和R4；第一输入输出端口与电阻R2的一端电连接，电阻R2的另一端与烧录输出接口的第二引脚电连接，烧录输出接口的第一引脚接地；第二输入输出端口与电阻R1的一端和PMOS管Q1的栅极电连接，电阻R1的另一端和PMOS管Q1的源极都连接电源VCC，PMOS管Q1的漏极与烧录输出接口的第二引脚电连接；第三输入输出端口与电阻R3的一端和PMOS管Q2的栅极电连接，电阻R3的另一端、PMOS管Q2的源极都与烧录输出接口的第二引脚电连接，PMOS管Q2的漏极与电阻R4的一端电连接，电阻R4的另一端接地。
  14. 如权利要求11所述的数据写入系统，其特征在于，当通过所述第一信号转换电路控制所述集成电路芯片供电正极输入电压的电性参数对集成电路芯片进行数据写入时，所述集成电路芯片包括输入输出接口、VDD引脚和GND引脚，GND引脚接地；所述第二信号转换电路包括烧录输入接口和电阻R5；所述隔离电路包括二极管D1和电容C1；烧录输入接口的第二引脚与电阻R5的一端和二极管D1的正极电连接，电阻R5的另一端与集成电路芯片的输入输出接口电连接，二极管D1的负极电连接于集成电路芯片的VDD引脚和电容C1的正极，电容C1的负极接地。
  15. 如权利要求9至12任一项所述的数据写入系统，其特征在于，当通过所述第一信号转换电路控制所述集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行数据写入时，所述主控包括输入输出端口GPIO4、输入输出端口GPIO5和输入输出端口GPIO6；所述第一信号转换电路包括烧录输出接口，PMOS管Q3和NMOS管Q4，电阻R10、R11、R12；输入输出端口GPIO4与电阻R11的一端电连接，电阻R11的另一端与烧录输出接口的第一引脚电连接；输入输出端口GPIO5分别与电阻R10的一端、PMOS管Q3的栅极电连接，电阻R10的另一端和PMOS管Q3的源极都连接电源VCC，PMOS管Q3的漏极与烧录输出接口的第一引脚电连接；输入输出端口GPIO6分别与电阻R12的一端、NMOS管Q4的栅极电连接，电阻R12的另一端、NMOS管Q4的源极都接地， NMOS管Q4的漏极与烧录输出接口的第一引脚电连接。
  16. 如权利要求11所述的数据写入系统，其特征在于，当通过所述第一信号转换电路控制所述集成电路芯片供电负极输入电压的电性参数对集成电路芯片进行数据写入时，所述集成电路芯片包括输入输出接口、VDD引脚和GND引脚；所述第二信号转换电路包括烧录输入接口和电阻R14；所述隔离电路包括二极管D2和电容C2；烧录输入接口的第一引脚与电阻R14的一端电连接，电阻R14的另一端与集成电路芯片的输入输出接口电连接，烧录输入接口的第一引脚还与二极管D2的负极电连接，二极管D2的正极电连接于集成电路芯片的GND引脚，集成电路芯片的GND引脚接地，烧录输入接口的第二引脚分别电连接于集成电路芯片VDD引脚、电容C2的正极，电容C2的负极接地。
  17. 一种集成电路芯片的数据写入装置，配置于烧录器，其特征在于，所述集成电路芯片通过供电正极和供电负极与所述烧录器电连接；所述数据写入装置包括：
    发送单元，用于发送数据写入指令至所述集成电路芯片；所述数据写入指令用于指示所述集成电路芯片接收所述数据写入指令后，进入数据写入模式；
    控制执行单元，用于在所述集成电路芯片进入数据写入模式后，通过控制所述集成电路芯片供电正极或供电负极输入电压的电性参数对集成电路芯片进行数据写入。
  18. 一种集成电路芯片的数据写入装置，配置于集成电路芯片，其特征在于，所述集成电路芯片通过供电正极和供电负极与烧录器电连接；所述数据写入装置包括：
    接收单元，用于接收烧录器发送的数据写入指令，进入数据写入模式；
    检测执行单元，用于通过检测所述烧录器控制的供电正极或供电负极输入电压的电性参数，确定烧录器传输的数据；
    启用单元，用于启用所述烧录器传输的数据。
  19. 一种集成电路芯片的数据写入设备，包括存储器、处理器以及存储在所述存储器中并可在所述处理器上运行的计算机可读指令，其特征在于，所述处理器执行所述计算机可读指令时实现如权利要求1至8任一项所述方法的步骤。
  20. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机可读指令，其特征在于，所述计算机可读指令被处理器执行时实现如权利要求1至8任一项所述方法的步骤。
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