WO2019205487A1 - 阵列基板及芯片邦定方法 - Google Patents

阵列基板及芯片邦定方法 Download PDF

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Publication number
WO2019205487A1
WO2019205487A1 PCT/CN2018/107974 CN2018107974W WO2019205487A1 WO 2019205487 A1 WO2019205487 A1 WO 2019205487A1 CN 2018107974 W CN2018107974 W CN 2018107974W WO 2019205487 A1 WO2019205487 A1 WO 2019205487A1
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Prior art keywords
terminal group
chip
output terminal
type
bonding
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Ceased
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PCT/CN2018/107974
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English (en)
French (fr)
Inventor
国春朋
王英琪
黄俊宏
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US16/308,484 priority Critical patent/US11101230B2/en
Publication of WO2019205487A1 publication Critical patent/WO2019205487A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/607—Located on parts of packages, e.g. on encapsulations or on package substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07221—Aligning
    • H10W72/07223—Active alignment, e.g. using optical alignment using marks or sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07321—Aligning
    • H10W72/07323—Active alignment, e.g. using optical alignment using marks or sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07332—Compression bonding, e.g. thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/074—Connecting or disconnecting of anisotropic conductive adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/261—Functions other than electrical connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a chip bonding method.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • Chip on Glass Mura (COG Mura) is currently an important quality problem for LCD panels.
  • the existing chip bonding process includes: attaching an anisotropic conductive film (ACF) to the surface of the array substrate, and then placing the chip on a predetermined bonding position on the array substrate, and finally The chip is pressed by a thermal head, and the chip pins are electrically connected to the bonding terminals on the array substrate through the conductive particles contained in the ACF, and the ACF is converted into a solid state by the gel, and the chip is fixed on the array substrate.
  • ACF anisotropic conductive film
  • the reason why the chip is poorly pressed is that when the ACF is cured at a high temperature, the high temperature causes the chip and the thin film transistor to also expand, thereby causing the cell gap near the chip portion to be uneven, which appears during display. Contrast difference.
  • the typical chip is as shown A chip that is not integrated with a random access memory (RAM) and a chip that integrates a random access RAM, as shown in FIG. 1, the existing chip that is not integrated with the random access memory includes: a first input pin group 101, and the first An input pin group 102 of an input pin group 101 and a first alignment mark 103 located on both sides of the first input pin group 101, as shown in FIG.
  • RAM random access memory
  • FIG. 1 the existing chip that is not integrated with the random access memory
  • the chip includes: a second input pin set 201, a second output pin set 202 spaced apart from the second input pin set 201, and a second alignment on both sides of the second input pin set 201
  • the mark 203, the chip shown in FIG. 1 and FIG. 2 is different in that the distance between the first input pin group 101 and the first output pin group 102 is smaller than the second input pin group 201 and the second output.
  • the distance between the pin groups 202, in order to make the array substrate the same Compatible with the above two kinds of chips, as shown in FIG.
  • the prior art provides an array substrate, comprising: a display area 300, and a bonding area 400 located at a periphery of the display area 300, the bonding area
  • the input terminal group 401 and the output terminal group 402 are disposed in the 400, and the output terminal group 402 is located on a side of the input terminal group 401 away from the display area 300, wherein the length of each terminal in the input terminal group 401 is compared
  • the common terminal is longer and the chip timing is performed.
  • the chip is a chip without integrated random access memory
  • the first output pin group 102 is bonded to the output terminal group 402. Simultaneously bonding the first input pin group 101 to the upper half of the input terminal group 401; as shown in FIG.
  • the second output is When the pin group 202 is contracted with the output terminal group 402, the second input pin group 201 is bonded to the lower half of the input terminal group 401, so that the array substrate can be simultaneously compatible with the two Kind of chip.
  • the distance from the edge of the chip to the edge of the array substrate is known to be one of the main factors affecting the poor bonding of the chip.
  • the distance from the edge of the array substrate after the two chips are bonded together is also very close to the edge of the array substrate, resulting in a high probability of chip failure.
  • Another object of the present invention is to provide a chip bonding method capable of reducing chip bonding failure and ensuring display quality.
  • the present invention provides an array substrate comprising: a display area, and a bonding area located at a periphery of the display area, wherein the bonding area is provided with an input terminal group, a first output terminal group, and a second Output terminal group;
  • the first output terminal group is located at a side of the input terminal group away from the display area, and the second output terminal group is located between the first output terminal group and the input terminal group;
  • the chip timing is selected according to the type of the chip, and the first output terminal group or the second output terminal group is matched with the input terminal group to perform chip bonding.
  • the bonding area is further provided with a first alignment mark corresponding to the first output terminal group and a second alignment mark corresponding to the second output terminal group.
  • the bonding region is further provided with a first output lead connecting the first output terminal group and the display area, and a second output lead connecting the second output terminal group and the display area.
  • the type of the chip is two, which are a first type chip and a second type chip, respectively, the size of the first type chip is larger than the chip of the second type; the first type chip passes the first output The terminal group cooperates with the input terminal group to perform bonding, and the second type chip cooperates with the input terminal group through the second output terminal group to perform bonding.
  • the first type of chip is a chip integrated with a random access memory
  • the second type of chip is not integrated with a random access memory chip.
  • the invention also provides a chip bonding method, comprising the following steps:
  • Step S1 providing an array substrate, the array substrate comprising: a display area, and a bonding area located at a periphery of the display area, wherein the bonding area is provided with an input terminal group, a first output terminal group, and a second output Terminal group
  • the first output terminal group is located at a side of the input terminal group away from the display area, and the second output terminal group is located between the first output terminal group and the input terminal group;
  • Step S2 providing a chip, determining a type of the chip, and selecting the first output terminal group or the second output terminal group to cooperate with the input terminal group to perform chip bonding according to a type of the chip.
  • a first alignment mark corresponding to the first output terminal group, a second alignment mark corresponding to the second output terminal group, and the first output terminal group are connected to the bonding area.
  • the chip is aligned with the first output terminal group or the second alignment mark is caused by the first alignment mark to make the chip and the second The output terminal group is aligned.
  • the type of the chip is two, respectively a first type chip and a second type chip, and the size of the first type chip is larger than the second type of chip;
  • step S2 when the chip is a first type of chip, chip bonding is performed by the first output terminal group and the input terminal group, and when the chip is a second type chip, The second output terminal group cooperates with the input terminal group to perform chip bonding.
  • the first type of chip is a chip integrated with a random access memory
  • the second type of chip is not integrated with a random access memory chip.
  • the present invention provides an array substrate, the array substrate comprising: a display area, and a bonding area located at a periphery of the display area, wherein the bonding area is provided with an input terminal group and a first output a terminal group and a second output terminal group; the first output terminal group is located at a side of the input terminal group away from the display area, and the second output terminal group is located at the first output terminal group and the input Between the terminal groups; chip timing, selecting the first output terminal group or the second output terminal group and the input terminal group according to the type of the chip to perform chip bonding, and simultaneously setting the first output terminal group and the second
  • the output terminal group can increase the distance between the chip bonded to the second output terminal group and the edge of the array substrate, thereby reducing the probability of occurrence of poor chip pressing and ensuring display quality.
  • the invention also provides a chip bonding method, which can reduce chip pressing failure and ensure display quality.
  • FIG. 1 is a schematic structural view of a chip not integrated with a random access memory
  • FIG. 2 is a schematic structural diagram of a chip integrated with a random access memory
  • FIG. 3 is a schematic view of a conventional array substrate
  • FIG. 4 is a schematic diagram of bonding a chip that is not integrated with a random access memory on an existing array substrate;
  • FIG. 5 is a schematic diagram of a chip integrated with a random access memory on an existing array substrate
  • Figure 6 is a schematic view of an array substrate of the present invention.
  • FIG. 7 is a schematic diagram of a chip that is not integrated with a random access memory on the array substrate of the present invention.
  • FIG. 8 is a schematic diagram of a chip integrated with a random access memory on a conventional array substrate
  • FIG. 9 is a flow chart of a chip bonding method of the present invention.
  • the present invention provides an array substrate, including: a display area 10, and a bonding area 20 located at a periphery of the display area 10.
  • the bonding area 20 is provided with an input terminal group 21 and a first output. Terminal group 22 and second output terminal group 23;
  • the first output terminal group 22 is located at a side of the input terminal group 21 away from the display area 10, and the second output terminal group 23 is located at the first output terminal group 22 and the input terminal group 21 That is, the first output terminal group 22, the second output terminal group 23, and the input terminal group 21 are arranged in order from the top to the bottom, and the distance from the edge of the array substrate is sequentially increased.
  • the chip timing is selected according to the type of the chip, and the first output terminal group 22 or the second output terminal group 23 is matched with the input terminal group 21 for chip bonding.
  • the input terminal group 21 includes a plurality of input terminals 211 arranged in a row from left to right, and the first output terminal group 22 A plurality of first output terminals 221 are sequentially arranged in two rows from left to right, and the second output terminal group 23 includes a plurality of second output terminals 231 which are sequentially arranged in two rows from left to right.
  • the number and arrangement of the plurality of first output terminals 221 and the plurality of second output terminals 231 are the same.
  • the bonding area 20 is further provided with a first output lead 42 connecting the first output terminal group 22 and the display area 10, and Connecting the second output terminal group 23 and the second output lead 43 of the display area 10, further, the number of the first output leads 42 is equal to the number of the first output terminals 221, each first The output terminal 221 is electrically connected to the display area 10 through a first output lead 42.
  • the number of the second output leads 43 is equal to the number of the second output terminals 231, and each of the second output terminals 231 corresponds to The display area 10 is electrically connected through a second output lead 43.
  • the input terminal 211, the first output terminal 221, and the second output terminal 231 are formed on the same metal layer, and the first output lead 42 and the second output lead 43 are formed on the input terminal 211 and the first output.
  • the bonding area 20 is further provided with a first alignment mark 31 corresponding to the first output terminal group 22 and a second alignment mark 32 corresponding to the second output terminal group 23, further
  • the first aligning mark 31 and the second aligning mark 32 are both in the shape of a cross, and the two first aligning marks 31 are respectively located in the first output terminal group.
  • the two second alignment marks 32 are located on the left and right sides of the second output terminal group 23, respectively.
  • the type of the chip is two, respectively a first type chip and a second type chip, and the size of the first type chip is larger than the second type of chip;
  • the first type of chip cooperates with the input terminal group 21 through the first output terminal group 22, and the second type chip cooperates with the input terminal group 21 through the second output terminal group 23 Make a bond.
  • the first type of chip is a chip integrated with a random access memory as shown in FIG. 2
  • the second type of chip is a chip not integrated with a random access memory as shown in FIG.
  • the specific bonding process includes: first determining that the chip is a first type chip or a second type chip. Referring to FIG. 7 , when the chip is a first type of chip, corresponding to the input terminal of the array substrate The regions of the group 21 and the first output terminal group 22 are attached with ACF glue, and then the first alignment mark 31 is aligned with the chip, so that the output pins on the chip are aligned with the first output terminal group 22.
  • the input pin is aligned with the input terminal group 21, and finally the chip is pressed by a thermal indenter, and the chip pins are electrically connected to the bonding terminals on the array substrate through the conductive particles contained in the ACF, and at the same time
  • the ACF is converted into a solid state by a gel, and the chip is fixed on the array substrate to realize bonding of the chip.
  • the chip is a second type of chip
  • the corresponding input terminal of the array substrate is The regions of the group 21 and the second output terminal group 23 are attached with ACF glue, and then the second alignment mark 32 is aligned with the chip, so that the output pins on the chip are aligned with the second output terminal group 23.
  • the chip bonded to the second output terminal group can be increased in the bonding of the second type chip, that is, the chip not integrated with the random access memory.
  • the distance from the edge of the array substrate reduces the probability of occurrence of poor chip press.
  • a chip bonding method is characterized in that the method includes the following steps:
  • an array substrate is provided.
  • the array substrate includes: a display area 10, and a bonding area 20 located at a periphery of the display area 10.
  • the bonding area 20 is provided with an input terminal group 21 and a first output terminal.
  • Group 22 and second output terminal group 23 are provided.
  • the first output terminal group 22 is located at a side of the input terminal group 21 away from the display area 10, and the second output terminal group 23 is located at the first output terminal group 22 and the input terminal group 21 between. That is, the first output terminal group 22, the second output terminal group 23, and the input terminal group 21 are arranged in order from the top to the bottom, and the distance from the edge of the array substrate is sequentially increased.
  • the input terminal group 21 includes a plurality of input terminals 211 arranged in a row from left to right, and the first output terminal group 22 A plurality of first output terminals 221 are sequentially arranged in two rows from left to right, and the second output terminal group 23 includes a plurality of second output terminals 231 which are sequentially arranged in two rows from left to right.
  • the number and arrangement of the plurality of first output terminals 221 and the plurality of second output terminals 231 are the same.
  • the bonding area 20 is further provided with a first output lead 42 connecting the first output terminal group 22 and the display area 10, and Connecting the second output terminal group 23 and the second output lead 43 of the display area 10, further, the number of the first output leads 42 is equal to the number of the first output terminals 221, each first The output terminal 221 is electrically connected to the display area 10 through a first output lead 42.
  • the number of the second output leads 43 is equal to the number of the second output terminals 231, and each of the second output terminals 231 corresponds to The display area 10 is electrically connected through a second output lead 43.
  • the input terminal 211, the first output terminal 221, and the second output terminal 231 are formed on the same metal layer, and the first output lead 42 and the second output lead 43 are formed on the input terminal 211 and the first output.
  • the bonding area 20 is further provided with a first alignment mark 31 corresponding to the first output terminal group 22 and a second alignment mark 32 corresponding to the second output terminal group 23, further
  • the first aligning mark 31 and the second aligning mark 32 are both in the shape of a cross, and the two first aligning marks 31 are respectively located in the first output terminal group.
  • the two second alignment marks 32 are located on the left and right sides of the second output terminal group 23, respectively.
  • the type of the chip is two, respectively a first type chip and a second type chip, and the size of the first type chip is larger than the second type of chip;
  • the first type of chip cooperates with the input terminal group 21 through the first output terminal group 22, and the second type chip cooperates with the input terminal group 21 through the second output terminal group 23 Make a bond.
  • the first type of chip is a chip integrated with a random access memory as shown in FIG. 2
  • the second type of chip is a chip not integrated with a random access memory as shown in FIG.
  • Step S2 providing a chip, determining the type of the chip, and selecting the first output terminal group 22 or the second output terminal group 23 to cooperate with the input terminal group 21 to perform chip bonding according to the type of the chip.
  • an ACF glue is attached to an area of the array substrate corresponding to the input terminal group 21 and the first output terminal group 22, and then passes through.
  • the first alignment mark 31 is aligned with the chip such that the output pin on the chip is aligned with the first output terminal group 22, the input pin is aligned with the input terminal group 21, and finally the thermal head is passed. Pressing the chip, electrically connecting the chip pins to the bonding terminals on the array substrate through the conductive particles contained in the ACF, and simultaneously converting the ACF from the gel to the solid state, and fixing the chip on the array substrate to realize the chip Referring to FIG.
  • an ACF glue is attached to an area of the array substrate corresponding to the input terminal group 21 and the second output terminal group 23, and then passes through.
  • the second alignment mark 32 is aligned with the chip such that the output pin on the chip is aligned with the second output terminal group 23, the input pin is aligned with the input terminal group 21, and finally passes through the thermal head Pressing the chip and passing the conductive particles contained in the ACF
  • the chip pin is electrically connected to the bonding terminal on the array substrate, and the ACF is converted into a solid state by a gel, and the chip is fixed on the array substrate to realize bonding of the chip.
  • the chip bonded to the second output terminal group can be increased in the bonding of the second type chip, that is, the chip not integrated with the random access memory.
  • the distance from the edge of the array substrate reduces the probability of occurrence of poor chip press.
  • the present invention provides an array substrate, the array substrate includes: a display area, and a bonding area located at a periphery of the display area, wherein the bonding area is provided with an input terminal group and a first output terminal And a second output terminal group; the first output terminal group is located at a side of the input terminal group away from the display area, and the second output terminal group is located at the first output terminal group and the input terminal Between the groups; chip timing, according to the type of the chip, the first output terminal group or the second output terminal group is matched with the input terminal group for chip bonding, and the first output terminal group and the second output are simultaneously set.
  • the terminal group can increase the distance between the chip on the second output terminal group and the edge of the array substrate, thereby reducing the probability of occurrence of poor chip pressing and ensuring display quality.
  • the invention also provides a chip bonding method, which can reduce chip pressing failure and ensure display quality.

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Abstract

本发明提供一种阵列基板及芯片邦定方法。所述阵列基板包括：显示区、以及位于所述显示区外围的邦定区，所述邦定区中设有输入端子组、第一输出端子组及第二输出端子组；所述第一输出端子组位于所述输入端子组远离所述显示区的一侧，所述第二输出端子组位于所述第一输出端子组和所述输入端子组之间；芯片邦定时，根据芯片的类型选择所述第一输出端子组或第二输出端子组与所述输入端子组配合进行芯片邦定，通过同时设置第一输出端子组和第二输出端子组，能够增大邦定在第二输出端子组上的芯片与阵列基板的边缘的距离，降低芯片压合不良出现的机率，保证显示品质。

Description

阵列基板及芯片邦定方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及芯片邦定方法。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
芯片压合不良(Chip on Glass Mura，COG Mura)是目前困扰液晶显示面板重要品质问题。现有的芯片压合过程包括：将阵列基板的表面贴附异方性导电胶(Anisotropic Conductive Film，ACF)，接着将芯片置于所述阵列基板上预设的邦定(Bonding)位置，最后通过热压头压合所述芯片，通过ACF内含的导电粒子将芯片引脚与阵列基板上的邦定端子电性连接，同时使ACF由胶状转化为固态，将芯片固定在阵列基板上。芯片压合不良产生的原因在于，在高温压合使得ACF固化时，高温还会使得芯片和薄膜晶体管也发生膨胀，进而造成靠近芯片部分的液晶盒厚(cell gap)不均匀，在显示时出现对比度差异。
随着显示的技术发展，产品的类型越来越多，芯片的种类也越来越多，在阵列基板的设计过程中常常要兼顾多种不同芯片的邦定，典型的芯片为如图所示的未集成有随机存储器(RAM)的芯片和集成有随机存储器RAM的芯片，如图1所示，现有的未集成有随机存储器的芯片包括：第一输入引脚组101、与所述第一输入引脚组101间隔设置的输出引脚组102以及与位于所述第一输入引脚组101两侧的第一对位标记103，如图2所示，现有的集成有随机存储器的芯片包括：第二输入引脚组201、与所述第二输入引脚组201间隔设置的第二输出引脚组202以及与位于所述第二输入引脚组201两侧的第二对位标记203，图1和图2所示的芯片的不同在于所述第一输入引脚组101和第一输出引脚组102之间的距离小于所述第二输入引脚组201和第二输出引脚组202之间的距离，为了使得阵列基板能够同时兼容上述的两种的芯片，如图3所示，现有的技术提供了一种阵列基板，包括：显示区300、以及位于所述显示区300外围的邦定区400，所述邦定区400中设有输入端子组401、输出端子组402，所述输出端子组402位于所 述输入端子组401远离所述显示区300的一侧，其中输入端子组401中的各个端子的长度相比普通的端子更长，进行芯片邦定时，如图4所示，若所述芯片为未集成有随机存储器的芯片，则将所述第一输出引脚组102与所述输出端子组402贴合同时将所述第一输入引脚组101与所述输入端子组401的上半部分贴合；如图5所示，若所述芯片为集成有随机存储器的芯片，则将所述第二输出引脚组202与所述输出端子组402贴合同时将所述第二输入引脚组201与所述输入端子组401的下半部分贴合，从而使得所述阵列基板能够同时兼容上述的两种的芯片。
目前已知芯片边缘到阵列基板边缘的距离是目前已知的影响芯片压合不良的主要原因之一，在图3所示的阵列基板中，两种芯片贴合后，距离阵列基板边缘的距离是相同的，尺寸较小且应用较广的未集成随机存储器的芯片也十分贴近阵列基板的边缘，导致芯片压合不良的出现的机率始终较高。
发明内容
本发明的目的在于提供一种阵列基板，能够减少芯片压合不良，保证显示品质。
本发明的目的还在于提供一种芯片邦定方法，能够减少芯片压合不良，保证显示品质。
为实现上述目的，本发明提供一种阵列基板，包括：显示区、以及位于所述显示区外围的邦定区，所述邦定区中设有输入端子组、第一输出端子组及第二输出端子组；
所述第一输出端子组位于所述输入端子组远离所述显示区的一侧，所述第二输出端子组位于所述第一输出端子组和所述输入端子组之间；
芯片邦定时，根据芯片的类型选择所述第一输出端子组或第二输出端子组与所述输入端子组配合进行芯片邦定。
所述邦定区中还设有对应所述第一输出端子组设置的第一对位标记以及对应所述第二输出端子组设置的第二对位标记。
所述邦定区中还设有连接所述第一输出端子组与所述显示区的第一输出引线以及连接所述第二输出端子组与所述显示区的第二输出引线。
所述芯片的类型为两种，分别为第一类型芯片和第二类型芯片，所述第一类型芯片的尺寸大于所述第二类型的芯片；所述第一类型芯片通过所述第一输出端子组与所述输入端子组配合进行邦定，所述第二类型芯片通过所述第二输出端子组与所述输入端子组配合进行邦定。
所述第一类型芯片为集成有随机存储器的芯片，所述第二类型芯片未集成有随机存储器的芯片。
本发明还提供一种芯片邦定方法，包括如下步骤：
步骤S1、提供一阵列基板，所述阵列基板包括：显示区、以及位于所述显示区外围的邦定区，所述邦定区中设有输入端子组、第一输出端子组及第二输出端子组；
所述第一输出端子组位于所述输入端子组远离所述显示区的一侧，所述第二输出端子组位于所述第一输出端子组和所述输入端子组之间；
步骤S2、提供一芯片，确定所述芯片的类型，并根据芯片的类型选择所述第一输出端子组或第二输出端子组与所述输入端子组配合进行芯片邦定。
所述邦定区中还设有对应所述第一输出端子组设置的第一对位标记、对应所述第二输出端子组设置的第二对位标记、连接所述第一输出端子组与所述显示区的第一输出引线以及连接所述第二输出端子组与所述显示区的第二输出引线。
所述步骤S2中进行芯片邦定之前，先通过第一对位标记使得所述芯片与所述第一输出端子组对位或通过所述第二对位标记使得所述芯片与所述第二输出端子组对位。
所述芯片的类型为两种，分别为第一类型芯片和第二类型芯片，所述第一类型芯片的尺寸大于所述第二类型的芯片；
所述步骤S2中当所述芯片为第一类型芯片时，通过所述第一输出端子组与所述输入端子组配合进行芯片邦定，当所述芯片为第二类型芯片时，通过所述第二输出端子组与所述输入端子组配合进行芯片邦定。
所述第一类型芯片为集成有随机存储器的芯片，所述第二类型芯片未集成有随机存储器的芯片。
本发明的有益效果：本发明提供一种阵列基板，所述阵列基板包括：显示区、以及位于所述显示区外围的邦定区，所述邦定区中设有输入端子组、第一输出端子组及第二输出端子组；所述第一输出端子组位于所述输入端子组远离所述显示区的一侧，所述第二输出端子组位于所述第一输出端子组和所述输入端子组之间；芯片邦定时，根据芯片的类型选择所述第一输出端子组或第二输出端子组与所述输入端子组配合进行芯片邦定，通过同时设置第一输出端子组和第二输出端子组，能够增大邦定在第二输出端子组上的芯片与阵列基板的边缘的距离，降低芯片压合不良出现的机率，保证显示品质。本发明还提供一种芯片邦定方法，能够减少芯片压合不良， 保证显示品质。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为未集成有随机存储器的芯片的结构示意图；
图2为集成有随机存储器的芯片的结构示意图；
图3为现有的阵列基板的示意图；
图4为在现有的阵列基板上邦定未集成有随机存储器的芯片时的示意图；
图5为在现有的阵列基板上邦定集成有随机存储器的芯片时的示意图；
图6为本发明的阵列基板的示意图；
图7为在本发明的阵列基板上邦定未集成有随机存储器的芯片时的示意图；
图8为在现有的阵列基板上邦定集成有随机存储器的芯片时的示意图；
图9为本发明的芯片邦定方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图6，本发明提供一种阵列基板，包括：显示区10、以及位于所述显示区10外围的邦定区20，所述邦定区20中设有输入端子组21、第一输出端子组22及第二输出端子组23；
所述第一输出端子组22位于所述输入端子组21远离所述显示区10的一侧，所述第二输出端子组23位于所述第一输出端子组22和所述输入端子组21之间；也即所述第一输出端子组22、第二输出端子组23及输入端子组21从上往下依次排列，距离所述阵列基板的边缘的距离依次增大。
芯片邦定时，根据芯片的类型选择所述第一输出端子组22或第二输出端子组23与所述输入端子组21配合进行芯片邦定。
具体地，如图6所示，在本发明的优选实施例中，所述输入端子组21包括从左到右依次隔间排列成一行的多个输入端子211，所述第一输出端子 组22包括从左到右依次间隔排列成两行的多个第一输出端子221，所述第二输出端子组23包括从左到右依次间隔排列成两行的多个第二输出端子231，所述多个第一输出端子221和多个第二输出端子231的数量及排列方式均相同。
具体地，为了使得芯片邦定后能够与所述显示区10通讯，所述邦定区20中还设有连接所述第一输出端子组22与所述显示区10的第一输出引线42以及连接所述第二输出端子组23与所述显示区10的第二输出引线43，进一步地，所述第一输出引线42的数量与所述第一输出端子221的数量相等，每一个第一输出端子221对应通过一条第一输出引线42与所述显示区10电性连接，所述第二输出引线43的数量与所述第二输出端子231的数量相等，每一个第二输出端子231对应通过一条第二输出引线43与所述显示区10电性连接。
需要说明的是，输入端子211、第一输出端子221及第二输出端子231形成于同一金属层，所述第一输出引线42及第二输出引线43形成于所述输入端子211、第一输出端子221及第二输出端子231所在金属层的下方的另一金属层，所述第一输出引线42及第二输出引线43通过分别通过过孔与所述第一输出端子221及第二输出端子231电性连接。
具体地，所述邦定区20中还设有对应所述第一输出端子组22设置的第一对位标记31以及对应所述第二输出端子组23设置的第二对位标记32，进一步地，所述第一对位标记31和第二对位标记32的数量均为两个，其形状均为十字形，所述两个第一对位标记31分别位于所述第一输出端子组22的左右两侧，所述两个第二对位标记32分别位于所述第二输出端子组23的左右两侧。
具体地，在本发明的优选实施例中，所述芯片的类型为两种，分别为第一类型芯片和第二类型芯片，所述第一类型芯片的尺寸大于所述第二类型的芯片；所述第一类型芯片通过所述第一输出端子组22与所述输入端子组21配合进行邦定，所述第二类型芯片通过所述第二输出端子组23与所述输入端子组21配合进行邦定。
进一步地，所述第一类型芯片为如图2所示的集成有随机存储器的芯片，所述第二类型芯片为如图1所示的未集成有随机存储器的芯片。
具体邦定过程包括：首先确定所述芯片为第一类型芯片或第二类型芯片，请参阅图7，当所述芯片为第一类型芯片时，则在所述阵列基板的对应所述输入端子组21及第一输出端子组22的区域贴附ACF胶，接着将通过第一对位标记31与所述芯片对位，使得芯片上的输出引脚与所述第一输出 端子组22对位，输入引脚与所述输入端子组21对位，最后通过热压头压合所述芯片，通过ACF内含的导电粒子将芯片引脚与阵列基板上的邦定端子电性连接，同时使ACF由胶状转化为固态，将芯片固定在阵列基板上，实现芯片的邦定；请参阅图8，当所述芯片为第二类型芯片时，则在所述阵列基板的对应所述输入端子组21及第二输出端子组23的区域贴附ACF胶，接着将通过第二对位标记32与所述芯片对位，使得芯片上的输出引脚与所述第二输出端子组23对位，输入引脚与所述输入端子组21对位，最后通过热压头压合所述芯片，通过ACF内含的导电粒子将芯片引脚与阵列基板上的邦定端子电性连接，同时使ACF由胶状转化为固态，将芯片固定在阵列基板上，实现芯片的邦定。
需要说明的是，通过同时设置第一输出端子组和第二输出端子组，在邦定第二类型芯片即未集成有随机存储器的芯片，能够增大邦定在第二输出端子组上的芯片与阵列基板的边缘的距离，降低芯片压合不良出现的机率。
请参阅图9，一种芯片邦定方法，其特征在于，包括如下步骤：
步骤S1、提供一阵列基板，所述阵列基板包括：显示区10、以及位于所述显示区10外围的邦定区20，所述邦定区20中设有输入端子组21、第一输出端子组22及第二输出端子组23
所述第一输出端子组22位于所述输入端子组21远离所述显示区10的一侧，所述第二输出端子组23位于所述第一输出端子组22和所述输入端子组21之间。也即所述第一输出端子组22、第二输出端子组23及输入端子组21从上往下依次排列，距离所述阵列基板的边缘的距离依次增大。
具体地，如图6所示，在本发明的优选实施例中，所述输入端子组21包括从左到右依次隔间排列成一行的多个输入端子211，所述第一输出端子组22包括从左到右依次间隔排列成两行的多个第一输出端子221，所述第二输出端子组23包括从左到右依次间隔排列成两行的多个第二输出端子231，所述多个第一输出端子221和多个第二输出端子231的数量及排列方式均相同。
具体地，为了使得芯片邦定后能够与所述显示区10通讯，所述邦定区20中还设有连接所述第一输出端子组22与所述显示区10的第一输出引线42以及连接所述第二输出端子组23与所述显示区10的第二输出引线43，进一步地，所述第一输出引线42的数量与所述第一输出端子221的数量相等，每一个第一输出端子221对应通过一条第一输出引线42与所述显示区10电性连接，所述第二输出引线43的数量与所述第二输出端子231的数量 相等，每一个第二输出端子231对应通过一条第二输出引线43与所述显示区10电性连接。
需要说明的是，输入端子211、第一输出端子221及第二输出端子231形成于同一金属层，所述第一输出引线42及第二输出引线43形成于所述输入端子211、第一输出端子221及第二输出端子231所在金属层的下方的另一金属层，所述第一输出引线42及第二输出引线43通过分别通过过孔与所述第一输出端子221及第二输出端子231电性连接。
具体地，所述邦定区20中还设有对应所述第一输出端子组22设置的第一对位标记31以及对应所述第二输出端子组23设置的第二对位标记32，进一步地，所述第一对位标记31和第二对位标记32的数量均为两个，其形状均为十字形，所述两个第一对位标记31分别位于所述第一输出端子组22的左右两侧，所述两个第二对位标记32分别位于所述第二输出端子组23的左右两侧。
具体地，在本发明的优选实施例中，所述芯片的类型为两种，分别为第一类型芯片和第二类型芯片，所述第一类型芯片的尺寸大于所述第二类型的芯片；所述第一类型芯片通过所述第一输出端子组22与所述输入端子组21配合进行邦定，所述第二类型芯片通过所述第二输出端子组23与所述输入端子组21配合进行邦定。
进一步地，所述第一类型芯片为如图2所示的集成有随机存储器的芯片，所述第二类型芯片为如图1所示的未集成有随机存储器的芯片。
步骤S2、提供一芯片，确定所述芯片的类型，并根据芯片的类型选择所述第一输出端子组22或第二输出端子组23与所述输入端子组21配合进行芯片邦定。
具体地，请参阅图7，当所述芯片为第一类型芯片时，则在所述阵列基板的对应所述输入端子组21及第一输出端子组22的区域贴附ACF胶，接着将通过第一对位标记31与所述芯片对位，使得芯片上的输出引脚与所述第一输出端子组22对位，输入引脚与所述输入端子组21对位，最后通过热压头压合所述芯片，通过ACF内含的导电粒子将芯片引脚与阵列基板上的邦定端子电性连接，同时使ACF由胶状转化为固态，将芯片固定在阵列基板上，实现芯片的邦定；请参阅图8，当所述芯片为第二类型芯片时，则在所述阵列基板的对应所述输入端子组21及第二输出端子组23的区域贴附ACF胶，接着将通过第二对位标记32与所述芯片对位，使得芯片上的输出引脚与所述第二输出端子组23对位，输入引脚与所述输入端子组21对位，最后通过热压头压合所述芯片，通过ACF内含的导电粒子将芯片引 脚与阵列基板上的邦定端子电性连接，同时使ACF由胶状转化为固态，将芯片固定在阵列基板上，实现芯片的邦定。
需要说明的是，通过同时设置第一输出端子组和第二输出端子组，在邦定第二类型芯片即未集成有随机存储器的芯片，能够增大邦定在第二输出端子组上的芯片与阵列基板的边缘的距离，降低芯片压合不良出现的机率。
综上所述，本发明提供一种阵列基板，所述阵列基板包括：显示区、以及位于所述显示区外围的邦定区，所述邦定区中设有输入端子组、第一输出端子组及第二输出端子组；所述第一输出端子组位于所述输入端子组远离所述显示区的一侧，所述第二输出端子组位于所述第一输出端子组和所述输入端子组之间；芯片邦定时，根据芯片的类型选择所述第一输出端子组或第二输出端子组与所述输入端子组配合进行芯片邦定，通过同时设置第一输出端子组和第二输出端子组，能够增大邦定在第二输出端子组上的芯片与阵列基板的边缘的距离，降低芯片压合不良出现的机率，保证显示品质。本发明还提供一种芯片邦定方法，能够减少芯片压合不良，保证显示品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种阵列基板，包括：显示区、以及位于所述显示区外围的邦定区，所述邦定区中设有输入端子组、第一输出端子组及第二输出端子组；
    所述第一输出端子组位于所述输入端子组远离所述显示区的一侧，所述第二输出端子组位于所述第一输出端子组和所述输入端子组之间；
    芯片邦定时，根据芯片的类型选择所述第一输出端子组或第二输出端子组与所述输入端子组配合进行芯片邦定。
  2. 如权利要求1所述的阵列基板，其中，所述邦定区中还设有对应所述第一输出端子组设置的第一对位标记以及对应所述第二输出端子组设置的第二对位标记。
  3. 如权利要求1所述的阵列基板，其中，所述邦定区中还设有连接所述第一输出端子组与所述显示区的第一输出引线以及连接所述第二输出端子组与所述显示区的第二输出引线。
  4. 如权利要求1所述的阵列基板，其中，所述芯片的类型为两种，分别为第一类型芯片和第二类型芯片，所述第一类型芯片的尺寸大于所述第二类型的芯片；所述第一类型芯片通过所述第一输出端子组与所述输入端子组配合进行邦定，所述第二类型芯片通过所述第二输出端子组与所述输入端子组配合进行邦定。
  5. 如权利要求4所述的阵列基板，其中，所述第一类型芯片为集成有随机存储器的芯片，所述第二类型芯片为未集成有随机存储器的芯片。
  6. 一种芯片邦定方法，包括如下步骤：
    步骤S1、提供一阵列基板，所述阵列基板包括：显示区、以及位于所述显示区外围的邦定区，所述邦定区中设有输入端子组、第一输出端子组及第二输出端子组
    所述第一输出端子组位于所述输入端子组远离所述显示区的一侧，所述第二输出端子组位于所述第一输出端子组和所述输入端子组之间；
    步骤S2、提供一芯片，确定所述芯片的类型，并根据芯片的类型选择所述第一输出端子组或第二输出端子组与所述输入端子组配合进行芯片邦定。
  7. 如权利要求6所述的芯片邦定方法，其中，所述邦定区中还设有对应所述第一输出端子组设置的第一对位标记、对应所述第二输出端子组设置的第二对位标记、连接所述第一输出端子组与所述显示区的第一输出引 线以及连接所述第二输出端子组与所述显示区的第二输出引线。
  8. 如权利要求7所述的芯片邦定方法，其中，所述步骤S2中进行芯片邦定之前，先通过第一对位标记使得所述芯片与所述第一输出端子组对位或通过所述第二对位标记使得所述芯片与所述第二输出端子组对位。
  9. 如权利要求6所述的芯片邦定方法，其中，所述芯片的类型为两种，分别为第一类型芯片和第二类型芯片，所述第一类型芯片的尺寸大于所述第二类型的芯片；
    所述步骤S2中当所述芯片为第一类型芯片时，通过所述第一输出端子组与所述输入端子组配合进行芯片邦定，当所述芯片为第二类型芯片时，通过所述第二输出端子组与所述输入端子组配合进行芯片邦定。
  10. 如权利要求9所述的芯片邦定方法，其中，所述第一类型芯片为集成有随机存储器的芯片，所述第二类型芯片为未集成有随机存储器的芯片。
PCT/CN2018/107974 2018-04-27 2018-09-27 阵列基板及芯片邦定方法 Ceased WO2019205487A1 (zh)

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