CN108375849A - 阵列基板及芯片邦定方法 - Google Patents

阵列基板及芯片邦定方法 Download PDF

Info

Publication number
CN108375849A
CN108375849A CN201810390115.4A CN201810390115A CN108375849A CN 108375849 A CN108375849 A CN 108375849A CN 201810390115 A CN201810390115 A CN 201810390115A CN 108375849 A CN108375849 A CN 108375849A
Authority
CN
China
Prior art keywords
chip
lead
subgroup
bonding
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810390115.4A
Other languages
English (en)
Inventor
国春朋
王英琪
黄俊宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to CN201810390115.4A priority Critical patent/CN108375849A/zh
Publication of CN108375849A publication Critical patent/CN108375849A/zh
Priority to US16/308,484 priority patent/US11101230B2/en
Priority to PCT/CN2018/107974 priority patent/WO2019205487A1/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/06177—Combinations of arrays with different layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8313—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本发明提供一种阵列基板及芯片邦定方法。所述阵列基板包括：显示区、以及位于所述显示区外围的邦定区，所述邦定区中设有输入端子组、第一输出端子组及第二输出端子组；所述第一输出端子组位于所述输入端子组远离所述显示区的一侧，所述第二输出端子组位于所述第一输出端子组和所述输入端子组之间；芯片邦定时，根据芯片的类型选择所述第一输出端子组或第二输出端子组与所述输入端子组配合进行芯片邦定，通过同时设置第一输出端子组和第二输出端子组，能够增大邦定在第二输出端子组上的芯片与阵列基板的边缘的距离，降低芯片压合不良出现的机率，保证显示品质。

Description

阵列基板及芯片邦定方法
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及芯片邦定方法。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
芯片压合不良(Chip on Glass Mura，COG Mura)是目前困扰液晶显示面板重要品质问题。现有的芯片压合过程包括：将阵列基板的表面贴附异方性导电胶(AnisotropicConductive Film，ACF)，接着将芯片置于所述阵列基板上预设的邦定(Bonding)位置，最后通过热压头压合所述芯片，通过ACF内含的导电粒子将芯片引脚与阵列基板上的邦定端子电性连接，同时使ACF由胶状转化为固态，将芯片固定在阵列基板上。芯片压合不良产生的原因在于，在高温压合使得ACF固化时，高温还会使得芯片和薄膜晶体管也发生膨胀，进而造成靠近芯片部分的液晶盒厚(cell gap)不均匀，在显示时出现对比度差异。
随着显示的技术发展，产品的类型越来越多，芯片的种类也越来越多，在阵列基板的设计过程中常常要兼顾多种不同芯片的邦定，典型的芯片为如图所示的未集成有随机存储器(RAM)的芯片和集成有随机存储器RAM的芯片，如图1所示，现有的未集成有随机存储器的芯片包括：第一输入引脚组101、与所述第一输入引脚组101间隔设置的输出引脚组102以及与位于所述第一输入引脚组101两侧的第一对位标记103，如图2所示，现有的集成有随机存储器的芯片包括：第二输入引脚组201、与所述第二输入引脚组201间隔设置的第二输出引脚组202以及与位于所述第二输入引脚组201两侧的第二对位标记203，图1和图2所示的芯片的不同在于所述第一输入引脚组101和第一输出引脚组102之间的距离小于所述第二输入引脚组201和第二输出引脚组202之间的距离，为了使得阵列基板能够同时兼容上述的两种的芯片，如图3所示，现有的技术提供了一种阵列基板，包括：显示区300、以及位于所述显示区300外围的邦定区400，所述邦定区400中设有输入端子组401、输出端子组402，所述输出端子组402位于所述输入端子组401远离所述显示区300的一侧，其中输入端子组401中的各个端子的长度相比普通的端子更长，进行芯片邦定时，如图4所示，若所述芯片为未集成有随机存储器的芯片，则将所述第一输出引脚组102与所述输出端子组402贴合同时将所述第一输入引脚组101与所述输入端子组401的上半部分贴合；如图5所示，若所述芯片为集成有随机存储器的芯片，则将所述第二输出引脚组202与所述输出端子组402贴合同时将所述第二输入引脚组201与所述输入端子组401的下半部分贴合，从而使得所述阵列基板能够同时兼容上述的两种的芯片。
目前已知芯片边缘到阵列基板边缘的距离是目前已知的影响芯片压合不良的主要原因之一，在图3所示的阵列基板中，两种芯片贴合后，距离阵列基板边缘的距离是相同的，尺寸较小且应用较广的未集成随机存储器的芯片也十分贴近阵列基板的边缘，导致芯片压合不良的出现的机率始终较高。
发明内容
本发明的目的在于提供一种阵列基板，能够减少芯片压合不良，保证显示品质。
本发明的目的还在于提供一种芯片邦定方法，能够减少芯片压合不良，保证显示品质。
为实现上述目的，本发明提供一种阵列基板，包括：显示区、以及位于所述显示区外围的邦定区，所述邦定区中设有输入端子组、第一输出端子组及第二输出端子组；
所述第一输出端子组位于所述输入端子组远离所述显示区的一侧，所述第二输出端子组位于所述第一输出端子组和所述输入端子组之间；
芯片邦定时，根据芯片的类型选择所述第一输出端子组或第二输出端子组与所述输入端子组配合进行芯片邦定。
所述邦定区中还设有对应所述第一输出端子组设置的第一对位标记以及对应所述第二输出端子组设置的第二对位标记。
所述邦定区中还设有连接所述第一输出端子组与所述显示区的第一输出引线以及连接所述第二输出端子组与所述显示区的第二输出引线。
所述芯片的类型为两种，分别为第一类型芯片和第二类型芯片，所述第一类型芯片的尺寸大于所述第二类型的芯片；所述第一类型芯片通过所述第一输出端子组与所述输入端子组配合进行邦定，所述第二类型芯片通过所述第二输出端子组与所述输入端子组配合进行邦定。
所述第一类型芯片为集成有随机存储器的芯片，所述第二类型芯片未集成有随机存储器的芯片。
本发明还提供一种芯片邦定方法，包括如下步骤：
步骤S1、提供一阵列基板，所述阵列基板包括：显示区、以及位于所述显示区外围的邦定区，所述邦定区中设有输入端子组、第一输出端子组及第二输出端子组；
所述第一输出端子组位于所述输入端子组远离所述显示区的一侧，所述第二输出端子组位于所述第一输出端子组和所述输入端子组之间；
步骤S2、提供一芯片，确定所述芯片的类型，并根据芯片的类型选择所述第一输出端子组或第二输出端子组与所述输入端子组配合进行芯片邦定。
所述邦定区中还设有对应所述第一输出端子组设置的第一对位标记、对应所述第二输出端子组设置的第二对位标记、连接所述第一输出端子组与所述显示区的第一输出引线以及连接所述第二输出端子组与所述显示区的第二输出引线。
所述步骤S2中进行芯片邦定之前，先通过第一对位标记使得所述芯片与所述第一输出端子组对位或通过所述第二对位标记使得所述芯片与所述第二输出端子组对位。
所述芯片的类型为两种，分别为第一类型芯片和第二类型芯片，所述第一类型芯片的尺寸大于所述第二类型的芯片；
所述步骤S2中当所述芯片为第一类型芯片时，通过所述第一输出端子组与所述输入端子组配合进行芯片邦定，当所述芯片为第二类型芯片时，通过所述第二输出端子组与所述输入端子组配合进行芯片邦定。
所述第一类型芯片为集成有随机存储器的芯片，所述第二类型芯片未集成有随机存储器的芯片。
本发明的有益效果：本发明提供一种阵列基板，所述阵列基板包括：显示区、以及位于所述显示区外围的邦定区，所述邦定区中设有输入端子组、第一输出端子组及第二输出端子组；所述第一输出端子组位于所述输入端子组远离所述显示区的一侧，所述第二输出端子组位于所述第一输出端子组和所述输入端子组之间；芯片邦定时，根据芯片的类型选择所述第一输出端子组或第二输出端子组与所述输入端子组配合进行芯片邦定，通过同时设置第一输出端子组和第二输出端子组，能够增大邦定在第二输出端子组上的芯片与阵列基板的边缘的距离，降低芯片压合不良出现的机率，保证显示品质。本发明还提供一种芯片邦定方法，能够减少芯片压合不良，保证显示品质。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为未集成有随机存储器的芯片的结构示意图；
图2为集成有随机存储器的芯片的结构示意图；
图3为现有的阵列基板的示意图；
图4为在现有的阵列基板上邦定未集成有随机存储器的芯片时的示意图；
图5为在现有的阵列基板上邦定集成有随机存储器的芯片时的示意图；
图6为本发明的阵列基板的示意图；
图7为在本发明的阵列基板上邦定未集成有随机存储器的芯片时的示意图；
图8为在现有的阵列基板上邦定集成有随机存储器的芯片时的示意图；
图9为本发明的芯片邦定方法的流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图6，本发明提供一种阵列基板，包括：显示区10、以及位于所述显示区10外围的邦定区20，所述邦定区20中设有输入端子组21、第一输出端子组22及第二输出端子组23；
所述第一输出端子组22位于所述输入端子组21远离所述显示区10的一侧，所述第二输出端子组23位于所述第一输出端子组22和所述输入端子组21之间；也即所述第一输出端子组22、第二输出端子组23及输入端子组21从上往下依次排列，距离所述阵列基板的边缘的距离依次增大。
芯片邦定时，根据芯片的类型选择所述第一输出端子组22或第二输出端子组23与所述输入端子组21配合进行芯片邦定。
具体地，如图6所示，在本发明的优选实施例中，所述输入端子组21包括从左到右依次隔间排列成一行的多个输入端子211，所述第一输出端子组22包括从左到右依次间隔排列成两行的多个第一输出端子221，所述第二输出端子组23包括从左到右依次间隔排列成两行的多个第二输出端子231，所述多个第一输出端子221和多个第二输出端子231的数量及排列方式均相同。
具体地，为了使得芯片邦定后能够与所述显示区10通讯，所述邦定区20中还设有连接所述第一输出端子组22与所述显示区10的第一输出引线42以及连接所述第二输出端子组23与所述显示区10的第二输出引线43，进一步地，所述第一输出引线42的数量与所述第一输出端子221的数量相等，每一个第一输出端子221对应通过一条第一输出引线42与所述显示区10电性连接，所述第二输出引线43的数量与所述第二输出端子231的数量相等，每一个第二输出端子231对应通过一条第二输出引线43与所述显示区10电性连接。
需要说明的是，输入端子211、第一输出端子221及第二输出端子231形成于同一金属层，所述第一输出引线42及第二输出引线43形成于所述输入端子211、第一输出端子221及第二输出端子231所在金属层的下方的另一金属层，所述第一输出引线42及第二输出引线43通过分别通过过孔与所述第一输出端子221及第二输出端子231电性连接。
具体地，所述邦定区20中还设有对应所述第一输出端子组22设置的第一对位标记31以及对应所述第二输出端子组23设置的第二对位标记32，进一步地，所述第一对位标记31和第二对位标记32的数量均为两个，其形状均为十字形，所述两个第一对位标记31分别位于所述第一输出端子组22的左右两侧，所述两个第二对位标记32分别位于所述第二输出端子组23的左右两侧。
具体地，在本发明的优选实施例中，所述芯片的类型为两种，分别为第一类型芯片和第二类型芯片，所述第一类型芯片的尺寸大于所述第二类型的芯片；所述第一类型芯片通过所述第一输出端子组22与所述输入端子组21配合进行邦定，所述第二类型芯片通过所述第二输出端子组23与所述输入端子组21配合进行邦定。
进一步地，所述第一类型芯片为如图2所示的集成有随机存储器的芯片，所述第二类型芯片为如图1所示的未集成有随机存储器的芯片。
具体邦定过程包括：首先确定所述芯片为第一类型芯片或第二类型芯片，请参阅图7，当所述芯片为第一类型芯片时，则在所述阵列基板的对应所述输入端子组21及第一输出端子组22的区域贴附ACF胶，接着将通过第一对位标记31与所述芯片对位，使得芯片上的输出引脚与所述第一输出端子组22对位，输入引脚与所述输入端子组21对位，最后通过热压头压合所述芯片，通过ACF内含的导电粒子将芯片引脚与阵列基板上的邦定端子电性连接，同时使ACF由胶状转化为固态，将芯片固定在阵列基板上，实现芯片的邦定；请参阅图8，当所述芯片为第二类型芯片时，则在所述阵列基板的对应所述输入端子组21及第二输出端子组23的区域贴附ACF胶，接着将通过第二对位标记32与所述芯片对位，使得芯片上的输出引脚与所述第二输出端子组23对位，输入引脚与所述输入端子组21对位，最后通过热压头压合所述芯片，通过ACF内含的导电粒子将芯片引脚与阵列基板上的邦定端子电性连接，同时使ACF由胶状转化为固态，将芯片固定在阵列基板上，实现芯片的邦定。
需要说明的是，通过同时设置第一输出端子组和第二输出端子组，在邦定第二类型芯片即未集成有随机存储器的芯片，能够增大邦定在第二输出端子组上的芯片与阵列基板的边缘的距离，降低芯片压合不良出现的机率。
请参阅图9，一种芯片邦定方法，其特征在于，包括如下步骤：
步骤S1、提供一阵列基板，所述阵列基板包括：显示区10、以及位于所述显示区10外围的邦定区20，所述邦定区20中设有输入端子组21、第一输出端子组22及第二输出端子组23
所述第一输出端子组22位于所述输入端子组21远离所述显示区10的一侧，所述第二输出端子组23位于所述第一输出端子组22和所述输入端子组21之间。也即所述第一输出端子组22、第二输出端子组23及输入端子组21从上往下依次排列，距离所述阵列基板的边缘的距离依次增大。
具体地，如图6所示，在本发明的优选实施例中，所述输入端子组21包括从左到右依次隔间排列成一行的多个输入端子211，所述第一输出端子组22包括从左到右依次间隔排列成两行的多个第一输出端子221，所述第二输出端子组23包括从左到右依次间隔排列成两行的多个第二输出端子231，所述多个第一输出端子221和多个第二输出端子231的数量及排列方式均相同。
具体地，为了使得芯片邦定后能够与所述显示区10通讯，所述邦定区20中还设有连接所述第一输出端子组22与所述显示区10的第一输出引线42以及连接所述第二输出端子组23与所述显示区10的第二输出引线43，进一步地，所述第一输出引线42的数量与所述第一输出端子221的数量相等，每一个第一输出端子221对应通过一条第一输出引线42与所述显示区10电性连接，所述第二输出引线43的数量与所述第二输出端子231的数量相等，每一个第二输出端子231对应通过一条第二输出引线43与所述显示区10电性连接。
需要说明的是，输入端子211、第一输出端子221及第二输出端子231形成于同一金属层，所述第一输出引线42及第二输出引线43形成于所述输入端子211、第一输出端子221及第二输出端子231所在金属层的下方的另一金属层，所述第一输出引线42及第二输出引线43通过分别通过过孔与所述第一输出端子221及第二输出端子231电性连接。
具体地，所述邦定区20中还设有对应所述第一输出端子组22设置的第一对位标记31以及对应所述第二输出端子组23设置的第二对位标记32，进一步地，所述第一对位标记31和第二对位标记32的数量均为两个，其形状均为十字形，所述两个第一对位标记31分别位于所述第一输出端子组22的左右两侧，所述两个第二对位标记32分别位于所述第二输出端子组23的左右两侧。
具体地，在本发明的优选实施例中，所述芯片的类型为两种，分别为第一类型芯片和第二类型芯片，所述第一类型芯片的尺寸大于所述第二类型的芯片；所述第一类型芯片通过所述第一输出端子组22与所述输入端子组21配合进行邦定，所述第二类型芯片通过所述第二输出端子组23与所述输入端子组21配合进行邦定。
进一步地，所述第一类型芯片为如图2所示的集成有随机存储器的芯片，所述第二类型芯片为如图1所示的未集成有随机存储器的芯片。
步骤S2、提供一芯片，确定所述芯片的类型，并根据芯片的类型选择所述第一输出端子组22或第二输出端子组23与所述输入端子组21配合进行芯片邦定。
具体地，请参阅图7，当所述芯片为第一类型芯片时，则在所述阵列基板的对应所述输入端子组21及第一输出端子组22的区域贴附ACF胶，接着将通过第一对位标记31与所述芯片对位，使得芯片上的输出引脚与所述第一输出端子组22对位，输入引脚与所述输入端子组21对位，最后通过热压头压合所述芯片，通过ACF内含的导电粒子将芯片引脚与阵列基板上的邦定端子电性连接，同时使ACF由胶状转化为固态，将芯片固定在阵列基板上，实现芯片的邦定；请参阅图8，当所述芯片为第二类型芯片时，则在所述阵列基板的对应所述输入端子组21及第二输出端子组23的区域贴附ACF胶，接着将通过第二对位标记32与所述芯片对位，使得芯片上的输出引脚与所述第二输出端子组23对位，输入引脚与所述输入端子组21对位，最后通过热压头压合所述芯片，通过ACF内含的导电粒子将芯片引脚与阵列基板上的邦定端子电性连接，同时使ACF由胶状转化为固态，将芯片固定在阵列基板上，实现芯片的邦定。
需要说明的是，通过同时设置第一输出端子组和第二输出端子组，在邦定第二类型芯片即未集成有随机存储器的芯片，能够增大邦定在第二输出端子组上的芯片与阵列基板的边缘的距离，降低芯片压合不良出现的机率。
综上所述，本发明提供一种阵列基板，所述阵列基板包括：显示区、以及位于所述显示区外围的邦定区，所述邦定区中设有输入端子组、第一输出端子组及第二输出端子组；所述第一输出端子组位于所述输入端子组远离所述显示区的一侧，所述第二输出端子组位于所述第一输出端子组和所述输入端子组之间；芯片邦定时，根据芯片的类型选择所述第一输出端子组或第二输出端子组与所述输入端子组配合进行芯片邦定，通过同时设置第一输出端子组和第二输出端子组，能够增大邦定在第二输出端子组上的芯片与阵列基板的边缘的距离，降低芯片压合不良出现的机率，保证显示品质。本发明还提供一种芯片邦定方法，能够减少芯片压合不良，保证显示品质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

1.一种阵列基板，其特征在于，包括：显示区(10)、以及位于所述显示区(10)外围的邦定区(20)，所述邦定区(20)中设有输入端子组(21)、第一输出端子组(22)及第二输出端子组(23)；
所述第一输出端子组(22)位于所述输入端子组(21)远离所述显示区(10)的一侧，所述第二输出端子组(23)位于所述第一输出端子组(22)和所述输入端子组(21)之间；
芯片邦定时，根据芯片的类型选择所述第一输出端子组(22)或第二输出端子组(23)与所述输入端子组(21)配合进行芯片邦定。
2.如权利要求1所述的阵列基板，其特征在于，所述邦定区(20)中还设有对应所述第一输出端子组(22)设置的第一对位标记(31)以及对应所述第二输出端子组(23)设置的第二对位标记(32)。
3.如权利要求1所述的阵列基板，其特征在于，所述邦定区(20)中还设有连接所述第一输出端子组(22)与所述显示区(10)的第一输出引线(42)以及连接所述第二输出端子组(23)与所述显示区(10)的第二输出引线(43)。
4.如权利要求1所述的阵列基板，其特征在于，所述芯片的类型为两种，分别为第一类型芯片和第二类型芯片，所述第一类型芯片的尺寸大于所述第二类型的芯片；所述第一类型芯片通过所述第一输出端子组(22)与所述输入端子组(21)配合进行邦定，所述第二类型芯片通过所述第二输出端子组(23)与所述输入端子组(21)配合进行邦定。
5.如权利要求4所述的阵列基板，其特征在于，所述第一类型芯片为集成有随机存储器的芯片，所述第二类型芯片为未集成有随机存储器的芯片。
6.一种芯片邦定方法，其特征在于，包括如下步骤：
步骤S1、提供一阵列基板，所述阵列基板包括：显示区(10)、以及位于所述显示区(10)外围的邦定区(20)，所述邦定区(20)中设有输入端子组(21)、第一输出端子组(22)及第二输出端子组(23)
所述第一输出端子组(22)位于所述输入端子组(21)远离所述显示区(10)的一侧，所述第二输出端子组(23)位于所述第一输出端子组(22)和所述输入端子组(21)之间；
步骤S2、提供一芯片，确定所述芯片的类型，并根据芯片的类型选择所述第一输出端子组(22)或第二输出端子组(23)与所述输入端子组(21)配合进行芯片邦定。
7.如权利要求6所述的芯片邦定方法，其特征在于，所述邦定区(20)中还设有对应所述第一输出端子组(22)设置的第一对位标记(31)、对应所述第二输出端子组(23)设置的第二对位标记(32)、连接所述第一输出端子组(22)与所述显示区(10)的第一输出引线(42)以及连接所述第二输出端子组(23)与所述显示区(10)的第二输出引线(43)。
8.如权利要求7所述的芯片邦定方法，其特征在于，所述步骤S2中进行芯片邦定之前，先通过第一对位标记(31)使得所述芯片与所述第一输出端子组(22)对位或通过所述第二对位标记(32)使得所述芯片与所述第二输出端子组(23)对位。
9.如权利要求6所述的芯片邦定方法，其特征在于，所述芯片的类型为两种，分别为第一类型芯片和第二类型芯片，所述第一类型芯片的尺寸大于所述第二类型的芯片；
所述步骤S2中当所述芯片为第一类型芯片时，通过所述第一输出端子组(22)与所述输入端子组(21)配合进行芯片邦定，当所述芯片为第二类型芯片时，通过所述第二输出端子组(23)与所述输入端子组(21)配合进行芯片邦定。
10.如权利要求9所述的芯片邦定方法，其特征在于，所述第一类型芯片为集成有随机存储器的芯片，所述第二类型芯片为未集成有随机存储器的芯片。
CN201810390115.4A 2018-04-27 2018-04-27 阵列基板及芯片邦定方法 Pending CN108375849A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201810390115.4A CN108375849A (zh) 2018-04-27 2018-04-27 阵列基板及芯片邦定方法
US16/308,484 US11101230B2 (en) 2018-04-27 2018-09-27 Array substrate and chip bonding method
PCT/CN2018/107974 WO2019205487A1 (zh) 2018-04-27 2018-09-27 阵列基板及芯片邦定方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810390115.4A CN108375849A (zh) 2018-04-27 2018-04-27 阵列基板及芯片邦定方法

Publications (1)

Publication Number Publication Date
CN108375849A true CN108375849A (zh) 2018-08-07

Family

ID=63032777

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810390115.4A Pending CN108375849A (zh) 2018-04-27 2018-04-27 阵列基板及芯片邦定方法

Country Status (3)

Country Link
US (1) US11101230B2 (zh)
CN (1) CN108375849A (zh)
WO (1) WO2019205487A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019205487A1 (zh) * 2018-04-27 2019-10-31 武汉华星光电技术有限公司 阵列基板及芯片邦定方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7369559B2 (ja) * 2019-07-30 2023-10-26 トヨタ自動車株式会社 ３次元成型品加飾用積層フィルム

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09244051A (ja) * 1996-03-05 1997-09-19 Hitachi Ltd 液晶駆動装置および液晶表示装置
CN101419954A (zh) * 2007-10-22 2009-04-29 南茂科技股份有限公司 用于芯片封装构造的对位装置
CN201319098Y (zh) * 2008-10-14 2009-09-30 Tcl集团股份有限公司 Lcd模组
JP2011175215A (ja) * 2010-02-25 2011-09-08 Seiko Instruments Inc 表示装置及び表示装置の製造方法
CN206134145U (zh) * 2016-10-31 2017-04-26 上海天马微电子有限公司 一种显示面板及显示装置
CN107329297A (zh) * 2017-08-30 2017-11-07 上海中航光电子有限公司 显示面板的绑定结构和显示面板
CN107422551A (zh) * 2017-07-25 2017-12-01 武汉天马微电子有限公司 一种显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040075377A (ko) * 2003-02-20 2004-08-30 삼성전자주식회사 구동 아이씨 및 이를 갖는 디스플레이 장치
CN100414360C (zh) 2005-12-08 2008-08-27 群康科技(深圳)有限公司 液晶显示面板
JP2008304495A (ja) 2007-06-05 2008-12-18 Funai Electric Co Ltd 液晶セル及びそれを備えた液晶表示装置
CN101271206B (zh) 2008-04-21 2010-10-06 友达光电股份有限公司 可配置不同大小的驱动芯片的显示装置
CN108375849A (zh) 2018-04-27 2018-08-07 武汉华星光电技术有限公司 阵列基板及芯片邦定方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09244051A (ja) * 1996-03-05 1997-09-19 Hitachi Ltd 液晶駆動装置および液晶表示装置
CN101419954A (zh) * 2007-10-22 2009-04-29 南茂科技股份有限公司 用于芯片封装构造的对位装置
CN201319098Y (zh) * 2008-10-14 2009-09-30 Tcl集团股份有限公司 Lcd模组
JP2011175215A (ja) * 2010-02-25 2011-09-08 Seiko Instruments Inc 表示装置及び表示装置の製造方法
CN206134145U (zh) * 2016-10-31 2017-04-26 上海天马微电子有限公司 一种显示面板及显示装置
CN107422551A (zh) * 2017-07-25 2017-12-01 武汉天马微电子有限公司 一种显示装置
CN107329297A (zh) * 2017-08-30 2017-11-07 上海中航光电子有限公司 显示面板的绑定结构和显示面板

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019205487A1 (zh) * 2018-04-27 2019-10-31 武汉华星光电技术有限公司 阵列基板及芯片邦定方法
US11101230B2 (en) 2018-04-27 2021-08-24 Wuhan China Star Optoelectronics Technology Co., Ltd. Array substrate and chip bonding method

Also Published As

Publication number Publication date
WO2019205487A1 (zh) 2019-10-31
US11101230B2 (en) 2021-08-24
US20210091027A1 (en) 2021-03-25

Similar Documents

Publication Publication Date Title
US10971465B2 (en) Driving chip, display substrate, display device and method for manufacturing display device
CN103217845B (zh) 下基板及其制造方法、液晶显示面板和液晶显示器
CN110416264B (zh) 显示装置的绑定方法及显示装置
CN108957812A (zh) 液晶显示装置的制作方法及液晶显示装置
CN109307961A (zh) 显示面板电路结构
CN110286531A (zh) 显示装置及其制作方法
WO2020133794A1 (zh) 窄边框显示屏的制作方法及显示装置
WO2021103354A1 (zh) 一种显示装置
CN108375849A (zh) 阵列基板及芯片邦定方法
CN105372866A (zh) 液晶显示面板
WO2023279449A1 (zh) 显示模组及其制备方法、移动终端
CN107283989B (zh) 压合装置及在显示面板上压合胶体的方法
CN109445200A (zh) 基板及对位贴合方法
WO2015096234A1 (zh) 一种覆晶薄膜 cof 模组、显示面板和显示器
US10444577B2 (en) Polymer stabilization vertical alignment (PSVA) liquid crystal display panel
CN106383422A (zh) 液晶显示面板及其制造方法
Yen et al. ACF particle distribution in COG process
CN107390411A (zh) 液晶显示面板及其制作方法
CN110187566A (zh) 框胶及液晶显示面板
CN109799652A (zh) 母板结构及液晶显示面板的制作方法
CN101118330A (zh) 显示屏与驱动部分共用一层各向异性导电膜连接的方法
CN106353932A (zh) 液晶面板贴合方法
CN100480786C (zh) 玻璃覆晶结构和采用该玻璃覆晶结构的液晶显示器
CN1325983C (zh) 液晶显示面板的封装结构及其制作工艺
Yin et al. 55.2: A novel sn paste free approach for manufacturing mini‐LED display

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20180807

WD01 Invention patent application deemed withdrawn after publication