Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
  • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/04—Coating on selected surface areas, e.g. using masks
  • C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
  • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
  • C23C16/40—Oxides
  • C23C16/401—Oxides containing silicon
  • C23C16/402—Silicon dioxide
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
  • C23C16/45523—Pulsed gas flow or change of composition over time
  • C23C16/45525—Atomic layer deposition [ALD]
  • C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
  • C23C16/45534—Use of auxiliary reactants other than used for contributing to the composition of the main film, e.g. catalysts, activators or scavengers
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
  • C23C16/45523—Pulsed gas flow or change of composition over time
  • C23C16/45525—Atomic layer deposition [ALD]
  • C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
  • C23C16/45536—Use of plasma, radiation or electromagnetic fields
  • C23C16/4554—Plasma being used non-continuously in between ALD reactions
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
  • C23C16/45523—Pulsed gas flow or change of composition over time
  • C23C16/45525—Atomic layer deposition [ALD]
  • C23C16/45553—Atomic layer deposition [ALD] characterized by the use of precursors specially adapted for ALD
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
  • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
• • H—ELECTRICITY
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
  • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
  • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
  • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
  • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
  • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
  • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
  • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
  • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
  • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
  • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
  • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
  • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
  • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/764—Air gaps
• • H—ELECTRICITY
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
  • H01L21/76846—Layer combinations
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
  • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
  • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
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  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01022—Titanium [Ti]

Definitions

• the present invention relates to the field of semiconductor manufacturing and semiconductor devices, and more particularly, to a method of forming a semiconductor device with air gaps for low capacitance interconnects.
• This disclosure describes a novel method of fabricating air gaps in advanced
• the method includes providing a substrate containing raised features with top areas and sidewalls, and bottom areas between the raised features, and exposing the substrate to a gas pulse sequence to deposit a material that forms an air gap between the raised features, where the gas pulse sequence includes, in any order: a) sequentially first, exposing the substrate to a first precursor gas to non-conformally form a first precursor layer on the top areas and on the upper parts of the sidewalls, but not on the lower parts of the sidewalls and the bottom areas, and second, exposing the substrate to a second precursor gas that reacts with the first precursor layer to form a layer of the material on the substrate, and b) sequentially first, exposing the substrate to the first precursor gas to conformally form a second precursor layer on the top areas, on the sidewalls, and on the bottom areas, and second, exposing the substrate to the second precursor gas that reacts with the second precursor layer to form a second layer of the material on the substrate.
• the method includes providing a substrate containing raised features with top areas and sidewalls, and bottom areas between the raised features, and exposing the substrate to a gas pulse sequence to deposit a material that forms an air gap between the raised features, where the gas pulse sequence includes, in any order: a) sequentially first, exposing the substrate to a first precursor gas to conformally form a first precursor layer on the top areas, on the sidewalls, and on the bottom areas, second, exposing the substrate to a plasma-excited halogen-containing gas to deactivate or at least partially remove the first precursor layer in the top areas and the bottom areas, and third, exposing the substrate to the second precursor gas that reacts with the first precursor layer to form a layer of the material on the sidewalls, and b) sequentially first, exposing the substrate to the first precursor gas to conformally form a second precursor layer on the top areas, on the sidewalls, and on the bottom areas, and second, exposing the substrate to the second precursor gas that reacts with the second precursor layer to
• FIG. 1 is a process flow diagram for processing a substrate according to an embodiment of the invention
• FIGS. 2A-2F schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention
• FIG. 3 is a process flow diagram for processing a substrate according to an embodiment of the invention.
• FIGS. 4A-4G schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention.
• FIG. 5 shows a cross-sectional scanning electron micrograph (SEM) image of air gaps formed in a SiOz material according to an embodiment of the invention.
• FIG. 1 A method of fabricating air gaps in advanced semiconductor devices is described.
• FIGS. 2A-2F schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention.
• the process flow 1 in FIG. 1 includes in 100, providing a substrate 2 containing a base film 200 and raised features 202 with top areas 201 and sidewalls 208, and bottom areas 206 between the raised features 202.
• the raised features 202 define a recessed feature 204 between the raised features 202.
• the recessed feature 204 can, for example, have a width 207 that is less than 200nm, less than lOOnm, less than 50nm, less than 25nm, less than 20nm, or less than lOnm.
• the recessed feature 204 can have a width 207 that is between 5nm and lOnm, between lOnm and 20nm, between 20nm and 50nm, between 50nm and lOOnm, between lOOnm and 200nm, between lOnm and 50nm, or between lOnm and lOOnm.
• the width 207 can also be referred to as a critical dimension (CD).
• the recessed feature 204 can, for example, have a depth of 25nm, 50nm, lOOnm, 200nm, or greater.
• the base film 200 and the raised features 202 may contain or consist of the same material.
• the base film 200 and the raised features 202 may contain or consist of Si.
• the raised features 202 may contain a dielectric material, for example S1O2, SiON, SiN, a high-k material, a low-k material, or an ultra-low-k material.
• the recessed feature 204 may be formed using well-known lithography and etching processes.
• the process flow 1 further includes exposing the substrate 2 to a gas pulse sequence to deposit a material that forms an air gap on the substrate 2, where the gas pulse sequence includes, in any order: in 102, sequentially first, exposing the substrate to a first precursor gas to non-conformally form a first precursor layer on the top areas and on the upper parts of the sidewalls, but not on the lower parts of the sidewalls and the bottom areas (FIG. 2B), and second, exposing the substrate to a second precursor gas that reacts with the first precursor layer to form a first layer of the material on the substrate (FIG.
• FIG. 2B schematically shows a first precursor layer 210 that is non-conformally formed on the top areas 201 and on the upper parts of the sidewalls 208, but not on the lower parts of the sidewalls 208 and the bottom areas 206.
• the first precursor layer 210 may be deposited or formed by various methods including a) controlling the saturation regime at the substrate using an undersaturated exposure of the first precursor gas that results in depletion of the first precursor gas in the recessed feature 204, b) pressure control at the substrate to limit the diffusion of the first precursor gas to the bottom areas 206, c) spatial rapid horizontal movement of a rotating substrate below a gas inlet dispensing the first precursor gas during an atomic layer deposition (ALD) process, or d) plasma densification of a conformal precursor layer on the top areas 201 and on the upper parts of the sidewalls 208, followed by etching of the conformal precursor layer the lower parts of the sidewalls 208 and the bottom areas 206.
• ALD atomic layer deposition
• FIG. 2C shows the formation of a first layer of material 212 from exposure of the second precursor gas that reacts with the first precursor layer 210 in FIG. 2B.
• FIG. 2D shows a second precursor layer 214 that is conformally formed on the top areas 201, on the sidewalls 208, and on the bottom areas 206.
• the second precursor layer 214 may be deposited using a saturated exposure of the first precursor gas that reaches and saturates the bottom areas 206 between the raised features 202.
• FIG. 2E shows the formation of a second layer of material 216 from exposure of the second precursor gas that reacts with the second precursor layer 214 in FIG. 2D.
• Steps 102, 104, or both 102 and 104 may be repeated at least once until an air gap is formed on the substrate 2.
• Steps 102 and 104 may be performed in any order, i.e., step 102 before step 104, or step 104 before step 102.
• FIG. 2F shows the formation of an air gap 220 in the material 218 following deposition of additional material until the recessed feature 204 is pinched off near the top.
• the material 218 containing the air gap 220 includes the first layer of material 212, the second layer of material 216, and any further materials needed to close the opening near the top of the recessed feature 204.
• the first precursor gas can include a metal -containing precursor and the first and second precursor layers 210 and 214 can form an adsorbed layer of the first precursor that is approximately one atomic layer thick.
• the metal -containing precursor contains aluminum, titanium, or a combination thereof.
• metal -containing precursor include aluminum (Al), titanium (Ti), or both aluminum and titanium.
• the first and second precursor layers 210 and 214 are selected from the group consisting of Al, AI2O3, AIN, AION, an Al-containing precursor, Al-alloys, CuAl, TiAIN, TaAIN, Ti, TiAlC, TiCh, TiON, TiN, a Ti- containing precursor, Ti-alloys, and combinations thereof.
• Embodiments of the invention may utilize a wide variety of A1 -containing precursors.
• Li, L 2 , L3 are individual anionic ligands
• D is a neutral donor ligand where x can be 0, 1, or 2.
• Each Li, L2, L3 ligand may be individually selected from the groups of alkoxides, halides, aryloxides, amides, cyclopentadienyls, alkyls, silyls, amidinates, b-diketonates, ketoiminates, silanoates, and carboxylates.
• D ligands may be selected from groups of ethers, fiirans, pyridines, pyroles, pyrolidines, amines, crown ethers, glymes, and nitriles.
• aluminum precursors include:
• Embodiments of the invention may utilize a wide variety of Ti-containing precursors.
• Ti-containing precursors having“Ti-N” intra-molecular bonds include Ti(NEt2)4 (TDEAT), Ti(NMeEt)4 (TEMAT), Ti(NMe2)4 (TDMAT).
• Other examples include Ti- containing precursors containing“Ti-N” intra-molecular bonds.
• the second precursor gas may include a silanol gas and the material deposited on the substrate can include S1O2.
• the silanol gas may be selected from the group consisting of tris(tert-pentoxy) silanol (TPSOL), tris(tert-butoxy) silanol, and bis(tert-butoxy)(isopropoxy) silanol.
• the substrate may be exposed, at a substrate temperature of approximately 150°C or less, to a process gas containing a silanol gas to deposit a S1O2 film.
• the thickness of the S1O2 film is controlled by self-limiting adsorption of the silanol gas on the precursor layer. This catalytic effect has been observed until the S1O2 films were about 3nm thick, thereafter the S1O2 deposition stopped.
• the substrate temperature may be approximately 120°C or less. In yet another embodiment, the substrate temperature may be approximately 100°C or less.
• FIG. 5 shows a cross-sectional scanning electron micrograph (SEM) image of air gaps 502 formed in a S1O2 material 500 according to an embodiment of the invention.
• the S1O2 material 500 was deposited over raised features according to the embodiment described in FIGS. 1 and 2A-2F.
• the first precursor contained AlMes and the second precursor contained tris(tert- pentoxy) silanol.
• FIG. 3 is a process flow diagram for processing a substrate according to an embodiment of the invention
• FIGS. 4A-4G schematically show through cross-sectional views a method of processing a substrate according to an embodiment of the invention.
• the process flow 3 includes, in 300, providing a substrate 4 containing a base film 400 and raised features 402 with top areas 401 and sidewalls 408, and bottom areas 406 between the raised features 402.
• the raised features 402 define a recessed feature 404 having a width 407 between the raised features 402.
• the process flow 3 further includes exposing the substrate 4 to a gas pulse sequence to deposit a material that forms an air gap on the substrate 4, where the gas pulse sequence includes, in any order: in 302, sequentially first, exposing the substrate to a first precursor gas to conformally form a first precursor layer on the top areas, on the sidewalls, and on the bottom areas (FIG. 4B), second, exposing the substrate to a plasma-excited halogen-containing gas to deactivate or at least partially remove the first precursor layer in the top areas and the bottom areas (FIG. 4C), and third, exposing the substrate to the second precursor gas that reacts with the precursor layer to form a first layer of the material on the sidewalls (FIG.
• Steps a), b) or a) and b), may be repeated at least once to increase a thickness of the first and second material layers.
• FIG. 4B shows the first precursor layer 410 that is conformally formed on the top areas 401, on the sidewalls 408, and on the bottom areas 406.
• the first precursor layer 410 may be deposited using a saturated exposure of the first precursor gas.
• FIG. 4C shows the first precursor layer 410 following exposing the substrate 4 to a plasma-excited halogen-containing gas.
• the exposure to the plasma-excited halogen-containing gas removes the first precursor layer 410 from the top areas 401 and the bottom areas 406.
• Nonlimiting examples of the halogen-containing gas contain Ck, BCb, CCU, HC1, HBr, TiCU, or a combination thereof.
• the halogen-containing gas can further include an inert gas such as Argon (Ar).
• the plasma-excitation may be performed using a high density plasma source, for example an inductively coupled plasma (ICP) source or a microwave plasma source.
• ICP inductively coupled plasma
• the substrate 4 may be biased through a substrate holder to further enhance the anisotropic characteristics of the plasma exposure. Further, processing conditions such as substrate temperature, gas pressure, and plasma power, may be selected to control the removal of the first precursor layer 410 and to minimize the damage to the substrate 4.
• FIG. 4D shows the formation of a second layer of material 412 from exposure of the second precursor gas that reacts with the first precursor layer 410 in FIG. 4C on the sidewalls 408.
• FIG. 4E shows the second precursor layer 414 that is conformally formed on the top areas 401, on the sidewalls 408, and on the bottom areas 406.
• the second precursor layer 414 may be deposited using a saturated exposure of the first precursor gas that reaches and saturates the bottom areas 406 between the raised features 402.
• FIG. 4F shows the formation of a second layer of material 416 from exposure of the second precursor gas that reacts with the second precursor layer 414 in FIG. 4E.
• Steps 302, 304, or both 302 and 304 may be repeated at least once until an air gap is formed on the substrate 4.
• Steps 302 and 304 may be performed in any order, i.e., step 302 before step 304, or step 304 before step 302.
• FIG. 4G shows the formation of an air gap 420 in the material 418 following deposition of additional material until the recessed feature 404 is pinched off near the top.
• the material 418 containing the air gap 420 includes the layer of material 412, the additional layer of material 216, and any further materials needed to close the opening near the top of the recessed feature 204.

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