KR102740088B1 - 저 커패시턴스 상호연결을 위한 에어 갭을 가진 반도체 디바이스를 형성하는 방법 - Google Patents

저 커패시턴스 상호연결을 위한 에어 갭을 가진 반도체 디바이스를 형성하는 방법 Download PDF

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KR102740088B1
KR102740088B1 KR1020207032197A KR20207032197A KR102740088B1 KR 102740088 B1 KR102740088 B1 KR 102740088B1 KR 1020207032197 A KR1020207032197 A KR 1020207032197A KR 20207032197 A KR20207032197 A KR 20207032197A KR 102740088 B1 KR102740088 B1 KR 102740088B1
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substrate
precursor
gas
layer
exposing
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KR20200130497A (ko
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칸다바라 타필리
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도쿄엘렉트론가부시키가이샤
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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KR1020207032197A 2018-04-09 2019-04-09 저 커패시턴스 상호연결을 위한 에어 갭을 가진 반도체 디바이스를 형성하는 방법 Active KR102740088B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201862654760P 2018-04-09 2018-04-09
US62/654,760 2018-04-09
PCT/US2019/026590 WO2019199834A1 (en) 2018-04-09 2019-04-09 Method of forming a semiconductor device with air gaps for low capacitance interconnects

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KR20200130497A KR20200130497A (ko) 2020-11-18
KR102740088B1 true KR102740088B1 (ko) 2024-12-06

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JP (1) JP7205929B2 (enExample)
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WO (1) WO2019199834A1 (enExample)

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WO2020154294A1 (en) * 2019-01-22 2020-07-30 Averatek Corporation Pattern formation using catalyst blocker
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