WO2019188843A1 - 配線基板、および配線基板を製造する方法 - Google Patents

配線基板、および配線基板を製造する方法 Download PDF

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Publication number
WO2019188843A1
WO2019188843A1 PCT/JP2019/012249 JP2019012249W WO2019188843A1 WO 2019188843 A1 WO2019188843 A1 WO 2019188843A1 JP 2019012249 W JP2019012249 W JP 2019012249W WO 2019188843 A1 WO2019188843 A1 WO 2019188843A1
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Prior art keywords
substrate
metal element
diffusion layer
metal
metal film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/JP2019/012249
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English (en)
French (fr)
Japanese (ja)
Inventor
宏樹 古庄
敦子 千吉良
恵大 笹生
宏 馬渡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2020509993A priority Critical patent/JP7468342B2/ja
Priority to CN201980020134.0A priority patent/CN111868301A/zh
Priority to CN202311150946.1A priority patent/CN117320265A/zh
Priority to KR1020207027438A priority patent/KR102720915B1/ko
Priority to KR1020247034782A priority patent/KR20240159006A/ko
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Publication of WO2019188843A1 publication Critical patent/WO2019188843A1/ja
Priority to US17/011,260 priority patent/US12028972B2/en
Anticipated expiration legal-status Critical
Priority to US18/381,789 priority patent/US20240049384A1/en
Priority to JP2024008072A priority patent/JP7666668B2/ja
Priority to JP2025064481A priority patent/JP2025103022A/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • C—CHEMISTRY; METALLURGY
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/08—Oxides
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
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    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/58—After-treatment
    • C23C14/5893—Mixing of deposited material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
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    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/02—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition
    • C23C18/12—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material
    • C23C18/125—Process of deposition of the inorganic material
    • C23C18/1295—Process of deposition of the inorganic material with after-treatment of the deposited inorganic material
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1633—Process of electroless plating
    • C23C18/1646—Characteristics of the product obtained
    • C23C18/165—Multilayered product
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    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/32—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer
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    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/34—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates
    • C23C28/345—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates with at least one oxide layer
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    • C25D3/00—Electroplating: Baths therefor
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    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
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    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
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    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/02—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition
    • C23C18/12—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material
    • C23C18/1204—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material inorganic material, e.g. non-oxide and non-metallic such as sulfides, nitrides based compounds
    • C23C18/1208—Oxides, e.g. ceramics
    • C23C18/1216—Metal oxides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/02—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition
    • C23C18/12—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by thermal decomposition characterised by the deposition of inorganic material other than metallic material
    • C23C18/125—Process of deposition of the inorganic material
    • C23C18/1254—Sol or sol-gel processing
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1633—Process of electroless plating
    • C23C18/1689—After-treatment
    • C23C18/1692—Heat-treatment
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/38—Coating with copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means

Definitions

  • the present disclosure relates to a wiring board in which wiring is formed on a substrate, a method for manufacturing the wiring board, and a semiconductor device including the wiring board.
  • a basic structure including a substrate and wiring provided thereon (hereinafter referred to as a wiring substrate) is usually used.
  • a wiring substrate not only functions as a semiconductor device itself, but also as a substrate for electrically connecting various electronic components, or as a substrate (interposer) for mounting the semiconductor device on an electronic device.
  • Various methods for providing a wiring on a substrate have been developed. For example, in the methods disclosed in Patent Documents 1 and 2, a film containing a metal oxide is provided between an insulating substrate and a wiring, thereby Improvement of adhesion between the substrate and the wiring is achieved.
  • One of the problems of the present disclosure is to provide a wiring board and a manufacturing method thereof.
  • one of the problems of the present disclosure is to provide a wiring board having high adhesion between the board and the wiring and a manufacturing method thereof.
  • one of the problems of the present disclosure is to provide a semiconductor device having this wiring board.
  • the wiring substrate includes a substrate including a first element, a diffusion layer including a first metal element in contact with the substrate, and a first metal film including a second metal element in contact with the diffusion layer.
  • the diffusion layer has a region including at least a first element and a first metal element, and a region including a first metal element and a second metal element.
  • One embodiment of the present disclosure is a method for manufacturing a wiring board.
  • the manufacturing method includes forming a first intermediate layer including an oxide of a first metal element on a substrate including the first element, and diffusing the first element into the first intermediate layer. Converting one intermediate layer into a second intermediate layer, forming a first metal film containing a second metal element on the second intermediate layer, and converting the second metal element into a second intermediate layer Converting the second intermediate layer into a diffusion layer by diffusing into the intermediate layer.
  • the typical sectional view of the wiring board concerning one of the embodiments and the schematic diagram of the concentration profile of the thickness direction of the wiring board.
  • the schematic diagram of the element concentration profile in the thickness direction of the wiring board which concerns on one of embodiment The schematic diagram of the element concentration profile in the thickness direction of the wiring board which concerns on one of embodiment.
  • the schematic diagram of the element concentration profile in the thickness direction of the wiring board which concerns on one of embodiment The schematic diagram of the element concentration profile in the thickness direction of the wiring board which concerns on one of embodiment.
  • the schematic diagram of the element concentration profile in the thickness direction of the wiring board which concerns on one of embodiment. 1 is a schematic cross-sectional view of a wiring board according to one embodiment.
  • the typical sectional view showing the manufacturing method of the wiring board concerning one of the embodiments The typical sectional view showing the manufacturing method of the wiring board concerning one of the embodiments.
  • the typical sectional view showing the manufacturing method of the wiring board concerning one of the embodiments. 1 is a schematic cross-sectional view of a semiconductor device including a wiring board according to one embodiment. 1 is a schematic cross-sectional view of a semiconductor device including a wiring board according to one embodiment. 1 is a schematic cross-sectional view of a semiconductor device including a wiring board according to one embodiment.
  • a structure is exposed from another structure means an aspect in which a part of a structure is not covered by another structure.
  • the part which is not covered with the structure includes an aspect covered with another structure.
  • the wiring substrate 100 includes a substrate 102, a diffusion layer 106 that is located on the substrate 102 and in contact with the substrate 102, and a first metal film 104 that is located on the diffusion layer 106 and is in contact with the diffusion layer 106.
  • the wiring board 100 may further include a second metal film 108 positioned on the first metal film 104 and in contact with the first metal film 104 as an arbitrary configuration.
  • the substrate 102 includes a first element.
  • the first element is an element selected from elements other than oxygen and included in the main component of the substrate 102.
  • a main component of a certain configuration is a component that occupies 90% by weight or more of the configuration.
  • a single crystal metal oxide such as a glass substrate, a quartz substrate, a semiconductor substrate including a semiconductor such as silicon, germanium, gallium arsenide, or gallium nitride, a ceramic substrate including a ceramic such as alumina or zirconia, or a sapphire substrate is used.
  • substrate etc. which are included are illustrated.
  • a resin may be combined.
  • the first element is selected from silicon, germanium, aluminum, zirconium, arsenic, nitrogen, and the like.
  • glass substrates are preferable when the wiring substrate 100 is used as an interposer of a semiconductor device because it can be obtained at low cost and exhibits excellent insulation.
  • the glass contained in the glass substrate include soda lime glass, fluoride glass, phosphate glass, and borate glass.
  • the surface roughness of the substrate 102 is not limited, and may be, for example, 0.1 nm or more, 1 nm or more, 5 nm or more.
  • the surface roughness of the substrate 102 may be 200 nm or less, 100 nm or less, or 50 nm or less.
  • the surface roughness of the substrate 102 may be 0.1 nm to 200 nm, 1 nm to 100 nm, 5 nm to 50 nm.
  • the surface roughness may be measured using, for example, an optical interference microscope. When a relatively thin wiring is provided on the substrate 102, the surface roughness of the substrate 102 is reflected on the surface.
  • the surface roughness of the substrate 102 By adjusting the surface roughness of the substrate 102 to the above-described range, the surface roughness of the wiring is reflected. The increase in height is also suppressed. For this reason, when the wiring board 100 is applied to a high frequency circuit board, transmission loss can be reduced. Further, when the wiring is processed by photolithography, scattering of light from the exposure machine can be suppressed, and the fine processing of the wiring can be prevented from being hindered.
  • the surface roughness can be evaluated by an arithmetic average roughness Ra, which is a parameter represented by the following equation.
  • L is the measurement length on the substrate 102 to be evaluated
  • f (x) is the height when the measurement length direction is x
  • Ra is an average of the absolute value of the height in the measurement length by the measurement length.
  • An example of a method for measuring the arithmetic average roughness Ra is as follows. First, a plurality of arbitrary measurement areas on the substrate 102 are selected. The size of the measurement region may be a square of, for example, 0.30 mm ⁇ 0.22 mm. For example, the four corners on the substrate 102 and the five points at the center may be selected as the measurement region. Next, two arbitrary points are set in each of the plurality of regions. The distance between the two points is 0.1 mm, which corresponds to the measurement length L. The arithmetic average roughness Ra between the two points is measured, and the average of the arithmetic average roughness Ra obtained in a plurality of measurement regions is adopted as the surface roughness of the substrate 102.
  • the average of the five measurement results is the surface roughness of the substrate 102.
  • a plurality of measurements may be performed in each measurement region, and the average may be adopted as the arithmetic average roughness Ra in one measurement region.
  • the arithmetic average roughness Ra can be measured using, for example, a 3D optical profiler using a white interferometer (for example, 3D optical profiler Zygo New View 5000 manufactured by Zygo).
  • the first metal film 104 includes a zero-valent metal element (second metal element), and various wirings (not shown) provided as wiring of the wiring substrate 100 or on the second metal film 108 or the wiring substrate 100. No) can function as a seed layer for forming by electroplating.
  • the second metal element include copper, titanium, chromium, nickel, and gold.
  • limiting in the thickness of the 1st metal film 104 For example, they are 0.5 micrometer or more, 1 micrometer or more, or 5 micrometers or more, and can be 50 micrometers or less, 30 micrometers or less, or 20 micrometers or less.
  • the thickness of the first metal film 104 may be 0.5 ⁇ m or more and 50 ⁇ m or less, 1 ⁇ m or more and 30 ⁇ m or less, or 5 ⁇ m or more and 20 ⁇ m or less. By setting the thickness of the first metal film 104 within this range, it is possible to ensure sufficient conductivity as a wiring. For example, even when the first metal film 104 is formed by a plating method, the first metal film 104 can be formed in a short time. Even when the first metal film 104 is formed by photolithography, microfabrication can be easily performed. .
  • the diffusion layer 106 has a function of firmly bonding the first metal film 104 to the substrate 102 and is therefore also called an adhesion layer.
  • the diffusion layer 106 is generated by mutual diffusion of an intermediate layer provided between the first metal film 104 and the substrate 102.
  • the intermediate layer includes a first metal element.
  • the intermediate layer includes an oxide or nitride of a first metal, and examples of the first metal include zinc, titanium, zirconium, aluminum, and tin.
  • a region including the first metal in the intermediate layer is a diffusion layer 106.
  • the thickness of the diffusion layer 106 may be 1 nm or more.
  • the diffusion layer 106 can follow the surface roughness of the substrate 102, and not only can ensure high adhesion between the first metal film 104 and the substrate 102, but also the fineness at the same time as the first metal film 104. Processing can be performed.
  • the thickness of the diffusion layer 106 may be 1 ⁇ m or less, 100 nm or less, 20 nm or less, or 10 nm or less.
  • the thickness of the diffusion layer 106 may be 1 nm to 1 ⁇ m, 1 nm to 100 nm, 1 nm to 20 nm, or 1 nm to 10 nm.
  • the diffusion layer 106 can be formed in a short time, and an etching residue does not remain on the substrate 102 during processing such as etching, so that adjacent wirings can be reliably insulated.
  • the thickness of the diffusion layer 106 may be set in the range of 10 nm to 20 nm.
  • the diffusion layer 106 further includes a first element contained in the substrate 102 and a second metal element contained in the first metal film 104 in addition to the first metal element. More specifically, the diffusion layer 106 includes a region where the first element, the first metal element, and the second metal element coexist, a region where the first metal element and the first element coexist, It includes at least one of the regions where the first metal element and the second metal element coexist. For example, the diffusion layer 106 may have a region containing the first metal element and the first element, and a region containing the first metal element and the second metal element.
  • the thickness of the diffusion layer 106 does not necessarily match the thickness of the intermediate layer, and can be defined as the thickness of the portion where at least one of the three regions exists.
  • the thickness in this case can be measured by energy dispersive X-ray (EDX) analysis.
  • EDX energy dispersive X-ray
  • FIB focused ion beam
  • An electron beam is irradiated from the substrate 102 side so as to scan the interface, and characteristic X-rays are detected using a Si drift detector or the like.
  • the atomic composition fraction (atomic%) of each element is obtained based on the characteristic X-ray intensity. Thereby, an element distribution in the depth direction is obtained, and the region is specified.
  • the thickness of the diffusion layer 106 can be obtained by calculating the thickness of the portion where at least one of these regions exists.
  • FIG. 1B schematically shows concentration profiles of the first element, the first metal element, and the second metal element in the thickness direction of the wiring substrate 100.
  • the vertical axis indicates the normalized element concentration (that is, the first element, the first metal element, and the second metal element per unit volume).
  • the horizontal axis represents the depth of the wiring board 100. The depth is a distance from the upper surface of the first metal film 104 in the direction toward the substrate 102 along the normal line of the upper surface of the first metal film 104.
  • the concentration 102a of the first element decreases as it approaches the first metal film 104 from the interface 103 between the substrate 102 and the diffusion layer 106 in the thickness direction.
  • the concentration 104 a of the second metal element decreases as the distance from the interface 105 between the diffusion layer 106 and the first metal film 104 approaches the substrate 102 in the thickness direction.
  • These concentration changes may be continuous.
  • the interface 103 is located between a region where the first metal element is not present or substantially undetectable and a region where the first metal element is present or is detectable, and This surface is closer to the substrate 102 than the metal film 104.
  • the interface 105 is located between a region where the first metal element is not present or substantially undetectable and a region where the first metal element is present or is detectable, and is located more than the substrate 102. 1 is a surface close to the metal film 104 (see FIG. 1B). Between the interfaces 103 and 105 is a diffusion layer 106, and the plot with respect to the depth of the concentration 106a of the first metal element gives at least one peak in the diffusion layer 106 (FIG. 1B).
  • the plot of the concentration 104a of the second metal element with respect to the depth of the wiring substrate 100 is a plot of the first element with respect to the depth (FIG. 1B).
  • Crosses the broken line in the middle Note that the concentration 102a of the first element, the concentration 106a of the first metal element, and the concentration 104a of the second metal element can be measured by, for example, EDX analysis.
  • the concentration 104 a of the second metal element decreases as it approaches the substrate 102 in the diffusion layer 106 and becomes substantially undetectable at the interface 103.
  • the concentration 102 a of the first element decreases as it approaches the first metal film 104 in the diffusion layer 106 and becomes substantially undetectable at the interface 105.
  • the first element, the first metal element, and the second metal element coexist throughout the entire diffusion layer 106.
  • the concentration profile of the first element and the second metal element in the diffusion layer 106 is not limited to that shown in FIG.
  • the diffusion layer 106 may have a region 106b on the interface 105 side where the first element does not exist or is substantially undetectable.
  • the diffusion layer 106 may have a region 106c on the interface 103 side where the second metal element does not exist or cannot be substantially detected.
  • the second metal element may be included not only in the diffusion layer 106 but also in the substrate 102.
  • the concentration 104 a of the second metal element in the substrate 102 decreases as the distance from the interface 103 increases.
  • the first element may be included not only in the diffusion layer 106 but also in the first metal film 104 (FIG. 3B). In this case, the concentration 102 a of the first element in the first metal film 104 decreases as the distance from the interface 105 increases.
  • the diffusion layer 106 may be configured such that the above-described concentration profiles are combined.
  • the diffusion layer 106 may have both the region 106b and the region 106c on the interface 105 side and the 103 side, respectively.
  • a region where the first element, the first metal element, and the second metal element coexist in the diffusion layer 106 is sandwiched between the regions 106b and 106c.
  • the diffusion layer 106 may have a region 106c, and the first element may be included not only in the diffusion layer 106 but also in the first metal film 104.
  • the diffusion layer 106 may include the region 106 b and the second metal element may be included in the substrate 102 as well as the diffusion layer 106.
  • the first element is included not only in the diffusion layer 106 but also in the first metal film 104, and the second metal element is included in not only the diffusion layer 106 but also the substrate 102. May be.
  • the plot of the concentration 104a of the second metal element against the depth of the wiring substrate 100 intersects the plot of the concentration of the first element against the depth. Therefore, in any region of the diffusion layer 106, in addition to the first metal element, at least one of the first element and the second metal element is included, and the first metal element and the first metal element are included although the first metal element is included. There is no region where both of the two metal elements are not included.
  • the substrate 102 of the wiring substrate 100 may have a through hole 110.
  • the diffusion layer 106 and the first metal film 104 are provided so as to cover the upper and lower surfaces of the substrate 102 and the side wall of the through hole 110.
  • the second metal film 108 provided as an arbitrary configuration may also be disposed so as to cover the upper and lower surfaces of the substrate 102 and the side wall of the through hole 110.
  • the filler 112 may be formed so as to fill the through hole 110.
  • the filler 112 include organic compounds such as epoxy resin, acrylic resin, polyimide, polyamide, and polyester.
  • An inorganic material such as silicon oxide may be mixed in the organic compound.
  • the second metal film 108 or the first metal film 104 may be provided so as to close the through hole 110.
  • the first metal film 104 or the stack of the first metal film 104 and the second metal film 108 is used for electrically connecting various elements and semiconductor devices mounted on the substrate 102. It can function as a through wiring.
  • the diffusion layer 106 is a film having a region which is substantially composed only of the oxide of the first element. Compared with, it has high etching resistance. Therefore, the diffusion layer 106 exhibits an etching rate comparable to that of the first metal film 104, and when the first metal film 104 is etched, the diffusion layer 106 located under the first metal film 104 is etched (side Etching) is less likely to occur.
  • the diffusion layer 106 has a region in which the first element, the first metal element, and the second metal element coexist, the intermediate layer does not exist by itself, so that such side etching is prevented. High adhesive strength can be expressed. As a result, the phenomenon in which the first metal film 104 is separated from the substrate 102 can be effectively suppressed, and a highly reliable wiring substrate and a semiconductor device including the wiring substrate can be provided.
  • a first intermediate layer 120 serving as a precursor of the diffusion layer 106 is formed on the substrate 102-1 (FIG. 7, S1).
  • the first intermediate layer 120 includes an oxide of the first element, and is formed by a sputtering method, a physical vapor deposition (PVP) method such as electron beam evaporation or vacuum evaporation, or a sol-gel method.
  • PVP physical vapor deposition
  • sol-gel method a metal alkoxide such as tetraethylzinc, tetraethoxytitanium, tetraethoxyzirconium or the like is used as a raw material, and a solution or mixture containing this is prepared by spin coating, dip coating, printing, etc.
  • the first intermediate layer 120 is formed by coating on the substrate 102-1 and then hydrolyzing the metal alkoxide.
  • the thickness of the first intermediate layer 120 may be 5 nm or more, and may be 20 nm or 15 nm or less.
  • the thickness of the first intermediate layer 120 may be 5 nm to 20 nm, or 5 nm to 15 nm.
  • the thickness of the intermediate layer can be measured by a thin film calibration curve method. Specifically, first, a metal thin film having a known thickness and containing a metal contained in the intermediate layer 120 is used as a standard sample, and the fluorescent X-ray intensity obtained by irradiating the thin film with X-rays is measured. Using a plurality of samples having different thicknesses, a calibration curve showing the relationship between the thickness and the fluorescent X-ray intensity is prepared. Next, the same measurement is performed on the intermediate layer 120 formed on the substrate 102, and the thickness is estimated from the obtained fluorescent X-ray intensity using a calibration curve.
  • this measurement it is possible to adopt a value obtained by measuring in a plurality of regions of the intermediate layer 120 and averaging the thicknesses obtained in the respective regions and the thickness of the intermediate layer 120.
  • the plurality of regions for example, five regions at the four corners and the center of the substrate 102 can be selected.
  • the measuring apparatus there is a Seiko Instruments fluorescent X-ray analyzer SFT9450 in which both a semiconductor detector and a proportional counter are mounted as detectors and a 0.1 mm diameter collimator is mounted.
  • the thickness of the intermediate layer 120 is measured according to the method described above under the conditions of a tube current of 1500 ⁇ A and a measurement time of 30 seconds.
  • heat treatment is performed on the substrate 102-1 and the first intermediate layer 120 formed thereon, and the first element contained in the substrate 102-1 is diffused into the first intermediate layer 120.
  • the heat treatment is, for example, 100 ° C. or higher, 200 ° C. or higher, 250 ° C. or higher, or 350 ° C. or higher, and may be performed at a temperature set from a temperature range of 700 ° C. or lower, 600 ° C. or lower, or 550 ° C. or lower. This temperature range may be 100 ° C. or higher and 700 ° C. or lower, 200 ° C. or higher and 700 ° C. or lower, 250 ° C. or higher and 600 ° C. or lower, or 350 ° C. or higher and 550 ° C.
  • the heating time may be, for example, 10 minutes or more, 15 minutes or more, or 30 minutes or more, and may be 5 hours or less, or 2 hours or less. A typical heating time is 1 hour.
  • the heating time may be 10 minutes to 5 hours, 15 minutes to 5 hours, or 30 minutes to 2 hours.
  • the first intermediate layer 120 is converted into the second intermediate layer 122 containing the first metal element and the first element (FIG. 7, S2). At least a part of the first metal element exists as an oxide.
  • the substrate 102-1 and the first intermediate layer 120 are converted into the substrate 102-2 and the second intermediate layer 122 by mutual diffusion, respectively.
  • a metal film 104-1 is formed on the second intermediate layer 122.
  • the second intermediate layer 122 is formed by, for example, an electroless plating method, a sputtering method, a chemical vapor deposition (CVD) method including a metal organic chemical vapor deposition (MOCVD) method, a PVD method such as vacuum deposition or electron beam deposition, or the like. do it.
  • the temperature at this time is room temperature (20 ° C. or higher and 25 ° C. or lower) or room temperature or higher, and can be performed at a temperature of 100 ° C. or lower or 50 ° C. or lower (FIG. 7, S3).
  • the temperature at which the metal film 104-1 is formed may be room temperature to 100 ° C., or room temperature to 50 ° C.
  • heat treatment is performed again to diffuse the first metal contained in the metal film 104-1 into the second intermediate layer 122.
  • the temperature and time of the heat treatment can be appropriately selected from the ranges described above.
  • the first element contained in the substrate 102 may further diffuse into the second intermediate layer 122.
  • the second intermediate layer 122 is converted into the diffusion layer 106 having the concentration profile described in the first embodiment (FIG. 7, S4).
  • the metal film 104-1 after interdiffusion with the second intermediate layer 122 is referred to as the first metal film 104.
  • the second metal film 108 may be formed over the first metal film 104.
  • the second metal film 108 can be formed by a sputtering method, a CVD method, a PVD method, or the like. Alternatively, the second metal film 108 may be formed by using the first metal film 104 as a seed layer and supplying power to the first metal film 104.
  • the through-hole 110 is provided in the substrate 102 (FIG. 8, S10).
  • the through hole 110 may be formed by etching such as plasma etching or wet etching, laser irradiation, or mechanical processing such as sand blasting or ultrasonic drilling. If necessary, the substrate 102 may be treated with hydrofluoric acid after the through hole 110 is formed, and the upper and lower surfaces of the substrate 102 and the side wall of the through hole 110 may be planarized.
  • the first intermediate layer 120 is formed so as to cover the upper and lower surfaces of the substrate 102 and the side wall of the through hole 110 (FIG. 8, S11). Thereafter, the first intermediate layer 120 is converted into the second intermediate layer 122 by the heat treatment described above (FIG. 8, S12), and the metal film 104-1 is formed on the second intermediate layer 122 (FIG. 8, S13). Thereafter, the heat treatment described above is performed to convert the second intermediate layer 122 into the diffusion layer 106 (FIG. 9, S14).
  • the second metal film 108 is formed on part of the upper surface and the lower surface of the substrate 102.
  • a resist mask 124 is provided on the first metal film 104 so as to cover a region where the second metal film 108 is not provided.
  • the resist mask 124 may be formed by applying and curing a liquid resist.
  • the substrate 102 has the through holes 110, a film-like resist is attached to the upper surface and the lower surface of the substrate 102, and then The resist mask 124 can be efficiently formed by performing exposure and development.
  • the second metal film 108 is formed on the first metal film 104 exposed from the resist mask 124 (FIG. 9, S16).
  • the resist mask 124 is removed (FIG. 10, S17), and the first metal film 104 and the diffusion layer 106 exposed from the second metal film 108 are removed by etching (FIG. 10, S18).
  • Etching can be performed using an etchant containing an acid such as sulfuric acid.
  • the diffusion layer 106 of the present disclosure exhibits an etching rate comparable to that of the first metal film 104, side etching of the diffusion layer 106 also occurs in the etching process (S18) of the first metal film 104. Not or very slow. Therefore, a sufficient contact area can be provided between the first metal film 104 and the substrate 102 via the diffusion layer 106. As a result, peeling of the first metal film 104 and the second metal film 108 can be effectively prevented.
  • a semiconductor device 130 shown in FIG. 11 includes a main substrate 132 and a plurality of wiring substrates 100 (wiring substrates 100-1, 100-2, 100-3) stacked thereon.
  • the number of wiring boards 100 is not limited and is determined according to the performance required for the semiconductor device 130.
  • Various semiconductor chips memory device, central processing unit
  • semiconductor elements such as micro electro mechanical system (MEMS)
  • FIG. 11 shows an example in which the central processing unit 133 is installed on the main board 132.
  • the wiring substrate 100 functions as a through wiring, and the second metal film 108 and the first metal film 104 (hereinafter, these are connected together) provided on the upper surface and the lower surface of the substrate 102.
  • connection wiring 134 contributes to the vertical electrical connection in the semiconductor device 130.
  • the connection wiring 134 of the lowermost wiring substrate 100-1 is electrically connected to a terminal 138 provided on the main substrate 132 via the bump 136-1 through a via hole or wiring disposed between the interlayer insulating layers 142, 142. Connected.
  • the connection wiring 134 provided on the wiring substrate 100-1 is electrically connected to the wiring substrate 100-2 through the bump 136-2 through a via hole or wiring provided between the interlayer insulating layers 139 and 140. .
  • the wiring board 100-2 and the wiring board 100-3 are also electrically connected via the bump 136-3.
  • the bump 136 includes a metal such as indium, copper, or gold, or an alloy such as solder.
  • the stacked wiring boards 100 may have different sizes and shapes, and the number of wiring boards 100 stacked on the main board 132 may also be different.
  • two wiring boards 100-4 and 100-5 are stacked in some areas, and three wiring boards 100-1, 100-2, and 100-3 are stacked in some areas. Has been.
  • the semiconductor device 160 shown in FIG. 13 has a structure in which a plurality of semiconductor chips 162-1 and 162-2 are stacked on the main substrate 132 with the wiring substrate 100 interposed therebetween. Terminals 164 and 166 are formed on the semiconductor chips 162-1 and 162-2, respectively, and these are electrically connected to the connection wiring 134 of the wiring board 100-1 via the bumps 168.
  • the semiconductor chip include a driving chip for the semiconductor chip 162-1 and a memory chip for the semiconductor chip 162-2.
  • the semiconductor chips 162-1 and 162-2 are electrically connected to each other.
  • the semiconductor chip 162-2 and the main substrate 132 may be electrically connected by the wire wiring 170.
  • 11 to 13 show that the connection wiring 134 is directly connected to the bumps 136 and 168, but other wiring such as a lead wiring is provided between the bumps 136 and 168 and the connection wiring 134. Also good.
  • Example 1 In this example, the results of analysis of elements contained in the wiring board 100 manufactured according to the manufacturing method described in the second embodiment will be described.
  • the structure of the wiring substrate 100 is as shown in FIG. 1 (A), and a specific manufacturing method is as follows.
  • a film containing zinc oxide was formed on a glass substrate (30 cm ⁇ 40 cm, thickness 0.5 mm, surface roughness 5 nm) by a sol-gel method to form a first intermediate layer 120 (thickness 15 nm).
  • middle layer 120 was converted into the 2nd intermediate
  • an electroless plating method was applied to form a copper film (thickness: 0.5 ⁇ m) on the second intermediate layer 122 as the first metal film 104. Thereafter, heating was performed again at 450 ° C. for 1 hour, and the second intermediate layer 122 was converted into the diffusion layer 106.
  • the first metal film 104 was formed directly on the substrate without forming the first intermediate layer 120.
  • a sample was also made. Each of these samples corresponds to samples 8 to 10 in Table 1 described later, and is a sample that does not have the diffusion layer 106.
  • Elemental analysis was performed by EDX from the substrate 102 side so that the cross-section was exposed by processing the wiring substrate 100 after heating using FIB and the interface between each layer was scanned.
  • the obtained characteristic X-ray intensity was converted into an atomic composition fraction, and the element distribution in the depth direction was evaluated.
  • a measuring device a transmission electron microscope (manufactured by Hitachi High-Technologies, model number: HD-2700) equipped with an elemental analyzer is used, and an electron beam with a beam diameter of about 0.2 nm is irradiated onto the wiring substrate 100 at an acceleration voltage of 200 kV.
  • the generated characteristic X-rays were detected using a Si drift detector.
  • As an elemental analyzer EMAX Evolution manufactured by HORIBA, Ltd. was used. The energy resolution was about 130 eV, the X-ray extraction angle was 24.8 °, and the solid angle was 2.2 sr.
  • the number of capture points was 100, and each capture time was 1 second.
  • FIG. 14 shows changes in the concentrations of zinc, silicon, and copper with respect to the depth of the wiring board 100.
  • zinc cannot be substantially detected in a region having a depth of 0 nm to 35 nm and a region deeper than 50 nm. Therefore, it can be seen that the interface 103 between the substrate 102 and the diffusion layer 106 and the interface 105 between the diffusion layer 106 and the first metal film 104 are located at a depth of 35 nm and 50 nm, respectively.
  • the plot of the concentration of zinc contained in the diffusion layer 106 was confirmed to show one peak in the diffusion layer 106.
  • FIG. 14 shows that the concentration of silicon, which is the first element contained in the substrate 102, decreases as it approaches the first metal film 104 from the interface 103. Similarly, it is understood that the concentration of copper contained in the first metal film 104 also decreases as it approaches the substrate 102 from the interface 105. From the above, it was confirmed that the diffusion layer 106 contains zinc as the first metal element, and also contains silicon as the first element and copper as the second metal element. Further, in the diffusion layer 106, the concentration plots of silicon and copper with respect to depth intersect each other. From this, it was found that the diffusion layer 106 includes at least one of the first element and the second metal element in addition to the first metal element in any region.
  • Example 2 In this example, the result of evaluating the effect of the diffusion layer 106 on the adhesive force between the substrate 102 and the first metal film 104 is shown.
  • Example 2 Power was supplied to the first metal film 104 of the wiring substrate 100 manufactured in Example 1, and a copper film (thickness 3 ⁇ m) was formed as the second metal film 108 by electrolytic plating.
  • the thickness of the first intermediate layer 120 was 15 nm
  • the heating temperature after the second metal film 108 was formed was changed, and the effect of the diffusion layer 106 was evaluated.
  • Samples 8 to 10, that is, a wiring board without the diffusion layer 106 were also evaluated as comparative examples.
  • the effect of the diffusion layer 106 on the adhesion between the first metal film 104 and the substrate 102 was evaluated by a tape peel test and an etching test.
  • the former is a method in which an adhesive tape based on polyimide (manufactured by Nitto Denko Corporation, model number: polyimide adhesive tape for heat-resistant insulation No. 360UL) is attached to the second metal film 108, and then the adhesive tape is peeled off. It was evaluated by observing. The latter was performed by etching the wiring substrate 100 and visually confirming whether or not the first metal film 104 or the second metal film 108 was peeled off during the etching. Etching was performed using 1% ammonium persulfate as an etchant at 23 ° C. for 1 min.
  • the heating temperature after forming the second metal film 108 is 450 ° C. Even peeling was observed in the tape peel test.
  • a finely processed wiring is formed on a substrate having a surface roughness such that the anchor effect is not expected, that is, a substrate with extremely high surface flatness. Is possible. This contributes to the manufacture of a wiring board such as a high-frequency circuit board that requires high flatness of wiring.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Electrochemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Thermal Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Chemically Coating (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
PCT/JP2019/012249 2018-03-28 2019-03-22 配線基板、および配線基板を製造する方法 Ceased WO2019188843A1 (ja)

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JP2020509993A JP7468342B2 (ja) 2018-03-28 2019-03-22 配線基板、および配線基板を製造する方法
CN201980020134.0A CN111868301A (zh) 2018-03-28 2019-03-22 布线基板以及制造布线基板的方法
CN202311150946.1A CN117320265A (zh) 2018-03-28 2019-03-22 布线基板、半导体装置以及布线基板的制作方法
KR1020207027438A KR102720915B1 (ko) 2018-03-28 2019-03-22 배선 기판, 및 배선 기판을 제조하는 방법
KR1020247034782A KR20240159006A (ko) 2018-03-28 2019-03-22 배선 기판
US17/011,260 US12028972B2 (en) 2018-03-28 2020-09-03 Wiring board and manufacturing method of the wiring board
US18/381,789 US20240049384A1 (en) 2018-03-28 2023-10-19 Wiring board
JP2024008072A JP7666668B2 (ja) 2018-03-28 2024-01-23 配線基板
JP2025064481A JP2025103022A (ja) 2018-03-28 2025-04-09 配線基板

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TW202401528A (zh) 2024-01-01
US20200404781A1 (en) 2020-12-24
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