WO2019184416A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2019184416A1
WO2019184416A1 PCT/CN2018/118516 CN2018118516W WO2019184416A1 WO 2019184416 A1 WO2019184416 A1 WO 2019184416A1 CN 2018118516 W CN2018118516 W CN 2018118516W WO 2019184416 A1 WO2019184416 A1 WO 2019184416A1
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WIPO (PCT)
Prior art keywords
touch
lines
conductor
touch signal
line
Prior art date
Application number
PCT/CN2018/118516
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English (en)
French (fr)
Inventor
武新国
王凤国
史大为
刘弘
王子峰
李峰
马波
郭志轩
李元博
段岑鸿
赵晶
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US16/473,718 priority Critical patent/US20210333968A1/en
Publication of WO2019184416A1 publication Critical patent/WO2019184416A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes

Definitions

  • the present disclosure relates to the field of display, for example, to an array substrate, a method of manufacturing the same, and a display device.
  • a touch product such as a touch and display driver integration (TDDI)
  • TDDI touch and display driver integration
  • An array substrate includes a display area and a peripheral circuit area, and the array substrate further includes:
  • any one of the touch electrodes is connected to the at least one first conductor line in the thickness direction thereof, the touch electrode is connected to the at least one touch signal line, and the at least one touch signal line is connected to the at least one second conductor line. And the at least one second conductor line connecting the at least one first conductor line.
  • any one of the touch electrodes is connected to the peripheral circuit area through the at least one touch signal line;
  • the plurality of first conductor lines include at least one invalid touch signal line, wherein the at least one invalid touch signal line is in the same strip as any one of the plurality of touch signal lines except one of the plurality of touch signal lines Conductor lines on a straight line.
  • the array substrate includes a plurality of rows of gate lines and a plurality of columns of data lines, wherein the plurality of second conductor lines and the plurality of rows of gate lines are formed in a same patterning process, and A plurality of first conductor lines, the plurality of touch signal lines, and the plurality of columns of data lines are formed in the same patterning process.
  • the array substrate includes an insulating layer, wherein the plurality of rows of gate lines and the plurality of columns of data lines are respectively located on opposite sides of the insulating layer in a thickness direction, and the insulating layer is disposed in the insulating layer
  • the first via, and each of the second conductor lines connect the corresponding first conductor line and the corresponding touch signal line through the first via.
  • the array substrate includes an insulating layer, wherein the plurality of touch signal lines and the plurality of touch electrodes are respectively located on opposite sides of the insulating layer in a thickness direction;
  • a plurality of second via holes are disposed in the insulating layer, and each of the touch signal lines is connected to the corresponding touch electrodes through the at least one second via hole, and each of the first conductor lines passes through the at least one second via hole and corresponds to Touch electrode connection;
  • the plurality of touch signal lines and the plurality of first conductor lines are formed in the same patterning process
  • the plurality of touch signal lines, the plurality of first conductor lines, and the plurality of second conductor lines are all formed in the same patterning process.
  • the display area includes a plurality of rows and columns of pixel open areas, each touch signal line is located between adjacent two columns of pixel open areas, and each of the first conductive lines is located in two adjacent columns. Between the pixel open areas, and each of the second conductor lines are located between adjacent two rows of pixel open areas.
  • all of the first conductor lines connected to one touch electrode are located in an area where the touch electrode is located;
  • a second conductor line connected to all of the first conductor lines connected to the touch electrode is located in a region where the touch electrode is located.
  • the number of the second conductor lines connected to all the first conductor lines connected to one touch electrode is one, and the second conductor lines are located at the center of the area where the touch electrodes are located;
  • the number of the second conductor lines connected to all the first conductor lines connected to one touch electrode is two, and one of the two second conductor lines is located at the first edge of the area where the touch electrode is located. And the other of the two second conductor lines is located at a second edge of the area where the touch electrode is located.
  • a display device includes the array substrate of any of the above.
  • a method of manufacturing an array substrate comprising:
  • the array substrate includes a display area and a peripheral circuit area, the plurality of touch electrodes are located in the display area, and the plurality of touch signal lines are the plurality of touch a control electrode is connected to the peripheral circuit area;
  • any one of the touch electrodes is connected to the at least one first conductor line in the thickness direction thereof, the touch electrode is connected to the at least one touch signal line, and the at least one touch signal line is connected to the at least one second conductor line. And the at least one second conductor line connecting the at least one first conductor line.
  • 1 is a schematic structural diagram of an array substrate provided by some embodiments.
  • FIG. 2 is a schematic diagram of internal wiring of a display area of an array substrate provided by some embodiments
  • FIG. 3 is a schematic cross-sectional view of an array substrate provided at a first via hole according to some embodiments
  • FIG. 4 is a schematic cross-sectional view of an array substrate provided at some second via holes according to some embodiments
  • FIG. 5A is a schematic diagram of touch wiring of an array substrate according to some embodiments.
  • FIG. 5B is a schematic diagram of touch wiring of an array substrate according to another embodiment
  • FIG. 6 is a schematic diagram of touch wiring of an array substrate provided by other embodiments.
  • FIG. 7 is a schematic diagram of touch wiring of an array substrate provided by other embodiments.
  • FIG. 8 is a schematic diagram of touch wiring of an array substrate according to another embodiment.
  • FIG. 9 is a schematic diagram of touch wiring of an array substrate provided by other embodiments.
  • FIG. 10 is a schematic flow chart of a method for fabricating an array substrate according to some embodiments.
  • FIG. 11 is a schematic structural diagram of a display device according to some embodiments.
  • connection refers to an electrical connection. In some embodiments, the connection is a direct or indirect connection.
  • a touch product using TDDI In a touch product using TDDI, it is easy to cause poor touch due to excessive resistance of the transparent touch electrode and low signal strength of the touch signal received by the touch electrode.
  • the touch electrodes In a touch product using TDDI, for example, in a display area covering 5 mm ⁇ 5 mm, the touch electrodes generally pass the collected touch signals to the external chip through metal leads, because the number of metal leads is limited by the aperture ratio.
  • the touch signals generated on the touch electrodes at a position farther away from the metal leads have a relatively large signal attenuation during the transmission process. Therefore, the local touch signal is easily covered by noise, resulting in a touch. Poor control.
  • FIG. 1 is a schematic structural view of an array substrate provided by some embodiments.
  • the array substrate includes a display area A1 and a peripheral circuit area A2.
  • the array substrate further includes a plurality of touch electrodes 11 located in the display area A1.
  • the peripheral circuit area A2 in FIG. 1 is located on one side of the display area A1, and the plurality of touch electrodes 11 are arranged in a plurality of rows and columns in the display area A1.
  • the peripheral circuit area A2 is located on opposite sides of the display area A1.
  • the peripheral circuit area A2 is wrapped around the display area A1.
  • the plurality of touch electrodes 11 are arranged in a cell arrangement manner in any one of the planes.
  • the plurality of touch electrodes 11 are arranged in an inclined grid, a triangular mesh, or a diamond mesh.
  • the touch circuit 21 in the peripheral circuit area A2 is also shown in FIG. 1 , and the touch circuit 21 is configured to implement touch sensing by collecting electrical signals on the plurality of touch electrodes 11 .
  • the touch control circuit 21 is electrically connected to the plurality of touch electrodes 11, that is, the plurality of touch electrodes 11 are connected to the peripheral circuit area A2 through the plurality of touch signal lines 12.
  • the touch control circuit 21 is located on the display area A1 side, and the plurality of touch signal lines 12 extend in a direction from the display area A1 to the peripheral circuit area A2.
  • FIG. 2 is a schematic diagram of internal traces of a display area of an array substrate according to some embodiments of the present disclosure.
  • the array substrate includes the plurality of touch electrodes 11, the plurality of touch signal lines 12, the plurality of first conductor lines 13, the plurality of second conductor lines 14, the plurality of rows of gate lines 101, and the plurality of columns of data. Line 102.
  • FIG. 1 the array substrate includes the plurality of touch electrodes 11, the plurality of touch signal lines 12, the plurality of first conductor lines 13, the plurality of second conductor lines 14, the plurality of rows of gate lines 101, and the plurality of columns of data.
  • Line 102 As shown in FIG.
  • the plurality of touch signal lines 12 in the array substrate have the same extending direction, and each of the first conductor lines 13 extends in the same direction as the plurality of touch signal lines 12
  • the extending direction of each of the second conductor lines 14 is different from the extending direction of the plurality of touch signal lines 12.
  • each of the first conductor lines 13 is connected to the touch electrode 11 in the thickness direction of one touch electrode 11, and each second conductor line 14 corresponds to one touch electrode 11 and any second The conductor line 14 is connected to the touch signal line 12 to which the corresponding touch electrode 11 is connected, and any second conductor line 14 is connected to each of the first conductor lines 13 to which the corresponding touch electrode 11 is connected.
  • any of the touch electrodes 11 is connected to a plurality of first conductor lines 13 in a thickness direction thereof, and any one of the touch electrodes 11 is connected to a touch signal line 12, and the touch signal lines 12 are connected.
  • Each of the second conductor wires 14 and the second conductor wires 14 connected to the touch signal wires 12 are connected to the plurality of first conductor wires 13 connected to the touch electrodes 11 .
  • a plurality of first conductor lines 13 connected to any one of the touch electrodes 11 are located in the area of any one of the touch electrodes 11; and any one of the touch electrodes 11 is connected to a touch signal line.
  • the plurality of second conductor lines 14 connected to the touch signal line 12 are located in the area of any one of the touch electrodes 11.
  • the touch signal on the touch electrode 11 is not only directly transmitted to the touch signal line 12 but also through the first conductor line 13 and the first
  • the two conductor wires 14 are transmitted to the touch signal lines 12, and the resistance between the plurality of positions on the touch electrodes 11 and the touch signal lines 12 is also uniformized. That is, the above embodiment of the present disclosure increases the number of contact points between the touch signal line and the touch electrode, and reduces the resistance between the edge of the touch electrode and the touch signal line, thereby improving the touch.
  • the signal strength of the touch signal received by the electrode reduces the poor touch and improves the touch performance of the product.
  • the plurality of second conductor lines 14 and the plurality of rows of gate lines 101 are formed in the same patterning process, and the plurality of first conductor lines 13, the plurality of touch signal lines 12, and the plurality of columns of data lines 102 are the same time. Formed in the patterning process. As such, the second conductor line 14 and the gate line 101 are located in the same layer, and the first conductor line 13, the touch signal line 12, and the data line 102 are located in the same layer.
  • the array substrate further includes a first insulating layer 17, a plurality of rows of gate lines 101 (same layer as the second conductor lines 14), and a plurality of columns of data lines 102 (with the first conductor lines) 13 and the same layer of the touch signal line 12 are respectively located on both sides in the thickness direction of the first insulating layer 17.
  • the second conductor line 14 and the gate line GL are located on the first side of the first insulating layer, and the first conductor line 13, the touch signal line 12, and the data line 102 is located on a second side of the first insulating layer.
  • FIG. 3 is a schematic cross-sectional view of an array substrate provided at some first vias according to some embodiments.
  • Fig. 3 shows a cross-sectional view at the position indicated by the mark "15" in Fig. 2.
  • the array substrate includes a first insulating layer 17, and a first via 15 is disposed in the first insulating layer 17, and any one of the second conductive lines 14 is connected through the first via 15 The conductor line 13 and the touch signal line 12.
  • the touch signal line 12 and the second conductor line 14 are connected by the first via 15 at the intersection of the projections on the touch electrode 11 , and the first conductor line 13 and the second conductor line 14 pass through.
  • the first vias 15 at the intersections of the projections on the touch electrodes 11 are connected.
  • the array substrate further includes a second insulating layer, and the plurality of touch signal lines 12 and the plurality of touch electrodes 11 are respectively located on two sides of the second insulating layer in the thickness direction.
  • the touch electrode 11 is located on the side of the second insulating layer away from the first insulating layer.
  • the first conductive line 13 , the touch signal line 12 , and the data line 102 are located on the first side of the second insulating layer.
  • the control electrode 11 is located on the second side of the second insulating layer.
  • the plurality of touch electrodes 11 in the above example are common electrodes that provide a common voltage.
  • FIG. 4 is a schematic cross-sectional view of an array substrate provided at some second via holes according to some embodiments.
  • Figure 4 is a cross-sectional view showing the position indicated by the mark "16" in Figure 2.
  • the array substrate includes a second insulating layer 18, and the second insulating layer 18 is provided with a plurality of second vias 16, and any one of the touch signal lines 12 passes through the at least one second via 16 and the corresponding touch electrode. 11 is connected, and each of the first conductor lines 13 is connected to the corresponding touch electrode 11 through at least one second via hole 16 .
  • connection between the touch signal line 12 and the touch electrode 11 and the connection between the first conductor line 13 and the touch electrode 11 are all implemented by at least one second via 16 .
  • the second conductor line 14 is located on the first side of the first insulating layer 17, and the first conductor line 13 and the touch signal line 12 are located on the second side of the first insulating layer 17.
  • a first via 15 is provided in the first insulating layer 17, and the second conductor line 14 is connected to the corresponding first conductor line 13 through the first via 15.
  • the first conductor line 13 and the touch signal line 12 are located on the first side of the second insulating layer 18, and the touch electrode 11 is located on the second side of the second insulating layer 18.
  • a plurality of second via holes 16 are disposed in the second insulating layer 18, and the touch signal lines 12 are connected to the corresponding touch electrodes 11 through the second via holes 16.
  • the four touch signal lines 12 are respectively connected to the upper left, lower left, upper right, and lower right touch electrodes 11, and the touch electrodes 11 are connected to the corresponding touch signals through the second vias 16.
  • Line 12 In FIG. 2, in the order from left to right, the four touch signal lines 12 are respectively connected to the upper left, lower left, upper right, and lower right touch electrodes 11, and the touch electrodes 11 are connected to the corresponding touch signals through the second vias 16. Line 12.
  • each touch signal line 12 in the array substrate connects one touch electrode 11 to the peripheral circuit region, and electrically insulates the plurality of touch electrodes 11 while satisfying the requirements for the touch signal collection.
  • the touch signals on the different touch electrodes 11 are prevented from interfering with each other.
  • the row-direction projection range of each column of the touch electrodes 11 is at least accommodated in comparison with FIG. 1 and FIG.
  • the same number of touch signal lines 12 of the touch electrodes are arranged in parallel in the row to the projection range, that is, the size of the touch electrodes 11 , the line width of the touch signal lines 12 , and the arrangement of the touch signal lines 12 .
  • the spacing meets the corresponding constraints.
  • each touch signal line 12 leads the touch signals on the connected touch electrodes 11 to the peripheral circuit area along the column direction. A2, so that the row-direction projection range of each column of the touch electrodes 11 accommodates at least three touch signal lines 12 arranged in parallel in the row to the projection range.
  • the number of touch signal lines 12 in the projection range of each column of the touch electrodes 11 is not less than the total number of rows of the touch electrodes 11 .
  • the touch electrodes are connected to two or more touches. Signal line 12.
  • some touch electrodes 11 connect two touch signal lines 12
  • some touch electrodes connect three touch signal lines 12 .
  • the touch electrodes 11 disposed away from the touch circuit 21 are connected to more than one touch signal line 12 to compensate for the touch signals on the remote touch electrodes 11 away from the touch circuit 21 to some extent. Resistance drop.
  • the touch electrode 11 farthest from the touch circuit 21 is connected to at least two touch signal lines 12, and the touch electrode 11 closest to the touch circuit 21 is connected to a touch signal line 12.
  • the array substrate of FIG. 6 is simplified on the basis of the structure shown in FIG. 5A. As seen in FIG. 5A and FIG. 6, the array substrate after the simplified wiring is retained. The trace corresponding to the transmission path of the touch signal removes the trace of the touch signal line 12 that does not function to transmit the touch signal. Since this change is realized only by modifying the mask pattern corresponding to the conductor film layer where the touch signal line is located, it does not have a large influence on the original manufacturing process. In this way, the wiring space of the excess traces is advantageously omitted, and the redundant traces are prevented from causing short circuits or crosstalk.
  • FIG. 7 shows the structure of the array substrate after some embodiments are performed on the basis of the structure shown in FIG. 5A, and it is seen from FIG. 6 and FIG. 7 that the embodiment of the present disclosure is not completely removed.
  • the portion of the touch signal line 12 that does not function as a transmission is removed, but the trace between the adjacent two rows of touch electrodes 11 in the portion of the trace is removed (also by modifying the conductor film where the touch signal line is located)
  • the mask pattern corresponding to the layer is implemented, thereby advantageously utilizing the manufacturing process of the touch signal line 12 to form the first to facilitate the conduction of the touch signal from the touch electrode 11 to the touch signal line 12.
  • Conductor line 13 is
  • the first conductor line 13 directly separated from the touch signal line 12 is a conductor line which does not have any useful function without being connected by other connections (where "useful function" means a function of transmitting a signal).
  • useful function means a function of transmitting a signal.
  • a conductor line that is separated from the above-mentioned at least one touch signal line and is on the same straight line as any one of the touch signal lines is referred to as an invalid touch signal line.
  • the first conductor lines 13 are not necessarily all invalid touch signal lines (for example, the rightmost first conductor line 13 in the orthographic projection range of each touch electrode 11 in FIG. 7 is not an invalid touch signal line).
  • the first conductor line 13 indicated by the mark "13" in the region where the touch electrode 11 is located in the upper right direction in FIG. 2 is an invalid touch signal line.
  • the first conductor line 13 as shown in FIG. 7 needs to be connected to the corresponding touch electrode 11 and the corresponding touch signal line 12.
  • the manner of connecting the first conductor line 13 and the touch electrode 11 is implemented by referring to the connection manner of the touch signal line 12 and the touch electrode 11.
  • the second insulating layer is set as a connection touch.
  • the control signal line 12 and the second via hole 16 of the touch electrode 11 are disposed between the first conductor line 13 and the touch electrode 11 to realize the first conductor line 13 and the touch electrode without increasing the number of process steps.
  • the first conductor line 13 and the touch signal line 12 are electrically connected by the second conductor line 14 extending in the row direction.
  • a row direction is arranged at the center of each touch electrode 11 in the direction of the row.
  • An extended second conductor line 14 and the second conductor line 14 is connected to each of the intersecting first conductor lines 13 through the first via 15 (one of the touch electrodes electrically connected to the second conductor line 14
  • the first conductor line 13) and the touch signal line 12 are electrically connected, so that the first conductor line 13 can be connected to the Corresponding touch signal line 12.
  • the second conductor line 14 is formed separately from the inside of the array substrate as described above, and is formed in the same patterning process as the gate line 101 (refer to the double gate line design of the array substrate), or with the touch signal.
  • the line 12 and the first conductor line 13 are formed in the same patterning process, and the effects of improving the signal strength of the touch signal can be achieved.
  • the plurality of touch signal lines 12, the plurality of first conductor lines 13, and the plurality of second conductor lines 14 are formed in the same patterning process, which reduces the number of via holes and helps to improve the touch.
  • the signal strength of the signal is the same patterning process, which reduces the number of via holes and helps to improve the touch. The signal strength of the signal.
  • FIG. 2 An example of the arrangement of the two second conductor wires 14 is shown in Figs. 2 and 8, respectively.
  • the number of the second conductor lines 14 connected to all the first conductor lines 13 connected to one touch electrode 11 is two, and one of the two second conductor lines 14 is located at the touch electrode 11
  • the first edge of the region where the second conductor line 14 is located is located at the second edge of the region where the touch electrode 11 is located (the first edge and the second edge are in FIG. 2
  • the upper and lower edges of the touch electrode 11 the number of the second conductor lines 14 connected to all the first conductor lines 13 connected to one touch electrode 11 is one, and the second conductor lines 14 are located in the row direction of the area where the touch electrodes 11 are located.
  • the display area A1 includes a plurality of rows and columns of pixel opening areas A11, and each of the touch signal lines 12 is located between adjacent two columns of pixel opening areas A11, each of the first conductors.
  • the lines 13 are respectively located between the adjacent two columns of pixel opening areas A11, and each of the second conductor lines 14 is located between the adjacent two rows of pixel opening areas A11.
  • the touch signal line 12, the first conductor line 13, and the second conductor line 14 are all disposed within the area blocked by the black matrix 19, which reduces the influence on the display effect.
  • each touch signal line 12 is arranged in parallel with the data line 102 between adjacent two columns of pixel open areas, and each of the first conductive lines 13 is separated from one touch signal line 12.
  • the touch signal line 12, the first conductor line 13 and the data line 102 are all in the source-drain conductive layer of the array substrate.
  • each of the second conductor lines 14 is arranged in parallel with the gate lines 101 between adjacent two rows of pixel opening regions, and the second conductor lines 14 and the gate lines 101 are both in the gate conductive layer of the array substrate.
  • all the first conductor lines 13 connected to one touch electrode 11 are located in the area where the touch electrodes 11 are located, and are connected to all the first conductor lines 13 connected to one touch electrode 11 .
  • the two conductor lines 14 are located in the area where the touch electrodes 11 are located. In this way, the mutual interference of the touch signals on the adjacent touch electrodes 11 is avoided, and the touch performance is improved.
  • the above examples are all illustrative examples of the present disclosure.
  • the technical solution of the present disclosure can be applied to any of the solutions in which multiple touch electrodes are connected to the display area by using multiple touch signal lines.
  • the related arrangement of the first conductor line and the second conductor line increases the number of contact points between the touch signal line and the touch electrode, thereby improving the signal strength of the touch signal received through the touch electrode, thereby helping to reduce the correlation Poor touch, improve the touch performance of the product.
  • FIG. 10 is a schematic flow chart of a method for fabricating an array substrate according to some embodiments of the present disclosure, wherein the array substrate includes a display area and a peripheral circuit area. Referring to FIG. 10, the method includes steps 701 to 702.
  • step 701 a plurality of touch signal lines are formed.
  • the plurality of touch signal lines have the same extending direction.
  • step 702 a plurality of first conductor lines are formed.
  • the extending direction of the plurality of first conductor lines is the same as the plurality of touch signal lines.
  • step 703 a plurality of second conductor lines are formed.
  • the extending direction of the plurality of second conductor lines is different from the direction in which the plurality of touch signal lines extend.
  • step 704 a plurality of touch electrodes are formed.
  • the plurality of touch electrodes are located in the display area, and the plurality of touch signal lines connect the plurality of touch electrodes to the peripheral circuit area.
  • each of the first conductor lines is connected to the touch electrode in a thickness direction of one touch electrode; any second conductor line is connected to a touch signal line connected to the corresponding touch electrode Any second conductor line is connected to each of the first conductor lines to which the corresponding touch electrodes are connected.
  • the order of execution of the above steps 701 to 704 is not necessarily strictly as shown in FIG. In some embodiments, the order of execution of the various steps described above is adaptively adjusted in accordance with the location of each layer within the array substrate.
  • the number of contact points between the touch signal line and the touch electrode is increased, and the edge of the touch electrode and the touch signal line are reduced.
  • the resistance between the two increases the signal strength of the touch signal received through the touch electrode, reduces the poor touch, and improves the touch performance of the product.
  • the method of fabricating the above array substrate includes the following process.
  • a pattern including a gate conductive layer is formed on the base substrate.
  • the setting of parameters such as the thickness of the film layer is achieved by, for example, adjusting the relevant process parameters.
  • the patterning process of the metal material film distributed over the entire surface includes coating a layer of photoresist on the film of the metal material that has not been patterned, for example, by spin coating (here, positive lithography)
  • the photoresist is irradiated with ultraviolet light through a mask to completely expose the photoresist in the region to be etched, and then the entire structure is placed in the developer to be in the region to be etched by development.
  • the photoresist is completely removed, and the remaining photoresist is etched using the remaining photoresist as a mask, and the remaining photoresist is removed after the etching is completed.
  • the material for forming the gate conductive layer is, for example, a metal material including at least one element selected from the group consisting of iron, copper, aluminum, molybdenum, nickel, titanium, silver, zinc, tin, lead, chromium, and manganese, and is set according to a desired electrical conductivity. Component.
  • the gate conductive layer includes the gate line 101, the plurality of second conductor lines 14, and a gate electrode of a thin film transistor in the array substrate.
  • a gate insulating layer (as the first insulating layer 17) overlying the substrate and the gate conductive layer is deposited on the substrate substrate and the gate conductive layer by a chemical vapor deposition process (CVD).
  • CVD chemical vapor deposition process
  • the film thickness of the gate insulating layer satisfies the relevant requirements for the thickness of the gate insulating layer of the thin film transistor, and the setting of parameters such as the film thickness is achieved by, for example, means for adjusting the relevant process parameters.
  • a photoresist is applied on the first insulating layer on which the first via 15 has not been formed, for example, by spin coating (here, a positive photoresist is taken as an example), and ultraviolet light is used.
  • the light is irradiated through the mask plate to completely expose the photoresist in the region to be etched, and the exposed structure is placed in the developing solution to remove all the photoresist in the region to be etched by development.
  • the first insulating layer that has not formed the first via hole 15 is etched by using the remaining photoresist as a mask to form a pattern including the first via hole 15 in the first insulating layer, after the etching is completed The remaining photoresist is removed.
  • a pattern including an active layer is formed.
  • a layer of semiconductor material is formed over the first insulating layer and the layer of semiconductor material is patterned to form an active layer having the desired pattern.
  • the semiconductor material forming the active layer comprises amorphous silicon, polycrystalline silicon, single crystal silicon, or a metal oxide semiconductor, and at least a portion of the region is doped in accordance with characteristics of the thin film transistor to be implemented.
  • a pattern including a source-drain conductive layer is formed.
  • a source/drain conductive layer (source conductive layer and drain conductive layer) that has not been patterned, a film thickness, and the like are deposited on a first insulating layer and an active layer by a physical vapor deposition process using a metal material.
  • the setting is achieved by means such as adjusting the relevant process parameters.
  • the patterning process of the source-drain conductive layer distributed over the entire surface includes: coating a layer of photoresist on the source-drain conductive layer that has not been patterned, for example, by spin coating (here positive)
  • the photoresist is taken as an example.
  • the photoresist in the region to be etched is irradiated with ultraviolet light through the mask to expose it sufficiently, and the exposed structure is placed in the developer to be developed by the development.
  • the photoresist in the etched region is completely removed, and the remaining photoresist is used as a mask to etch the unpatterned source/drain conductive layer, and the remaining photoresist is removed after the etching is completed.
  • the material for forming the source-drain conductive layer is, for example, a metal material including at least one element selected from the group consisting of iron, copper, aluminum, molybdenum, nickel, titanium, silver, zinc, tin, lead, chromium, and manganese, and is set according to a desired electrical conductivity. Component.
  • the source/drain conductive layer includes the data line 102, the plurality of touch signal lines 12 and the plurality of first conductor lines 13, and source and drain electrodes of the thin film transistor. The connection between the second conductor line 14 and the touch signal line 12 and the connection between the second conductor line 14 and the first conductor line 13 are achieved by the first via 15.
  • a second insulating layer overlying the first insulating layer and the source-drain conductive layer is deposited using a chemical vapor deposition process over the first insulating layer and the source-drain conductive layer.
  • a layer of photoresist is applied on the second insulating layer on which the second via hole 16 has not been formed, for example, by spin coating (here, a positive photoresist is taken as an example), and ultraviolet light is used. The light is irradiated through the mask plate to completely expose the photoresist in the region to be etched, and the exposed structure is placed in the developing solution to remove all the photoresist in the region to be etched by development.
  • a pattern including the first transparent conductive layer is formed.
  • a transparent conductive material for example, at least one of indium tin oxide ITO, graphene, metal mesh, conductive polymer, and nano conductive material, or silver thin film
  • the physical vapor deposition process of the translucent conductive material deposits a pattern of the first transparent conductive layer that has not been patterned, and the setting of parameters such as the thickness of the film layer is achieved by, for example, means for adjusting the relevant process parameters.
  • patterning the transparent conductive material distributed over the entire surface includes coating a layer of photoresist on the first transparent conductive layer that has not been patterned, for example, by spin coating (here positive) The photoresist is taken as an example.
  • the photoresist in the region to be etched is irradiated with ultraviolet light through the mask to expose it sufficiently, and the exposed structure is placed in the developer to be developed by the development.
  • the photoresist in the etched region is completely removed, and the remaining photoresist is etched using the remaining photoresist as a mask, and the remaining photoresist is removed after the etching is completed.
  • the first transparent conductive layer includes the plurality of touch electrodes 11 , and the connection between the touch electrodes 11 and the touch signal lines 12 and the connection between the touch electrodes 11 and the first conductive lines 13 have passed through the second Via 16 is implemented.
  • a pattern including source and drain connection via holes is formed.
  • a third insulating layer overlying the second insulating layer and the first transparent conductive layer is deposited using a chemical vapor deposition process over the second insulating layer and the first transparent conductive layer.
  • a photoresist is applied on the third insulating layer which has not formed the source/drain connection via, for example, by spin coating (here, a positive photoresist is taken as an example), and ultraviolet light is used. The light is irradiated through the mask plate to completely expose the photoresist in the region to be etched, and the exposed structure is placed in the developing solution to remove all the photoresist in the region to be etched by development.
  • the pattern of the vias is connected, and the remaining photoresist is removed after the etching is completed.
  • a pattern including the second transparent conductive layer is formed.
  • a pattern of a second transparent conductive layer that has not been patterned is deposited on a third insulating layer using a physical vapor deposition process of a transparent conductive material, and the parameters such as the thickness of the film layer are set by, for example, adjusting the relevant process parameters.
  • patterning the transparent conductive material distributed over the entire surface includes coating a layer of photoresist on the second transparent conductive layer that has not been patterned, for example, by spin coating (here positive)
  • the photoresist is taken as an example.
  • the photoresist in the region to be etched is irradiated with ultraviolet light through the mask to be fully exposed, and then placed in the developer to develop the region to be etched.
  • the photoresist inside is completely removed, and the remaining photoresist is etched using the remaining photoresist as a mask, and the remaining photoresist is removed after the etching is completed.
  • the second transparent conductive layer includes a plurality of pixel electrodes respectively filling the opening area of each pixel, and the pixel electrode is connected to the source electrode or the drain electrode through the source/drain connection via.
  • Forming a planarization layer overlying the third insulating layer and the second transparent conductive layer completes the fabrication of the array substrate.
  • Some embodiments provide a display device comprising the array substrate of any of the above.
  • the display device is any display product, component such as a display panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
  • FIG. 11 is a schematic structural diagram of a display device provided by some embodiments.
  • the display device includes any one of the above display substrates.
  • the display area of the display substrate includes a sub-pixel region Px disposed in a row and a column, and each of the sub-pixel regions Px is provided with a pixel opening region.
  • the display device provided in the above embodiment increases the number of contact points between the touch signal line and the touch electrode, and reduces the edge of the touch electrode to the touch based on the arrangement of the first conductor line and the second conductor line.
  • the resistance between the signal lines increases the signal strength of the touch signal received through the touch electrodes, reduces touch defects, and improves the touch performance of the product.

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Abstract

本公开提供了一种阵列基板及其制造方法、显示装置。所述阵列基板包括显示区和周边电路区。所述阵列基板还包括：位于所述显示区内的多个触控电极；将所述多个触控电极连接至所述周边电路区的多条触控信号线；延伸方向与所述多条触控信号线相同的多条第一导体线；以及，延伸方向与所述多条触控信号线不同的多条第二导体线。任一触控电极在其厚度方向上连接至少一条第一导体线，所述任一触控电极连接至少一条触控信号线，所述至少一条触控信号线连接至少一条第二导体线，以及所述至少一条第二导体线连接所述至少一条第一导体线。

Description

阵列基板及其制造方法、显示装置
相关申请的交叉引用
本申请主张在2018年3月27日在中国提交的中国专利申请号No.201810258988.X的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示领域，例如，涉及一种阵列基板及其制造方法、显示装置。
背景技术
在例如触控与显示驱动器集成(Touch and Display driver Integration，TDDI)的触控产品中，容易因透明的触控电极的电阻过大、所接收到的触控信号的信号强度过低而产生触控不良。
发明内容
一种阵列基板，包括显示区和周边电路区，所述阵列基板还包括：
位于所述显示区内的多个触控电极；
将所述多个触控电极连接至所述周边电路区的多条触控信号线；
延伸方向与所述多条触控信号线相同的多条第一导体线；以及，
延伸方向与所述多条触控信号线不同的多条第二导体线；
其中，任一触控电极在其厚度方向上连接至少一条第一导体线，所述任一触控电极连接至少一条触控信号线，所述至少一条触控信号线连接至少一条第二导体线，以及所述至少一条第二导体线连接所述至少一条第一导体线。
一些实施例中，所述任一个触控电极通过所述至少一条触控信号线连接至所述周边电路区；
所述多个触控信号线与所述多条第一导体线在同一次构图工艺中形成；以及，
所述多条第一导体线包括至少一条无效触控信号线，其中，所述至少一 条无效触控信号线是所述多条触控信号线以外的与任一条触控信号线处在同一条直线上的导体线。
一些实施例中，所述的阵列基板包括多行栅线和多列数据线，其中，所述多条第二导体线与所述多行栅线在同一次构图工艺中形成，以及，所述多条第一导体线、所述多条触控信号线以及所述多列数据线在同一次构图工艺中形成。
一些实施例中，所述的阵列基板包括绝缘层，其中，所述多行栅线和所述多列数据线分别位于所述绝缘层的厚度方向上的两侧，所述绝缘层中设有第一过孔，以及每条第二导体线通过所述第一过孔连接对应的第一导体线和对应的触控信号线。
一些实施例中，所述的阵列基板包括绝缘层，其中，所述多个触控信号线和所述多个触控电极分别位于所述绝缘层在厚度方向上的两侧；
所述绝缘层中设有多个第二过孔，每条触控信号线通过至少一个第二过孔与对应的触控电极连接，每条第一导体线通过至少一个第二过孔与对应的触控电极连接；以及
所述多个触控信号线与所述多条第一导体线在同一次构图工艺中形成；。
一些实施例中，所述多条触控信号线、所述多条第一导体线以及所述多条第二导体线均在同一次构图工艺中形成。
一些实施例中，所述显示区包括多行多列的像素开口区，每个触控信号线均位于相邻两列的像素开口区之间，每个第一导体线均位于相邻两列的像素开口区之间，以及每个第二导体线均位于相邻两行的像素开口区之间。
一些实施例中，与一个触控电极相连的所有的第一导体线均位于该触控电极所在的区域内；以及
与所述触控电极连接的所有的第一导体线相连的第二导体线位于该触控电极所在的区域内。
一些实施例中，与一个触控电极所连接的所有的第一导体线连接的第二导体线的数量为一条，以及该条第二导体线位于该触控电极所在的区域的中央；
或者，
与一个触控电极所连接的所有的第一导体线连接的第二导体线的数量为两条，该两条第二导体线中的一个位于该触控电极所在的区域的第一个边缘，以及该两条第二导体线中的另一个位于该触控电极所在的区域的第二个边缘。
一种显示装置包括如上任一项所述的阵列基板。
一种阵列基板的制造方法，包括：
形成多条触控信号线，其中，所述多条触控信号线具有相同的延伸方向；
形成多条第一导体线，其中，所述多条第一导体线的延伸方向与所述多条触控信号线的延伸方向相同；
形成多条第二导体线，其中，所述多条第二导体线的延伸方向与所述多条触控信号线的延伸方向不同；以及，
形成多个触控电极，其中，所述阵列基板包括显示区和周边电路区，所述多个触控电极位于所述显示区内，以及所述多条触控信号线将所述多个触控电极连接至所述周边电路区；
其中，任一触控电极在其厚度方向上连接至少一条第一导体线，所述任一触控电极连接至少一条触控信号线，所述至少一条触控信号线连接至少一条第二导体线，以及所述至少一条第二导体线连接所述至少一条第一导体线。
附图说明
图1是一些实施例提供的阵列基板的结构示意图；
图2是一些实施例提供的阵列基板的显示区内部走线示意图；
图3是一些实施例提供的阵列基板在第一过孔处的剖面示意图；
图4是一些实施例提供的阵列基板在第二过孔处的剖面示意图；
图5A是一些实施例提供的阵列基板的触控布线示意图；
图5B是另一些实施例提供的阵列基板的触控布线示意图；
图6是另一些实施例提供的阵列基板的触控布线示意图；
图7是另一些实施例提供的阵列基板的触控布线示意图；
图8是另一些实施例提供的阵列基板的触控布线示意图；
图9是另一些实施例提供的阵列基板的触控布线示意图；
图10是一些实施例提供的阵列基板的制造方法的流程示意图；以及
图11是一些实施例提供的显示装置的结构示意图。
具体实施方式
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。单独出现的“连接”或者“连接”等类似的词语并非限定于物理的或者机械的连接。一些实施例中，该连接指包括电性的连接。一些实施例中，该连接是直接的或间接的连接。
在采用TDDI的触控产品中，容易因透明的触控电极的电阻过大以及触控电极接收到的触控信号的信号强度过低而产生触控不良。在采用TDDI的触控产品中，例如，在覆盖5mm×5mm的显示区域中，触控电极一般通过金属引线将收集的触控信号导出给外部芯片，由于金属引线的数量受到开口率方面的限制无法密集排列，而触控电极上距离金属引线比较远的位置处产生的触控信号在传输过程中，存在相当大的信号衰减，因此，出现局部触控信号容易被噪声覆盖的问题，导致触控不良。
图1是一些实施例提供的阵列基板的结构示意图。参见图1，该阵列基板包括显示区A1和周边电路区A2。该阵列基板还包括位于显示区A1内的多个触控电极11。示例性地，图1中的周边电路区A2位于显示区A1的一侧，并且多个触控电极11在显示区A1内排成多行多列。
一些实施例中，周边电路区A2位于显示区A1相对的两侧。
一些实施例中，周边电路区A2环绕在显示区A1四周。
一些实施例中，多个触控电极11按照任意一种平面内的单元排布方式进行排列，例如，多个触控电极11排列成倾斜网格、三角网格或者菱形网格。
示例性地，图1中还示出了位于周边电路区A2中的触控电路21，该触控电路21被配置为通过采集多个触控电极11上的电信号来实现触摸感测。
一些实施例中，触控电路21与多个触控电极11之间电性连接，即，多 个触控电极11通过多条触控信号线12连接至周边电路区A2。
一些实施例中，如图1所示，触控电路21位于显示区A1一侧，上述多条触控信号线12的延伸方向均为从显示区A1指向周边电路区A2的方向。
图2是本公开一些实施例提供的阵列基板的显示区内部走线示意图。图2中示例性地示出了排成两行两列的四个触控电极11。如图2所示，阵列基板包括上述多个触控电极11、多条触控信号线12、多条第一导体线13、多条第二导体线14，多行栅线101以及多列数据线102。如图2所示，阵列基板中的所述多条触控信号线12均具有相同的延伸方向，并且每条第一导体线13的延伸方向均与多条触控信号线12的延伸方向相同，每条第二导体线14的延伸方向均与多条触控信号线12的延伸方向不同。
在连接关系上，每条第一导体线13在一个触控电极11的厚度方向上与该触控电极11相连，每条第二导体线14与一个触控电极11相对应，任一第二导体线14连接所对应的触控电极11所连接的触控信号线12，以及任一第二导体线14分别连接所对应的触控电极11所连接的每条第一导体线13。
如图2所示，任一触控电极11在其厚度方向上连接多条第一导体线13，所述任一触控电极11连接一条触控信号线12，该触控信号线12连接多条第二导体线14，且与该触控信号线12连接的每条第二导体线14连接至所述任一触控电极11连接的多条第一导体线13。
如图2所示，与任一触控电极11连接的多条第一导体线13，位于所述任一触控电极11的区域内；所述任一触控电极11连接一条触控信号线12，该触控信号线12连接的多条第二导体线14位于所述任一触控电极11的区域内。
上述实施例中，基于第一导体线13和第二导体线14的设置，触控电极上11上的触控信号不仅直接传输至触控信号线12上，还通过第一导体线13和第二导体线14传输至触控信号线12上，而且触控电极11上多个位置与触控信号线12之间的电阻也得以均匀化。即，本公开上述实施例增加了触控信号线与触控电极之间接触点的数量，并减小了触控电极的边缘到触控信号线之间的电阻，因而，提升了通过触控电极接收到的触控信号的信号强度，减少了触控不良，提升了产品的触控性能。
示例性地，多条第二导体线14与多行栅线101在同一次构图工艺中形成，而多条第一导体线13、多条触控信号线12以及多列数据线102在同一次构图工艺中形成。如此，第二导体线14和栅线101位于同一层中，第一导体线13、触控信号线12以及数据线102位于同一层中。
示例性地，如图3和图4所示，阵列基板还包括第一绝缘层17，多行栅线101(与第二导体线14同层)和多列数据线102(与第一导体线13和触控信号线12同层)分别位于该第一绝缘层17的厚度方向上的两侧。
以第一绝缘层包括栅绝缘层的底栅结构为例，第二导体线14和栅线GL位于第一绝缘层的第一侧，而第一导体线13、触控信号线12以及数据线102位于第一绝缘层的第二侧。
图3是一些实施例提供的阵列基板在第一过孔处的剖面示意图。对照图2，图3示出的是图2中标记“15”所指位置处的剖面图。示例性地，参见图3，阵列基板包括第一绝缘层17，第一绝缘层17中设有第一过孔15，任一条第二导体线14通过第一过孔15连接所对应的第一导体线13和触控信号线12。如此，上述触控信号线12与第二导体线14通过两者在触控电极11上的投影相交位置处的第一过孔15连接，以及上述第一导体线13与第二导体线14通过两者在触控电极11上的投影相交位置处的第一过孔15连接。
示例性地，阵列基板还包括第二绝缘层，多个触控信号线12和多个触控电极11分别位于第二绝缘层在厚度方向上的两侧。
如此，以触控电极11位于第二绝缘层远离第一绝缘层的一侧为例，第一导体线13、触控信号线12以及数据线102位于第二绝缘层的第一侧，而触控电极11位于第二绝缘层的第二侧。
一些是实施例中，上述示例中的多个触控电极11为提供公共电压的公共电极。
图4是一些实施例提供的阵列基板在第二过孔处的剖面示意图。图4示出的是图2中标记“16”所指位置处的剖面图。示例性地，阵列基板包括第二绝缘层18，第二绝缘层18中设有多个第二过孔16，任一条触控信号线12通过至少一个第二过孔16与对应的触控电极11连接，每条第一导体线13通过至少一个第二过孔16与对应的触控电极11连接。
如此，上述触控信号线12与触控电极11之间的连接，以及上述第一导体线13与触控电极11之间的连接，均通过至少一个第二过孔16来实现。
第二导体线14位于第一绝缘层17的第一侧，而第一导体线13和触控信号线12位于第一绝缘层17的第二侧。第一绝缘层17中设有第一过孔15，以及第二导体线14通过第一过孔15连接所对应的第一导体线13。第一导体线13和触控信号线12位于第二绝缘层18的第一侧，而触控电极11位于第二绝缘层18的第二侧。第二绝缘层18中设有多个第二过孔16，触控信号线12通过第二过孔16与对应的触控电极11连接。
图2中，按照从左至右的顺序，四条触控信号线12分别连接左上、左下、右上、右下的触控电极11，触控电极11通过第二过孔16连接相应的触控信号线12。
以图2为例，阵列基板中的每条触控信号线12将一个触控电极11连接至周边电路区，在满足触控信号采集需求的同时使多个触控电极11之间电性绝缘，避免不同触控电极11上的触控信号彼此干扰。
一些实施例中，比照图1和图2，为了使每个触控电极11上的触控信号都能单独地传输至周边电路区A2，每列触控电极11的行向投影范围至少容纳与触控电极的行数相同数量的触控信号线12在该行向投影范围内列向平行排列，即触控电极11的尺寸、触控信号线12的线宽以及触控信号线12的排列间距均满足相对应的限制条件。
例如，图5A中示出了排成3行4列的触控电极11，由于每条触控信号线12沿着列向将所连接的触控电极11上的触控信号引接至周边电路区A2，因此每列触控电极11的行向投影范围容纳至少3条触控信号线12在该行向投影范围内列向平行排列。本示例中每列触控电极11行向投影范围内的触控信号线12的条数不少于触控电极11的总行数。
一些实施例中，在每列触控电极11行向投影范围内的触控信号线12的条数大于触控电极11的总行数时，部分触控电极连接两条或两条以上的触控信号线12。
一些实施例中，如图5B所示，一些触控电极11连接两条触控信号线12，一些触控电极连接三条触控信号线12。
在一个示例中，设置远离触控电路21的触控电极11连接多于一条的触控信号线12，以在一定程度上补偿远离触控电路21的远端触控电极11上触控信号的电阻压降。例如，距离触控电路21最远的触控电极11连接至少两条触控信号线12，以及距离触控电路21最近的触控电极11连接一条触控信号线12。
一些实施例中，如图6所示，图6中的阵列基板在图5A所示结构基础上进行简化布线，比照图5A和图6看出的是，简化布线后的阵列基板中，保留了触控信号的传输路径对应的走线，去除了触控信号线12中没有起到传输触控信号作用的走线。由于这一变化仅通过修改触控信号线所在导体膜层所对应的掩膜板图案来实现，因此未对原有的制作工艺造成大的影响。如此，有利地省去了多余走线的布线空间，避免多余走线引发短路或串扰。
一些实施例中，图7示出了一些实施例在图5A所示结构基础上进行布线简化之后的阵列基板的结构，比照图6和图7看出的是，本公开实施例中没有完全去除触控信号线12中没有起到传输作用的部分走线，而是去除了该部分走线中处于相邻两行触控电极11之间的走线(同样通过修改触控信号线所在导体膜层所对应的掩膜板图案来实现)，从而有利地利用触控信号线12的制作工艺，形成上述有助于将触控信号从触控电极11传导至触控信号线12上的第一导体线13。
直接从触控信号线12上分离出来的第一导体线13在未经过其他连接设置的情况下为不具有任何有用功能的导体线(其中，“有用功能”是指传输信号的功能)。为叙述方便，本文将此类脱离于上述至少一条触控信号线以外的且与任一条触控信号线处于同一条直线上的导体线称为无效触控信号线。第一导体线13并不一定全部都是无效触控信号线(例如图7中每个触控电极11的正投影范围内最右侧的第一导体线13就不是无效触控信号线)。
一些实施例中，不同的触控电极11所在区域内无效触控信号线的数量存在差异(如图7所示)。图2中右上方触控电极11所在区域中以标记“13”示出的第一导体线13即为无效触控信号线。
一些实施例中，为了提升触控信号的信号强度，如图7所示的第一导体线13还需要与所对应的触控电极11和所对应的触控信号线12相连。其中， 第一导体线13与触控电极11的连接方式参照触控信号线12与触控电极11的连接方式来实现，例如上文所述的那样，将第二绝缘层中设置为连接触控信号线12和触控电极11的第二过孔16设置到第一导体线13和触控电极11之间，以在不增加工艺步骤的情况下实现第一导体线13和触控电极之间的连接。第一导体线13与触控信号线12之间借助行向延伸的第二导体线14实现电连接，例如，如图8所示，在每个触控电极11行向的中央设置一条行向延伸的第二导体线14，并且该第二导体线14通过第一过孔15与每一条相交的第一导体线13(与该第二导体线14电连接的一个触控电极连接的每一第一导体线13)及触控信号线12(与该第二导体线14电连接的一个触控电极连接的触控信号线12)相电连接连，使得第一导体线13能够连接到所对应的触控信号线12。
第二导体线14除了单独制作在阵列基板内部之外，还如上文所述的那样与栅线101在同一次构图工艺中形成(可参照阵列基板的双栅线设计)，或者与触控信号线12及第一导体线13在同一次构图工艺中形成，均能够实现上述提升触控信号的信号强度的效果。
一些实施例中，多条触控信号线12、多条第一导体线13以及多条第二导体线14均在同一次构图工艺中形成，减少了过孔的数量，有助于提升触控信号的信号强度。
图2和图8分别给出了两种第二导体线14的设置方式示例。图2中，与一个触控电极11所连接的所有的第一导体线13连接的第二导体线14的数量为两条，这两条第二导体线14中的一个位于该触控电极11的所在区域的第一个边缘，这两条第二导体线14中的另一个位于该触控电极11的所在区域的第二个边缘(第一个边缘和第二个边缘即图2中中的触控电极11的上边缘和下边缘)。图8中，与一个触控电极11所连接的所有的第一导体线13连接的第二导体线14的数量为一条，该条第二导体线14位于该触控电极11所在区域沿行方向的中央。
一些实施例中，参见图9，显示区A1均包括多行多列的像素开口区A11，并且每条触控信号线12均位于相邻两列像素开口区A11之间，每条第一导体线13均位于相邻两列像素开口区A11之间，每条第二导体线14均位于相邻 两行像素开口区A11之间。如此，将触控信号线12、第一导体线13和第二导体线14均设置在黑矩阵19所遮挡的区域范围内，减小了对显示效果造成的影响。
在一个示例中，每条触控信号线12在相邻两列像素开口区之间与数据线102并行排列，而每条第一导体线13均为从一条触控信号线12上分离出来的无效触控信号线，触控信号线12、第一导体线13和数据线102均处于阵列基板的源漏导电层当中。而且，每条第二导体线14在相邻两行像素开口区之间与栅线101并行排列，第二导体线14和栅线101均处于阵列基板的栅极导电层当中。
上述示例中，与一个触控电极11相连的所有的第一导体线13均位于该触控电极11所在区域内，并且与一个触控电极11所连接的所有的第一导体线13相连的第二导体线14位于该触控电极11所在区域内。如此，避免了相邻的触控电极11上触控信号的相互干扰，更有助于触控性能的提升。
以上示例均为本公开的示例性说明，在任意一种利用多条触控信号线将多个触控电极引接至显示区之外的方案的基础上均可应用本公开的技术方案，以通过第一导体线和第二导体线的相关设置增加触控信号线与触控电极之间接触点的数量，从而提升通过触控电极接收到的触控信号的信号强度，有助于减少相关的触控不良，提升产品的触控性能。
图10是本公开一些实施例提供的阵列基板的制造方法的流程示意图，其中，所述阵列基板包括显示区和周边电路区。参见图10，该方法包括步骤701至步骤702。
在步骤701中，形成多条触控信号线。
其中，所述多条触控信号线具有相同的延伸方向。
在步骤702中，形成多条第一导体线。
其中，所述多条第一导体线的延伸方向与所述多条触控信号线相同。
在步骤703中，形成多条第二导体线。
其中，所述多条第二导体线的延伸方向与所述多条触控信号线的方向延伸方向不同。
在步骤704中，形成多个触控电极。
其中，所述多个触控电极位于所述显示区内，所述多条触控信号线将所述多个触控电极连接至所述周边电路区。
上述方法实施例中，每条所述第一导体线在一个触控电极的厚度方向上与该触控电极相连；任一第二导体线连接其对应的触控电极所连接的触控信号线，任一第二导体线连接其对应的触控电极所连接的每条第一导体线。
上述步骤701至步骤704的执行顺序并不一定要严格按照如图10中所示出的那样。在一些实施例中，依照每个图形在阵列基板内部所在层的位置，适应性调整上述各步骤的执行顺序。
上述方法实施例中，基于第一导体线和第二导体线的设置，增加了触控信号线与触控电极之间接触点的数量，并减小了触控电极的边缘与触控信号线之间的电阻，因而，提升了通过触控电极接收到的触控信号的信号强度，减少了触控不良，以及提升了产品的触控性能。
在一个示例中，结合图2，上述阵列基板的制造方法包括以下过程。
在第一次构图工艺中，在衬底基板上形成包括栅极导电层的图形。
在一个示例中，在对衬底基板(材质例如是玻璃、硅片或有机聚合物)的表面进行清洗和烘干之后，在衬底基板的表面上采用金属材料的物理气相沉积工艺(Physical Vapor Deposition，PVD)沉积一层金属材料薄膜，膜层厚度等参数的设置通过例如调整相关工艺参数的手段来实现。在此基础之上，对整面分布的金属材料薄膜进行图案化处理包括，在还未图案化的金属材料薄膜上采用例如旋涂的方式涂覆一层光刻胶(此处以正性光刻胶为例进行说明)，采用紫外光透过掩膜板照射全部待刻蚀区域内的光刻胶以使其充分曝光，再将全部结构置于显影液中以通过显影将待刻蚀区域内的光刻胶全部去除，将余留下来的光刻胶作为掩膜对未图案化的栅极导电层进行刻蚀，刻蚀完成后再去除剩余的光刻胶。
栅极导电层的形成材料是例如包括铁、铜、铝、钼、镍、钛、银、锌、锡、铅、铬、锰中至少一种元素的金属材料，并依照所期望的电导率设置组分。所述栅极导电层中包括上述栅线101、上述多条第二导体线14以及阵列基板中薄膜晶体管的栅电极。
在第二次构图工艺中，在形成第一绝缘层之后，形成包括第一过孔的图 形。
在一个示例中，在衬底基板和栅极导电层之上采用化学气相沉积工艺(Chemical Vapor Deposition，CVD)沉积覆盖在基板和栅极导电层上的栅绝缘层(作为第一绝缘层17)，其中栅绝缘层的膜层厚度满足对于薄膜晶体管的栅绝缘层的厚度的相关要求，对于膜层厚度等参数的设置通过例如调整相关工艺参数的手段来实现。在此基础之上，在还未形成第一过孔15的第一绝缘层上采用例如旋涂的方式涂覆一层光刻胶(此处以正性光刻胶为例进行说明)，采用紫外光透过掩膜板照射全部待刻蚀区域内的光刻胶以使其充分曝光，再将曝光后的结构置于显影液中以通过显影将待刻蚀区域内的光刻胶全部去除，将余留下来的光刻胶作为掩膜对还未形成第一过孔15的第一绝缘层进行刻蚀，以在第一绝缘层中形成包括第一过孔15的图形，刻蚀完成后再去除剩余的光刻胶。
在第三次构图工艺中，形成包括有源层的图形。
在一个示例中，在第一绝缘层上形成半导体材料层，并对半导体材料层进行图案化处理，以形成具有预期图案的有源层。
一些实施例中，形成有源层的半导体材料包括非晶硅、多晶硅、单晶硅或者金属氧化物半导体，并依照所要实现的薄膜晶体管的特性对至少部分区域进行掺杂。
在第四次构图工艺中，形成包括源漏导电层的图形。
在一个示例中，在第一绝缘层和有源层上采用金属材料的物理气相沉积工艺沉积还未图案化的源漏导电层(源极导电层和漏极导电层)，膜层厚度等参数的设置通过例如调整相关工艺参数的手段来实现。在此基础之上，对整面分布的源漏导电层进行图案化处理包括：在还未图案化的源漏导电层上采用例如旋涂的方式涂覆一层光刻胶(此处以正性光刻胶为例进行说明)，采用紫外光透过掩膜板照射全部待刻蚀区域内的光刻胶以使其充分曝光，再将曝光后的结构置于显影液中以通过显影将待刻蚀区域内的光刻胶全部去除，将余留下来的光刻胶作为掩膜对未图案化的源漏导电层进行刻蚀，以及刻蚀完成后再去除剩余的光刻胶。
源漏导电层的形成材料是例如包括铁、铜、铝、钼、镍、钛、银、锌、 锡、铅、铬、锰中至少一种元素的金属材料，并依照所期望的电导率设置组分。所述源漏导电层中包括上述数据线102、上述多条触控信号线12和上述多条第一导体线13，以及薄膜晶体管的源电极和漏电极。第二导体线14与触控信号线12之间的连接以及第二导体线14与第一导体线13之间的连接通过第一过孔15实现。
在第五次构图工艺中，在形成第二绝缘层后，形成包括第二过孔的图形。
在一个示例中，在第一绝缘层和源漏导电层之上采用化学气相沉积工艺沉积覆盖在第一绝缘层和源漏导电层上的第二绝缘层。在此基础之上，在还未形成第二过孔16的第二绝缘层上采用例如旋涂的方式涂覆一层光刻胶(此处以正性光刻胶为例进行说明)，采用紫外光透过掩膜板照射全部待刻蚀区域内的光刻胶以使其充分曝光，再将曝光后的结构置于显影液中以通过显影将待刻蚀区域内的光刻胶全部去除，将余留下来的光刻胶作为掩膜对还未形成第二过孔16的第二绝缘层进行刻蚀，以在第二绝缘层中形成包括第二过孔16的图形，以及刻蚀完成后再去除剩余的光刻胶。
在第六次构图工艺中，形成包括第一透明导电层的图形。
在一个示例中，在第二绝缘层上采用透明导电材料(例如包括铟锡氧化物ITO、石墨烯、金属网格、导电聚合物和纳米导电材料中至少一种材料，或者是银薄膜一类的半透明的导电材料)的物理气相沉积工艺沉积还未图案化的第一透明导电层的图形，膜层厚度等参数的设置通过例如调整相关工艺参数的手段来实现。在此基础之上，对整面分布的透明导电材料进行图案化处理包括，在还未图案化的第一透明导电层上采用例如旋涂的方式涂覆一层光刻胶(此处以正性光刻胶为例进行说明)，采用紫外光透过掩膜板照射全部待刻蚀区域内的光刻胶以使其充分曝光，再将曝光后的结构置于显影液中以通过显影将待刻蚀区域内的光刻胶全部去除，将余留下来的光刻胶作为掩膜对未图案化的第一透明导电层进行刻蚀，以及刻蚀完成后再去除剩余的光刻胶。第一透明导电层中，包括上述多个触控电极11，并且触控电极11与触控信号线12之间的连接以及触控电极11与第一导体线13之间的连接已通过第二过孔16实现。
在第七次构图工艺中，在形成第三绝缘层后，形成包括源漏连接过孔的 图形。
在一个示例中，在第二绝缘层和第一透明导电层之上采用化学气相沉积工艺沉积覆盖在第二绝缘层和第一透明导电层上的第三绝缘层。在此基础之上，在还未形成源漏连接过孔的第三绝缘层上采用例如旋涂的方式涂覆一层光刻胶(此处以正性光刻胶为例进行说明)，采用紫外光透过掩膜板照射全部待刻蚀区域内的光刻胶以使其充分曝光，再将曝光后的结构置于显影液中以通过显影将待刻蚀区域内的光刻胶全部去除，将余留下来的光刻胶作为掩膜对还未形成源漏连接过孔的第二绝缘层和第三绝缘层进行刻蚀，以在第二绝缘层和第三绝缘层中形成包括源漏连接过孔的图形，以及刻蚀完成后再去除剩余的光刻胶。
在第八次构图工艺中，形成包括第二透明导电层的图形。
在一个示例中，在第三绝缘层上采用透明导电材料的物理气相沉积工艺沉积还未图案化的第二透明导电层的图形，膜层厚度等参数的设置通过例如调整相关工艺参数的手段来实现。在此基础之上，对整面分布的透明导电材料进行图案化处理包括，在还未图案化的第二透明导电层上采用例如旋涂的方式涂覆一层光刻胶(此处以正性光刻胶为例进行说明)，采用紫外光透过掩膜板照射全部待刻蚀区域内的光刻胶以使其充分曝光，再将其置于显影液中以通过显影将待刻蚀区域内的光刻胶全部去除，将余留下来的光刻胶作为掩膜对未图案化的第二透明导电层进行刻蚀，以及刻蚀完成后再去除剩余的光刻胶。第二透明导电层包括分别填满每个像素开口区域的多个像素电极，并且像素电极通过源漏连接过孔与上述源电极或漏电极相连。
形成覆盖在第三绝缘层和第二透明导电层之上的平坦化层，即完成了阵列基板的制作。
一些实施例提供一种显示装置，该显示装置包括上述任意一种的阵列基板。
一些实施例中，显示装置为显示面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框以及导航仪等任何具有显示功能的产品或部件。
作为一种示例，图11是一些实施例提供的显示装置的结构示意图。所述显示装置包括上述任意一种显示基板，该显示基板的显示区内包括行列设置 的子像素区域Px，每个子像素区域Px中都设置有一个像素开口区域。
基于第一导体线和第二导体线的设置，上述实施例提供的显示装置增加了触控信号线与触控电极之间的接触点的数量，并减小了触控电极的边缘到触控信号线之间的电阻，因而，提升了通过触控电极接收到的触控信号的信号强度，减少了触控不良，提升了产品的触控性能。

Claims (11)

  1. 一种阵列基板，包括显示区和周边电路区，所述阵列基板还包括：
    位于所述显示区内的多个触控电极；
    将所述多个触控电极连接至所述周边电路区的多条触控信号线；
    延伸方向与所述多条触控信号线相同的多条第一导体线；以及，
    延伸方向与所述多条触控信号线不同的多条第二导体线；
    其中，任一触控电极在其厚度方向上连接至少一条第一导体线，所述任一触控电极连接至少一条触控信号线，所述至少一条触控信号线连接至少一条第二导体线，以及所述至少一条第二导体线连接所述至少一条第一导体线。
  2. 根据权利要求1所述的阵列基板，其中，
    所述任一个触控电极通过所述至少一条触控信号线连接至所述周边电路区；
    所述多个触控信号线与所述多条第一导体线在同一次构图工艺中形成；以及，
    所述多条第一导体线包括至少一条无效触控信号线，其中，所述至少一条无效触控信号线是所述多条触控信号线以外的与任一条触控信号线处在同一条直线上的导体线。
  3. 根据权利要求1所述的阵列基板，包括多行栅线和多列数据线，其中，所述多条第二导体线与所述多行栅线在同一次构图工艺中形成，以及，所述多条第一导体线、所述多条触控信号线以及所述多列数据线在同一次构图工艺中形成。
  4. 根据权利要求3所述的阵列基板，包括绝缘层，其中，所述多行栅线和所述多列数据线分别位于所述绝缘层的厚度方向上的两侧，所述绝缘层中设有第一过孔，以及每条第二导体线通过所述第一过孔连接对应的第一导体线和对应的触控信号线。
  5. 根据权利要求1所述的阵列基板，包括绝缘层，其中，所述多个触控信号线和所述多个触控电极分别位于所述绝缘层在厚度方向上的两侧；
    所述绝缘层中设有多个过孔，每条触控信号线通过至少一个过孔与对应 的触控电极连接，每条第一导体线通过至少一个过孔与对应的触控电极连接；以及
    所述多个触控信号线与所述多条第一导体线在同一次构图工艺中形成。
  6. 根据权利要求1所述的阵列基板，其中，所述多条触控信号线、所述多条第一导体线以及所述多条第二导体线均在同一次构图工艺中形成。
  7. 根据权利要求1至6中任一项所述的阵列基板，其中，所述显示区包括多行多列的像素开口区，每个触控信号线均位于相邻两列的像素开口区之间，每个第一导体线均位于相邻两列的像素开口区之间，以及每个第二导体线均位于相邻两行的像素开口区之间。
  8. 根据权利要求1至6中任一项所述的阵列基板，其中，
    与一个触控电极相连的所有的第一导体线均位于该触控电极所在的区域内；以及
    与所述触控电极连接的所有的第一导体线相连的第二导体线位于该触控电极所在的区域内。
  9. 根据权利要求1至6中任一项所述的阵列基板，其中，
    与一个触控电极所连接的所有的第一导体线连接的第二导体线的数量为一条，以及该条第二导体线位于该触控电极所在的区域的中央；
    或者，
    与一个触控电极所连接的所有的第一导体线连接的第二导体线的数量为两条，该两条第二导体线中的一个位于该触控电极所在的区域的第一个边缘，以及该两条第二导体线中的另一个位于该触控电极所在的区域的第二个边缘。
  10. 一种显示装置，包括如权利要求1至9中任一项所述的阵列基板。
  11. 一种阵列基板的制造方法，包括：
    形成多条触控信号线，其中，所述多条触控信号线具有相同的延伸方向；
    形成多条第一导体线，其中，所述多条第一导体线的延伸方向与所述多条触控信号线的延伸方向相同；
    形成多条第二导体线，其中，所述多条第二导体线的延伸方向与所述多条触控信号线的延伸方向不同；以及，
    形成多个触控电极，其中，所述阵列基板包括显示区和周边电路区，所 述多个触控电极位于所述显示区内，以及所述多条触控信号线将所述多个触控电极连接至所述周边电路区；
    其中，任一触控电极在其厚度方向上连接至少一条第一导体线，所述任一触控电极连接至少一条触控信号线，所述至少一条触控信号线连接至少一条第二导体线，以及所述至少一条第二导体线连接所述至少一条第一导体线。
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