WO2019184254A1 - 柔性tft背板的制作方法及柔性tft背板 - Google Patents

柔性tft背板的制作方法及柔性tft背板 Download PDF

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WO2019184254A1
WO2019184254A1 PCT/CN2018/104485 CN2018104485W WO2019184254A1 WO 2019184254 A1 WO2019184254 A1 WO 2019184254A1 CN 2018104485 W CN2018104485 W CN 2018104485W WO 2019184254 A1 WO2019184254 A1 WO 2019184254A1
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layer
film
insulating layer
flexible
gate
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PCT/CN2018/104485
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English (en)
French (fr)
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刘方梅
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/090,191 priority Critical patent/US10665721B1/en
Publication of WO2019184254A1 publication Critical patent/WO2019184254A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1292—Multistep manufacturing methods using liquid deposition, e.g. printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H10K10/488—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising a layer of composite material having interpenetrating or embedded materials, e.g. a mixture of donor and acceptor moieties, that form a bulk heterojunction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a flexible TFT backplane and a flexible TFT backplane.
  • OLED organic light emitting diodes
  • LCDs liquid crystal displays
  • OLEDs organic light emitting diodes
  • the OLED display has self-illumination, low driving voltage, high luminous efficiency, short response time, high definition and contrast, near 180° viewing angle, wide temperature range, and can realize flexible display and large-area full-color display. Recognized by the industry as the most promising display device.
  • Existing flexible OLED displays generally include a flexible TFT (Thin Film Transistor Array Substrate) backplane and an OLED device disposed on the flexible TFT backplane.
  • the flexible TFT backplane is used for driving an OLED device;
  • the OLED device includes an anode, a hole injection layer disposed on the anode, a hole transport layer disposed on the hole injection layer, and a hole transport layer The upper light-emitting layer, the electron transport layer provided on the light-emitting layer, the electron injection layer provided on the electron transport layer, and the cathode provided on the electron injection layer.
  • the principle of illumination of an OLED device is that, under a certain voltage, electrons and holes are injected from the cathode and the anode to the electron transport layer and the hole transport layer, respectively, and electrons and holes migrate to the light through the electron transport layer and the hole transport layer, respectively.
  • the flexible substrate used for fabricating the flexible TFT backsheet can generally withstand relatively low temperatures, and the conventional method for preparing TFT on a flexible substrate is limited by temperature to prevent flexibility. The substrate causes damage.
  • the TFT prepared by the conventional method of preparing a TFT on a flexible substrate has a low electron mobility.
  • the process temperature is low, the flexible substrate material is not limited, and on the other hand, the electron mobility of the active layer of the TFT can be improved.
  • Another object of the present invention is to provide a flexible TFT backplane in which the active layer of the TFT has high electron mobility and good strength and flexibility.
  • the present invention first provides a method for fabricating a flexible TFT backplane, including the following steps:
  • Step S1 providing a glass substrate, and cleaning and pre-baking the glass substrate;
  • Step S2 coating a flexible substrate on the glass substrate
  • Step S3 firstly depositing a silicon nitride film on the flexible substrate and a silicon oxide film laminated on the silicon nitride film several times, and then depositing an aluminum oxide film to form a buffer layer;
  • Step S4 depositing a first metal thin film on the buffer layer and patterning the first metal thin film to form a gate;
  • Step S5 depositing a gate insulating layer on the gate and the buffer layer;
  • Step S6 configuring a mixed solution of the carbon nanotubes and the metal oxide, and then coating the mixed solution of the carbon nanotubes and the metal oxide on the gate insulating layer and drying to obtain carbon nanotubes and metal oxide Mixed film;
  • Step S7 patterning the carbon nanotube and metal oxide mixed film to form an active layer above the gate
  • Step S8 depositing an interlayer insulating layer on the active layer and the gate insulating layer, and patterning the interlayer insulating layer to form a first via and a second through the interlayer insulating layer a via hole, the first via hole and the second via hole respectively exposing both ends of the active layer;
  • Step S9 depositing a second metal thin film on the interlayer insulating layer and patterning the second metal thin film to form a source and a drain, wherein the source and the drain respectively pass through the first The hole and the second via contact the two ends of the active layer;
  • the gate, the active layer, the source and the drain constitute a TFT.
  • the manufacturing method of the flexible TFT backplane further includes:
  • Step S10 depositing a passivation layer on the interlayer insulating layer, the source and the drain, and patterning the passivation layer to form a third via hole penetrating the passivation layer, Three vias exposing the drain;
  • Step S11 removing the glass substrate.
  • the flexible substrate is a yellow polyimide film or a transparent polyimide film.
  • the step S3 repeats depositing the silicon nitride film and the silicon oxide film laminated on the silicon nitride film twice or three times, and the laminated thickness of the silicon nitride film and the silicon oxide film is
  • the step S3 deposits an aluminum oxide film by an atomic layer deposition process, and the thickness of the aluminum oxide film is
  • the metal oxide is zinc oxide; when the mixed solution of carbon nanotubes and zinc oxide is disposed in the step S6, the weight ratio of the carbon nanotubes to the zinc oxide is 5:100 to 20:100.
  • the solvent used in the step S6 in which the mixed solution of carbon nanotubes and zinc oxide is disposed is polyethylene glycol.
  • the gate insulating layer is made of silicon oxide and has a thickness of
  • the interlayer insulating layer is made of silicon oxide and has a thickness of
  • the material of the passivation layer is silicon oxide or silicon nitride, and the thickness is
  • the material of the first metal film and the second metal film is a laminated combination of one or more of molybdenum, aluminum, copper and titanium, and the thickness is
  • the invention also provides a flexible TFT backplane, comprising:
  • the buffer layer comprises a plurality of layers of silicon nitride film and silicon oxide film laminated on each other and an uppermost layer of aluminum oxide film from bottom to top;
  • interlayer insulating layer covering the active layer and the gate insulating layer;
  • the interlayer insulating layer has a first via hole and a second via hole, and the first via hole and the second via hole respectively expose the Both ends of the active layer;
  • a source and a drain disposed on the interlayer insulating layer; the source and the drain respectively contact the two ends of the active layer via the first via and the second via;
  • the gate, the active layer, the source and the drain constitute a TFT.
  • the flexible TFT backplane further includes a passivation layer covering the interlayer insulating layer, a source and a drain; the passivation layer has a third via, and the third via exposes the drain.
  • the invention also provides a manufacturing method of a flexible TFT backplane, comprising the following steps:
  • Step S1 providing a glass substrate, and cleaning and pre-baking the glass substrate;
  • Step S2 coating a flexible substrate on the glass substrate
  • Step S3 firstly depositing a silicon nitride film on the flexible substrate and a silicon oxide film laminated on the silicon nitride film several times, and then depositing an aluminum oxide film to form a buffer layer;
  • Step S4 depositing a first metal thin film on the buffer layer and patterning the first metal thin film to form a gate;
  • Step S5 depositing a gate insulating layer on the gate and the buffer layer;
  • Step S6 configuring a mixed solution of the carbon nanotubes and the metal oxide, and then coating the mixed solution of the carbon nanotubes and the metal oxide on the gate insulating layer and drying to obtain carbon nanotubes and metal oxide Mixed film;
  • Step S7 patterning the carbon nanotube and metal oxide mixed film to form an active layer above the gate
  • Step S8 depositing an interlayer insulating layer on the active layer and the gate insulating layer, and patterning the interlayer insulating layer to form a first via and a second through the interlayer insulating layer a via hole, the first via hole and the second via hole respectively exposing both ends of the active layer;
  • Step S9 depositing a second metal thin film on the interlayer insulating layer and patterning the second metal thin film to form a source and a drain, wherein the source and the drain respectively pass through the first The hole and the second via contact the two ends of the active layer;
  • the gate, the active layer, the source and the drain constitute a TFT
  • Step S10 depositing a passivation layer on the interlayer insulating layer, the source and the drain, and patterning the passivation layer to form a third via hole penetrating the passivation layer, Three vias exposing the drain;
  • Step S11 removing the glass substrate
  • the flexible substrate is a yellow polyimide film or a transparent polyimide film
  • the step S3 repeats depositing the silicon nitride film and the silicon oxide film laminated on the silicon nitride film twice or three times, and the laminated thickness of the silicon nitride film and the silicon oxide film is
  • an aluminum oxide film is deposited by an atomic layer deposition process, and the thickness of the aluminum oxide film is
  • the present invention provides a method for fabricating a flexible TFT back sheet, which uses a mixed solution of carbon nanotubes and metal oxides to prepare an active layer of a TFT, which has a low process temperature and does not affect a flexible substrate.
  • the damage is caused, so the material of the flexible substrate is not limited, and the use of the vacuum device can be reduced, and the production cost can be reduced; the conductivity of the carbon nanotube is excellent, and the mixing with the metal oxide can significantly increase the active layer of the TFT.
  • the buffer layer formed by the method for fabricating the flexible TFT back sheet provided by the present invention is in contact with the flexible substrate, and the lowermost layer is a silicon nitride film, which can adhere the buffer layer to the flexible substrate.
  • the uppermost layer of the buffer layer is an aluminum oxide film, which enables the buffer layer to have a good water vapor resistance.
  • the present invention provides a flexible TFT backplane in which a thin film of carbon nanotubes and a metal oxide is used as an active layer of the TFT, which can significantly improve electron mobility, and the carbon nanotubes have good strength of the active layer of the TFT.
  • the lowermost layer that contacts the buffer layer and the flexible substrate is provided as a silicon nitride film, which can make the adhesion between the buffer layer and the flexible substrate good, and the buffer layer is the most
  • the upper layer is provided as an aluminum oxide film, which enables the buffer layer to have a good water vapor resistance.
  • FIG. 1 is a flow chart of a method for fabricating a flexible TFT backplane of the present invention
  • step S1 of a method for fabricating a flexible TFT backplane according to the present invention
  • step S2 of the method for fabricating a flexible TFT backplane of the present invention
  • step S3 is a schematic diagram of step S3 of the method for fabricating a flexible TFT backplane of the present invention
  • step S4 of the method for fabricating a flexible TFT backplane of the present invention
  • step S5 is a schematic diagram of step S5 of the method for fabricating a flexible TFT backplane of the present invention.
  • step S6 is a schematic diagram of step S6 of the method for fabricating a flexible TFT backplane of the present invention.
  • step S7 is a schematic diagram of step S7 of the method for fabricating a flexible TFT backplane of the present invention.
  • step S8 is a schematic diagram of step S8 of the method for fabricating a flexible TFT backplane of the present invention.
  • step S9 is a schematic diagram of step S9 of the method for fabricating a flexible TFT backplane of the present invention.
  • step S10 is a schematic diagram of step S10 of a method for fabricating a flexible TFT backplane according to the present invention.
  • FIG. 12 is a schematic diagram of the step S11 of the method for fabricating the flexible TFT backplane of the present invention and the present invention A schematic diagram of the structure of a flexible TFT backplane.
  • the present invention first provides a method for fabricating a flexible TFT backplane, including the following steps:
  • Step S1 as shown in FIG. 2, a glass substrate 1 is provided, and the glass substrate 1 is cleaned and prebaked.
  • Step S2 as shown in FIG. 3, a flexible substrate 2 is coated on the glass substrate 1.
  • the flexible substrate 2 coated in the step S2 is a yellow polyimide (PI) film or a transparent PI film.
  • the yellow PI film can withstand temperatures higher than the temperature that the transparent PI film can withstand.
  • Step S3 firstly depositing a silicon nitride (SiNx) film 31 and a silicon oxide (SiOx) film 32 laminated on the silicon nitride film 31 several times on the flexible substrate 2, Further, an aluminum oxide (Al 2 O 3 ) film 33 is deposited by an atomic layer deposition (ALD) to form a buffer layer 3.
  • SiNx silicon nitride
  • SiOx silicon oxide
  • Al 2 O 3 aluminum oxide
  • the number of times of repeatedly depositing the silicon nitride film 31 and the silicon oxide film 32 laminated on the silicon nitride film 31 in the step S3 is preferably 2 to 3 times to increase the waterproof performance of the buffer layer 3
  • the laminated thickness of the silicon nitride film 31 and the silicon oxide film 32 is Since the lowermost layer of the buffer layer 3 in contact with the flexible substrate 2 is the silicon nitride film 31, the silicon nitride film 31 has strong adhesion and is not easily peeled off, so that the buffer layer 3 and the flexible substrate 2 can be provided between Good adhesion.
  • the thickness of the aluminum oxide film 33 is Since the texture of the aluminum oxide film 33 is dense, the ability to cover defects is strong, and the effect of blocking moisture is remarkable, so that the buffer layer 3 can have a good water vapor resistance.
  • Step S4 as shown in FIG. 5, a first metal thin film is deposited on the buffer layer 3, and the first metal thin film is patterned by a yellow light or an etching process to form a gate electrode 4.
  • the material of the first metal thin film may be a laminated combination of one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and the thickness is
  • Step S5 as shown in FIG. 6, a gate insulating layer 5 is deposited on the gate electrode 4 and the buffer layer 3.
  • the material of the gate insulating layer 5 is silicon oxide, and the thickness is
  • Step S6 first configuring a mixed solution of carbon nanotubes (CNTs) and a metal oxide, and then coating the mixture of the carbon nanotubes and the metal oxide on the gate insulating layer 5 as shown in FIG. The solution is dried and a film 6 in which carbon nanotubes are mixed with a metal oxide is obtained.
  • CNTs carbon nanotubes
  • the metal oxide is preferably zinc oxide (ZnO);
  • the ratio of the weight of the carbon nanotubes to the zinc oxide as the solute is 5:100 to 20:100;
  • the drying temperature may be lower than 200 ° C, and the flexible substrate 2 may not be damaged. Therefore, the material of the flexible substrate 2 is not limited.
  • Step S7 as shown in FIG. 8, the film 6 in which the carbon nanotubes and the metal oxide are mixed is patterned by a yellow light or an etching process to form an active layer 61 located above the gate electrode 4.
  • the carbon nanotubes are excellent in electrical conductivity, their mixing with the metal oxide as the active layer 61 can significantly improve the electron mobility, and the carbon nanotubes give the active layer 61 good strength and flexibility.
  • the active layer 61 is prepared by the solution method in the step S6 and the step S7, and the conventional method of preparing the active layer can reduce the use of the vacuum device and reduce the production cost.
  • Step S8 as shown in FIG. 9, an interlayer insulating layer 7 is deposited on the active layer 61 and the gate insulating layer 5, and the interlayer insulating layer 7 is patterned by a yellow light or etching process.
  • a first via 71 and a second via 72 are formed through the interlayer insulating layer 7, and the first via 71 and the second via 72 respectively expose both ends of the active layer 61.
  • the material of the interlayer insulating layer 7 is silicon oxide, and the thickness is
  • Step S9 depositing a second metal thin film on the interlayer insulating layer 7 and patterning the second metal thin film by a yellow light or etching process to form a source 81 and a drain 82.
  • the source 81 and the drain 82 are in contact with both ends of the active layer 61 via the first via 71 and the second via 72, respectively.
  • the gate electrode 4, the active layer 61, the source electrode 81, and the drain electrode 82 constitute a TFT T.
  • the material of the second metal thin film may be a laminated combination of one or more of molybdenum, aluminum, copper, and titanium, and the thickness is
  • Step S10 as shown in FIG. 11, a passivation layer 9 is deposited on the interlayer insulating layer 7, the source 81 and the drain 82, and the passivation layer 9 is patterned by a yellow light or etching process. Forming a third via 91 through the passivation layer 9, the third via 91 exposing the drain 82.
  • the material of the passivation layer 9 is silicon oxide or silicon nitride, and the thickness is The third via 91 is used to provide a path for the subsequent OLED device to be fabricated to connect the drain 82.
  • Step S11 as shown in FIG. 12, the glass substrate 1 is removed.
  • the active layer 61 of the TFT T is prepared by using a mixed solution of carbon nanotubes and a metal oxide, and the process temperature is low, and damage to the flexible substrate 2 is not caused, so
  • the material of the flexible substrate 2 is not limited, and the use of the vacuum apparatus can be reduced, and the production cost can be reduced; the conductivity of the carbon nanotube is excellent, and mixing with the metal oxide as the active layer 61 of the TFT T can significantly improve the electron mobility.
  • the lowermost layer of the buffer layer 3 in contact with the flexible substrate 2 is a silicon nitride film 31, which can make the adhesion between the buffer layer 3 and the flexible substrate 2 good
  • the uppermost layer of the buffer layer 3 is an aluminum oxide film 33.
  • the buffer layer 3 can be provided with a good water vapor resistance.
  • the present invention further provides a flexible TFT backplane manufactured by the method for fabricating the flexible TFT backplane, comprising:
  • the buffer layer 3 includes a plurality of layers of silicon nitride film 31 and a silicon oxide film 32 laminated on each other and an aluminum oxide film 33 located at the uppermost layer from bottom to top ;
  • the interlayer insulating layer 7 has a first via 71 and a second via 72, the first via 71 and the second Via holes 72 respectively expose both ends of the active layer 61;
  • a passivation layer 9 covering the interlayer insulating layer 7, the source 81 and the drain 82;
  • the passivation layer 9 has a third via 91, and the third via 91 exposes the drain 82 ;
  • the gate electrode 4, the active layer 61, the source electrode 81, and the drain electrode 82 constitute a TFT T.
  • the flexible substrate 2 is a yellow PI film or a transparent PI film
  • the laminated thickness of the silicon nitride film 31 and the silicon oxide film 32 is Since the lowermost layer of the buffer layer 3 in contact with the flexible substrate 2 is the silicon nitride film 31, the silicon nitride film 31 has strong adhesion and is not easily peeled off, so that the buffer layer 3 and the flexible substrate 2 can be provided between Good adhesion; the thickness of the aluminum oxide film 33 is Since the texture of the aluminum oxide film 33 is dense, the ability to cover defects is strong, and the effect of blocking water vapor is remarkable, so that the buffer layer 3 can have a good water vapor resistance;
  • the material of the gate 4 may be a laminated combination of one or more of molybdenum, aluminum, copper, titanium, and the thickness is
  • the material of the gate insulating layer 5 is silicon oxide, and the thickness is
  • the material of the active layer 61 is preferably a film of carbon nanotubes mixed with zinc oxide, and the weight percentage of the carbon nanotubes and the zinc oxide is 5% to 20%; and the carbon nanotubes are excellent in conductivity, and are mixed with zinc oxide.
  • the active layer 61 as the TFT T can significantly improve the electron mobility, and the carbon nanotubes make the active layer 61 have good strength and flexibility, thereby making the TFT back sheet more flexible and more suitable for making a flexible display. device;
  • the interlayer insulating layer 7 is made of silicon oxide and has a thickness of
  • the material of the source 81 and the drain 82 may be a laminated combination of one or more of molybdenum, aluminum, copper, and titanium, and the thickness is
  • the material of the passivation layer 9 is silicon oxide or silicon nitride, and the thickness is
  • the flexible TFT back sheet of the present invention a film in which carbon nanotubes and a metal oxide are mixed is used as an active layer of the TFT T, and the electron mobility can be remarkably improved, and the carbon nanotubes make the active layer 61 of the TFT T have good strength.
  • the lowermost layer contacting the buffer layer 3 with the flexible substrate 2 is provided as a silicon nitride film 31, which enables adhesion between the buffer layer 3 and the flexible substrate 2.
  • the uppermost layer of the buffer layer 3 is provided as an aluminum oxide film 33, so that the buffer layer 3 can have a good water vapor resistance.
  • the method for fabricating the flexible TFT back sheet of the present invention uses a mixed solution of carbon nanotubes and metal oxide to prepare an active layer of the TFT, and the process temperature is low, and damage to the flexible substrate is not caused.
  • the material of the flexible substrate is not limited, and the use of the vacuum device can be reduced, and the production cost can be reduced; the conductivity of the carbon nanotube is excellent, and mixing with the metal oxide as the active layer of the TFT can significantly improve the electron mobility;
  • the buffer layer formed by the method for fabricating the flexible TFT back sheet of the present invention is in contact with the flexible substrate, and the lowermost layer is a silicon nitride film, which can make the adhesion between the buffer layer and the flexible substrate good, and the buffer layer is The uppermost layer is an aluminum oxide film, which enables the buffer layer to have a good water vapor resistance.
  • the present invention provides a flexible TFT backplane in which a thin film of carbon nanotubes and a metal oxide is used as an active layer of the TFT, which can significantly improve electron mobility, and the carbon nanotubes have good strength of the active layer of the TFT.
  • Flexibility more suitable for making flexible display devices; in addition, the lowermost layer that contacts the buffer layer and the flexible substrate is provided as a silicon nitride film, which can make the adhesion between the buffer layer and the flexible substrate good, and the buffer layer is the most
  • the upper layer is provided as an aluminum oxide film, which enables the buffer layer to have a good water vapor resistance.

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Abstract

本发明提供一种柔性TFT背板的制作方法及柔性TFT背板。该柔性TFT背板的制作方法采用碳纳米管与金属氧化物的混合溶液来制备TFT（T）的有源层（61），制程温度较低，不会对柔性衬底（2）造成损害，因此所述柔性衬底（2）的材料不受限制，且可以减少真空设备的使用，降低生产成本；碳纳米管的导电性优良，其与金属氧化物混合作为TFT的有源层（61）能够显著提高电子迁移率；另外，该柔性TFT背板的制作方法所制作出的缓冲层（3）与柔性衬底（2）接触的最下层为氮化硅薄膜（31），能够使缓冲层（3）与柔性衬底（2）之间的黏附性好，缓冲层（3）的最上层为氧化铝薄膜（33），能够使缓冲层（3）具备较好的防水汽能力。

Description

柔性TFT背板的制作方法及柔性TFT背板 技术领域
本发明涉及显示技术领域，尤其涉及一种柔性TFT背板的制作方法及柔性TFT背板。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平板显示技术已经逐步取代CRT显示器。其中，OLED显示器具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
现有的柔性OLED显示器一般包括柔性TFT(Thin Film Transistor Array Substrate，薄膜晶体管)背板以及设于柔性TFT背板上的OLED器件。所述柔性TFT背板用于对OLED器件进行驱动；所述OLED器件包括阳极、设于阳极上的空穴注入层、设于空穴注入层上的空穴传输层、设于空穴传输层上的发光层、设于发光层上的电子传输层、设于电子传输层上的电子注入层及设于电子注入层上的阴极。OLED器件的发光原理为：在一定电压驱动下，电子和空穴分别从阴极和阳极注入到电子传输层和空穴传输层，电子和空穴分别经过电子传输层和空穴传输层迁移到发光层，并在发光层中相遇，形成激子并使发光分子激发，后者经过辐射弛豫而发出可见光。
在现有的技术条件下，制作柔性TFT背板所使用的柔性衬底所能够耐受的温度一般比较低，常规的在柔性衬底上制备TFT的方法会受到温度的限制，以防止对柔性衬底造成损害。
另外，常规的在柔性衬底上制备TFT的方法所制备出的TFT的电子迁移率较低。
发明内容
本发明的目的在于提供一种柔性TFT背板的制作方法，一方面制程温度低，对柔性衬底材料没有限制，另一方面能够提高TFT有源层的电子迁移率。
本发明的另一目的在于提供一种柔性TFT背板，其内TFT有源层的电子迁移率高，强度和柔韧性好。
为实现上述目的，本发明首先提供一种柔性TFT背板的制作方法，包括以下步骤：
步骤S1、提供玻璃基板，对所述玻璃基板进行清洗和预烘烤；
步骤S2、在所述玻璃基板上涂布柔性衬底；
步骤S3、先在所述柔性衬底上反复沉积氮化硅薄膜与层叠在所述氮化硅薄膜上的氧化硅薄膜数次，再沉积氧化铝薄膜，形成缓冲层；
步骤S4、在所述缓冲层上沉积第一金属薄膜并对所述第一金属薄膜进行图案化处理，形成栅极；
步骤S5、在所述栅极与缓冲层上沉积栅极绝缘层；
步骤S6、配置碳纳米管与金属氧化物的混合溶液，然后在所述栅极绝缘层上涂布所述碳纳米管与金属氧化物的混合溶液并进行烘干，获得碳纳米管与金属氧化物混合的薄膜；
步骤S7、对所述碳纳米管与金属氧化物混合的薄膜进行图案化处理，形成位于所述栅极上方的有源层；
步骤S8、在所述有源层与栅极绝缘层上沉积层间绝缘层，并对所述层间绝缘层进行图案化处理，形成贯穿所述层间绝缘层的第一过孔与第二过孔，所述第一过孔与第二过孔分别暴露出所述有源层的两端；
步骤S9、在所述层间绝缘层上沉积第二金属薄膜并对所述第二金属薄膜进行图案化处理，形成源极与漏极，所述源极与漏极分别经由所述第一过孔与第二过孔接触所述有源层的两端；
所述栅极、有源层、源极与漏极构成TFT。
所述柔性TFT背板的制作方法还包括：
步骤S10、在所述层间绝缘层、源极与漏极上沉积钝化层，并对所述钝化层进行图案化处理，形成贯穿所述钝化层的第三过孔，所述第三过孔暴露出所述漏极；
步骤S11、去除所述玻璃基板。
所述柔性衬底为黄色的聚酰亚胺薄膜或透明的聚酰亚胺薄膜。
所述步骤S3反复沉积氮化硅薄膜与层叠在所述氮化硅薄膜上的氧化硅薄膜的次数为2次～3次，所述氮化硅薄膜与氧化硅薄膜的叠层厚度为
Figure PCTCN2018104485-appb-000001
所述步骤S3采用原子层沉积工艺沉积氧化铝薄膜，所述氧化铝薄膜的厚度为
Figure PCTCN2018104485-appb-000002
所述金属氧化物为氧化锌；所述步骤S6中配置碳纳米管与氧化锌的混合溶液时，碳纳米管与氧化锌的重量之比为5：100～20：100。
所述步骤S6中配置碳纳米管与氧化锌的混合溶液时所使用的溶剂为聚乙二醇。
所述栅极绝缘层的材料为氧化硅，厚度为
Figure PCTCN2018104485-appb-000003
所述层间绝缘层的材料为氧化硅，厚度为
Figure PCTCN2018104485-appb-000004
所述钝化层的材料为氧化硅或氮化硅，厚度为
Figure PCTCN2018104485-appb-000005
所述第一金属薄膜与第二金属薄膜的材料均为钼、铝、铜、钛中的一种或多种的层叠组合，厚度均为
Figure PCTCN2018104485-appb-000006
本发明还提供一种柔性TFT背板，包括：
柔性衬底；
覆盖所述柔性衬底的缓冲层；所述缓冲层自下至上包括数层相互层叠的氮化硅薄膜与氧化硅薄膜及位于最上层的氧化铝薄膜；
设于所述缓冲层上的栅极；
覆盖所述栅极与缓冲层的栅极绝缘层；
于所述栅极上方设在所述栅极绝缘层上的有源层；所述有源层的材料为碳纳米管与金属氧化物混合的薄膜；
覆盖所述有源层与栅极绝缘层的层间绝缘层；所述层间绝缘层具有第一过孔与第二过孔，所述第一过孔与第二过孔分别暴露出所述有源层的两端；
以及设在所述层间绝缘层上的源极与漏极；所述源极与漏极分别经由所述第一过孔与第二过孔接触所述有源层的两端；
所述栅极、有源层、源极与漏极构成TFT。
所述柔性TFT背板还包括覆盖所述层间绝缘层、源极与漏极的钝化层；所述钝化层具有第三过孔，所述第三过孔暴露出所述漏极。
本发明还提供一种柔性TFT背板的制作方法，包括以下步骤：
步骤S1、提供玻璃基板，对所述玻璃基板进行清洗和预烘烤；
步骤S2、在所述玻璃基板上涂布柔性衬底；
步骤S3、先在所述柔性衬底上反复沉积氮化硅薄膜与层叠在所述氮化硅薄膜上的氧化硅薄膜数次，再沉积氧化铝薄膜，形成缓冲层；
步骤S4、在所述缓冲层上沉积第一金属薄膜并对所述第一金属薄膜进行图案化处理，形成栅极；
步骤S5、在所述栅极与缓冲层上沉积栅极绝缘层；
步骤S6、配置碳纳米管与金属氧化物的混合溶液，然后在所述栅极绝 缘层上涂布所述碳纳米管与金属氧化物的混合溶液并进行烘干，获得碳纳米管与金属氧化物混合的薄膜；
步骤S7、对所述碳纳米管与金属氧化物混合的薄膜进行图案化处理，形成位于所述栅极上方的有源层；
步骤S8、在所述有源层与栅极绝缘层上沉积层间绝缘层，并对所述层间绝缘层进行图案化处理，形成贯穿所述层间绝缘层的第一过孔与第二过孔，所述第一过孔与第二过孔分别暴露出所述有源层的两端；
步骤S9、在所述层间绝缘层上沉积第二金属薄膜并对所述第二金属薄膜进行图案化处理，形成源极与漏极，所述源极与漏极分别经由所述第一过孔与第二过孔接触所述有源层的两端；
所述栅极、有源层、源极与漏极构成TFT；
步骤S10、在所述层间绝缘层、源极与漏极上沉积钝化层，并对所述钝化层进行图案化处理，形成贯穿所述钝化层的第三过孔，所述第三过孔暴露出所述漏极；
步骤S11、去除所述玻璃基板；
其中，所述柔性衬底为黄色的聚酰亚胺薄膜或透明的聚酰亚胺薄膜；
其中，所述步骤S3反复沉积氮化硅薄膜与层叠在所述氮化硅薄膜上的氧化硅薄膜的次数为2次～3次，所述氮化硅薄膜与氧化硅薄膜的叠层厚度为
Figure PCTCN2018104485-appb-000007
其中，所述步骤S3采用原子层沉积工艺沉积氧化铝薄膜，所述氧化铝薄膜的厚度为
Figure PCTCN2018104485-appb-000008
本发明的有益效果：本发明提供的一种柔性TFT背板的制作方法，采用碳纳米管与金属氧化物的混合溶液来制备TFT的有源层，制程温度较低，不会对柔性衬底造成损害，因此所述柔性衬底的材料不受限制，并且可以减少真空设备的使用，降低生产成本；碳纳米管的导电性优良，其与金属氧化物混合作为TFT的有源层能够显著提高电子迁移率；另外，本发明所提供的柔性TFT背板的制作方法所制作出的缓冲层与柔性衬底接触的最下层为氮化硅薄膜，能够使缓冲层与柔性衬底之间的黏附性好，缓冲层的最上层为氧化铝薄膜，能够使所述缓冲层具备较好的防水汽能力。本发明提供的一种柔性TFT背板，以碳纳米管与金属氧化物混合的薄膜作为TFT的有源层，能够显著提高电子迁移率，并且碳纳米管使得TFT有源层具有良好的强度和柔韧性，更适于制作柔性显示设备；此外，将缓冲层与柔性衬底接触的最下层设置为氮化硅薄膜，能够使缓冲层与柔性衬底之间的黏附性好，缓冲层的最上层设置为氧化铝薄膜，能够使所述缓冲层具备较好的 防水汽能力。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的柔性TFT背板的制作方法的流程图；
图2为本发明的柔性TFT背板的制作方法的步骤S1的示意图；
图3为本发明的柔性TFT背板的制作方法的步骤S2的示意图；
图4为本发明的柔性TFT背板的制作方法的步骤S3的示意图；
图5为本发明的柔性TFT背板的制作方法的步骤S4的示意图；
图6为本发明的柔性TFT背板的制作方法的步骤S5的示意图；
图7为本发明的柔性TFT背板的制作方法的步骤S6的示意图；
图8为本发明的柔性TFT背板的制作方法的步骤S7的示意图；
图9为本发明的柔性TFT背板的制作方法的步骤S8的示意图；
图10为本发明的柔性TFT背板的制作方法的步骤S9的示意图；
图11为本发明的柔性TFT背板的制作方法的步骤S10的示意图；
图12为本发明的柔性TFT背板的制作方法的步骤S11的示意图暨本发 明的柔性TFT背板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明首先提供一种柔性TFT背板的制作方法，包括如下步骤：
步骤S1、如图2所示，提供玻璃基板1，对所述玻璃基板1进行清洗和预烘烤。
步骤S2、如图3所示，在所述玻璃基板1上涂布柔性衬底2。
具体地，该步骤S2所涂布的柔性衬底2为黄色的聚酰亚胺(Polyimide，PI)薄膜或透明的PI薄膜。黄色的PI薄膜可耐受的温度高于透明的PI薄膜可耐受的温度。
步骤S3、如图4所示，先在所述柔性衬底2上反复沉积氮化硅(SiNx)薄膜31与层叠在所述氮化硅薄膜31上的氧化硅(SiOx)薄膜32数次，再 采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积氧化铝(Al 2O 3)薄膜33，形成缓冲层3。
具体地，该步骤S3反复沉积氮化硅薄膜31与层叠在所述氮化硅薄膜31上的氧化硅薄膜32的次数优选为2次～3次，以增加所述缓冲层3的防水性能，最终所述氮化硅薄膜31与氧化硅薄膜32的叠层厚度为
Figure PCTCN2018104485-appb-000009
Figure PCTCN2018104485-appb-000010
由于所述缓冲层3与柔性衬底2接触的最下层为氮化硅薄膜31，氮化硅薄膜31的附着性强，不易剥落，能够使得所述缓冲层3与柔性衬底2之间具有良好的黏附性。
所述氧化铝薄膜33的厚度为
Figure PCTCN2018104485-appb-000011
由于所述氧化铝薄膜33的质地致密，覆盖缺陷的能力很强，阻挡水汽的效果显著，能够使所述缓冲层3具备较好的防水汽能力。
步骤S4、如图5所示，在所述缓冲层3上沉积第一金属薄膜并通过黄光、蚀刻制程对所述第一金属薄膜进行图案化处理，形成栅极4。
具体地，所述第一金属薄膜的材料可以是钼(Mo)、铝(Al)、铜(Cu)、钛(Ti)中的一种或多种的层叠组合，厚度为
Figure PCTCN2018104485-appb-000012
步骤S5、如图6所示，在所述栅极4与缓冲层3上沉积栅极绝缘层5。
具体地，所述栅极绝缘层5的材料为氧化硅，厚度为
Figure PCTCN2018104485-appb-000013
步骤S6、先配置碳纳米管(Carbon Nanotube，CNT)与金属氧化物的混合溶液，然后如图7所示在所述栅极绝缘层5上涂布所述碳纳米管与金属氧化物的混合溶液并进行烘干，获得碳纳米管与金属氧化物混合的薄膜6。
具体地：
所述金属氧化物优选为氧化锌(ZnO)；
该步骤S6配置碳纳米管与氧化锌的混合溶液时，使用聚乙二醇为溶剂，作为溶质的碳纳米管与氧化锌的重量之比为5：100～20：100；
对涂布在所述栅极绝缘层5上的碳纳米管与金属氧化物的混合溶液进行烘干时，烘干的温度可低于200℃，不会对所述柔性衬底2造成损害，因此所述柔性衬底2的材料不受限制。
步骤S7、如图8所示，通过黄光、蚀刻制程对所述碳纳米管与金属氧化物混合的薄膜6进行图案化处理，形成位于所述栅极4上方的有源层61。
由于碳纳米管的导电性优良，其与金属氧化物混合作为有源层61能够显著提高电子迁移率，并且碳纳米管使得所述有源层61具有良好的强度和柔韧性。
所述步骤S6与步骤S7即采用溶液法制备出了所述有源层61，相比现 有的制备有源层的常规方式可以减少真空设备的使用，降低生产成本。
步骤S8、如图9所示，在所述有源层61与栅极绝缘层5上沉积层间绝缘层7，并通过黄光、蚀刻制程对所述层间绝缘层7进行图案化处理，形成贯穿所述层间绝缘层7的第一过孔71与第二过孔72，所述第一过孔71与第二过孔72分别暴露出所述有源层61的两端。
具体地，所述层间绝缘层7的材料为氧化硅，厚度为
Figure PCTCN2018104485-appb-000014
步骤S9、如图10所示，在所述层间绝缘层7上沉积第二金属薄膜并通过黄光、蚀刻制程对所述第二金属薄膜进行图案化处理，形成源极81与漏极82，所述源极81与漏极82分别经由所述第一过孔71与第二过孔72接触所述有源层61的两端。
完成该步骤S9后，所述栅极4、有源层61、源极81与漏极82构成TFT T。
具体地，所述第二金属薄膜的材料可以是钼、铝、铜、钛中的一种或多种的层叠组合，厚度为
Figure PCTCN2018104485-appb-000015
步骤S10、如图11所示，在所述层间绝缘层7、源极81与漏极82上沉积钝化层9，并通过黄光、蚀刻制程对所述钝化层9进行图案化处理，形成贯穿所述钝化层9的第三过孔91，所述第三过孔91暴露出所述漏极82。
具体地，所述钝化层9的材料为氧化硅或氮化硅，厚度为
Figure PCTCN2018104485-appb-000016
Figure PCTCN2018104485-appb-000017
所述第三过孔91用于为后续要制作的OLED器件连接所述漏极82提供路径。
步骤S11、如图12所示，去除所述玻璃基板1。
至此完成柔性TFT背板的制作。
本发明的柔性TFT背板的制作方法，采用碳纳米管与金属氧化物的混合溶液来制备TFT T的有源层61，制程温度较低，不会对柔性衬底2造成损害，因此所述柔性衬底2的材料不受限制，并且可以减少真空设备的使用，降低生产成本；碳纳米管的导电性优良，其与金属氧化物混合作为TFT T的有源层61能够显著提高电子迁移率；另外，缓冲层3与柔性衬底2接触的最下层为氮化硅薄膜31，能够使缓冲层3与柔性衬底2之间的黏附性好，缓冲层3的最上层为氧化铝薄膜33，能够使所述缓冲层3具备较好的防水汽能力。
请参阅图12，本发明还提供一种经上述柔性TFT背板的制作方法所制作出的柔性TFT背板，包括：
柔性衬底2；覆盖所述柔性衬底2的缓冲层3；所述缓冲层3自下至上包括数层相互层叠的氮化硅薄膜31与氧化硅薄膜32及位于最上层的氧化 铝薄膜33；
设于所述缓冲层3上的栅极4；
覆盖所述栅极4与缓冲层3的栅极绝缘层5；
于所述栅极4上方设在所述栅极绝缘层5上的有源层61；所述有源层61的材料为碳纳米管与金属氧化物混合的薄膜；
覆盖所述有源层61与栅极绝缘层5的层间绝缘层7；所述层间绝缘层7具有第一过孔71与第二过孔72，所述第一过孔71与第二过孔72分别暴露出所述有源层61的两端；
设在所述层间绝缘层7上的源极81与漏极82；所述源极81与漏极82分别经由所述第一过孔71与第二过孔72接触所述有源层61的两端；
以及覆盖所述层间绝缘层7、源极81与漏极82的钝化层9；所述钝化层9具有第三过孔91，所述第三过孔91暴露出所述漏极82；
所述栅极4、有源层61、源极81与漏极82构成TFT T。
具体地：
所述柔性衬底2为黄色的PI薄膜或透明的PI薄膜；
在所述缓冲层3中：所述氮化硅薄膜31与氧化硅薄膜32的叠层厚度为
Figure PCTCN2018104485-appb-000018
由于所述缓冲层3与柔性衬底2接触的最下层为氮化硅薄膜31，氮化硅薄膜31的附着性强，不易剥落，能够使得所述缓冲层3与柔性衬底2之间具有良好的黏附性；所述氧化铝薄膜33的厚度为
Figure PCTCN2018104485-appb-000019
Figure PCTCN2018104485-appb-000020
由于所述氧化铝薄膜33的质地致密，覆盖缺陷的能力很强，阻挡水汽的效果显著，能够使所述缓冲层3具备较好的防水汽能力；
所述栅极4的材料可以是钼、铝、铜、钛中的一种或多种的层叠组合，厚度为
Figure PCTCN2018104485-appb-000021
所述栅极绝缘层5的材料为氧化硅，厚度为
Figure PCTCN2018104485-appb-000022
所述有源层61的材料优选为碳纳米管与氧化锌混合的薄膜，碳纳米管与氧化锌的重量百分比为5％～20％；由于碳纳米管的导电性优良，其与氧化锌混合作为TFT T的有源层61能够显著提高电子迁移率，并且碳纳米管使得所述有源层61具有良好的强度和柔韧性，从而使得TFT背板的柔性更佳，更适于制作柔性显示设备；
所述层间绝缘层7的材料为氧化硅，厚度为
Figure PCTCN2018104485-appb-000023
所述源极81与漏极82的材料可以是钼、铝、铜、钛中的一种或多种的层叠组合，厚度为
Figure PCTCN2018104485-appb-000024
所述钝化层9的材料为氧化硅或氮化硅，厚度为
Figure PCTCN2018104485-appb-000025
本发明的柔性TFT背板，以碳纳米管与金属氧化物混合的薄膜作为 TFT T的有源层，能够显著提高电子迁移率，并且碳纳米管使得TFT T的有源层61具有良好的强度和柔韧性，更适于制作柔性显示设备；此外，将缓冲层3与柔性衬底2接触的最下层设置为氮化硅薄膜31，能够使缓冲层3与柔性衬底2之间的黏附性好，缓冲层3的最上层设置为氧化铝薄膜33，能够使所述缓冲层3具备较好的防水汽能力。
综上所述，本发明的柔性TFT背板的制作方法，采用碳纳米管与金属氧化物的混合溶液来制备TFT的有源层，制程温度较低，不会对柔性衬底造成损害，因此所述柔性衬底的材料不受限制，并且可以减少真空设备的使用，降低生产成本；碳纳米管的导电性优良，其与金属氧化物混合作为TFT的有源层能够显著提高电子迁移率；另外，本发明的柔性TFT背板的制作方法所制作出的缓冲层与柔性衬底接触的最下层为氮化硅薄膜，能够使缓冲层与柔性衬底之间的黏附性好，缓冲层的最上层为氧化铝薄膜，能够使所述缓冲层具备较好的防水汽能力。本发明提供的一种柔性TFT背板，以碳纳米管与金属氧化物混合的薄膜作为TFT的有源层，能够显著提高电子迁移率，并且碳纳米管使得TFT有源层具有良好的强度和柔韧性，更适于制作柔性显示设备；此外，将缓冲层与柔性衬底接触的最下层设置为氮化硅薄膜，能够使缓冲层与柔性衬底之间的黏附性好，缓冲层的最上层设置为氧化铝薄膜，能够使所述缓冲层具备较好的防水汽能力。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明的权利要求的保护范围。

Claims (14)

  1. 一种柔性TFT背板的制作方法，包括以下步骤：
    步骤S1、提供玻璃基板，对所述玻璃基板进行清洗和预烘烤；
    步骤S2、在所述玻璃基板上涂布柔性衬底；
    步骤S3、先在所述柔性衬底上反复沉积氮化硅薄膜与层叠在所述氮化硅薄膜上的氧化硅薄膜数次，再沉积氧化铝薄膜，形成缓冲层；
    步骤S4、在所述缓冲层上沉积第一金属薄膜并对所述第一金属薄膜进行图案化处理，形成栅极；
    步骤S5、在所述栅极与缓冲层上沉积栅极绝缘层；
    步骤S6、配置碳纳米管与金属氧化物的混合溶液，然后在所述栅极绝缘层上涂布所述碳纳米管与金属氧化物的混合溶液并进行烘干，获得碳纳米管与金属氧化物混合的薄膜；
    步骤S7、对所述碳纳米管与金属氧化物混合的薄膜进行图案化处理，形成位于所述栅极上方的有源层；
    步骤S8、在所述有源层与栅极绝缘层上沉积层间绝缘层，并对所述层间绝缘层进行图案化处理，形成贯穿所述层间绝缘层的第一过孔与第二过孔，所述第一过孔与第二过孔分别暴露出所述有源层的两端；
    步骤S9、在所述层间绝缘层上沉积第二金属薄膜并对所述第二金属薄膜进行图案化处理，形成源极与漏极，所述源极与漏极分别经由所述第一过孔与第二过孔接触所述有源层的两端；
    所述栅极、有源层、源极与漏极构成TFT。
  2. 如权利要求1所述的柔性TFT背板的制作方法，还包括：
    步骤S10、在所述层间绝缘层、源极与漏极上沉积钝化层，并对所述钝化层进行图案化处理，形成贯穿所述钝化层的第三过孔，所述第三过孔暴露出所述漏极；
    步骤S11、去除所述玻璃基板。
  3. 如权利要求1所述的柔性TFT背板的制作方法，其中，所述柔性衬底为黄色的聚酰亚胺薄膜或透明的聚酰亚胺薄膜。
  4. 如权利要求1所述的柔性TFT背板的制作方法，其中，所述步骤S3反复沉积氮化硅薄膜与层叠在所述氮化硅薄膜上的氧化硅薄膜的次数为2次～3次，所述氮化硅薄膜与氧化硅薄膜的叠层厚度为
    Figure PCTCN2018104485-appb-100001
  5. 如权利要求1所述的柔性TFT背板的制作方法，其中，所述步骤 S3采用原子层沉积工艺沉积氧化铝薄膜，所述氧化铝薄膜的厚度为
    Figure PCTCN2018104485-appb-100002
    Figure PCTCN2018104485-appb-100003
  6. 如权利要求1所述的柔性TFT背板的制作方法，其中，所述金属氧化物为氧化锌；所述步骤S6中配置碳纳米管与氧化锌的混合溶液时，碳纳米管与氧化锌的重量之比为5：100～20：100。
  7. 如权利要求6所述的柔性TFT背板的制作方法，其中，所述步骤S6中配置碳纳米管与氧化锌的混合溶液时所使用的溶剂为聚乙二醇。
  8. 如权利要求2所述的柔性TFT背板的制作方法，其中，所述栅极绝缘层的材料为氧化硅，厚度为
    Figure PCTCN2018104485-appb-100004
    所述层间绝缘层的材料为氧化硅，厚度为
    Figure PCTCN2018104485-appb-100005
    所述钝化层的材料为氧化硅或氮化硅，厚度为
    Figure PCTCN2018104485-appb-100006
    所述第一金属薄膜与第二金属薄膜的材料均为钼、铝、铜、钛中的一种或多种的层叠组合，厚度均为
    Figure PCTCN2018104485-appb-100007
  9. 一种柔性TFT背板，包括：
    柔性衬底；
    覆盖所述柔性衬底的缓冲层；所述缓冲层自下至上包括数层相互层叠的氮化硅薄膜与氧化硅薄膜及位于最上层的氧化铝薄膜；
    设于所述缓冲层上的栅极；
    覆盖所述栅极与缓冲层的栅极绝缘层；
    于所述栅极上方设在所述栅极绝缘层上的有源层；所述有源层的材料为碳纳米管与金属氧化物混合的薄膜；
    覆盖所述有源层与栅极绝缘层的层间绝缘层；所述层间绝缘层具有第一过孔与第二过孔，所述第一过孔与第二过孔分别暴露出所述有源层的两端；
    以及设在所述层间绝缘层上的源极与漏极；所述源极与漏极分别经由所述第一过孔与第二过孔接触所述有源层的两端；
    所述栅极、有源层、源极与漏极构成TFT。
  10. 如权利要求9所述的柔性TFT背板，还包括覆盖所述层间绝缘层、源极与漏极的钝化层；所述钝化层具有第三过孔，所述第三过孔暴露出所述漏极。
  11. 一种柔性TFT背板的制作方法，包括以下步骤：
    步骤S1、提供玻璃基板，对所述玻璃基板进行清洗和预烘烤；
    步骤S2、在所述玻璃基板上涂布柔性衬底；
    步骤S3、先在所述柔性衬底上反复沉积氮化硅薄膜与层叠在所述氮化 硅薄膜上的氧化硅薄膜数次，再沉积氧化铝薄膜，形成缓冲层；
    步骤S4、在所述缓冲层上沉积第一金属薄膜并对所述第一金属薄膜进行图案化处理，形成栅极；
    步骤S5、在所述栅极与缓冲层上沉积栅极绝缘层；
    步骤S6、配置碳纳米管与金属氧化物的混合溶液，然后在所述栅极绝缘层上涂布所述碳纳米管与金属氧化物的混合溶液并进行烘干，获得碳纳米管与金属氧化物混合的薄膜；
    步骤S7、对所述碳纳米管与金属氧化物混合的薄膜进行图案化处理，形成位于所述栅极上方的有源层；
    步骤S8、在所述有源层与栅极绝缘层上沉积层间绝缘层，并对所述层间绝缘层进行图案化处理，形成贯穿所述层间绝缘层的第一过孔与第二过孔，所述第一过孔与第二过孔分别暴露出所述有源层的两端；
    步骤S9、在所述层间绝缘层上沉积第二金属薄膜并对所述第二金属薄膜进行图案化处理，形成源极与漏极，所述源极与漏极分别经由所述第一过孔与第二过孔接触所述有源层的两端；
    所述栅极、有源层、源极与漏极构成TFT；
    步骤S10、在所述层间绝缘层、源极与漏极上沉积钝化层，并对所述钝化层进行图案化处理，形成贯穿所述钝化层的第三过孔，所述第三过孔暴露出所述漏极；
    步骤S11、去除所述玻璃基板；
    其中，所述柔性衬底为黄色的聚酰亚胺薄膜或透明的聚酰亚胺薄膜；
    其中，所述步骤S3反复沉积氮化硅薄膜与层叠在所述氮化硅薄膜上的氧化硅薄膜的次数为2次～3次，所述氮化硅薄膜与氧化硅薄膜的叠层厚度为
    Figure PCTCN2018104485-appb-100008
    其中，所述步骤S3采用原子层沉积工艺沉积氧化铝薄膜，所述氧化铝薄膜的厚度为
    Figure PCTCN2018104485-appb-100009
  12. 如权利要求11所述的柔性TFT背板的制作方法，其中，所述金属氧化物为氧化锌；所述步骤S6中配置碳纳米管与氧化锌的混合溶液时，碳纳米管与氧化锌的重量之比为5：100～20：100。
  13. 如权利要求12所述的柔性TFT背板的制作方法，其中，所述步骤S6中配置碳纳米管与氧化锌的混合溶液时所使用的溶剂为聚乙二醇。
  14. 如权利要求11所述的柔性TFT背板的制作方法，其中，所述栅极绝缘层的材料为氧化硅，厚度为
    Figure PCTCN2018104485-appb-100010
    所述层间绝缘层的材料为氧化硅，厚度为
    Figure PCTCN2018104485-appb-100011
    所述钝化层的材料为氧化硅或氮化硅，厚 度为
    Figure PCTCN2018104485-appb-100012
    所述第一金属薄膜与第二金属薄膜的材料均为钼、铝、铜、钛中的一种或多种的层叠组合，厚度均为
    Figure PCTCN2018104485-appb-100013
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